sound/arm/aaci.h

   1 /*
   2  *  linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef AACI_H
  11 #define AACI_H
  12
  13 /*
  14  * Control and status register offsets
  15  *  P39.
  16  */
  17 #define AACI_CSCH1      0x000
  18 #define AACI_CSCH2      0x014
  19 #define AACI_CSCH3      0x028
  20 #define AACI_CSCH4      0x03c
  21
  22 #define AACI_RXCR       0x000   /* 29 bits Control Rx FIFO */
  23 #define AACI_TXCR       0x004   /* 17 bits Control Tx FIFO */
  24 #define AACI_SR         0x008   /* 12 bits Status */
  25 #define AACI_ISR        0x00c   /* 7 bits  Int Status */
  26 #define AACI_IE         0x010   /* 7 bits  Int Enable */
  27
  28 /*
  29  * Other registers
  30  */
  31 #define AACI_SL1RX      0x050
  32 #define AACI_SL1TX      0x054
  33 #define AACI_SL2RX      0x058
  34 #define AACI_SL2TX      0x05c
  35 #define AACI_SL12RX     0x060
  36 #define AACI_SL12TX     0x064
  37 #define AACI_SLFR       0x068   /* slot flags */
  38 #define AACI_SLISTAT    0x06c   /* slot interrupt status */
  39 #define AACI_SLIEN      0x070   /* slot interrupt enable */
  40 #define AACI_INTCLR     0x074   /* interrupt clear */
  41 #define AACI_MAINCR     0x078   /* main control */
  42 #define AACI_RESET      0x07c   /* reset control */
  43 #define AACI_SYNC       0x080   /* sync control */
  44 #define AACI_ALLINTS    0x084   /* all fifo interrupt status */
  45 #define AACI_MAINFR     0x088   /* main flag register */
  46 #define AACI_DR1        0x090   /* data read/written fifo 1 */
  47 #define AACI_DR2        0x0b0   /* data read/written fifo 2 */
  48 #define AACI_DR3        0x0d0   /* data read/written fifo 3 */
  49 #define AACI_DR4        0x0f0   /* data read/written fifo 4 */
  50
  51 /*
  52  * transmit fifo control register. P48
  53  */
  54 #define TXCR_FEN        (1 << 16)       /* fifo enable */
  55 #define TXCR_COMPACT    (1 << 15)       /* compact mode */
  56 #define TXCR_TSZ16      (0 << 13)       /* 16 bits */
  57 #define TXCR_TSZ18      (1 << 13)       /* 18 bits */
  58 #define TXCR_TSZ20      (2 << 13)       /* 20 bits */
  59 #define TXCR_TSZ12      (3 << 13)       /* 12 bits */
  60 #define TXCR_TX12       (1 << 12)       /* transmits slot 12 */
  61 #define TXCR_TX11       (1 << 11)       /* transmits slot 12 */
  62 #define TXCR_TX10       (1 << 10)       /* transmits slot 12 */
  63 #define TXCR_TX9        (1 << 9)        /* transmits slot 12 */
  64 #define TXCR_TX8        (1 << 8)        /* transmits slot 12 */
  65 #define TXCR_TX7        (1 << 7)        /* transmits slot 12 */
  66 #define TXCR_TX6        (1 << 6)        /* transmits slot 12 */
  67 #define TXCR_TX5        (1 << 5)        /* transmits slot 12 */
  68 #define TXCR_TX4        (1 << 4)        /* transmits slot 12 */
  69 #define TXCR_TX3        (1 << 3)        /* transmits slot 12 */
  70 #define TXCR_TX2        (1 << 2)        /* transmits slot 12 */
  71 #define TXCR_TX1        (1 << 1)        /* transmits slot 12 */
  72 #define TXCR_TXEN       (1 << 0)        /* transmit enable */
  73
  74 /*
  75  * status register bits. P49
  76  */
  77 #define SR_RXTOFE       (1 << 11)       /* rx timeout fifo empty */
  78 #define SR_TXTO         (1 << 10)       /* rx timeout fifo nonempty */
  79 #define SR_TXU          (1 << 9)        /* tx underrun */
  80 #define SR_RXO          (1 << 8)        /* rx overrun */
  81 #define SR_TXB          (1 << 7)        /* tx busy */
  82 #define SR_RXB          (1 << 6)        /* rx busy */
  83 #define SR_TXFF         (1 << 5)        /* tx fifo full */
  84 #define SR_RXFF         (1 << 4)        /* rx fifo full */
  85 #define SR_TXHE         (1 << 3)        /* tx fifo half empty */
  86 #define SR_RXHF         (1 << 2)        /* rx fifo half full */
  87 #define SR_TXFE         (1 << 1)        /* tx fifo empty */
  88 #define SR_RXFE         (1 << 0)        /* rx fifo empty */
  89
  90 /*
  91  * interrupt status register bits.
  92  */
  93 #define ISR_RXTOFEINTR  (1 << 6)        /* rx fifo empty */
  94 #define ISR_URINTR      (1 << 5)        /* tx underflow */
  95 #define ISR_ORINTR      (1 << 4)        /* rx overflow */
  96 #define ISR_RXINTR      (1 << 3)        /* rx fifo */
  97 #define ISR_TXINTR      (1 << 2)        /* tx fifo intr */
  98 #define ISR_RXTOINTR    (1 << 1)        /* tx timeout */
  99 #define ISR_TXCINTR     (1 << 0)        /* tx complete */
 100
 101 /*
 102  * interrupt enable register bits.
 103  */
 104 #define IE_RXTOIE       (1 << 6)
 105 #define IE_URIE         (1 << 5)
 106 #define IE_ORIE         (1 << 4)
 107 #define IE_RXIE         (1 << 3)
 108 #define IE_TXIE         (1 << 2)
 109 #define IE_RXTIE        (1 << 1)
 110 #define IE_TXCIE        (1 << 0)
 111
 112 /*
 113  * interrupt status. P51
 114  */
 115 #define ISR_RXTOFE      (1 << 6)        /* rx timeout fifo empty */
 116 #define ISR_UR          (1 << 5)        /* tx fifo underrun */
 117 #define ISR_OR          (1 << 4)        /* rx fifo overrun */
 118 #define ISR_RX          (1 << 3)        /* rx interrupt status */
 119 #define ISR_TX          (1 << 2)        /* tx interrupt status */
 120 #define ISR_RXTO        (1 << 1)        /* rx timeout */
 121 #define ISR_TXC         (1 << 0)        /* tx complete */
 122
 123 /*
 124  * interrupt enable. P52
 125  */
 126 #define IE_RXTOFE       (1 << 6)        /* rx timeout fifo empty */
 127 #define IE_UR           (1 << 5)        /* tx fifo underrun */
 128 #define IE_OR           (1 << 4)        /* rx fifo overrun */
 129 #define IE_RX           (1 << 3)        /* rx interrupt status */
 130 #define IE_TX           (1 << 2)        /* tx interrupt status */
 131 #define IE_RXTO         (1 << 1)        /* rx timeout */
 132 #define IE_TXC          (1 << 0)        /* tx complete */
 133
 134 /*
 135  * slot flag register bits. P56
 136  */
 137 #define SLFR_RWIS       (1 << 13)       /* raw wake-up interrupt status */
 138 #define SLFR_RGPIOINTR  (1 << 12)       /* raw gpio interrupt */
 139 #define SLFR_12TXE      (1 << 11)       /* slot 12 tx empty */
 140 #define SLFR_12RXV      (1 << 10)       /* slot 12 rx valid */
 141 #define SLFR_2TXE       (1 << 9)        /* slot 2 tx empty */
 142 #define SLFR_2RXV       (1 << 8)        /* slot 2 rx valid */
 143 #define SLFR_1TXE       (1 << 7)        /* slot 1 tx empty */
 144 #define SLFR_1RXV       (1 << 6)        /* slot 1 rx valid */
 145 #define SLFR_12TXB      (1 << 5)        /* slot 12 tx busy */
 146 #define SLFR_12RXB      (1 << 4)        /* slot 12 rx busy */
 147 #define SLFR_2TXB       (1 << 3)        /* slot 2 tx busy */
 148 #define SLFR_2RXB       (1 << 2)        /* slot 2 rx busy */
 149 #define SLFR_1TXB       (1 << 1)        /* slot 1 tx busy */
 150 #define SLFR_1RXB       (1 << 0)        /* slot 1 rx busy */
 151
 152 /*
 153  * Interrupt clear register.
 154  */
 155 #define ICLR_RXTOFEC4   (1 << 12)
 156 #define ICLR_RXTOFEC3   (1 << 11)
 157 #define ICLR_RXTOFEC2   (1 << 10)
 158 #define ICLR_RXTOFEC1   (1 << 9)
 159 #define ICLR_TXUEC4     (1 << 8)
 160 #define ICLR_TXUEC3     (1 << 7)
 161 #define ICLR_TXUEC2     (1 << 6)
 162 #define ICLR_TXUEC1     (1 << 5)
 163 #define ICLR_RXOEC4     (1 << 4)
 164 #define ICLR_RXOEC3     (1 << 3)
 165 #define ICLR_RXOEC2     (1 << 2)
 166 #define ICLR_RXOEC1     (1 << 1)
 167 #define ICLR_WISC       (1 << 0)
 168
 169 /*
 170  * Main control register bits. P62
 171  */
 172 #define MAINCR_SCRA(x)  ((x) << 10)     /* secondary codec reg access */
 173 #define MAINCR_DMAEN    (1 << 9)        /* dma enable */
 174 #define MAINCR_SL12TXEN (1 << 8)        /* slot 12 transmit enable */
 175 #define MAINCR_SL12RXEN (1 << 7)        /* slot 12 receive enable */
 176 #define MAINCR_SL2TXEN  (1 << 6)        /* slot 2 transmit enable */
 177 #define MAINCR_SL2RXEN  (1 << 5)        /* slot 2 receive enable */
 178 #define MAINCR_SL1TXEN  (1 << 4)        /* slot 1 transmit enable */
 179 #define MAINCR_SL1RXEN  (1 << 3)        /* slot 1 receive enable */
 180 #define MAINCR_LPM      (1 << 2)        /* low power mode */
 181 #define MAINCR_LOOPBK   (1 << 1)        /* loopback */
 182 #define MAINCR_IE       (1 << 0)        /* aaci interface enable */
 183
 184 /*
 185  * Reset register bits. P65
 186  */
 187 #define RESET_NRST      (1 << 0)
 188
 189 /*
 190  * Sync register bits. P65
 191  */
 192 #define SYNC_FORCE      (1 << 0)
 193
 194 /*
 195  * Main flag register bits. P66
 196  */
 197 #define MAINFR_TXB      (1 << 1)        /* transmit busy */
 198 #define MAINFR_RXB      (1 << 0)        /* receive busy */
 199
 200
 201
 202 struct aaci_runtime {
 203         void                    __iomem *base;
 204         void                    __iomem *fifo;
 205
 206         struct ac97_pcm         *pcm;
 207         int                     pcm_open;
 208
 209         u32                     cr;
 210         struct snd_pcm_substream        *substream;
 211
 212         /*
 213          * PIO support
 214          */
 215         void                    *start;
 216         void                    *end;
 217         void                    *ptr;
 218         int                     bytes;
 219         unsigned int            period;
 220         unsigned int            fifosz;
 221 };
 222
 223 struct aaci {
 224         struct amba_device      *dev;
 225         struct snd_card         *card;
 226         void                    __iomem *base;
 227         unsigned int            fifosize;
 228
 229         /* AC'97 */
 230         struct mutex            ac97_sem;
 231         ac97_bus_t              *ac97_bus;
 232
 233         u32                     maincr;
 234         spinlock_t              lock;
 235
 236         struct aaci_runtime     playback;
 237         struct aaci_runtime     capture;
 238
 239         struct snd_pcm          *pcm;
 240 };
 241
 242 #define ACSTREAM_FRONT          0
 243 #define ACSTREAM_SURROUND       1
 244 #define ACSTREAM_LFE            2
 245
 246 #endif