| blob | cf466ea1dffcb3f867921452b19fb2a4c6dd68c3 |
1 /*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/delay.h>
25 #include <plat/common.h>
26 #include <plat/prcm.h>
27 #include <plat/irqs.h>
28 #include <plat/control.h>
39 #define MAX_MODULE_ENABLE_WAIT 100000
42 u32 control_padconf_sys_nirq;
43 u32 iva2_cm_clksel1;
44 u32 iva2_cm_clksel2;
45 u32 cm_sysconfig;
46 u32 sgx_cm_clksel;
47 u32 dss_cm_clksel;
48 u32 cam_cm_clksel;
49 u32 per_cm_clksel;
50 u32 emu_cm_clksel;
51 u32 emu_cm_clkstctrl;
52 u32 pll_cm_autoidle2;
53 u32 pll_cm_clksel4;
54 u32 pll_cm_clksel5;
55 u32 pll_cm_clken2;
56 u32 cm_polctrl;
57 u32 iva2_cm_fclken;
58 u32 iva2_cm_clken_pll;
59 u32 core_cm_fclken1;
60 u32 core_cm_fclken3;
61 u32 sgx_cm_fclken;
62 u32 wkup_cm_fclken;
63 u32 dss_cm_fclken;
64 u32 cam_cm_fclken;
65 u32 per_cm_fclken;
66 u32 usbhost_cm_fclken;
67 u32 core_cm_iclken1;
68 u32 core_cm_iclken2;
69 u32 core_cm_iclken3;
70 u32 sgx_cm_iclken;
71 u32 wkup_cm_iclken;
72 u32 dss_cm_iclken;
73 u32 cam_cm_iclken;
74 u32 per_cm_iclken;
75 u32 usbhost_cm_iclken;
76 u32 iva2_cm_autiidle2;
77 u32 mpu_cm_autoidle2;
78 u32 iva2_cm_clkstctrl;
79 u32 mpu_cm_clkstctrl;
80 u32 core_cm_clkstctrl;
81 u32 sgx_cm_clkstctrl;
82 u32 dss_cm_clkstctrl;
83 u32 cam_cm_clkstctrl;
84 u32 per_cm_clkstctrl;
85 u32 neon_cm_clkstctrl;
86 u32 usbhost_cm_clkstctrl;
87 u32 core_cm_autoidle1;
88 u32 core_cm_autoidle2;
89 u32 core_cm_autoidle3;
90 u32 wkup_cm_autoidle;
91 u32 dss_cm_autoidle;
92 u32 cam_cm_autoidle;
93 u32 per_cm_autoidle;
94 u32 usbhost_cm_autoidle;
95 u32 sgx_cm_sleepdep;
96 u32 dss_cm_sleepdep;
97 u32 cam_cm_sleepdep;
98 u32 per_cm_sleepdep;
99 u32 usbhost_cm_sleepdep;
100 u32 cm_clkout_ctrl;
101 u32 prm_clkout_ctrl;
102 u32 sgx_pm_wkdep;
103 u32 dss_pm_wkdep;
104 u32 cam_pm_wkdep;
105 u32 per_pm_wkdep;
106 u32 neon_pm_wkdep;
107 u32 usbhost_pm_wkdep;
108 u32 core_pm_mpugrpsel1;
109 u32 iva2_pm_ivagrpsel1;
110 u32 core_pm_mpugrpsel3;
111 u32 core_pm_ivagrpsel3;
112 u32 wkup_pm_mpugrpsel;
113 u32 wkup_pm_ivagrpsel;
114 u32 per_pm_mpugrpsel;
115 u32 per_pm_ivagrpsel;
116 u32 wkup_pm_wken;
117 };
122 {
123 /* XXX This presumably needs modification for 34XX */
125 }
128 /* Resets clock rates and reboots the system. Only called from system.h */
130 {
131 s16 prcm_offs;
137 u32 l;
141 /* Reserve the first word in scratchpad for communicating
142 * with the boot ROM. A pointer to a data structure
143 * describing the boot process can be stored there,
144 * cf. OMAP34xx TRM, Initialization / Software Booting
145 * Configuration. */
151 }
154 {
157 }
161 {
164 }
166 /* Read a register in a PRM module */
168 {
170 }
172 /* Write into a register in a PRM module */
174 {
176 }
178 /* Read-modify-write a register in a PRM module. Caller must lock */
180 {
181 u32 v;
189 }
191 /* Read a register in a CM module */
193 {
195 }
197 /* Write into a register in a CM module */
199 {
201 }
203 /* Read-modify-write a register in a CM module. Caller must lock */
205 {
206 u32 v;
214 }
216 /**
217 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
218 * @reg: physical address of module IDLEST register
219 * @mask: value to mask against to determine if the module is active
220 * @name: name of the clock (for printk)
221 *
222 * Returns 1 if the module indicated readiness in time, or 0 if it
223 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
224 */
226 {
230 /*
231 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
232 * 34xx reverses this, just to keep us on our toes
233 */
238 else
241 /* Wait for lock */
248 else
253 };
256 {
260 }
262 #ifdef CONFIG_ARCH_OMAP3
264 {
296 OMAP3430_CM_CLKEN_PLL);
380 OMAP3_CM_CLKOUT_CTRL_OFFSET);
382 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
413 }
416 {
418 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
420 CM_CLKSEL1);
422 CM_CLKSEL2);
425 CM_CLKSEL);
427 CM_CLKSEL);
429 CM_CLKSEL);
431 CM_CLKSEL);
433 CM_CLKSEL1);
435 CM_CLKSTCTRL);
437 CM_AUTOIDLE2);
439 OMAP3430ES2_CM_CLKSEL4);
441 OMAP3430ES2_CM_CLKSEL5);
443 OMAP3430ES2_CM_CLKEN2);
446 CM_FCLKEN);
448 OMAP3430_CM_CLKEN_PLL);
451 OMAP3430ES2_CM_FCLKEN3);
453 CM_FCLKEN);
456 CM_FCLKEN);
458 CM_FCLKEN);
460 CM_FCLKEN);
467 CM_ICLKEN);
470 CM_ICLKEN);
472 CM_ICLKEN);
474 CM_ICLKEN);
478 CM_AUTOIDLE2);
481 CM_CLKSTCTRL);
484 CM_CLKSTCTRL);
486 CM_CLKSTCTRL);
488 CM_CLKSTCTRL);
490 CM_CLKSTCTRL);
492 CM_CLKSTCTRL);
494 CM_CLKSTCTRL);
498 CM_AUTOIDLE1);
500 CM_AUTOIDLE2);
502 CM_AUTOIDLE3);
505 CM_AUTOIDLE);
507 CM_AUTOIDLE);
509 CM_AUTOIDLE);
513 OMAP3430_CM_SLEEPDEP);
515 OMAP3430_CM_SLEEPDEP);
517 OMAP3430_CM_SLEEPDEP);
519 OMAP3430_CM_SLEEPDEP);
523 OMAP3_CM_CLKOUT_CTRL_OFFSET);
525 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
527 PM_WKDEP);
529 PM_WKDEP);
531 PM_WKDEP);
533 PM_WKDEP);
535 PM_WKDEP);
539 OMAP3430_PM_MPUGRPSEL1);
541 OMAP3430_PM_IVAGRPSEL1);
543 OMAP3430ES2_PM_MPUGRPSEL3);
545 OMAP3430ES2_PM_IVAGRPSEL3);
547 OMAP3430_PM_MPUGRPSEL);
549 OMAP3430_PM_IVAGRPSEL);
551 OMAP3430_PM_MPUGRPSEL);
553 OMAP3430_PM_IVAGRPSEL);
556 }
557 #endif