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drm/radeon/kms/atom: fix typo in LVDS panel info parsing
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
bloba4813c6e8df6a16cc3db8105d33b920b81a83771
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id);
51
52 /* from radeon_legacy_encoder.c */
53 extern void
54 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
55 uint32_t supported_device);
56
57 union atom_supported_devices {
58 struct _ATOM_SUPPORTED_DEVICES_INFO info;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
61 };
62
63 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
64 *dev, uint8_t id)
65 {
66 struct radeon_device *rdev = dev->dev_private;
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset;
73
74 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
75 i2c.valid = false;
76
77 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
78
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
81 gpio = i2c_info->asGPIO_Info[id];
82
83 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
84 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
85 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
86 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
87 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
88 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
89 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
90 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
91 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
92 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
93 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
94 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
95 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
96 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
97 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
98 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
99 i2c.valid = true;
100
101 return i2c;
102 }
103
104 static bool radeon_atom_apply_quirks(struct drm_device *dev,
105 uint32_t supported_device,
106 int *connector_type,
107 struct radeon_i2c_bus_rec *i2c_bus,
108 uint16_t *line_mux)
109 {
110
111 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
112 if ((dev->pdev->device == 0x791e) &&
113 (dev->pdev->subsystem_vendor == 0x1043) &&
114 (dev->pdev->subsystem_device == 0x826d)) {
115 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
116 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
117 *connector_type = DRM_MODE_CONNECTOR_DVID;
118 }
119
120 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
121 if ((dev->pdev->device == 0x7941) &&
122 (dev->pdev->subsystem_vendor == 0x147b) &&
123 (dev->pdev->subsystem_device == 0x2412)) {
124 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
125 return false;
126 }
127
128 /* Falcon NW laptop lists vga ddc line for LVDS */
129 if ((dev->pdev->device == 0x5653) &&
130 (dev->pdev->subsystem_vendor == 0x1462) &&
131 (dev->pdev->subsystem_device == 0x0291)) {
132 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
133 i2c_bus->valid = false;
134 *line_mux = 53;
135 }
136 }
137
138 /* HIS X1300 is DVI+VGA, not DVI+DVI */
139 if ((dev->pdev->device == 0x7146) &&
140 (dev->pdev->subsystem_vendor == 0x17af) &&
141 (dev->pdev->subsystem_device == 0x2058)) {
142 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
143 return false;
144 }
145
146 /* Funky macbooks */
147 if ((dev->pdev->device == 0x71C5) &&
148 (dev->pdev->subsystem_vendor == 0x106b) &&
149 (dev->pdev->subsystem_device == 0x0080)) {
150 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
151 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
152 return false;
153 }
154
155 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
156 if ((dev->pdev->device == 0x9598) &&
157 (dev->pdev->subsystem_vendor == 0x1043) &&
158 (dev->pdev->subsystem_device == 0x01da)) {
159 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
160 *connector_type = DRM_MODE_CONNECTOR_DVII;
161 }
162 }
163
164 /* ASUS HD 3450 board lists the DVI port as HDMI */
165 if ((dev->pdev->device == 0x95C5) &&
166 (dev->pdev->subsystem_vendor == 0x1043) &&
167 (dev->pdev->subsystem_device == 0x01e2)) {
168 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
169 *connector_type = DRM_MODE_CONNECTOR_DVII;
170 }
171 }
172
173 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
174 * HDMI + VGA reporting as HDMI
175 */
176 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
177 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
178 *connector_type = DRM_MODE_CONNECTOR_VGA;
179 *line_mux = 0;
180 }
181 }
182
183 return true;
184 }
185
186 const int supported_devices_connector_convert[] = {
187 DRM_MODE_CONNECTOR_Unknown,
188 DRM_MODE_CONNECTOR_VGA,
189 DRM_MODE_CONNECTOR_DVII,
190 DRM_MODE_CONNECTOR_DVID,
191 DRM_MODE_CONNECTOR_DVIA,
192 DRM_MODE_CONNECTOR_SVIDEO,
193 DRM_MODE_CONNECTOR_Composite,
194 DRM_MODE_CONNECTOR_LVDS,
195 DRM_MODE_CONNECTOR_Unknown,
196 DRM_MODE_CONNECTOR_Unknown,
197 DRM_MODE_CONNECTOR_HDMIA,
198 DRM_MODE_CONNECTOR_HDMIB,
199 DRM_MODE_CONNECTOR_Unknown,
200 DRM_MODE_CONNECTOR_Unknown,
201 DRM_MODE_CONNECTOR_9PinDIN,
202 DRM_MODE_CONNECTOR_DisplayPort
203 };
204
205 const uint16_t supported_devices_connector_object_id_convert[] = {
206 CONNECTOR_OBJECT_ID_NONE,
207 CONNECTOR_OBJECT_ID_VGA,
208 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
209 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
210 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
211 CONNECTOR_OBJECT_ID_COMPOSITE,
212 CONNECTOR_OBJECT_ID_SVIDEO,
213 CONNECTOR_OBJECT_ID_LVDS,
214 CONNECTOR_OBJECT_ID_9PIN_DIN,
215 CONNECTOR_OBJECT_ID_9PIN_DIN,
216 CONNECTOR_OBJECT_ID_DISPLAYPORT,
217 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
218 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
219 CONNECTOR_OBJECT_ID_SVIDEO
220 };
221
222 const int object_connector_convert[] = {
223 DRM_MODE_CONNECTOR_Unknown,
224 DRM_MODE_CONNECTOR_DVII,
225 DRM_MODE_CONNECTOR_DVII,
226 DRM_MODE_CONNECTOR_DVID,
227 DRM_MODE_CONNECTOR_DVID,
228 DRM_MODE_CONNECTOR_VGA,
229 DRM_MODE_CONNECTOR_Composite,
230 DRM_MODE_CONNECTOR_SVIDEO,
231 DRM_MODE_CONNECTOR_Unknown,
232 DRM_MODE_CONNECTOR_Unknown,
233 DRM_MODE_CONNECTOR_9PinDIN,
234 DRM_MODE_CONNECTOR_Unknown,
235 DRM_MODE_CONNECTOR_HDMIA,
236 DRM_MODE_CONNECTOR_HDMIB,
237 DRM_MODE_CONNECTOR_LVDS,
238 DRM_MODE_CONNECTOR_9PinDIN,
239 DRM_MODE_CONNECTOR_Unknown,
240 DRM_MODE_CONNECTOR_Unknown,
241 DRM_MODE_CONNECTOR_Unknown,
242 DRM_MODE_CONNECTOR_DisplayPort
243 };
244
245 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
246 {
247 struct radeon_device *rdev = dev->dev_private;
248 struct radeon_mode_info *mode_info = &rdev->mode_info;
249 struct atom_context *ctx = mode_info->atom_context;
250 int index = GetIndexIntoMasterTable(DATA, Object_Header);
251 uint16_t size, data_offset;
252 uint8_t frev, crev, line_mux = 0;
253 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
254 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
255 ATOM_OBJECT_HEADER *obj_header;
256 int i, j, path_size, device_support;
257 int connector_type;
258 uint16_t igp_lane_info, conn_id, connector_object_id;
259 bool linkb;
260 struct radeon_i2c_bus_rec ddc_bus;
261
262 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
263
264 if (data_offset == 0)
265 return false;
266
267 if (crev < 2)
268 return false;
269
270 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
271 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
272 (ctx->bios + data_offset +
273 le16_to_cpu(obj_header->usDisplayPathTableOffset));
274 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
275 (ctx->bios + data_offset +
276 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
277 device_support = le16_to_cpu(obj_header->usDeviceSupport);
278
279 path_size = 0;
280 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
281 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
282 ATOM_DISPLAY_OBJECT_PATH *path;
283 addr += path_size;
284 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
285 path_size += le16_to_cpu(path->usSize);
286 linkb = false;
287
288 if (device_support & le16_to_cpu(path->usDeviceTag)) {
289 uint8_t con_obj_id, con_obj_num, con_obj_type;
290
291 con_obj_id =
292 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
293 >> OBJECT_ID_SHIFT;
294 con_obj_num =
295 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
296 >> ENUM_ID_SHIFT;
297 con_obj_type =
298 (le16_to_cpu(path->usConnObjectId) &
299 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
300
301 /* TODO CV support */
302 if (le16_to_cpu(path->usDeviceTag) ==
303 ATOM_DEVICE_CV_SUPPORT)
304 continue;
305
306 /* IGP chips */
307 if ((rdev->flags & RADEON_IS_IGP) &&
308 (con_obj_id ==
309 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
310 uint16_t igp_offset = 0;
311 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
312
313 index =
314 GetIndexIntoMasterTable(DATA,
315 IntegratedSystemInfo);
316
317 atom_parse_data_header(ctx, index, &size, &frev,
318 &crev, &igp_offset);
319
320 if (crev >= 2) {
321 igp_obj =
322 (ATOM_INTEGRATED_SYSTEM_INFO_V2
323 *) (ctx->bios + igp_offset);
324
325 if (igp_obj) {
326 uint32_t slot_config, ct;
327
328 if (con_obj_num == 1)
329 slot_config =
330 igp_obj->
331 ulDDISlot1Config;
332 else
333 slot_config =
334 igp_obj->
335 ulDDISlot2Config;
336
337 ct = (slot_config >> 16) & 0xff;
338 connector_type =
339 object_connector_convert
340 [ct];
341 connector_object_id = ct;
342 igp_lane_info =
343 slot_config & 0xffff;
344 } else
345 continue;
346 } else
347 continue;
348 } else {
349 igp_lane_info = 0;
350 connector_type =
351 object_connector_convert[con_obj_id];
352 connector_object_id = con_obj_id;
353 }
354
355 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
356 continue;
357
358 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
359 j++) {
360 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
361
362 enc_obj_id =
363 (le16_to_cpu(path->usGraphicObjIds[j]) &
364 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
365 enc_obj_num =
366 (le16_to_cpu(path->usGraphicObjIds[j]) &
367 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
368 enc_obj_type =
369 (le16_to_cpu(path->usGraphicObjIds[j]) &
370 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
371
372 /* FIXME: add support for router objects */
373 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
374 if (enc_obj_num == 2)
375 linkb = true;
376 else
377 linkb = false;
378
379 radeon_add_atom_encoder(dev,
380 enc_obj_id,
381 le16_to_cpu
382 (path->
383 usDeviceTag));
384
385 }
386 }
387
388 /* look up gpio for ddc */
389 if ((le16_to_cpu(path->usDeviceTag) &
390 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
391 == 0) {
392 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
393 if (le16_to_cpu(path->usConnObjectId) ==
394 le16_to_cpu(con_obj->asObjects[j].
395 usObjectID)) {
396 ATOM_COMMON_RECORD_HEADER
397 *record =
398 (ATOM_COMMON_RECORD_HEADER
399 *)
400 (ctx->bios + data_offset +
401 le16_to_cpu(con_obj->
402 asObjects[j].
403 usRecordOffset));
404 ATOM_I2C_RECORD *i2c_record;
405
406 while (record->ucRecordType > 0
407 && record->
408 ucRecordType <=
409 ATOM_MAX_OBJECT_RECORD_NUMBER) {
410 switch (record->
411 ucRecordType) {
412 case ATOM_I2C_RECORD_TYPE:
413 i2c_record =
414 (ATOM_I2C_RECORD
415 *) record;
416 line_mux =
417 i2c_record->
418 sucI2cId.
419 bfI2C_LineMux;
420 break;
421 }
422 record =
423 (ATOM_COMMON_RECORD_HEADER
424 *) ((char *)record
425 +
426 record->
427 ucRecordSize);
428 }
429 break;
430 }
431 }
432 } else
433 line_mux = 0;
434
435 if ((le16_to_cpu(path->usDeviceTag) ==
436 ATOM_DEVICE_TV1_SUPPORT)
437 || (le16_to_cpu(path->usDeviceTag) ==
438 ATOM_DEVICE_TV2_SUPPORT)
439 || (le16_to_cpu(path->usDeviceTag) ==
440 ATOM_DEVICE_CV_SUPPORT))
441 ddc_bus.valid = false;
442 else
443 ddc_bus = radeon_lookup_gpio(dev, line_mux);
444
445 conn_id = le16_to_cpu(path->usConnObjectId);
446
447 if (!radeon_atom_apply_quirks
448 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
449 &ddc_bus, &conn_id))
450 continue;
451
452 radeon_add_atom_connector(dev,
453 conn_id,
454 le16_to_cpu(path->
455 usDeviceTag),
456 connector_type, &ddc_bus,
457 linkb, igp_lane_info,
458 connector_object_id);
459
460 }
461 }
462
463 radeon_link_encoder_connector(dev);
464
465 return true;
466 }
467
468 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
469 int connector_type,
470 uint16_t devices)
471 {
472 struct radeon_device *rdev = dev->dev_private;
473
474 if (rdev->flags & RADEON_IS_IGP) {
475 return supported_devices_connector_object_id_convert
476 [connector_type];
477 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
478 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
479 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
480 struct radeon_mode_info *mode_info = &rdev->mode_info;
481 struct atom_context *ctx = mode_info->atom_context;
482 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
483 uint16_t size, data_offset;
484 uint8_t frev, crev;
485 ATOM_XTMDS_INFO *xtmds;
486
487 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
488 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
489
490 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
491 if (connector_type == DRM_MODE_CONNECTOR_DVII)
492 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
493 else
494 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
495 } else {
496 if (connector_type == DRM_MODE_CONNECTOR_DVII)
497 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
498 else
499 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
500 }
501 } else {
502 return supported_devices_connector_object_id_convert
503 [connector_type];
504 }
505 }
506
507 struct bios_connector {
508 bool valid;
509 uint16_t line_mux;
510 uint16_t devices;
511 int connector_type;
512 struct radeon_i2c_bus_rec ddc_bus;
513 };
514
515 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
516 drm_device
517 *dev)
518 {
519 struct radeon_device *rdev = dev->dev_private;
520 struct radeon_mode_info *mode_info = &rdev->mode_info;
521 struct atom_context *ctx = mode_info->atom_context;
522 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
523 uint16_t size, data_offset;
524 uint8_t frev, crev;
525 uint16_t device_support;
526 uint8_t dac;
527 union atom_supported_devices *supported_devices;
528 int i, j;
529 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
530
531 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
532
533 supported_devices =
534 (union atom_supported_devices *)(ctx->bios + data_offset);
535
536 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
537
538 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
539 ATOM_CONNECTOR_INFO_I2C ci =
540 supported_devices->info.asConnInfo[i];
541
542 bios_connectors[i].valid = false;
543
544 if (!(device_support & (1 << i))) {
545 continue;
546 }
547
548 if (i == ATOM_DEVICE_CV_INDEX) {
549 DRM_DEBUG("Skipping Component Video\n");
550 continue;
551 }
552
553 bios_connectors[i].connector_type =
554 supported_devices_connector_convert[ci.sucConnectorInfo.
555 sbfAccess.
556 bfConnectorType];
557
558 if (bios_connectors[i].connector_type ==
559 DRM_MODE_CONNECTOR_Unknown)
560 continue;
561
562 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
563
564 if ((rdev->family == CHIP_RS690) ||
565 (rdev->family == CHIP_RS740)) {
566 if ((i == ATOM_DEVICE_DFP2_INDEX)
567 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
568 bios_connectors[i].line_mux =
569 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
570 else if ((i == ATOM_DEVICE_DFP3_INDEX)
571 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
572 bios_connectors[i].line_mux =
573 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
574 else
575 bios_connectors[i].line_mux =
576 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
577 } else
578 bios_connectors[i].line_mux =
579 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
580
581 /* give tv unique connector ids */
582 if (i == ATOM_DEVICE_TV1_INDEX) {
583 bios_connectors[i].ddc_bus.valid = false;
584 bios_connectors[i].line_mux = 50;
585 } else if (i == ATOM_DEVICE_TV2_INDEX) {
586 bios_connectors[i].ddc_bus.valid = false;
587 bios_connectors[i].line_mux = 51;
588 } else if (i == ATOM_DEVICE_CV_INDEX) {
589 bios_connectors[i].ddc_bus.valid = false;
590 bios_connectors[i].line_mux = 52;
591 } else
592 bios_connectors[i].ddc_bus =
593 radeon_lookup_gpio(dev,
594 bios_connectors[i].line_mux);
595
596 /* Always set the connector type to VGA for CRT1/CRT2. if they are
597 * shared with a DVI port, we'll pick up the DVI connector when we
598 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
599 */
600 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
601 bios_connectors[i].connector_type =
602 DRM_MODE_CONNECTOR_VGA;
603
604 if (!radeon_atom_apply_quirks
605 (dev, (1 << i), &bios_connectors[i].connector_type,
606 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
607 continue;
608
609 bios_connectors[i].valid = true;
610 bios_connectors[i].devices = (1 << i);
611
612 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
613 radeon_add_atom_encoder(dev,
614 radeon_get_encoder_id(dev,
615 (1 << i),
616 dac),
617 (1 << i));
618 else
619 radeon_add_legacy_encoder(dev,
620 radeon_get_encoder_id(dev,
621 (1 <<
622 i),
623 dac),
624 (1 << i));
625 }
626
627 /* combine shared connectors */
628 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
629 if (bios_connectors[i].valid) {
630 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
631 if (bios_connectors[j].valid && (i != j)) {
632 if (bios_connectors[i].line_mux ==
633 bios_connectors[j].line_mux) {
634 if (((bios_connectors[i].
635 devices &
636 (ATOM_DEVICE_DFP_SUPPORT))
637 && (bios_connectors[j].
638 devices &
639 (ATOM_DEVICE_CRT_SUPPORT)))
640 ||
641 ((bios_connectors[j].
642 devices &
643 (ATOM_DEVICE_DFP_SUPPORT))
644 && (bios_connectors[i].
645 devices &
646 (ATOM_DEVICE_CRT_SUPPORT)))) {
647 bios_connectors[i].
648 devices |=
649 bios_connectors[j].
650 devices;
651 bios_connectors[i].
652 connector_type =
653 DRM_MODE_CONNECTOR_DVII;
654 bios_connectors[j].
655 valid = false;
656 }
657 }
658 }
659 }
660 }
661 }
662
663 /* add the connectors */
664 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
665 if (bios_connectors[i].valid) {
666 uint16_t connector_object_id =
667 atombios_get_connector_object_id(dev,
668 bios_connectors[i].connector_type,
669 bios_connectors[i].devices);
670 radeon_add_atom_connector(dev,
671 bios_connectors[i].line_mux,
672 bios_connectors[i].devices,
673 bios_connectors[i].
674 connector_type,
675 &bios_connectors[i].ddc_bus,
676 false, 0,
677 connector_object_id);
678 }
679 }
680
681 radeon_link_encoder_connector(dev);
682
683 return true;
684 }
685
686 union firmware_info {
687 ATOM_FIRMWARE_INFO info;
688 ATOM_FIRMWARE_INFO_V1_2 info_12;
689 ATOM_FIRMWARE_INFO_V1_3 info_13;
690 ATOM_FIRMWARE_INFO_V1_4 info_14;
691 };
692
693 bool radeon_atom_get_clock_info(struct drm_device *dev)
694 {
695 struct radeon_device *rdev = dev->dev_private;
696 struct radeon_mode_info *mode_info = &rdev->mode_info;
697 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
698 union firmware_info *firmware_info;
699 uint8_t frev, crev;
700 struct radeon_pll *p1pll = &rdev->clock.p1pll;
701 struct radeon_pll *p2pll = &rdev->clock.p2pll;
702 struct radeon_pll *spll = &rdev->clock.spll;
703 struct radeon_pll *mpll = &rdev->clock.mpll;
704 uint16_t data_offset;
705
706 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
707 &crev, &data_offset);
708
709 firmware_info =
710 (union firmware_info *)(mode_info->atom_context->bios +
711 data_offset);
712
713 if (firmware_info) {
714 /* pixel clocks */
715 p1pll->reference_freq =
716 le16_to_cpu(firmware_info->info.usReferenceClock);
717 p1pll->reference_div = 0;
718
719 if (crev < 2)
720 p1pll->pll_out_min =
721 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
722 else
723 p1pll->pll_out_min =
724 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
725 p1pll->pll_out_max =
726 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
727
728 if (p1pll->pll_out_min == 0) {
729 if (ASIC_IS_AVIVO(rdev))
730 p1pll->pll_out_min = 64800;
731 else
732 p1pll->pll_out_min = 20000;
733 } else if (p1pll->pll_out_min > 64800) {
734 /* Limiting the pll output range is a good thing generally as
735 * it limits the number of possible pll combinations for a given
736 * frequency presumably to the ones that work best on each card.
737 * However, certain duallink DVI monitors seem to like
738 * pll combinations that would be limited by this at least on
739 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
740 * family.
741 */
742 p1pll->pll_out_min = 64800;
743 }
744
745 p1pll->pll_in_min =
746 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
747 p1pll->pll_in_max =
748 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
749
750 *p2pll = *p1pll;
751
752 /* system clock */
753 spll->reference_freq =
754 le16_to_cpu(firmware_info->info.usReferenceClock);
755 spll->reference_div = 0;
756
757 spll->pll_out_min =
758 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
759 spll->pll_out_max =
760 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
761
762 /* ??? */
763 if (spll->pll_out_min == 0) {
764 if (ASIC_IS_AVIVO(rdev))
765 spll->pll_out_min = 64800;
766 else
767 spll->pll_out_min = 20000;
768 }
769
770 spll->pll_in_min =
771 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
772 spll->pll_in_max =
773 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
774
775 /* memory clock */
776 mpll->reference_freq =
777 le16_to_cpu(firmware_info->info.usReferenceClock);
778 mpll->reference_div = 0;
779
780 mpll->pll_out_min =
781 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
782 mpll->pll_out_max =
783 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
784
785 /* ??? */
786 if (mpll->pll_out_min == 0) {
787 if (ASIC_IS_AVIVO(rdev))
788 mpll->pll_out_min = 64800;
789 else
790 mpll->pll_out_min = 20000;
791 }
792
793 mpll->pll_in_min =
794 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
795 mpll->pll_in_max =
796 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
797
798 rdev->clock.default_sclk =
799 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
800 rdev->clock.default_mclk =
801 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
802
803 return true;
804 }
805 return false;
806 }
807
808 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
809 struct radeon_encoder_int_tmds *tmds)
810 {
811 struct drm_device *dev = encoder->base.dev;
812 struct radeon_device *rdev = dev->dev_private;
813 struct radeon_mode_info *mode_info = &rdev->mode_info;
814 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
815 uint16_t data_offset;
816 struct _ATOM_TMDS_INFO *tmds_info;
817 uint8_t frev, crev;
818 uint16_t maxfreq;
819 int i;
820
821 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
822 &crev, &data_offset);
823
824 tmds_info =
825 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
826 data_offset);
827
828 if (tmds_info) {
829 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
830 for (i = 0; i < 4; i++) {
831 tmds->tmds_pll[i].freq =
832 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
833 tmds->tmds_pll[i].value =
834 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
835 tmds->tmds_pll[i].value |=
836 (tmds_info->asMiscInfo[i].
837 ucPLL_VCO_Gain & 0x3f) << 6;
838 tmds->tmds_pll[i].value |=
839 (tmds_info->asMiscInfo[i].
840 ucPLL_DutyCycle & 0xf) << 12;
841 tmds->tmds_pll[i].value |=
842 (tmds_info->asMiscInfo[i].
843 ucPLL_VoltageSwing & 0xf) << 16;
844
845 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
846 tmds->tmds_pll[i].freq,
847 tmds->tmds_pll[i].value);
848
849 if (maxfreq == tmds->tmds_pll[i].freq) {
850 tmds->tmds_pll[i].freq = 0xffffffff;
851 break;
852 }
853 }
854 return true;
855 }
856 return false;
857 }
858
859 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
860 radeon_encoder
861 *encoder,
862 int id)
863 {
864 struct drm_device *dev = encoder->base.dev;
865 struct radeon_device *rdev = dev->dev_private;
866 struct radeon_mode_info *mode_info = &rdev->mode_info;
867 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
868 uint16_t data_offset;
869 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
870 uint8_t frev, crev;
871 struct radeon_atom_ss *ss = NULL;
872
873 if (id > ATOM_MAX_SS_ENTRY)
874 return NULL;
875
876 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
877 &crev, &data_offset);
878
879 ss_info =
880 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
881
882 if (ss_info) {
883 ss =
884 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
885
886 if (!ss)
887 return NULL;
888
889 ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage);
890 ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType;
891 ss->step = ss_info->asSS_Info[id].ucSS_Step;
892 ss->delay = ss_info->asSS_Info[id].ucSS_Delay;
893 ss->range = ss_info->asSS_Info[id].ucSS_Range;
894 ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div;
895 }
896 return ss;
897 }
898
899 union lvds_info {
900 struct _ATOM_LVDS_INFO info;
901 struct _ATOM_LVDS_INFO_V12 info_12;
902 };
903
904 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
905 radeon_encoder
906 *encoder)
907 {
908 struct drm_device *dev = encoder->base.dev;
909 struct radeon_device *rdev = dev->dev_private;
910 struct radeon_mode_info *mode_info = &rdev->mode_info;
911 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
912 uint16_t data_offset;
913 union lvds_info *lvds_info;
914 uint8_t frev, crev;
915 struct radeon_encoder_atom_dig *lvds = NULL;
916
917 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
918 &crev, &data_offset);
919
920 lvds_info =
921 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
922
923 if (lvds_info) {
924 lvds =
925 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
926
927 if (!lvds)
928 return NULL;
929
930 lvds->native_mode.clock =
931 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
932 lvds->native_mode.hdisplay =
933 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
934 lvds->native_mode.vdisplay =
935 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
936 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
937 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
938 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
939 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
940 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
941 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
942 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
943 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
944 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
945 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
946 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
947 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
948 lvds->panel_pwr_delay =
949 le16_to_cpu(lvds_info->info.usOffDelayInMs);
950 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
951 /* set crtc values */
952 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
953
954 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
955
956 encoder->native_mode = lvds->native_mode;
957 }
958 return lvds;
959 }
960
961 struct radeon_encoder_primary_dac *
962 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
963 {
964 struct drm_device *dev = encoder->base.dev;
965 struct radeon_device *rdev = dev->dev_private;
966 struct radeon_mode_info *mode_info = &rdev->mode_info;
967 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
968 uint16_t data_offset;
969 struct _COMPASSIONATE_DATA *dac_info;
970 uint8_t frev, crev;
971 uint8_t bg, dac;
972 struct radeon_encoder_primary_dac *p_dac = NULL;
973
974 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
975
976 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
977
978 if (dac_info) {
979 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
980
981 if (!p_dac)
982 return NULL;
983
984 bg = dac_info->ucDAC1_BG_Adjustment;
985 dac = dac_info->ucDAC1_DAC_Adjustment;
986 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
987
988 }
989 return p_dac;
990 }
991
992 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
993 struct drm_display_mode *mode)
994 {
995 struct radeon_mode_info *mode_info = &rdev->mode_info;
996 ATOM_ANALOG_TV_INFO *tv_info;
997 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
998 ATOM_DTD_FORMAT *dtd_timings;
999 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1000 u8 frev, crev;
1001 u16 data_offset, misc;
1002
1003 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1004
1005 switch (crev) {
1006 case 1:
1007 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1008 if (index > MAX_SUPPORTED_TV_TIMING)
1009 return false;
1010
1011 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1012 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1013 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1014 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1015 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1016
1017 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1018 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1019 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1020 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1021 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1022
1023 mode->flags = 0;
1024 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1025 if (misc & ATOM_VSYNC_POLARITY)
1026 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1027 if (misc & ATOM_HSYNC_POLARITY)
1028 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1029 if (misc & ATOM_COMPOSITESYNC)
1030 mode->flags |= DRM_MODE_FLAG_CSYNC;
1031 if (misc & ATOM_INTERLACE)
1032 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1033 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1034 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1035
1036 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1037
1038 if (index == 1) {
1039 /* PAL timings appear to have wrong values for totals */
1040 mode->crtc_htotal -= 1;
1041 mode->crtc_vtotal -= 1;
1042 }
1043 break;
1044 case 2:
1045 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1046 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1047 return false;
1048
1049 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1050 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1051 le16_to_cpu(dtd_timings->usHBlanking_Time);
1052 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1053 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1054 le16_to_cpu(dtd_timings->usHSyncOffset);
1055 mode->crtc_hsync_end = mode->crtc_hsync_start +
1056 le16_to_cpu(dtd_timings->usHSyncWidth);
1057
1058 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1059 le16_to_cpu(dtd_timings->usVBlanking_Time);
1060 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1061 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1062 le16_to_cpu(dtd_timings->usVSyncOffset);
1063 mode->crtc_vsync_end = mode->crtc_vsync_start +
1064 le16_to_cpu(dtd_timings->usVSyncWidth);
1065
1066 mode->flags = 0;
1067 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1068 if (misc & ATOM_VSYNC_POLARITY)
1069 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1070 if (misc & ATOM_HSYNC_POLARITY)
1071 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1072 if (misc & ATOM_COMPOSITESYNC)
1073 mode->flags |= DRM_MODE_FLAG_CSYNC;
1074 if (misc & ATOM_INTERLACE)
1075 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1076 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1077 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1078
1079 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1080 break;
1081 }
1082 return true;
1083 }
1084
1085 struct radeon_encoder_tv_dac *
1086 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1087 {
1088 struct drm_device *dev = encoder->base.dev;
1089 struct radeon_device *rdev = dev->dev_private;
1090 struct radeon_mode_info *mode_info = &rdev->mode_info;
1091 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1092 uint16_t data_offset;
1093 struct _COMPASSIONATE_DATA *dac_info;
1094 uint8_t frev, crev;
1095 uint8_t bg, dac;
1096 struct radeon_encoder_tv_dac *tv_dac = NULL;
1097
1098 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1099
1100 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1101
1102 if (dac_info) {
1103 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1104
1105 if (!tv_dac)
1106 return NULL;
1107
1108 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1109 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1110 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1111
1112 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1113 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1114 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1115
1116 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1117 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1118 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1119
1120 }
1121 return tv_dac;
1122 }
1123
1124 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1125 {
1126 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1127 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1128
1129 args.ucEnable = enable;
1130
1131 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1132 }
1133
1134 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1135 {
1136 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1137 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1138
1139 args.ucEnable = enable;
1140
1141 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1142 }
1143
1144 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1145 {
1146 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1147 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1148
1149 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1150 return args.ulReturnEngineClock;
1151 }
1152
1153 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1154 {
1155 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1156 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1157
1158 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1159 return args.ulReturnMemoryClock;
1160 }
1161
1162 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1163 uint32_t eng_clock)
1164 {
1165 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1166 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1167
1168 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1169
1170 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1171 }
1172
1173 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1174 uint32_t mem_clock)
1175 {
1176 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1177 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1178
1179 if (rdev->flags & RADEON_IS_IGP)
1180 return;
1181
1182 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1183
1184 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1185 }
1186
1187 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1188 {
1189 struct radeon_device *rdev = dev->dev_private;
1190 uint32_t bios_2_scratch, bios_6_scratch;
1191
1192 if (rdev->family >= CHIP_R600) {
1193 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1194 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1195 } else {
1196 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1197 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1198 }
1199
1200 /* let the bios control the backlight */
1201 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1202
1203 /* tell the bios not to handle mode switching */
1204 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1205
1206 if (rdev->family >= CHIP_R600) {
1207 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1208 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1209 } else {
1210 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1211 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1212 }
1213
1214 }
1215
1216 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1217 {
1218 uint32_t scratch_reg;
1219 int i;
1220
1221 if (rdev->family >= CHIP_R600)
1222 scratch_reg = R600_BIOS_0_SCRATCH;
1223 else
1224 scratch_reg = RADEON_BIOS_0_SCRATCH;
1225
1226 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1227 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1228 }
1229
1230 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1231 {
1232 uint32_t scratch_reg;
1233 int i;
1234
1235 if (rdev->family >= CHIP_R600)
1236 scratch_reg = R600_BIOS_0_SCRATCH;
1237 else
1238 scratch_reg = RADEON_BIOS_0_SCRATCH;
1239
1240 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1241 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1242 }
1243
1244 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1245 {
1246 struct drm_device *dev = encoder->dev;
1247 struct radeon_device *rdev = dev->dev_private;
1248 uint32_t bios_6_scratch;
1249
1250 if (rdev->family >= CHIP_R600)
1251 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1252 else
1253 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1254
1255 if (lock)
1256 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1257 else
1258 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1259
1260 if (rdev->family >= CHIP_R600)
1261 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1262 else
1263 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1264 }
1265
1266 /* at some point we may want to break this out into individual functions */
1267 void
1268 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1269 struct drm_encoder *encoder,
1270 bool connected)
1271 {
1272 struct drm_device *dev = connector->dev;
1273 struct radeon_device *rdev = dev->dev_private;
1274 struct radeon_connector *radeon_connector =
1275 to_radeon_connector(connector);
1276 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1277 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1278
1279 if (rdev->family >= CHIP_R600) {
1280 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1281 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1282 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1283 } else {
1284 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1285 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1286 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1287 }
1288
1289 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1290 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1291 if (connected) {
1292 DRM_DEBUG("TV1 connected\n");
1293 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1294 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1295 } else {
1296 DRM_DEBUG("TV1 disconnected\n");
1297 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1298 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1299 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1300 }
1301 }
1302 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1303 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1304 if (connected) {
1305 DRM_DEBUG("CV connected\n");
1306 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1307 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1308 } else {
1309 DRM_DEBUG("CV disconnected\n");
1310 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1311 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1312 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1313 }
1314 }
1315 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1316 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1317 if (connected) {
1318 DRM_DEBUG("LCD1 connected\n");
1319 bios_0_scratch |= ATOM_S0_LCD1;
1320 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1321 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1322 } else {
1323 DRM_DEBUG("LCD1 disconnected\n");
1324 bios_0_scratch &= ~ATOM_S0_LCD1;
1325 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1326 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1327 }
1328 }
1329 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1330 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1331 if (connected) {
1332 DRM_DEBUG("CRT1 connected\n");
1333 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1334 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1335 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1336 } else {
1337 DRM_DEBUG("CRT1 disconnected\n");
1338 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1339 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1340 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1341 }
1342 }
1343 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1344 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1345 if (connected) {
1346 DRM_DEBUG("CRT2 connected\n");
1347 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1348 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1349 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1350 } else {
1351 DRM_DEBUG("CRT2 disconnected\n");
1352 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1353 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1354 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1355 }
1356 }
1357 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1358 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1359 if (connected) {
1360 DRM_DEBUG("DFP1 connected\n");
1361 bios_0_scratch |= ATOM_S0_DFP1;
1362 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1363 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1364 } else {
1365 DRM_DEBUG("DFP1 disconnected\n");
1366 bios_0_scratch &= ~ATOM_S0_DFP1;
1367 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1368 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1369 }
1370 }
1371 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1372 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1373 if (connected) {
1374 DRM_DEBUG("DFP2 connected\n");
1375 bios_0_scratch |= ATOM_S0_DFP2;
1376 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1377 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1378 } else {
1379 DRM_DEBUG("DFP2 disconnected\n");
1380 bios_0_scratch &= ~ATOM_S0_DFP2;
1381 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1382 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1383 }
1384 }
1385 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1386 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1387 if (connected) {
1388 DRM_DEBUG("DFP3 connected\n");
1389 bios_0_scratch |= ATOM_S0_DFP3;
1390 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1391 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1392 } else {
1393 DRM_DEBUG("DFP3 disconnected\n");
1394 bios_0_scratch &= ~ATOM_S0_DFP3;
1395 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1396 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1397 }
1398 }
1399 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1400 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1401 if (connected) {
1402 DRM_DEBUG("DFP4 connected\n");
1403 bios_0_scratch |= ATOM_S0_DFP4;
1404 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1405 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1406 } else {
1407 DRM_DEBUG("DFP4 disconnected\n");
1408 bios_0_scratch &= ~ATOM_S0_DFP4;
1409 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1410 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1411 }
1412 }
1413 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1414 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1415 if (connected) {
1416 DRM_DEBUG("DFP5 connected\n");
1417 bios_0_scratch |= ATOM_S0_DFP5;
1418 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1419 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1420 } else {
1421 DRM_DEBUG("DFP5 disconnected\n");
1422 bios_0_scratch &= ~ATOM_S0_DFP5;
1423 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1424 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1425 }
1426 }
1427
1428 if (rdev->family >= CHIP_R600) {
1429 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1430 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1431 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1432 } else {
1433 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1434 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1435 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1436 }
1437 }
1438
1439 void
1440 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1441 {
1442 struct drm_device *dev = encoder->dev;
1443 struct radeon_device *rdev = dev->dev_private;
1444 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1445 uint32_t bios_3_scratch;
1446
1447 if (rdev->family >= CHIP_R600)
1448 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1449 else
1450 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1451
1452 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1453 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1454 bios_3_scratch |= (crtc << 18);
1455 }
1456 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1457 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1458 bios_3_scratch |= (crtc << 24);
1459 }
1460 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1461 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1462 bios_3_scratch |= (crtc << 16);
1463 }
1464 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1465 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1466 bios_3_scratch |= (crtc << 20);
1467 }
1468 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1469 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1470 bios_3_scratch |= (crtc << 17);
1471 }
1472 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1473 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1474 bios_3_scratch |= (crtc << 19);
1475 }
1476 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1477 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1478 bios_3_scratch |= (crtc << 23);
1479 }
1480 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1481 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1482 bios_3_scratch |= (crtc << 25);
1483 }
1484
1485 if (rdev->family >= CHIP_R600)
1486 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1487 else
1488 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1489 }
1490
1491 void
1492 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1493 {
1494 struct drm_device *dev = encoder->dev;
1495 struct radeon_device *rdev = dev->dev_private;
1496 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1497 uint32_t bios_2_scratch;
1498
1499 if (rdev->family >= CHIP_R600)
1500 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1501 else
1502 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1503
1504 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1505 if (on)
1506 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1507 else
1508 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1509 }
1510 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1511 if (on)
1512 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1513 else
1514 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1515 }
1516 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1517 if (on)
1518 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1519 else
1520 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1521 }
1522 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1523 if (on)
1524 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1525 else
1526 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1527 }
1528 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1529 if (on)
1530 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1531 else
1532 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1533 }
1534 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1535 if (on)
1536 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1537 else
1538 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1539 }
1540 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1541 if (on)
1542 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1543 else
1544 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1545 }
1546 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1547 if (on)
1548 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1549 else
1550 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1551 }
1552 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1553 if (on)
1554 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1555 else
1556 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1557 }
1558 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1559 if (on)
1560 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1561 else
1562 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1563 }
1564
1565 if (rdev->family >= CHIP_R600)
1566 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1567 else
1568 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1569 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree