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tick-broadcast: Stop active broadcast device when replacing it
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / sata_mv.c
blobcf41126ff426d70c68f42e406e09db1cf5241021
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 /*
29 * sata_mv TODO list:
30 *
31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
42
43 /*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/platform_device.h>
63 #include <linux/ata_platform.h>
64 #include <linux/mbus.h>
65 #include <linux/bitops.h>
66 #include <scsi/scsi_host.h>
67 #include <scsi/scsi_cmnd.h>
68 #include <scsi/scsi_device.h>
69 #include <linux/libata.h>
70
71 #define DRV_NAME "sata_mv"
72 #define DRV_VERSION "1.28"
73
74 /*
75 * module options
76 */
77
78 static int msi;
79 #ifdef CONFIG_PCI
80 module_param(msi, int, S_IRUGO);
81 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
82 #endif
83
84 static int irq_coalescing_io_count;
85 module_param(irq_coalescing_io_count, int, S_IRUGO);
86 MODULE_PARM_DESC(irq_coalescing_io_count,
87 "IRQ coalescing I/O count threshold (0..255)");
88
89 static int irq_coalescing_usecs;
90 module_param(irq_coalescing_usecs, int, S_IRUGO);
91 MODULE_PARM_DESC(irq_coalescing_usecs,
92 "IRQ coalescing time threshold in usecs");
93
94 enum {
95 /* BAR's are enumerated in terms of pci_resource_start() terms */
96 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
97 MV_IO_BAR = 2, /* offset 0x18: IO space */
98 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
99
100 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
101 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
102
103 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
104 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
105 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
106 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
107
108 MV_PCI_REG_BASE = 0,
109
110 /*
111 * Per-chip ("all ports") interrupt coalescing feature.
112 * This is only for GEN_II / GEN_IIE hardware.
113 *
114 * Coalescing defers the interrupt until either the IO_THRESHOLD
115 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
116 */
117 COAL_REG_BASE = 0x18000,
118 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
119 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
120
121 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
122 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
123
124 /*
125 * Registers for the (unused here) transaction coalescing feature:
126 */
127 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
128 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
129
130 SATAHC0_REG_BASE = 0x20000,
131 FLASH_CTL = 0x1046c,
132 GPIO_PORT_CTL = 0x104f0,
133 RESET_CFG = 0x180d8,
134
135 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
136 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
137 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
138 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
139
140 MV_MAX_Q_DEPTH = 32,
141 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
142
143 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
144 * CRPB needs alignment on a 256B boundary. Size == 256B
145 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
146 */
147 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
148 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
149 MV_MAX_SG_CT = 256,
150 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
151
152 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
153 MV_PORT_HC_SHIFT = 2,
154 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
155 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
156 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
157
158 /* Host Flags */
159 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
160
161 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
162 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
163
164 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
165
166 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
167 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
168
169 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
170
171 CRQB_FLAG_READ = (1 << 0),
172 CRQB_TAG_SHIFT = 1,
173 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
174 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
175 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
176 CRQB_CMD_ADDR_SHIFT = 8,
177 CRQB_CMD_CS = (0x2 << 11),
178 CRQB_CMD_LAST = (1 << 15),
179
180 CRPB_FLAG_STATUS_SHIFT = 8,
181 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
182 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
183
184 EPRD_FLAG_END_OF_TBL = (1 << 31),
185
186 /* PCI interface registers */
187
188 MV_PCI_COMMAND = 0xc00,
189 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
190 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
191
192 PCI_MAIN_CMD_STS = 0xd30,
193 STOP_PCI_MASTER = (1 << 2),
194 PCI_MASTER_EMPTY = (1 << 3),
195 GLOB_SFT_RST = (1 << 4),
196
197 MV_PCI_MODE = 0xd00,
198 MV_PCI_MODE_MASK = 0x30,
199
200 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
201 MV_PCI_DISC_TIMER = 0xd04,
202 MV_PCI_MSI_TRIGGER = 0xc38,
203 MV_PCI_SERR_MASK = 0xc28,
204 MV_PCI_XBAR_TMOUT = 0x1d04,
205 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
206 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
207 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
208 MV_PCI_ERR_COMMAND = 0x1d50,
209
210 PCI_IRQ_CAUSE = 0x1d58,
211 PCI_IRQ_MASK = 0x1d5c,
212 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
213
214 PCIE_IRQ_CAUSE = 0x1900,
215 PCIE_IRQ_MASK = 0x1910,
216 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
217
218 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
219 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
220 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
221 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
222 SOC_HC_MAIN_IRQ_MASK = 0x20024,
223 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
224 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
225 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
226 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
227 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
228 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
229 PCI_ERR = (1 << 18),
230 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
231 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
232 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
233 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
234 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
235 GPIO_INT = (1 << 22),
236 SELF_INT = (1 << 23),
237 TWSI_INT = (1 << 24),
238 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
239 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
240 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
241
242 /* SATAHC registers */
243 HC_CFG = 0x00,
244
245 HC_IRQ_CAUSE = 0x14,
246 DMA_IRQ = (1 << 0), /* shift by port # */
247 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
248 DEV_IRQ = (1 << 8), /* shift by port # */
249
250 /*
251 * Per-HC (Host-Controller) interrupt coalescing feature.
252 * This is present on all chip generations.
253 *
254 * Coalescing defers the interrupt until either the IO_THRESHOLD
255 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
256 */
257 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
258 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
259
260 SOC_LED_CTRL = 0x2c,
261 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
262 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
263 /* with dev activity LED */
264
265 /* Shadow block registers */
266 SHD_BLK = 0x100,
267 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
268
269 /* SATA registers */
270 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
271 SATA_ACTIVE = 0x350,
272 FIS_IRQ_CAUSE = 0x364,
273 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
274
275 LTMODE = 0x30c, /* requires read-after-write */
276 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
277
278 PHY_MODE2 = 0x330,
279 PHY_MODE3 = 0x310,
280
281 PHY_MODE4 = 0x314, /* requires read-after-write */
282 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
283 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
284 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
285 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
286
287 SATA_IFCTL = 0x344,
288 SATA_TESTCTL = 0x348,
289 SATA_IFSTAT = 0x34c,
290 VENDOR_UNIQUE_FIS = 0x35c,
291
292 FISCFG = 0x360,
293 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
294 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
295
296 PHY_MODE9_GEN2 = 0x398,
297 PHY_MODE9_GEN1 = 0x39c,
298 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
299
300 MV5_PHY_MODE = 0x74,
301 MV5_LTMODE = 0x30,
302 MV5_PHY_CTL = 0x0C,
303 SATA_IFCFG = 0x050,
304
305 MV_M2_PREAMP_MASK = 0x7e0,
306
307 /* Port registers */
308 EDMA_CFG = 0,
309 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
310 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
311 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
312 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
313 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
314 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
315 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
316
317 EDMA_ERR_IRQ_CAUSE = 0x8,
318 EDMA_ERR_IRQ_MASK = 0xc,
319 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
320 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
321 EDMA_ERR_DEV = (1 << 2), /* device error */
322 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
323 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
324 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
325 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
326 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
327 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
328 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
329 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
330 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
331 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
332 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
333
334 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
335 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
336 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
337 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
338 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
339
340 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
341
342 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
343 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
344 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
345 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
346 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
347 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
348
349 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
350
351 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
352 EDMA_ERR_OVERRUN_5 = (1 << 5),
353 EDMA_ERR_UNDERRUN_5 = (1 << 6),
354
355 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
356 EDMA_ERR_LNK_CTRL_RX_1 |
357 EDMA_ERR_LNK_CTRL_RX_3 |
358 EDMA_ERR_LNK_CTRL_TX,
359
360 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
361 EDMA_ERR_PRD_PAR |
362 EDMA_ERR_DEV_DCON |
363 EDMA_ERR_DEV_CON |
364 EDMA_ERR_SERR |
365 EDMA_ERR_SELF_DIS |
366 EDMA_ERR_CRQB_PAR |
367 EDMA_ERR_CRPB_PAR |
368 EDMA_ERR_INTRL_PAR |
369 EDMA_ERR_IORDY |
370 EDMA_ERR_LNK_CTRL_RX_2 |
371 EDMA_ERR_LNK_DATA_RX |
372 EDMA_ERR_LNK_DATA_TX |
373 EDMA_ERR_TRANS_PROTO,
374
375 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
376 EDMA_ERR_PRD_PAR |
377 EDMA_ERR_DEV_DCON |
378 EDMA_ERR_DEV_CON |
379 EDMA_ERR_OVERRUN_5 |
380 EDMA_ERR_UNDERRUN_5 |
381 EDMA_ERR_SELF_DIS_5 |
382 EDMA_ERR_CRQB_PAR |
383 EDMA_ERR_CRPB_PAR |
384 EDMA_ERR_INTRL_PAR |
385 EDMA_ERR_IORDY,
386
387 EDMA_REQ_Q_BASE_HI = 0x10,
388 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
389
390 EDMA_REQ_Q_OUT_PTR = 0x18,
391 EDMA_REQ_Q_PTR_SHIFT = 5,
392
393 EDMA_RSP_Q_BASE_HI = 0x1c,
394 EDMA_RSP_Q_IN_PTR = 0x20,
395 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
396 EDMA_RSP_Q_PTR_SHIFT = 3,
397
398 EDMA_CMD = 0x28, /* EDMA command register */
399 EDMA_EN = (1 << 0), /* enable EDMA */
400 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
401 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
402
403 EDMA_STATUS = 0x30, /* EDMA engine status */
404 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
405 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
406
407 EDMA_IORDY_TMOUT = 0x34,
408 EDMA_ARB_CFG = 0x38,
409
410 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
411 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
412
413 BMDMA_CMD = 0x224, /* bmdma command register */
414 BMDMA_STATUS = 0x228, /* bmdma status register */
415 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
416 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
417
418 /* Host private flags (hp_flags) */
419 MV_HP_FLAG_MSI = (1 << 0),
420 MV_HP_ERRATA_50XXB0 = (1 << 1),
421 MV_HP_ERRATA_50XXB2 = (1 << 2),
422 MV_HP_ERRATA_60X1B2 = (1 << 3),
423 MV_HP_ERRATA_60X1C0 = (1 << 4),
424 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
425 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
426 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
427 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
428 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
429 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
430 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
431
432 /* Port private flags (pp_flags) */
433 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
434 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
435 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
436 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
437 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
438 };
439
440 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
441 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
442 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
443 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
444 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
445
446 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
447 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
448
449 enum {
450 /* DMA boundary 0xffff is required by the s/g splitting
451 * we need on /length/ in mv_fill-sg().
452 */
453 MV_DMA_BOUNDARY = 0xffffU,
454
455 /* mask of register bits containing lower 32 bits
456 * of EDMA request queue DMA address
457 */
458 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
459
460 /* ditto, for response queue */
461 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
462 };
463
464 enum chip_type {
465 chip_504x,
466 chip_508x,
467 chip_5080,
468 chip_604x,
469 chip_608x,
470 chip_6042,
471 chip_7042,
472 chip_soc,
473 };
474
475 /* Command ReQuest Block: 32B */
476 struct mv_crqb {
477 __le32 sg_addr;
478 __le32 sg_addr_hi;
479 __le16 ctrl_flags;
480 __le16 ata_cmd[11];
481 };
482
483 struct mv_crqb_iie {
484 __le32 addr;
485 __le32 addr_hi;
486 __le32 flags;
487 __le32 len;
488 __le32 ata_cmd[4];
489 };
490
491 /* Command ResPonse Block: 8B */
492 struct mv_crpb {
493 __le16 id;
494 __le16 flags;
495 __le32 tmstmp;
496 };
497
498 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
499 struct mv_sg {
500 __le32 addr;
501 __le32 flags_size;
502 __le32 addr_hi;
503 __le32 reserved;
504 };
505
506 /*
507 * We keep a local cache of a few frequently accessed port
508 * registers here, to avoid having to read them (very slow)
509 * when switching between EDMA and non-EDMA modes.
510 */
511 struct mv_cached_regs {
512 u32 fiscfg;
513 u32 ltmode;
514 u32 haltcond;
515 u32 unknown_rsvd;
516 };
517
518 struct mv_port_priv {
519 struct mv_crqb *crqb;
520 dma_addr_t crqb_dma;
521 struct mv_crpb *crpb;
522 dma_addr_t crpb_dma;
523 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
524 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
525
526 unsigned int req_idx;
527 unsigned int resp_idx;
528
529 u32 pp_flags;
530 struct mv_cached_regs cached;
531 unsigned int delayed_eh_pmp_map;
532 };
533
534 struct mv_port_signal {
535 u32 amps;
536 u32 pre;
537 };
538
539 struct mv_host_priv {
540 u32 hp_flags;
541 u32 main_irq_mask;
542 struct mv_port_signal signal[8];
543 const struct mv_hw_ops *ops;
544 int n_ports;
545 void __iomem *base;
546 void __iomem *main_irq_cause_addr;
547 void __iomem *main_irq_mask_addr;
548 u32 irq_cause_offset;
549 u32 irq_mask_offset;
550 u32 unmask_all_irqs;
551 /*
552 * These consistent DMA memory pools give us guaranteed
553 * alignment for hardware-accessed data structures,
554 * and less memory waste in accomplishing the alignment.
555 */
556 struct dma_pool *crqb_pool;
557 struct dma_pool *crpb_pool;
558 struct dma_pool *sg_tbl_pool;
559 };
560
561 struct mv_hw_ops {
562 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
563 unsigned int port);
564 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
565 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
566 void __iomem *mmio);
567 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
568 unsigned int n_hc);
569 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
570 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
571 };
572
573 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
574 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
575 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
576 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
577 static int mv_port_start(struct ata_port *ap);
578 static void mv_port_stop(struct ata_port *ap);
579 static int mv_qc_defer(struct ata_queued_cmd *qc);
580 static void mv_qc_prep(struct ata_queued_cmd *qc);
581 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
582 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
583 static int mv_hardreset(struct ata_link *link, unsigned int *class,
584 unsigned long deadline);
585 static void mv_eh_freeze(struct ata_port *ap);
586 static void mv_eh_thaw(struct ata_port *ap);
587 static void mv6_dev_config(struct ata_device *dev);
588
589 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
590 unsigned int port);
591 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
592 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
593 void __iomem *mmio);
594 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
595 unsigned int n_hc);
596 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
597 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
598
599 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
600 unsigned int port);
601 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
602 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
603 void __iomem *mmio);
604 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
605 unsigned int n_hc);
606 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
607 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
608 void __iomem *mmio);
609 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
611 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
612 void __iomem *mmio, unsigned int n_hc);
613 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
614 void __iomem *mmio);
615 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
616 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
617 void __iomem *mmio, unsigned int port);
618 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
619 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
620 unsigned int port_no);
621 static int mv_stop_edma(struct ata_port *ap);
622 static int mv_stop_edma_engine(void __iomem *port_mmio);
623 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
624
625 static void mv_pmp_select(struct ata_port *ap, int pmp);
626 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
627 unsigned long deadline);
628 static int mv_softreset(struct ata_link *link, unsigned int *class,
629 unsigned long deadline);
630 static void mv_pmp_error_handler(struct ata_port *ap);
631 static void mv_process_crpb_entries(struct ata_port *ap,
632 struct mv_port_priv *pp);
633
634 static void mv_sff_irq_clear(struct ata_port *ap);
635 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
636 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
637 static void mv_bmdma_start(struct ata_queued_cmd *qc);
638 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
639 static u8 mv_bmdma_status(struct ata_port *ap);
640 static u8 mv_sff_check_status(struct ata_port *ap);
641
642 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
643 * because we have to allow room for worst case splitting of
644 * PRDs for 64K boundaries in mv_fill_sg().
645 */
646 static struct scsi_host_template mv5_sht = {
647 ATA_BASE_SHT(DRV_NAME),
648 .sg_tablesize = MV_MAX_SG_CT / 2,
649 .dma_boundary = MV_DMA_BOUNDARY,
650 };
651
652 static struct scsi_host_template mv6_sht = {
653 ATA_NCQ_SHT(DRV_NAME),
654 .can_queue = MV_MAX_Q_DEPTH - 1,
655 .sg_tablesize = MV_MAX_SG_CT / 2,
656 .dma_boundary = MV_DMA_BOUNDARY,
657 };
658
659 static struct ata_port_operations mv5_ops = {
660 .inherits = &ata_sff_port_ops,
661
662 .lost_interrupt = ATA_OP_NULL,
663
664 .qc_defer = mv_qc_defer,
665 .qc_prep = mv_qc_prep,
666 .qc_issue = mv_qc_issue,
667
668 .freeze = mv_eh_freeze,
669 .thaw = mv_eh_thaw,
670 .hardreset = mv_hardreset,
671 .error_handler = ata_std_error_handler, /* avoid SFF EH */
672 .post_internal_cmd = ATA_OP_NULL,
673
674 .scr_read = mv5_scr_read,
675 .scr_write = mv5_scr_write,
676
677 .port_start = mv_port_start,
678 .port_stop = mv_port_stop,
679 };
680
681 static struct ata_port_operations mv6_ops = {
682 .inherits = &mv5_ops,
683 .dev_config = mv6_dev_config,
684 .scr_read = mv_scr_read,
685 .scr_write = mv_scr_write,
686
687 .pmp_hardreset = mv_pmp_hardreset,
688 .pmp_softreset = mv_softreset,
689 .softreset = mv_softreset,
690 .error_handler = mv_pmp_error_handler,
691
692 .sff_check_status = mv_sff_check_status,
693 .sff_irq_clear = mv_sff_irq_clear,
694 .check_atapi_dma = mv_check_atapi_dma,
695 .bmdma_setup = mv_bmdma_setup,
696 .bmdma_start = mv_bmdma_start,
697 .bmdma_stop = mv_bmdma_stop,
698 .bmdma_status = mv_bmdma_status,
699 };
700
701 static struct ata_port_operations mv_iie_ops = {
702 .inherits = &mv6_ops,
703 .dev_config = ATA_OP_NULL,
704 .qc_prep = mv_qc_prep_iie,
705 };
706
707 static const struct ata_port_info mv_port_info[] = {
708 { /* chip_504x */
709 .flags = MV_GEN_I_FLAGS,
710 .pio_mask = ATA_PIO4,
711 .udma_mask = ATA_UDMA6,
712 .port_ops = &mv5_ops,
713 },
714 { /* chip_508x */
715 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
716 .pio_mask = ATA_PIO4,
717 .udma_mask = ATA_UDMA6,
718 .port_ops = &mv5_ops,
719 },
720 { /* chip_5080 */
721 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
722 .pio_mask = ATA_PIO4,
723 .udma_mask = ATA_UDMA6,
724 .port_ops = &mv5_ops,
725 },
726 { /* chip_604x */
727 .flags = MV_GEN_II_FLAGS,
728 .pio_mask = ATA_PIO4,
729 .udma_mask = ATA_UDMA6,
730 .port_ops = &mv6_ops,
731 },
732 { /* chip_608x */
733 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
734 .pio_mask = ATA_PIO4,
735 .udma_mask = ATA_UDMA6,
736 .port_ops = &mv6_ops,
737 },
738 { /* chip_6042 */
739 .flags = MV_GEN_IIE_FLAGS,
740 .pio_mask = ATA_PIO4,
741 .udma_mask = ATA_UDMA6,
742 .port_ops = &mv_iie_ops,
743 },
744 { /* chip_7042 */
745 .flags = MV_GEN_IIE_FLAGS,
746 .pio_mask = ATA_PIO4,
747 .udma_mask = ATA_UDMA6,
748 .port_ops = &mv_iie_ops,
749 },
750 { /* chip_soc */
751 .flags = MV_GEN_IIE_FLAGS,
752 .pio_mask = ATA_PIO4,
753 .udma_mask = ATA_UDMA6,
754 .port_ops = &mv_iie_ops,
755 },
756 };
757
758 static const struct pci_device_id mv_pci_tbl[] = {
759 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
760 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
761 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
762 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
763 /* RocketRAID 1720/174x have different identifiers */
764 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
765 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
766 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
767
768 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
769 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
770 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
771 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
772 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
773
774 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
775
776 /* Adaptec 1430SA */
777 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
778
779 /* Marvell 7042 support */
780 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
781
782 /* Highpoint RocketRAID PCIe series */
783 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
784 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
785
786 { } /* terminate list */
787 };
788
789 static const struct mv_hw_ops mv5xxx_ops = {
790 .phy_errata = mv5_phy_errata,
791 .enable_leds = mv5_enable_leds,
792 .read_preamp = mv5_read_preamp,
793 .reset_hc = mv5_reset_hc,
794 .reset_flash = mv5_reset_flash,
795 .reset_bus = mv5_reset_bus,
796 };
797
798 static const struct mv_hw_ops mv6xxx_ops = {
799 .phy_errata = mv6_phy_errata,
800 .enable_leds = mv6_enable_leds,
801 .read_preamp = mv6_read_preamp,
802 .reset_hc = mv6_reset_hc,
803 .reset_flash = mv6_reset_flash,
804 .reset_bus = mv_reset_pci_bus,
805 };
806
807 static const struct mv_hw_ops mv_soc_ops = {
808 .phy_errata = mv6_phy_errata,
809 .enable_leds = mv_soc_enable_leds,
810 .read_preamp = mv_soc_read_preamp,
811 .reset_hc = mv_soc_reset_hc,
812 .reset_flash = mv_soc_reset_flash,
813 .reset_bus = mv_soc_reset_bus,
814 };
815
816 static const struct mv_hw_ops mv_soc_65n_ops = {
817 .phy_errata = mv_soc_65n_phy_errata,
818 .enable_leds = mv_soc_enable_leds,
819 .reset_hc = mv_soc_reset_hc,
820 .reset_flash = mv_soc_reset_flash,
821 .reset_bus = mv_soc_reset_bus,
822 };
823
824 /*
825 * Functions
826 */
827
828 static inline void writelfl(unsigned long data, void __iomem *addr)
829 {
830 writel(data, addr);
831 (void) readl(addr); /* flush to avoid PCI posted write */
832 }
833
834 static inline unsigned int mv_hc_from_port(unsigned int port)
835 {
836 return port >> MV_PORT_HC_SHIFT;
837 }
838
839 static inline unsigned int mv_hardport_from_port(unsigned int port)
840 {
841 return port & MV_PORT_MASK;
842 }
843
844 /*
845 * Consolidate some rather tricky bit shift calculations.
846 * This is hot-path stuff, so not a function.
847 * Simple code, with two return values, so macro rather than inline.
848 *
849 * port is the sole input, in range 0..7.
850 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
851 * hardport is the other output, in range 0..3.
852 *
853 * Note that port and hardport may be the same variable in some cases.
854 */
855 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
856 { \
857 shift = mv_hc_from_port(port) * HC_SHIFT; \
858 hardport = mv_hardport_from_port(port); \
859 shift += hardport * 2; \
860 }
861
862 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
863 {
864 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
865 }
866
867 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
868 unsigned int port)
869 {
870 return mv_hc_base(base, mv_hc_from_port(port));
871 }
872
873 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
874 {
875 return mv_hc_base_from_port(base, port) +
876 MV_SATAHC_ARBTR_REG_SZ +
877 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
878 }
879
880 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
881 {
882 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
883 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
884
885 return hc_mmio + ofs;
886 }
887
888 static inline void __iomem *mv_host_base(struct ata_host *host)
889 {
890 struct mv_host_priv *hpriv = host->private_data;
891 return hpriv->base;
892 }
893
894 static inline void __iomem *mv_ap_base(struct ata_port *ap)
895 {
896 return mv_port_base(mv_host_base(ap->host), ap->port_no);
897 }
898
899 static inline int mv_get_hc_count(unsigned long port_flags)
900 {
901 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
902 }
903
904 /**
905 * mv_save_cached_regs - (re-)initialize cached port registers
906 * @ap: the port whose registers we are caching
907 *
908 * Initialize the local cache of port registers,
909 * so that reading them over and over again can
910 * be avoided on the hotter paths of this driver.
911 * This saves a few microseconds each time we switch
912 * to/from EDMA mode to perform (eg.) a drive cache flush.
913 */
914 static void mv_save_cached_regs(struct ata_port *ap)
915 {
916 void __iomem *port_mmio = mv_ap_base(ap);
917 struct mv_port_priv *pp = ap->private_data;
918
919 pp->cached.fiscfg = readl(port_mmio + FISCFG);
920 pp->cached.ltmode = readl(port_mmio + LTMODE);
921 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
922 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
923 }
924
925 /**
926 * mv_write_cached_reg - write to a cached port register
927 * @addr: hardware address of the register
928 * @old: pointer to cached value of the register
929 * @new: new value for the register
930 *
931 * Write a new value to a cached register,
932 * but only if the value is different from before.
933 */
934 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
935 {
936 if (new != *old) {
937 unsigned long laddr;
938 *old = new;
939 /*
940 * Workaround for 88SX60x1-B2 FEr SATA#13:
941 * Read-after-write is needed to prevent generating 64-bit
942 * write cycles on the PCI bus for SATA interface registers
943 * at offsets ending in 0x4 or 0xc.
944 *
945 * Looks like a lot of fuss, but it avoids an unnecessary
946 * +1 usec read-after-write delay for unaffected registers.
947 */
948 laddr = (long)addr & 0xffff;
949 if (laddr >= 0x300 && laddr <= 0x33c) {
950 laddr &= 0x000f;
951 if (laddr == 0x4 || laddr == 0xc) {
952 writelfl(new, addr); /* read after write */
953 return;
954 }
955 }
956 writel(new, addr); /* unaffected by the errata */
957 }
958 }
959
960 static void mv_set_edma_ptrs(void __iomem *port_mmio,
961 struct mv_host_priv *hpriv,
962 struct mv_port_priv *pp)
963 {
964 u32 index;
965
966 /*
967 * initialize request queue
968 */
969 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
970 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
971
972 WARN_ON(pp->crqb_dma & 0x3ff);
973 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
974 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
975 port_mmio + EDMA_REQ_Q_IN_PTR);
976 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
977
978 /*
979 * initialize response queue
980 */
981 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
982 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
983
984 WARN_ON(pp->crpb_dma & 0xff);
985 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
986 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
987 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
988 port_mmio + EDMA_RSP_Q_OUT_PTR);
989 }
990
991 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
992 {
993 /*
994 * When writing to the main_irq_mask in hardware,
995 * we must ensure exclusivity between the interrupt coalescing bits
996 * and the corresponding individual port DONE_IRQ bits.
997 *
998 * Note that this register is really an "IRQ enable" register,
999 * not an "IRQ mask" register as Marvell's naming might suggest.
1000 */
1001 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1002 mask &= ~DONE_IRQ_0_3;
1003 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1004 mask &= ~DONE_IRQ_4_7;
1005 writelfl(mask, hpriv->main_irq_mask_addr);
1006 }
1007
1008 static void mv_set_main_irq_mask(struct ata_host *host,
1009 u32 disable_bits, u32 enable_bits)
1010 {
1011 struct mv_host_priv *hpriv = host->private_data;
1012 u32 old_mask, new_mask;
1013
1014 old_mask = hpriv->main_irq_mask;
1015 new_mask = (old_mask & ~disable_bits) | enable_bits;
1016 if (new_mask != old_mask) {
1017 hpriv->main_irq_mask = new_mask;
1018 mv_write_main_irq_mask(new_mask, hpriv);
1019 }
1020 }
1021
1022 static void mv_enable_port_irqs(struct ata_port *ap,
1023 unsigned int port_bits)
1024 {
1025 unsigned int shift, hardport, port = ap->port_no;
1026 u32 disable_bits, enable_bits;
1027
1028 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1029
1030 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1031 enable_bits = port_bits << shift;
1032 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1033 }
1034
1035 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1036 void __iomem *port_mmio,
1037 unsigned int port_irqs)
1038 {
1039 struct mv_host_priv *hpriv = ap->host->private_data;
1040 int hardport = mv_hardport_from_port(ap->port_no);
1041 void __iomem *hc_mmio = mv_hc_base_from_port(
1042 mv_host_base(ap->host), ap->port_no);
1043 u32 hc_irq_cause;
1044
1045 /* clear EDMA event indicators, if any */
1046 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1047
1048 /* clear pending irq events */
1049 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1050 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1051
1052 /* clear FIS IRQ Cause */
1053 if (IS_GEN_IIE(hpriv))
1054 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1055
1056 mv_enable_port_irqs(ap, port_irqs);
1057 }
1058
1059 static void mv_set_irq_coalescing(struct ata_host *host,
1060 unsigned int count, unsigned int usecs)
1061 {
1062 struct mv_host_priv *hpriv = host->private_data;
1063 void __iomem *mmio = hpriv->base, *hc_mmio;
1064 u32 coal_enable = 0;
1065 unsigned long flags;
1066 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1067 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1068 ALL_PORTS_COAL_DONE;
1069
1070 /* Disable IRQ coalescing if either threshold is zero */
1071 if (!usecs || !count) {
1072 clks = count = 0;
1073 } else {
1074 /* Respect maximum limits of the hardware */
1075 clks = usecs * COAL_CLOCKS_PER_USEC;
1076 if (clks > MAX_COAL_TIME_THRESHOLD)
1077 clks = MAX_COAL_TIME_THRESHOLD;
1078 if (count > MAX_COAL_IO_COUNT)
1079 count = MAX_COAL_IO_COUNT;
1080 }
1081
1082 spin_lock_irqsave(&host->lock, flags);
1083 mv_set_main_irq_mask(host, coal_disable, 0);
1084
1085 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1086 /*
1087 * GEN_II/GEN_IIE with dual host controllers:
1088 * one set of global thresholds for the entire chip.
1089 */
1090 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1091 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1092 /* clear leftover coal IRQ bit */
1093 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1094 if (count)
1095 coal_enable = ALL_PORTS_COAL_DONE;
1096 clks = count = 0; /* force clearing of regular regs below */
1097 }
1098
1099 /*
1100 * All chips: independent thresholds for each HC on the chip.
1101 */
1102 hc_mmio = mv_hc_base_from_port(mmio, 0);
1103 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1104 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1105 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1106 if (count)
1107 coal_enable |= PORTS_0_3_COAL_DONE;
1108 if (is_dual_hc) {
1109 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1110 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1111 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1112 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1113 if (count)
1114 coal_enable |= PORTS_4_7_COAL_DONE;
1115 }
1116
1117 mv_set_main_irq_mask(host, 0, coal_enable);
1118 spin_unlock_irqrestore(&host->lock, flags);
1119 }
1120
1121 /**
1122 * mv_start_edma - Enable eDMA engine
1123 * @base: port base address
1124 * @pp: port private data
1125 *
1126 * Verify the local cache of the eDMA state is accurate with a
1127 * WARN_ON.
1128 *
1129 * LOCKING:
1130 * Inherited from caller.
1131 */
1132 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1133 struct mv_port_priv *pp, u8 protocol)
1134 {
1135 int want_ncq = (protocol == ATA_PROT_NCQ);
1136
1137 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1138 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1139 if (want_ncq != using_ncq)
1140 mv_stop_edma(ap);
1141 }
1142 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1143 struct mv_host_priv *hpriv = ap->host->private_data;
1144
1145 mv_edma_cfg(ap, want_ncq, 1);
1146
1147 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1148 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1149
1150 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1151 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1152 }
1153 }
1154
1155 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1156 {
1157 void __iomem *port_mmio = mv_ap_base(ap);
1158 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1159 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1160 int i;
1161
1162 /*
1163 * Wait for the EDMA engine to finish transactions in progress.
1164 * No idea what a good "timeout" value might be, but measurements
1165 * indicate that it often requires hundreds of microseconds
1166 * with two drives in-use. So we use the 15msec value above
1167 * as a rough guess at what even more drives might require.
1168 */
1169 for (i = 0; i < timeout; ++i) {
1170 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1171 if ((edma_stat & empty_idle) == empty_idle)
1172 break;
1173 udelay(per_loop);
1174 }
1175 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1176 }
1177
1178 /**
1179 * mv_stop_edma_engine - Disable eDMA engine
1180 * @port_mmio: io base address
1181 *
1182 * LOCKING:
1183 * Inherited from caller.
1184 */
1185 static int mv_stop_edma_engine(void __iomem *port_mmio)
1186 {
1187 int i;
1188
1189 /* Disable eDMA. The disable bit auto clears. */
1190 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1191
1192 /* Wait for the chip to confirm eDMA is off. */
1193 for (i = 10000; i > 0; i--) {
1194 u32 reg = readl(port_mmio + EDMA_CMD);
1195 if (!(reg & EDMA_EN))
1196 return 0;
1197 udelay(10);
1198 }
1199 return -EIO;
1200 }
1201
1202 static int mv_stop_edma(struct ata_port *ap)
1203 {
1204 void __iomem *port_mmio = mv_ap_base(ap);
1205 struct mv_port_priv *pp = ap->private_data;
1206 int err = 0;
1207
1208 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1209 return 0;
1210 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1211 mv_wait_for_edma_empty_idle(ap);
1212 if (mv_stop_edma_engine(port_mmio)) {
1213 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1214 err = -EIO;
1215 }
1216 mv_edma_cfg(ap, 0, 0);
1217 return err;
1218 }
1219
1220 #ifdef ATA_DEBUG
1221 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1222 {
1223 int b, w;
1224 for (b = 0; b < bytes; ) {
1225 DPRINTK("%p: ", start + b);
1226 for (w = 0; b < bytes && w < 4; w++) {
1227 printk("%08x ", readl(start + b));
1228 b += sizeof(u32);
1229 }
1230 printk("\n");
1231 }
1232 }
1233 #endif
1234
1235 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1236 {
1237 #ifdef ATA_DEBUG
1238 int b, w;
1239 u32 dw;
1240 for (b = 0; b < bytes; ) {
1241 DPRINTK("%02x: ", b);
1242 for (w = 0; b < bytes && w < 4; w++) {
1243 (void) pci_read_config_dword(pdev, b, &dw);
1244 printk("%08x ", dw);
1245 b += sizeof(u32);
1246 }
1247 printk("\n");
1248 }
1249 #endif
1250 }
1251 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1252 struct pci_dev *pdev)
1253 {
1254 #ifdef ATA_DEBUG
1255 void __iomem *hc_base = mv_hc_base(mmio_base,
1256 port >> MV_PORT_HC_SHIFT);
1257 void __iomem *port_base;
1258 int start_port, num_ports, p, start_hc, num_hcs, hc;
1259
1260 if (0 > port) {
1261 start_hc = start_port = 0;
1262 num_ports = 8; /* shld be benign for 4 port devs */
1263 num_hcs = 2;
1264 } else {
1265 start_hc = port >> MV_PORT_HC_SHIFT;
1266 start_port = port;
1267 num_ports = num_hcs = 1;
1268 }
1269 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1270 num_ports > 1 ? num_ports - 1 : start_port);
1271
1272 if (NULL != pdev) {
1273 DPRINTK("PCI config space regs:\n");
1274 mv_dump_pci_cfg(pdev, 0x68);
1275 }
1276 DPRINTK("PCI regs:\n");
1277 mv_dump_mem(mmio_base+0xc00, 0x3c);
1278 mv_dump_mem(mmio_base+0xd00, 0x34);
1279 mv_dump_mem(mmio_base+0xf00, 0x4);
1280 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1281 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1282 hc_base = mv_hc_base(mmio_base, hc);
1283 DPRINTK("HC regs (HC %i):\n", hc);
1284 mv_dump_mem(hc_base, 0x1c);
1285 }
1286 for (p = start_port; p < start_port + num_ports; p++) {
1287 port_base = mv_port_base(mmio_base, p);
1288 DPRINTK("EDMA regs (port %i):\n", p);
1289 mv_dump_mem(port_base, 0x54);
1290 DPRINTK("SATA regs (port %i):\n", p);
1291 mv_dump_mem(port_base+0x300, 0x60);
1292 }
1293 #endif
1294 }
1295
1296 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1297 {
1298 unsigned int ofs;
1299
1300 switch (sc_reg_in) {
1301 case SCR_STATUS:
1302 case SCR_CONTROL:
1303 case SCR_ERROR:
1304 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1305 break;
1306 case SCR_ACTIVE:
1307 ofs = SATA_ACTIVE; /* active is not with the others */
1308 break;
1309 default:
1310 ofs = 0xffffffffU;
1311 break;
1312 }
1313 return ofs;
1314 }
1315
1316 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1317 {
1318 unsigned int ofs = mv_scr_offset(sc_reg_in);
1319
1320 if (ofs != 0xffffffffU) {
1321 *val = readl(mv_ap_base(link->ap) + ofs);
1322 return 0;
1323 } else
1324 return -EINVAL;
1325 }
1326
1327 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1328 {
1329 unsigned int ofs = mv_scr_offset(sc_reg_in);
1330
1331 if (ofs != 0xffffffffU) {
1332 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1333 if (sc_reg_in == SCR_CONTROL) {
1334 /*
1335 * Workaround for 88SX60x1 FEr SATA#26:
1336 *
1337 * COMRESETs have to take care not to accidently
1338 * put the drive to sleep when writing SCR_CONTROL.
1339 * Setting bits 12..15 prevents this problem.
1340 *
1341 * So if we see an outbound COMMRESET, set those bits.
1342 * Ditto for the followup write that clears the reset.
1343 *
1344 * The proprietary driver does this for
1345 * all chip versions, and so do we.
1346 */
1347 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1348 val |= 0xf000;
1349 }
1350 writelfl(val, addr);
1351 return 0;
1352 } else
1353 return -EINVAL;
1354 }
1355
1356 static void mv6_dev_config(struct ata_device *adev)
1357 {
1358 /*
1359 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1360 *
1361 * Gen-II does not support NCQ over a port multiplier
1362 * (no FIS-based switching).
1363 */
1364 if (adev->flags & ATA_DFLAG_NCQ) {
1365 if (sata_pmp_attached(adev->link->ap)) {
1366 adev->flags &= ~ATA_DFLAG_NCQ;
1367 ata_dev_printk(adev, KERN_INFO,
1368 "NCQ disabled for command-based switching\n");
1369 }
1370 }
1371 }
1372
1373 static int mv_qc_defer(struct ata_queued_cmd *qc)
1374 {
1375 struct ata_link *link = qc->dev->link;
1376 struct ata_port *ap = link->ap;
1377 struct mv_port_priv *pp = ap->private_data;
1378
1379 /*
1380 * Don't allow new commands if we're in a delayed EH state
1381 * for NCQ and/or FIS-based switching.
1382 */
1383 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1384 return ATA_DEFER_PORT;
1385
1386 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1387 * can run concurrently.
1388 * set excl_link when we want to send a PIO command in DMA mode
1389 * or a non-NCQ command in NCQ mode.
1390 * When we receive a command from that link, and there are no
1391 * outstanding commands, mark a flag to clear excl_link and let
1392 * the command go through.
1393 */
1394 if (unlikely(ap->excl_link)) {
1395 if (link == ap->excl_link) {
1396 if (ap->nr_active_links)
1397 return ATA_DEFER_PORT;
1398 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1399 return 0;
1400 } else
1401 return ATA_DEFER_PORT;
1402 }
1403
1404 /*
1405 * If the port is completely idle, then allow the new qc.
1406 */
1407 if (ap->nr_active_links == 0)
1408 return 0;
1409
1410 /*
1411 * The port is operating in host queuing mode (EDMA) with NCQ
1412 * enabled, allow multiple NCQ commands. EDMA also allows
1413 * queueing multiple DMA commands but libata core currently
1414 * doesn't allow it.
1415 */
1416 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1417 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1418 if (ata_is_ncq(qc->tf.protocol))
1419 return 0;
1420 else {
1421 ap->excl_link = link;
1422 return ATA_DEFER_PORT;
1423 }
1424 }
1425
1426 return ATA_DEFER_PORT;
1427 }
1428
1429 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1430 {
1431 struct mv_port_priv *pp = ap->private_data;
1432 void __iomem *port_mmio;
1433
1434 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1435 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1436 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1437
1438 ltmode = *old_ltmode & ~LTMODE_BIT8;
1439 haltcond = *old_haltcond | EDMA_ERR_DEV;
1440
1441 if (want_fbs) {
1442 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1443 ltmode = *old_ltmode | LTMODE_BIT8;
1444 if (want_ncq)
1445 haltcond &= ~EDMA_ERR_DEV;
1446 else
1447 fiscfg |= FISCFG_WAIT_DEV_ERR;
1448 } else {
1449 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1450 }
1451
1452 port_mmio = mv_ap_base(ap);
1453 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1454 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1455 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1456 }
1457
1458 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1459 {
1460 struct mv_host_priv *hpriv = ap->host->private_data;
1461 u32 old, new;
1462
1463 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1464 old = readl(hpriv->base + GPIO_PORT_CTL);
1465 if (want_ncq)
1466 new = old | (1 << 22);
1467 else
1468 new = old & ~(1 << 22);
1469 if (new != old)
1470 writel(new, hpriv->base + GPIO_PORT_CTL);
1471 }
1472
1473 /**
1474 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1475 * @ap: Port being initialized
1476 *
1477 * There are two DMA modes on these chips: basic DMA, and EDMA.
1478 *
1479 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1480 * of basic DMA on the GEN_IIE versions of the chips.
1481 *
1482 * This bit survives EDMA resets, and must be set for basic DMA
1483 * to function, and should be cleared when EDMA is active.
1484 */
1485 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1486 {
1487 struct mv_port_priv *pp = ap->private_data;
1488 u32 new, *old = &pp->cached.unknown_rsvd;
1489
1490 if (enable_bmdma)
1491 new = *old | 1;
1492 else
1493 new = *old & ~1;
1494 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1495 }
1496
1497 /*
1498 * SOC chips have an issue whereby the HDD LEDs don't always blink
1499 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1500 * of the SOC takes care of it, generating a steady blink rate when
1501 * any drive on the chip is active.
1502 *
1503 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1504 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1505 *
1506 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1507 * LED operation works then, and provides better (more accurate) feedback.
1508 *
1509 * Note that this code assumes that an SOC never has more than one HC onboard.
1510 */
1511 static void mv_soc_led_blink_enable(struct ata_port *ap)
1512 {
1513 struct ata_host *host = ap->host;
1514 struct mv_host_priv *hpriv = host->private_data;
1515 void __iomem *hc_mmio;
1516 u32 led_ctrl;
1517
1518 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1519 return;
1520 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1521 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1522 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1523 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1524 }
1525
1526 static void mv_soc_led_blink_disable(struct ata_port *ap)
1527 {
1528 struct ata_host *host = ap->host;
1529 struct mv_host_priv *hpriv = host->private_data;
1530 void __iomem *hc_mmio;
1531 u32 led_ctrl;
1532 unsigned int port;
1533
1534 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1535 return;
1536
1537 /* disable led-blink only if no ports are using NCQ */
1538 for (port = 0; port < hpriv->n_ports; port++) {
1539 struct ata_port *this_ap = host->ports[port];
1540 struct mv_port_priv *pp = this_ap->private_data;
1541
1542 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1543 return;
1544 }
1545
1546 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1547 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1548 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1549 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1550 }
1551
1552 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1553 {
1554 u32 cfg;
1555 struct mv_port_priv *pp = ap->private_data;
1556 struct mv_host_priv *hpriv = ap->host->private_data;
1557 void __iomem *port_mmio = mv_ap_base(ap);
1558
1559 /* set up non-NCQ EDMA configuration */
1560 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1561 pp->pp_flags &=
1562 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1563
1564 if (IS_GEN_I(hpriv))
1565 cfg |= (1 << 8); /* enab config burst size mask */
1566
1567 else if (IS_GEN_II(hpriv)) {
1568 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1569 mv_60x1_errata_sata25(ap, want_ncq);
1570
1571 } else if (IS_GEN_IIE(hpriv)) {
1572 int want_fbs = sata_pmp_attached(ap);
1573 /*
1574 * Possible future enhancement:
1575 *
1576 * The chip can use FBS with non-NCQ, if we allow it,
1577 * But first we need to have the error handling in place
1578 * for this mode (datasheet section 7.3.15.4.2.3).
1579 * So disallow non-NCQ FBS for now.
1580 */
1581 want_fbs &= want_ncq;
1582
1583 mv_config_fbs(ap, want_ncq, want_fbs);
1584
1585 if (want_fbs) {
1586 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1587 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1588 }
1589
1590 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1591 if (want_edma) {
1592 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1593 if (!IS_SOC(hpriv))
1594 cfg |= (1 << 18); /* enab early completion */
1595 }
1596 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1597 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1598 mv_bmdma_enable_iie(ap, !want_edma);
1599
1600 if (IS_SOC(hpriv)) {
1601 if (want_ncq)
1602 mv_soc_led_blink_enable(ap);
1603 else
1604 mv_soc_led_blink_disable(ap);
1605 }
1606 }
1607
1608 if (want_ncq) {
1609 cfg |= EDMA_CFG_NCQ;
1610 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1611 }
1612
1613 writelfl(cfg, port_mmio + EDMA_CFG);
1614 }
1615
1616 static void mv_port_free_dma_mem(struct ata_port *ap)
1617 {
1618 struct mv_host_priv *hpriv = ap->host->private_data;
1619 struct mv_port_priv *pp = ap->private_data;
1620 int tag;
1621
1622 if (pp->crqb) {
1623 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1624 pp->crqb = NULL;
1625 }
1626 if (pp->crpb) {
1627 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1628 pp->crpb = NULL;
1629 }
1630 /*
1631 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1632 * For later hardware, we have one unique sg_tbl per NCQ tag.
1633 */
1634 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1635 if (pp->sg_tbl[tag]) {
1636 if (tag == 0 || !IS_GEN_I(hpriv))
1637 dma_pool_free(hpriv->sg_tbl_pool,
1638 pp->sg_tbl[tag],
1639 pp->sg_tbl_dma[tag]);
1640 pp->sg_tbl[tag] = NULL;
1641 }
1642 }
1643 }
1644
1645 /**
1646 * mv_port_start - Port specific init/start routine.
1647 * @ap: ATA channel to manipulate
1648 *
1649 * Allocate and point to DMA memory, init port private memory,
1650 * zero indices.
1651 *
1652 * LOCKING:
1653 * Inherited from caller.
1654 */
1655 static int mv_port_start(struct ata_port *ap)
1656 {
1657 struct device *dev = ap->host->dev;
1658 struct mv_host_priv *hpriv = ap->host->private_data;
1659 struct mv_port_priv *pp;
1660 unsigned long flags;
1661 int tag;
1662
1663 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1664 if (!pp)
1665 return -ENOMEM;
1666 ap->private_data = pp;
1667
1668 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1669 if (!pp->crqb)
1670 return -ENOMEM;
1671 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1672
1673 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1674 if (!pp->crpb)
1675 goto out_port_free_dma_mem;
1676 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1677
1678 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1679 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1680 ap->flags |= ATA_FLAG_AN;
1681 /*
1682 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1683 * For later hardware, we need one unique sg_tbl per NCQ tag.
1684 */
1685 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1686 if (tag == 0 || !IS_GEN_I(hpriv)) {
1687 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1688 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1689 if (!pp->sg_tbl[tag])
1690 goto out_port_free_dma_mem;
1691 } else {
1692 pp->sg_tbl[tag] = pp->sg_tbl[0];
1693 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1694 }
1695 }
1696
1697 spin_lock_irqsave(ap->lock, flags);
1698 mv_save_cached_regs(ap);
1699 mv_edma_cfg(ap, 0, 0);
1700 spin_unlock_irqrestore(ap->lock, flags);
1701
1702 return 0;
1703
1704 out_port_free_dma_mem:
1705 mv_port_free_dma_mem(ap);
1706 return -ENOMEM;
1707 }
1708
1709 /**
1710 * mv_port_stop - Port specific cleanup/stop routine.
1711 * @ap: ATA channel to manipulate
1712 *
1713 * Stop DMA, cleanup port memory.
1714 *
1715 * LOCKING:
1716 * This routine uses the host lock to protect the DMA stop.
1717 */
1718 static void mv_port_stop(struct ata_port *ap)
1719 {
1720 unsigned long flags;
1721
1722 spin_lock_irqsave(ap->lock, flags);
1723 mv_stop_edma(ap);
1724 mv_enable_port_irqs(ap, 0);
1725 spin_unlock_irqrestore(ap->lock, flags);
1726 mv_port_free_dma_mem(ap);
1727 }
1728
1729 /**
1730 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1731 * @qc: queued command whose SG list to source from
1732 *
1733 * Populate the SG list and mark the last entry.
1734 *
1735 * LOCKING:
1736 * Inherited from caller.
1737 */
1738 static void mv_fill_sg(struct ata_queued_cmd *qc)
1739 {
1740 struct mv_port_priv *pp = qc->ap->private_data;
1741 struct scatterlist *sg;
1742 struct mv_sg *mv_sg, *last_sg = NULL;
1743 unsigned int si;
1744
1745 mv_sg = pp->sg_tbl[qc->tag];
1746 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1747 dma_addr_t addr = sg_dma_address(sg);
1748 u32 sg_len = sg_dma_len(sg);
1749
1750 while (sg_len) {
1751 u32 offset = addr & 0xffff;
1752 u32 len = sg_len;
1753
1754 if (offset + len > 0x10000)
1755 len = 0x10000 - offset;
1756
1757 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1758 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1759 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1760 mv_sg->reserved = 0;
1761
1762 sg_len -= len;
1763 addr += len;
1764
1765 last_sg = mv_sg;
1766 mv_sg++;
1767 }
1768 }
1769
1770 if (likely(last_sg))
1771 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1772 mb(); /* ensure data structure is visible to the chipset */
1773 }
1774
1775 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1776 {
1777 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1778 (last ? CRQB_CMD_LAST : 0);
1779 *cmdw = cpu_to_le16(tmp);
1780 }
1781
1782 /**
1783 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1784 * @ap: Port associated with this ATA transaction.
1785 *
1786 * We need this only for ATAPI bmdma transactions,
1787 * as otherwise we experience spurious interrupts
1788 * after libata-sff handles the bmdma interrupts.
1789 */
1790 static void mv_sff_irq_clear(struct ata_port *ap)
1791 {
1792 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1793 }
1794
1795 /**
1796 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1797 * @qc: queued command to check for chipset/DMA compatibility.
1798 *
1799 * The bmdma engines cannot handle speculative data sizes
1800 * (bytecount under/over flow). So only allow DMA for
1801 * data transfer commands with known data sizes.
1802 *
1803 * LOCKING:
1804 * Inherited from caller.
1805 */
1806 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1807 {
1808 struct scsi_cmnd *scmd = qc->scsicmd;
1809
1810 if (scmd) {
1811 switch (scmd->cmnd[0]) {
1812 case READ_6:
1813 case READ_10:
1814 case READ_12:
1815 case WRITE_6:
1816 case WRITE_10:
1817 case WRITE_12:
1818 case GPCMD_READ_CD:
1819 case GPCMD_SEND_DVD_STRUCTURE:
1820 case GPCMD_SEND_CUE_SHEET:
1821 return 0; /* DMA is safe */
1822 }
1823 }
1824 return -EOPNOTSUPP; /* use PIO instead */
1825 }
1826
1827 /**
1828 * mv_bmdma_setup - Set up BMDMA transaction
1829 * @qc: queued command to prepare DMA for.
1830 *
1831 * LOCKING:
1832 * Inherited from caller.
1833 */
1834 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1835 {
1836 struct ata_port *ap = qc->ap;
1837 void __iomem *port_mmio = mv_ap_base(ap);
1838 struct mv_port_priv *pp = ap->private_data;
1839
1840 mv_fill_sg(qc);
1841
1842 /* clear all DMA cmd bits */
1843 writel(0, port_mmio + BMDMA_CMD);
1844
1845 /* load PRD table addr. */
1846 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1847 port_mmio + BMDMA_PRD_HIGH);
1848 writelfl(pp->sg_tbl_dma[qc->tag],
1849 port_mmio + BMDMA_PRD_LOW);
1850
1851 /* issue r/w command */
1852 ap->ops->sff_exec_command(ap, &qc->tf);
1853 }
1854
1855 /**
1856 * mv_bmdma_start - Start a BMDMA transaction
1857 * @qc: queued command to start DMA on.
1858 *
1859 * LOCKING:
1860 * Inherited from caller.
1861 */
1862 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1863 {
1864 struct ata_port *ap = qc->ap;
1865 void __iomem *port_mmio = mv_ap_base(ap);
1866 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1867 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1868
1869 /* start host DMA transaction */
1870 writelfl(cmd, port_mmio + BMDMA_CMD);
1871 }
1872
1873 /**
1874 * mv_bmdma_stop - Stop BMDMA transfer
1875 * @qc: queued command to stop DMA on.
1876 *
1877 * Clears the ATA_DMA_START flag in the bmdma control register
1878 *
1879 * LOCKING:
1880 * Inherited from caller.
1881 */
1882 static void mv_bmdma_stop_ap(struct ata_port *ap)
1883 {
1884 void __iomem *port_mmio = mv_ap_base(ap);
1885 u32 cmd;
1886
1887 /* clear start/stop bit */
1888 cmd = readl(port_mmio + BMDMA_CMD);
1889 if (cmd & ATA_DMA_START) {
1890 cmd &= ~ATA_DMA_START;
1891 writelfl(cmd, port_mmio + BMDMA_CMD);
1892
1893 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1894 ata_sff_dma_pause(ap);
1895 }
1896 }
1897
1898 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1899 {
1900 mv_bmdma_stop_ap(qc->ap);
1901 }
1902
1903 /**
1904 * mv_bmdma_status - Read BMDMA status
1905 * @ap: port for which to retrieve DMA status.
1906 *
1907 * Read and return equivalent of the sff BMDMA status register.
1908 *
1909 * LOCKING:
1910 * Inherited from caller.
1911 */
1912 static u8 mv_bmdma_status(struct ata_port *ap)
1913 {
1914 void __iomem *port_mmio = mv_ap_base(ap);
1915 u32 reg, status;
1916
1917 /*
1918 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1919 * and the ATA_DMA_INTR bit doesn't exist.
1920 */
1921 reg = readl(port_mmio + BMDMA_STATUS);
1922 if (reg & ATA_DMA_ACTIVE)
1923 status = ATA_DMA_ACTIVE;
1924 else if (reg & ATA_DMA_ERR)
1925 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1926 else {
1927 /*
1928 * Just because DMA_ACTIVE is 0 (DMA completed),
1929 * this does _not_ mean the device is "done".
1930 * So we should not yet be signalling ATA_DMA_INTR
1931 * in some cases. Eg. DSM/TRIM, and perhaps others.
1932 */
1933 mv_bmdma_stop_ap(ap);
1934 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1935 status = 0;
1936 else
1937 status = ATA_DMA_INTR;
1938 }
1939 return status;
1940 }
1941
1942 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1943 {
1944 struct ata_taskfile *tf = &qc->tf;
1945 /*
1946 * Workaround for 88SX60x1 FEr SATA#24.
1947 *
1948 * Chip may corrupt WRITEs if multi_count >= 4kB.
1949 * Note that READs are unaffected.
1950 *
1951 * It's not clear if this errata really means "4K bytes",
1952 * or if it always happens for multi_count > 7
1953 * regardless of device sector_size.
1954 *
1955 * So, for safety, any write with multi_count > 7
1956 * gets converted here into a regular PIO write instead:
1957 */
1958 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1959 if (qc->dev->multi_count > 7) {
1960 switch (tf->command) {
1961 case ATA_CMD_WRITE_MULTI:
1962 tf->command = ATA_CMD_PIO_WRITE;
1963 break;
1964 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1965 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1966 /* fall through */
1967 case ATA_CMD_WRITE_MULTI_EXT:
1968 tf->command = ATA_CMD_PIO_WRITE_EXT;
1969 break;
1970 }
1971 }
1972 }
1973 }
1974
1975 /**
1976 * mv_qc_prep - Host specific command preparation.
1977 * @qc: queued command to prepare
1978 *
1979 * This routine simply redirects to the general purpose routine
1980 * if command is not DMA. Else, it handles prep of the CRQB
1981 * (command request block), does some sanity checking, and calls
1982 * the SG load routine.
1983 *
1984 * LOCKING:
1985 * Inherited from caller.
1986 */
1987 static void mv_qc_prep(struct ata_queued_cmd *qc)
1988 {
1989 struct ata_port *ap = qc->ap;
1990 struct mv_port_priv *pp = ap->private_data;
1991 __le16 *cw;
1992 struct ata_taskfile *tf = &qc->tf;
1993 u16 flags = 0;
1994 unsigned in_index;
1995
1996 switch (tf->protocol) {
1997 case ATA_PROT_DMA:
1998 if (tf->command == ATA_CMD_DSM)
1999 return;
2000 /* fall-thru */
2001 case ATA_PROT_NCQ:
2002 break; /* continue below */
2003 case ATA_PROT_PIO:
2004 mv_rw_multi_errata_sata24(qc);
2005 return;
2006 default:
2007 return;
2008 }
2009
2010 /* Fill in command request block
2011 */
2012 if (!(tf->flags & ATA_TFLAG_WRITE))
2013 flags |= CRQB_FLAG_READ;
2014 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2015 flags |= qc->tag << CRQB_TAG_SHIFT;
2016 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2017
2018 /* get current queue index from software */
2019 in_index = pp->req_idx;
2020
2021 pp->crqb[in_index].sg_addr =
2022 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2023 pp->crqb[in_index].sg_addr_hi =
2024 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2025 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2026
2027 cw = &pp->crqb[in_index].ata_cmd[0];
2028
2029 /* Sadly, the CRQB cannot accomodate all registers--there are
2030 * only 11 bytes...so we must pick and choose required
2031 * registers based on the command. So, we drop feature and
2032 * hob_feature for [RW] DMA commands, but they are needed for
2033 * NCQ. NCQ will drop hob_nsect, which is not needed there
2034 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2035 */
2036 switch (tf->command) {
2037 case ATA_CMD_READ:
2038 case ATA_CMD_READ_EXT:
2039 case ATA_CMD_WRITE:
2040 case ATA_CMD_WRITE_EXT:
2041 case ATA_CMD_WRITE_FUA_EXT:
2042 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2043 break;
2044 case ATA_CMD_FPDMA_READ:
2045 case ATA_CMD_FPDMA_WRITE:
2046 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2047 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2048 break;
2049 default:
2050 /* The only other commands EDMA supports in non-queued and
2051 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2052 * of which are defined/used by Linux. If we get here, this
2053 * driver needs work.
2054 *
2055 * FIXME: modify libata to give qc_prep a return value and
2056 * return error here.
2057 */
2058 BUG_ON(tf->command);
2059 break;
2060 }
2061 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2062 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2063 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2064 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2065 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2066 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2067 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2068 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2069 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2070
2071 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2072 return;
2073 mv_fill_sg(qc);
2074 }
2075
2076 /**
2077 * mv_qc_prep_iie - Host specific command preparation.
2078 * @qc: queued command to prepare
2079 *
2080 * This routine simply redirects to the general purpose routine
2081 * if command is not DMA. Else, it handles prep of the CRQB
2082 * (command request block), does some sanity checking, and calls
2083 * the SG load routine.
2084 *
2085 * LOCKING:
2086 * Inherited from caller.
2087 */
2088 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2089 {
2090 struct ata_port *ap = qc->ap;
2091 struct mv_port_priv *pp = ap->private_data;
2092 struct mv_crqb_iie *crqb;
2093 struct ata_taskfile *tf = &qc->tf;
2094 unsigned in_index;
2095 u32 flags = 0;
2096
2097 if ((tf->protocol != ATA_PROT_DMA) &&
2098 (tf->protocol != ATA_PROT_NCQ))
2099 return;
2100 if (tf->command == ATA_CMD_DSM)
2101 return; /* use bmdma for this */
2102
2103 /* Fill in Gen IIE command request block */
2104 if (!(tf->flags & ATA_TFLAG_WRITE))
2105 flags |= CRQB_FLAG_READ;
2106
2107 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2108 flags |= qc->tag << CRQB_TAG_SHIFT;
2109 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2110 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2111
2112 /* get current queue index from software */
2113 in_index = pp->req_idx;
2114
2115 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2116 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2117 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2118 crqb->flags = cpu_to_le32(flags);
2119
2120 crqb->ata_cmd[0] = cpu_to_le32(
2121 (tf->command << 16) |
2122 (tf->feature << 24)
2123 );
2124 crqb->ata_cmd[1] = cpu_to_le32(
2125 (tf->lbal << 0) |
2126 (tf->lbam << 8) |
2127 (tf->lbah << 16) |
2128 (tf->device << 24)
2129 );
2130 crqb->ata_cmd[2] = cpu_to_le32(
2131 (tf->hob_lbal << 0) |
2132 (tf->hob_lbam << 8) |
2133 (tf->hob_lbah << 16) |
2134 (tf->hob_feature << 24)
2135 );
2136 crqb->ata_cmd[3] = cpu_to_le32(
2137 (tf->nsect << 0) |
2138 (tf->hob_nsect << 8)
2139 );
2140
2141 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2142 return;
2143 mv_fill_sg(qc);
2144 }
2145
2146 /**
2147 * mv_sff_check_status - fetch device status, if valid
2148 * @ap: ATA port to fetch status from
2149 *
2150 * When using command issue via mv_qc_issue_fis(),
2151 * the initial ATA_BUSY state does not show up in the
2152 * ATA status (shadow) register. This can confuse libata!
2153 *
2154 * So we have a hook here to fake ATA_BUSY for that situation,
2155 * until the first time a BUSY, DRQ, or ERR bit is seen.
2156 *
2157 * The rest of the time, it simply returns the ATA status register.
2158 */
2159 static u8 mv_sff_check_status(struct ata_port *ap)
2160 {
2161 u8 stat = ioread8(ap->ioaddr.status_addr);
2162 struct mv_port_priv *pp = ap->private_data;
2163
2164 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2165 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2166 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2167 else
2168 stat = ATA_BUSY;
2169 }
2170 return stat;
2171 }
2172
2173 /**
2174 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2175 * @fis: fis to be sent
2176 * @nwords: number of 32-bit words in the fis
2177 */
2178 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2179 {
2180 void __iomem *port_mmio = mv_ap_base(ap);
2181 u32 ifctl, old_ifctl, ifstat;
2182 int i, timeout = 200, final_word = nwords - 1;
2183
2184 /* Initiate FIS transmission mode */
2185 old_ifctl = readl(port_mmio + SATA_IFCTL);
2186 ifctl = 0x100 | (old_ifctl & 0xf);
2187 writelfl(ifctl, port_mmio + SATA_IFCTL);
2188
2189 /* Send all words of the FIS except for the final word */
2190 for (i = 0; i < final_word; ++i)
2191 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2192
2193 /* Flag end-of-transmission, and then send the final word */
2194 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2195 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2196
2197 /*
2198 * Wait for FIS transmission to complete.
2199 * This typically takes just a single iteration.
2200 */
2201 do {
2202 ifstat = readl(port_mmio + SATA_IFSTAT);
2203 } while (!(ifstat & 0x1000) && --timeout);
2204
2205 /* Restore original port configuration */
2206 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2207
2208 /* See if it worked */
2209 if ((ifstat & 0x3000) != 0x1000) {
2210 ata_port_printk(ap, KERN_WARNING,
2211 "%s transmission error, ifstat=%08x\n",
2212 __func__, ifstat);
2213 return AC_ERR_OTHER;
2214 }
2215 return 0;
2216 }
2217
2218 /**
2219 * mv_qc_issue_fis - Issue a command directly as a FIS
2220 * @qc: queued command to start
2221 *
2222 * Note that the ATA shadow registers are not updated
2223 * after command issue, so the device will appear "READY"
2224 * if polled, even while it is BUSY processing the command.
2225 *
2226 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2227 *
2228 * Note: we don't get updated shadow regs on *completion*
2229 * of non-data commands. So avoid sending them via this function,
2230 * as they will appear to have completed immediately.
2231 *
2232 * GEN_IIE has special registers that we could get the result tf from,
2233 * but earlier chipsets do not. For now, we ignore those registers.
2234 */
2235 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2236 {
2237 struct ata_port *ap = qc->ap;
2238 struct mv_port_priv *pp = ap->private_data;
2239 struct ata_link *link = qc->dev->link;
2240 u32 fis[5];
2241 int err = 0;
2242
2243 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2244 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
2245 if (err)
2246 return err;
2247
2248 switch (qc->tf.protocol) {
2249 case ATAPI_PROT_PIO:
2250 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2251 /* fall through */
2252 case ATAPI_PROT_NODATA:
2253 ap->hsm_task_state = HSM_ST_FIRST;
2254 break;
2255 case ATA_PROT_PIO:
2256 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2257 if (qc->tf.flags & ATA_TFLAG_WRITE)
2258 ap->hsm_task_state = HSM_ST_FIRST;
2259 else
2260 ap->hsm_task_state = HSM_ST;
2261 break;
2262 default:
2263 ap->hsm_task_state = HSM_ST_LAST;
2264 break;
2265 }
2266
2267 if (qc->tf.flags & ATA_TFLAG_POLLING)
2268 ata_pio_queue_task(ap, qc, 0);
2269 return 0;
2270 }
2271
2272 /**
2273 * mv_qc_issue - Initiate a command to the host
2274 * @qc: queued command to start
2275 *
2276 * This routine simply redirects to the general purpose routine
2277 * if command is not DMA. Else, it sanity checks our local
2278 * caches of the request producer/consumer indices then enables
2279 * DMA and bumps the request producer index.
2280 *
2281 * LOCKING:
2282 * Inherited from caller.
2283 */
2284 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2285 {
2286 static int limit_warnings = 10;
2287 struct ata_port *ap = qc->ap;
2288 void __iomem *port_mmio = mv_ap_base(ap);
2289 struct mv_port_priv *pp = ap->private_data;
2290 u32 in_index;
2291 unsigned int port_irqs;
2292
2293 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2294
2295 switch (qc->tf.protocol) {
2296 case ATA_PROT_DMA:
2297 if (qc->tf.command == ATA_CMD_DSM) {
2298 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2299 return AC_ERR_OTHER;
2300 break; /* use bmdma for this */
2301 }
2302 /* fall thru */
2303 case ATA_PROT_NCQ:
2304 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2305 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2306 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2307
2308 /* Write the request in pointer to kick the EDMA to life */
2309 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2310 port_mmio + EDMA_REQ_Q_IN_PTR);
2311 return 0;
2312
2313 case ATA_PROT_PIO:
2314 /*
2315 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2316 *
2317 * Someday, we might implement special polling workarounds
2318 * for these, but it all seems rather unnecessary since we
2319 * normally use only DMA for commands which transfer more
2320 * than a single block of data.
2321 *
2322 * Much of the time, this could just work regardless.
2323 * So for now, just log the incident, and allow the attempt.
2324 */
2325 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2326 --limit_warnings;
2327 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2328 ": attempting PIO w/multiple DRQ: "
2329 "this may fail due to h/w errata\n");
2330 }
2331 /* drop through */
2332 case ATA_PROT_NODATA:
2333 case ATAPI_PROT_PIO:
2334 case ATAPI_PROT_NODATA:
2335 if (ap->flags & ATA_FLAG_PIO_POLLING)
2336 qc->tf.flags |= ATA_TFLAG_POLLING;
2337 break;
2338 }
2339
2340 if (qc->tf.flags & ATA_TFLAG_POLLING)
2341 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2342 else
2343 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2344
2345 /*
2346 * We're about to send a non-EDMA capable command to the
2347 * port. Turn off EDMA so there won't be problems accessing
2348 * shadow block, etc registers.
2349 */
2350 mv_stop_edma(ap);
2351 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2352 mv_pmp_select(ap, qc->dev->link->pmp);
2353
2354 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2355 struct mv_host_priv *hpriv = ap->host->private_data;
2356 /*
2357 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2358 *
2359 * After any NCQ error, the READ_LOG_EXT command
2360 * from libata-eh *must* use mv_qc_issue_fis().
2361 * Otherwise it might fail, due to chip errata.
2362 *
2363 * Rather than special-case it, we'll just *always*
2364 * use this method here for READ_LOG_EXT, making for
2365 * easier testing.
2366 */
2367 if (IS_GEN_II(hpriv))
2368 return mv_qc_issue_fis(qc);
2369 }
2370 return ata_sff_qc_issue(qc);
2371 }
2372
2373 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2374 {
2375 struct mv_port_priv *pp = ap->private_data;
2376 struct ata_queued_cmd *qc;
2377
2378 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2379 return NULL;
2380 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2381 if (qc) {
2382 if (qc->tf.flags & ATA_TFLAG_POLLING)
2383 qc = NULL;
2384 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2385 qc = NULL;
2386 }
2387 return qc;
2388 }
2389
2390 static void mv_pmp_error_handler(struct ata_port *ap)
2391 {
2392 unsigned int pmp, pmp_map;
2393 struct mv_port_priv *pp = ap->private_data;
2394
2395 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2396 /*
2397 * Perform NCQ error analysis on failed PMPs
2398 * before we freeze the port entirely.
2399 *
2400 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2401 */
2402 pmp_map = pp->delayed_eh_pmp_map;
2403 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2404 for (pmp = 0; pmp_map != 0; pmp++) {
2405 unsigned int this_pmp = (1 << pmp);
2406 if (pmp_map & this_pmp) {
2407 struct ata_link *link = &ap->pmp_link[pmp];
2408 pmp_map &= ~this_pmp;
2409 ata_eh_analyze_ncq_error(link);
2410 }
2411 }
2412 ata_port_freeze(ap);
2413 }
2414 sata_pmp_error_handler(ap);
2415 }
2416
2417 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2418 {
2419 void __iomem *port_mmio = mv_ap_base(ap);
2420
2421 return readl(port_mmio + SATA_TESTCTL) >> 16;
2422 }
2423
2424 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2425 {
2426 struct ata_eh_info *ehi;
2427 unsigned int pmp;
2428
2429 /*
2430 * Initialize EH info for PMPs which saw device errors
2431 */
2432 ehi = &ap->link.eh_info;
2433 for (pmp = 0; pmp_map != 0; pmp++) {
2434 unsigned int this_pmp = (1 << pmp);
2435 if (pmp_map & this_pmp) {
2436 struct ata_link *link = &ap->pmp_link[pmp];
2437
2438 pmp_map &= ~this_pmp;
2439 ehi = &link->eh_info;
2440 ata_ehi_clear_desc(ehi);
2441 ata_ehi_push_desc(ehi, "dev err");
2442 ehi->err_mask |= AC_ERR_DEV;
2443 ehi->action |= ATA_EH_RESET;
2444 ata_link_abort(link);
2445 }
2446 }
2447 }
2448
2449 static int mv_req_q_empty(struct ata_port *ap)
2450 {
2451 void __iomem *port_mmio = mv_ap_base(ap);
2452 u32 in_ptr, out_ptr;
2453
2454 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2455 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2456 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2457 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2458 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2459 }
2460
2461 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2462 {
2463 struct mv_port_priv *pp = ap->private_data;
2464 int failed_links;
2465 unsigned int old_map, new_map;
2466
2467 /*
2468 * Device error during FBS+NCQ operation:
2469 *
2470 * Set a port flag to prevent further I/O being enqueued.
2471 * Leave the EDMA running to drain outstanding commands from this port.
2472 * Perform the post-mortem/EH only when all responses are complete.
2473 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2474 */
2475 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2476 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2477 pp->delayed_eh_pmp_map = 0;
2478 }
2479 old_map = pp->delayed_eh_pmp_map;
2480 new_map = old_map | mv_get_err_pmp_map(ap);
2481
2482 if (old_map != new_map) {
2483 pp->delayed_eh_pmp_map = new_map;
2484 mv_pmp_eh_prep(ap, new_map & ~old_map);
2485 }
2486 failed_links = hweight16(new_map);
2487
2488 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2489 "failed_links=%d nr_active_links=%d\n",
2490 __func__, pp->delayed_eh_pmp_map,
2491 ap->qc_active, failed_links,
2492 ap->nr_active_links);
2493
2494 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2495 mv_process_crpb_entries(ap, pp);
2496 mv_stop_edma(ap);
2497 mv_eh_freeze(ap);
2498 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2499 return 1; /* handled */
2500 }
2501 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2502 return 1; /* handled */
2503 }
2504
2505 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2506 {
2507 /*
2508 * Possible future enhancement:
2509 *
2510 * FBS+non-NCQ operation is not yet implemented.
2511 * See related notes in mv_edma_cfg().
2512 *
2513 * Device error during FBS+non-NCQ operation:
2514 *
2515 * We need to snapshot the shadow registers for each failed command.
2516 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2517 */
2518 return 0; /* not handled */
2519 }
2520
2521 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2522 {
2523 struct mv_port_priv *pp = ap->private_data;
2524
2525 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2526 return 0; /* EDMA was not active: not handled */
2527 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2528 return 0; /* FBS was not active: not handled */
2529
2530 if (!(edma_err_cause & EDMA_ERR_DEV))
2531 return 0; /* non DEV error: not handled */
2532 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2533 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2534 return 0; /* other problems: not handled */
2535
2536 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2537 /*
2538 * EDMA should NOT have self-disabled for this case.
2539 * If it did, then something is wrong elsewhere,
2540 * and we cannot handle it here.
2541 */
2542 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2543 ata_port_printk(ap, KERN_WARNING,
2544 "%s: err_cause=0x%x pp_flags=0x%x\n",
2545 __func__, edma_err_cause, pp->pp_flags);
2546 return 0; /* not handled */
2547 }
2548 return mv_handle_fbs_ncq_dev_err(ap);
2549 } else {
2550 /*
2551 * EDMA should have self-disabled for this case.
2552 * If it did not, then something is wrong elsewhere,
2553 * and we cannot handle it here.
2554 */
2555 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2556 ata_port_printk(ap, KERN_WARNING,
2557 "%s: err_cause=0x%x pp_flags=0x%x\n",
2558 __func__, edma_err_cause, pp->pp_flags);
2559 return 0; /* not handled */
2560 }
2561 return mv_handle_fbs_non_ncq_dev_err(ap);
2562 }
2563 return 0; /* not handled */
2564 }
2565
2566 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2567 {
2568 struct ata_eh_info *ehi = &ap->link.eh_info;
2569 char *when = "idle";
2570
2571 ata_ehi_clear_desc(ehi);
2572 if (ap->flags & ATA_FLAG_DISABLED) {
2573 when = "disabled";
2574 } else if (edma_was_enabled) {
2575 when = "EDMA enabled";
2576 } else {
2577 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2578 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2579 when = "polling";
2580 }
2581 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2582 ehi->err_mask |= AC_ERR_OTHER;
2583 ehi->action |= ATA_EH_RESET;
2584 ata_port_freeze(ap);
2585 }
2586
2587 /**
2588 * mv_err_intr - Handle error interrupts on the port
2589 * @ap: ATA channel to manipulate
2590 *
2591 * Most cases require a full reset of the chip's state machine,
2592 * which also performs a COMRESET.
2593 * Also, if the port disabled DMA, update our cached copy to match.
2594 *
2595 * LOCKING:
2596 * Inherited from caller.
2597 */
2598 static void mv_err_intr(struct ata_port *ap)
2599 {
2600 void __iomem *port_mmio = mv_ap_base(ap);
2601 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2602 u32 fis_cause = 0;
2603 struct mv_port_priv *pp = ap->private_data;
2604 struct mv_host_priv *hpriv = ap->host->private_data;
2605 unsigned int action = 0, err_mask = 0;
2606 struct ata_eh_info *ehi = &ap->link.eh_info;
2607 struct ata_queued_cmd *qc;
2608 int abort = 0;
2609
2610 /*
2611 * Read and clear the SError and err_cause bits.
2612 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2613 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2614 */
2615 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2616 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2617
2618 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2619 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2620 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2621 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2622 }
2623 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2624
2625 if (edma_err_cause & EDMA_ERR_DEV) {
2626 /*
2627 * Device errors during FIS-based switching operation
2628 * require special handling.
2629 */
2630 if (mv_handle_dev_err(ap, edma_err_cause))
2631 return;
2632 }
2633
2634 qc = mv_get_active_qc(ap);
2635 ata_ehi_clear_desc(ehi);
2636 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2637 edma_err_cause, pp->pp_flags);
2638
2639 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2640 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2641 if (fis_cause & FIS_IRQ_CAUSE_AN) {
2642 u32 ec = edma_err_cause &
2643 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2644 sata_async_notification(ap);
2645 if (!ec)
2646 return; /* Just an AN; no need for the nukes */
2647 ata_ehi_push_desc(ehi, "SDB notify");
2648 }
2649 }
2650 /*
2651 * All generations share these EDMA error cause bits:
2652 */
2653 if (edma_err_cause & EDMA_ERR_DEV) {
2654 err_mask |= AC_ERR_DEV;
2655 action |= ATA_EH_RESET;
2656 ata_ehi_push_desc(ehi, "dev error");
2657 }
2658 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2659 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2660 EDMA_ERR_INTRL_PAR)) {
2661 err_mask |= AC_ERR_ATA_BUS;
2662 action |= ATA_EH_RESET;
2663 ata_ehi_push_desc(ehi, "parity error");
2664 }
2665 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2666 ata_ehi_hotplugged(ehi);
2667 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2668 "dev disconnect" : "dev connect");
2669 action |= ATA_EH_RESET;
2670 }
2671
2672 /*
2673 * Gen-I has a different SELF_DIS bit,
2674 * different FREEZE bits, and no SERR bit:
2675 */
2676 if (IS_GEN_I(hpriv)) {
2677 eh_freeze_mask = EDMA_EH_FREEZE_5;
2678 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2679 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2680 ata_ehi_push_desc(ehi, "EDMA self-disable");
2681 }
2682 } else {
2683 eh_freeze_mask = EDMA_EH_FREEZE;
2684 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2685 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2686 ata_ehi_push_desc(ehi, "EDMA self-disable");
2687 }
2688 if (edma_err_cause & EDMA_ERR_SERR) {
2689 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2690 err_mask |= AC_ERR_ATA_BUS;
2691 action |= ATA_EH_RESET;
2692 }
2693 }
2694
2695 if (!err_mask) {
2696 err_mask = AC_ERR_OTHER;
2697 action |= ATA_EH_RESET;
2698 }
2699
2700 ehi->serror |= serr;
2701 ehi->action |= action;
2702
2703 if (qc)
2704 qc->err_mask |= err_mask;
2705 else
2706 ehi->err_mask |= err_mask;
2707
2708 if (err_mask == AC_ERR_DEV) {
2709 /*
2710 * Cannot do ata_port_freeze() here,
2711 * because it would kill PIO access,
2712 * which is needed for further diagnosis.
2713 */
2714 mv_eh_freeze(ap);
2715 abort = 1;
2716 } else if (edma_err_cause & eh_freeze_mask) {
2717 /*
2718 * Note to self: ata_port_freeze() calls ata_port_abort()
2719 */
2720 ata_port_freeze(ap);
2721 } else {
2722 abort = 1;
2723 }
2724
2725 if (abort) {
2726 if (qc)
2727 ata_link_abort(qc->dev->link);
2728 else
2729 ata_port_abort(ap);
2730 }
2731 }
2732
2733 static void mv_process_crpb_response(struct ata_port *ap,
2734 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2735 {
2736 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2737
2738 if (qc) {
2739 u8 ata_status;
2740 u16 edma_status = le16_to_cpu(response->flags);
2741 /*
2742 * edma_status from a response queue entry:
2743 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2744 * MSB is saved ATA status from command completion.
2745 */
2746 if (!ncq_enabled) {
2747 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2748 if (err_cause) {
2749 /*
2750 * Error will be seen/handled by mv_err_intr().
2751 * So do nothing at all here.
2752 */
2753 return;
2754 }
2755 }
2756 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2757 if (!ac_err_mask(ata_status))
2758 ata_qc_complete(qc);
2759 /* else: leave it for mv_err_intr() */
2760 } else {
2761 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2762 __func__, tag);
2763 }
2764 }
2765
2766 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2767 {
2768 void __iomem *port_mmio = mv_ap_base(ap);
2769 struct mv_host_priv *hpriv = ap->host->private_data;
2770 u32 in_index;
2771 bool work_done = false;
2772 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2773
2774 /* Get the hardware queue position index */
2775 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2776 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2777
2778 /* Process new responses from since the last time we looked */
2779 while (in_index != pp->resp_idx) {
2780 unsigned int tag;
2781 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2782
2783 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2784
2785 if (IS_GEN_I(hpriv)) {
2786 /* 50xx: no NCQ, only one command active at a time */
2787 tag = ap->link.active_tag;
2788 } else {
2789 /* Gen II/IIE: get command tag from CRPB entry */
2790 tag = le16_to_cpu(response->id) & 0x1f;
2791 }
2792 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2793 work_done = true;
2794 }
2795
2796 /* Update the software queue position index in hardware */
2797 if (work_done)
2798 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2799 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2800 port_mmio + EDMA_RSP_Q_OUT_PTR);
2801 }
2802
2803 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2804 {
2805 struct mv_port_priv *pp;
2806 int edma_was_enabled;
2807
2808 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2809 mv_unexpected_intr(ap, 0);
2810 return;
2811 }
2812 /*
2813 * Grab a snapshot of the EDMA_EN flag setting,
2814 * so that we have a consistent view for this port,
2815 * even if something we call of our routines changes it.
2816 */
2817 pp = ap->private_data;
2818 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2819 /*
2820 * Process completed CRPB response(s) before other events.
2821 */
2822 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2823 mv_process_crpb_entries(ap, pp);
2824 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2825 mv_handle_fbs_ncq_dev_err(ap);
2826 }
2827 /*
2828 * Handle chip-reported errors, or continue on to handle PIO.
2829 */
2830 if (unlikely(port_cause & ERR_IRQ)) {
2831 mv_err_intr(ap);
2832 } else if (!edma_was_enabled) {
2833 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2834 if (qc)
2835 ata_sff_host_intr(ap, qc);
2836 else
2837 mv_unexpected_intr(ap, edma_was_enabled);
2838 }
2839 }
2840
2841 /**
2842 * mv_host_intr - Handle all interrupts on the given host controller
2843 * @host: host specific structure
2844 * @main_irq_cause: Main interrupt cause register for the chip.
2845 *
2846 * LOCKING:
2847 * Inherited from caller.
2848 */
2849 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2850 {
2851 struct mv_host_priv *hpriv = host->private_data;
2852 void __iomem *mmio = hpriv->base, *hc_mmio;
2853 unsigned int handled = 0, port;
2854
2855 /* If asserted, clear the "all ports" IRQ coalescing bit */
2856 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2857 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2858
2859 for (port = 0; port < hpriv->n_ports; port++) {
2860 struct ata_port *ap = host->ports[port];
2861 unsigned int p, shift, hardport, port_cause;
2862
2863 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2864 /*
2865 * Each hc within the host has its own hc_irq_cause register,
2866 * where the interrupting ports bits get ack'd.
2867 */
2868 if (hardport == 0) { /* first port on this hc ? */
2869 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2870 u32 port_mask, ack_irqs;
2871 /*
2872 * Skip this entire hc if nothing pending for any ports
2873 */
2874 if (!hc_cause) {
2875 port += MV_PORTS_PER_HC - 1;
2876 continue;
2877 }
2878 /*
2879 * We don't need/want to read the hc_irq_cause register,
2880 * because doing so hurts performance, and
2881 * main_irq_cause already gives us everything we need.
2882 *
2883 * But we do have to *write* to the hc_irq_cause to ack
2884 * the ports that we are handling this time through.
2885 *
2886 * This requires that we create a bitmap for those
2887 * ports which interrupted us, and use that bitmap
2888 * to ack (only) those ports via hc_irq_cause.
2889 */
2890 ack_irqs = 0;
2891 if (hc_cause & PORTS_0_3_COAL_DONE)
2892 ack_irqs = HC_COAL_IRQ;
2893 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2894 if ((port + p) >= hpriv->n_ports)
2895 break;
2896 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2897 if (hc_cause & port_mask)
2898 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2899 }
2900 hc_mmio = mv_hc_base_from_port(mmio, port);
2901 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2902 handled = 1;
2903 }
2904 /*
2905 * Handle interrupts signalled for this port:
2906 */
2907 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2908 if (port_cause)
2909 mv_port_intr(ap, port_cause);
2910 }
2911 return handled;
2912 }
2913
2914 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2915 {
2916 struct mv_host_priv *hpriv = host->private_data;
2917 struct ata_port *ap;
2918 struct ata_queued_cmd *qc;
2919 struct ata_eh_info *ehi;
2920 unsigned int i, err_mask, printed = 0;
2921 u32 err_cause;
2922
2923 err_cause = readl(mmio + hpriv->irq_cause_offset);
2924
2925 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2926 err_cause);
2927
2928 DPRINTK("All regs @ PCI error\n");
2929 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2930
2931 writelfl(0, mmio + hpriv->irq_cause_offset);
2932
2933 for (i = 0; i < host->n_ports; i++) {
2934 ap = host->ports[i];
2935 if (!ata_link_offline(&ap->link)) {
2936 ehi = &ap->link.eh_info;
2937 ata_ehi_clear_desc(ehi);
2938 if (!printed++)
2939 ata_ehi_push_desc(ehi,
2940 "PCI err cause 0x%08x", err_cause);
2941 err_mask = AC_ERR_HOST_BUS;
2942 ehi->action = ATA_EH_RESET;
2943 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2944 if (qc)
2945 qc->err_mask |= err_mask;
2946 else
2947 ehi->err_mask |= err_mask;
2948
2949 ata_port_freeze(ap);
2950 }
2951 }
2952 return 1; /* handled */
2953 }
2954
2955 /**
2956 * mv_interrupt - Main interrupt event handler
2957 * @irq: unused
2958 * @dev_instance: private data; in this case the host structure
2959 *
2960 * Read the read only register to determine if any host
2961 * controllers have pending interrupts. If so, call lower level
2962 * routine to handle. Also check for PCI errors which are only
2963 * reported here.
2964 *
2965 * LOCKING:
2966 * This routine holds the host lock while processing pending
2967 * interrupts.
2968 */
2969 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2970 {
2971 struct ata_host *host = dev_instance;
2972 struct mv_host_priv *hpriv = host->private_data;
2973 unsigned int handled = 0;
2974 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2975 u32 main_irq_cause, pending_irqs;
2976
2977 spin_lock(&host->lock);
2978
2979 /* for MSI: block new interrupts while in here */
2980 if (using_msi)
2981 mv_write_main_irq_mask(0, hpriv);
2982
2983 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2984 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2985 /*
2986 * Deal with cases where we either have nothing pending, or have read
2987 * a bogus register value which can indicate HW removal or PCI fault.
2988 */
2989 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2990 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2991 handled = mv_pci_error(host, hpriv->base);
2992 else
2993 handled = mv_host_intr(host, pending_irqs);
2994 }
2995
2996 /* for MSI: unmask; interrupt cause bits will retrigger now */
2997 if (using_msi)
2998 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2999
3000 spin_unlock(&host->lock);
3001
3002 return IRQ_RETVAL(handled);
3003 }
3004
3005 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3006 {
3007 unsigned int ofs;
3008
3009 switch (sc_reg_in) {
3010 case SCR_STATUS:
3011 case SCR_ERROR:
3012 case SCR_CONTROL:
3013 ofs = sc_reg_in * sizeof(u32);
3014 break;
3015 default:
3016 ofs = 0xffffffffU;
3017 break;
3018 }
3019 return ofs;
3020 }
3021
3022 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
3023 {
3024 struct mv_host_priv *hpriv = link->ap->host->private_data;
3025 void __iomem *mmio = hpriv->base;
3026 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3027 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3028
3029 if (ofs != 0xffffffffU) {
3030 *val = readl(addr + ofs);
3031 return 0;
3032 } else
3033 return -EINVAL;
3034 }
3035
3036 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3037 {
3038 struct mv_host_priv *hpriv = link->ap->host->private_data;
3039 void __iomem *mmio = hpriv->base;
3040 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3041 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3042
3043 if (ofs != 0xffffffffU) {
3044 writelfl(val, addr + ofs);
3045 return 0;
3046 } else
3047 return -EINVAL;
3048 }
3049
3050 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3051 {
3052 struct pci_dev *pdev = to_pci_dev(host->dev);
3053 int early_5080;
3054
3055 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3056
3057 if (!early_5080) {
3058 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3059 tmp |= (1 << 0);
3060 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3061 }
3062
3063 mv_reset_pci_bus(host, mmio);
3064 }
3065
3066 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3067 {
3068 writel(0x0fcfffff, mmio + FLASH_CTL);
3069 }
3070
3071 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3072 void __iomem *mmio)
3073 {
3074 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3075 u32 tmp;
3076
3077 tmp = readl(phy_mmio + MV5_PHY_MODE);
3078
3079 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3080 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3081 }
3082
3083 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3084 {
3085 u32 tmp;
3086
3087 writel(0, mmio + GPIO_PORT_CTL);
3088
3089 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3090
3091 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3092 tmp |= ~(1 << 0);
3093 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3094 }
3095
3096 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3097 unsigned int port)
3098 {
3099 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3100 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3101 u32 tmp;
3102 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3103
3104 if (fix_apm_sq) {
3105 tmp = readl(phy_mmio + MV5_LTMODE);
3106 tmp |= (1 << 19);
3107 writel(tmp, phy_mmio + MV5_LTMODE);
3108
3109 tmp = readl(phy_mmio + MV5_PHY_CTL);
3110 tmp &= ~0x3;
3111 tmp |= 0x1;
3112 writel(tmp, phy_mmio + MV5_PHY_CTL);
3113 }
3114
3115 tmp = readl(phy_mmio + MV5_PHY_MODE);
3116 tmp &= ~mask;
3117 tmp |= hpriv->signal[port].pre;
3118 tmp |= hpriv->signal[port].amps;
3119 writel(tmp, phy_mmio + MV5_PHY_MODE);
3120 }
3121
3122
3123 #undef ZERO
3124 #define ZERO(reg) writel(0, port_mmio + (reg))
3125 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3126 unsigned int port)
3127 {
3128 void __iomem *port_mmio = mv_port_base(mmio, port);
3129
3130 mv_reset_channel(hpriv, mmio, port);
3131
3132 ZERO(0x028); /* command */
3133 writel(0x11f, port_mmio + EDMA_CFG);
3134 ZERO(0x004); /* timer */
3135 ZERO(0x008); /* irq err cause */
3136 ZERO(0x00c); /* irq err mask */
3137 ZERO(0x010); /* rq bah */
3138 ZERO(0x014); /* rq inp */
3139 ZERO(0x018); /* rq outp */
3140 ZERO(0x01c); /* respq bah */
3141 ZERO(0x024); /* respq outp */
3142 ZERO(0x020); /* respq inp */
3143 ZERO(0x02c); /* test control */
3144 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3145 }
3146 #undef ZERO
3147
3148 #define ZERO(reg) writel(0, hc_mmio + (reg))
3149 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3150 unsigned int hc)
3151 {
3152 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3153 u32 tmp;
3154
3155 ZERO(0x00c);
3156 ZERO(0x010);
3157 ZERO(0x014);
3158 ZERO(0x018);
3159
3160 tmp = readl(hc_mmio + 0x20);
3161 tmp &= 0x1c1c1c1c;
3162 tmp |= 0x03030303;
3163 writel(tmp, hc_mmio + 0x20);
3164 }
3165 #undef ZERO
3166
3167 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3168 unsigned int n_hc)
3169 {
3170 unsigned int hc, port;
3171
3172 for (hc = 0; hc < n_hc; hc++) {
3173 for (port = 0; port < MV_PORTS_PER_HC; port++)
3174 mv5_reset_hc_port(hpriv, mmio,
3175 (hc * MV_PORTS_PER_HC) + port);
3176
3177 mv5_reset_one_hc(hpriv, mmio, hc);
3178 }
3179
3180 return 0;
3181 }
3182
3183 #undef ZERO
3184 #define ZERO(reg) writel(0, mmio + (reg))
3185 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3186 {
3187 struct mv_host_priv *hpriv = host->private_data;
3188 u32 tmp;
3189
3190 tmp = readl(mmio + MV_PCI_MODE);
3191 tmp &= 0xff00ffff;
3192 writel(tmp, mmio + MV_PCI_MODE);
3193
3194 ZERO(MV_PCI_DISC_TIMER);
3195 ZERO(MV_PCI_MSI_TRIGGER);
3196 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3197 ZERO(MV_PCI_SERR_MASK);
3198 ZERO(hpriv->irq_cause_offset);
3199 ZERO(hpriv->irq_mask_offset);
3200 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3201 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3202 ZERO(MV_PCI_ERR_ATTRIBUTE);
3203 ZERO(MV_PCI_ERR_COMMAND);
3204 }
3205 #undef ZERO
3206
3207 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3208 {
3209 u32 tmp;
3210
3211 mv5_reset_flash(hpriv, mmio);
3212
3213 tmp = readl(mmio + GPIO_PORT_CTL);
3214 tmp &= 0x3;
3215 tmp |= (1 << 5) | (1 << 6);
3216 writel(tmp, mmio + GPIO_PORT_CTL);
3217 }
3218
3219 /**
3220 * mv6_reset_hc - Perform the 6xxx global soft reset
3221 * @mmio: base address of the HBA
3222 *
3223 * This routine only applies to 6xxx parts.
3224 *
3225 * LOCKING:
3226 * Inherited from caller.
3227 */
3228 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3229 unsigned int n_hc)
3230 {
3231 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3232 int i, rc = 0;
3233 u32 t;
3234
3235 /* Following procedure defined in PCI "main command and status
3236 * register" table.
3237 */
3238 t = readl(reg);
3239 writel(t | STOP_PCI_MASTER, reg);
3240
3241 for (i = 0; i < 1000; i++) {
3242 udelay(1);
3243 t = readl(reg);
3244 if (PCI_MASTER_EMPTY & t)
3245 break;
3246 }
3247 if (!(PCI_MASTER_EMPTY & t)) {
3248 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3249 rc = 1;
3250 goto done;
3251 }
3252
3253 /* set reset */
3254 i = 5;
3255 do {
3256 writel(t | GLOB_SFT_RST, reg);
3257 t = readl(reg);
3258 udelay(1);
3259 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3260
3261 if (!(GLOB_SFT_RST & t)) {
3262 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3263 rc = 1;
3264 goto done;
3265 }
3266
3267 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3268 i = 5;
3269 do {
3270 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3271 t = readl(reg);
3272 udelay(1);
3273 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3274
3275 if (GLOB_SFT_RST & t) {
3276 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3277 rc = 1;
3278 }
3279 done:
3280 return rc;
3281 }
3282
3283 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3284 void __iomem *mmio)
3285 {
3286 void __iomem *port_mmio;
3287 u32 tmp;
3288
3289 tmp = readl(mmio + RESET_CFG);
3290 if ((tmp & (1 << 0)) == 0) {
3291 hpriv->signal[idx].amps = 0x7 << 8;
3292 hpriv->signal[idx].pre = 0x1 << 5;
3293 return;
3294 }
3295
3296 port_mmio = mv_port_base(mmio, idx);
3297 tmp = readl(port_mmio + PHY_MODE2);
3298
3299 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3300 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3301 }
3302
3303 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3304 {
3305 writel(0x00000060, mmio + GPIO_PORT_CTL);
3306 }
3307
3308 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3309 unsigned int port)
3310 {
3311 void __iomem *port_mmio = mv_port_base(mmio, port);
3312
3313 u32 hp_flags = hpriv->hp_flags;
3314 int fix_phy_mode2 =
3315 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3316 int fix_phy_mode4 =
3317 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3318 u32 m2, m3;
3319
3320 if (fix_phy_mode2) {
3321 m2 = readl(port_mmio + PHY_MODE2);
3322 m2 &= ~(1 << 16);
3323 m2 |= (1 << 31);
3324 writel(m2, port_mmio + PHY_MODE2);
3325
3326 udelay(200);
3327
3328 m2 = readl(port_mmio + PHY_MODE2);
3329 m2 &= ~((1 << 16) | (1 << 31));
3330 writel(m2, port_mmio + PHY_MODE2);
3331
3332 udelay(200);
3333 }
3334
3335 /*
3336 * Gen-II/IIe PHY_MODE3 errata RM#2:
3337 * Achieves better receiver noise performance than the h/w default:
3338 */
3339 m3 = readl(port_mmio + PHY_MODE3);
3340 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3341
3342 /* Guideline 88F5182 (GL# SATA-S11) */
3343 if (IS_SOC(hpriv))
3344 m3 &= ~0x1c;
3345
3346 if (fix_phy_mode4) {
3347 u32 m4 = readl(port_mmio + PHY_MODE4);
3348 /*
3349 * Enforce reserved-bit restrictions on GenIIe devices only.
3350 * For earlier chipsets, force only the internal config field
3351 * (workaround for errata FEr SATA#10 part 1).
3352 */
3353 if (IS_GEN_IIE(hpriv))
3354 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3355 else
3356 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3357 writel(m4, port_mmio + PHY_MODE4);
3358 }
3359 /*
3360 * Workaround for 60x1-B2 errata SATA#13:
3361 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3362 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3363 * Or ensure we use writelfl() when writing PHY_MODE4.
3364 */
3365 writel(m3, port_mmio + PHY_MODE3);
3366
3367 /* Revert values of pre-emphasis and signal amps to the saved ones */
3368 m2 = readl(port_mmio + PHY_MODE2);
3369
3370 m2 &= ~MV_M2_PREAMP_MASK;
3371 m2 |= hpriv->signal[port].amps;
3372 m2 |= hpriv->signal[port].pre;
3373 m2 &= ~(1 << 16);
3374
3375 /* according to mvSata 3.6.1, some IIE values are fixed */
3376 if (IS_GEN_IIE(hpriv)) {
3377 m2 &= ~0xC30FF01F;
3378 m2 |= 0x0000900F;
3379 }
3380
3381 writel(m2, port_mmio + PHY_MODE2);
3382 }
3383
3384 /* TODO: use the generic LED interface to configure the SATA Presence */
3385 /* & Acitivy LEDs on the board */
3386 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3387 void __iomem *mmio)
3388 {
3389 return;
3390 }
3391
3392 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3393 void __iomem *mmio)
3394 {
3395 void __iomem *port_mmio;
3396 u32 tmp;
3397
3398 port_mmio = mv_port_base(mmio, idx);
3399 tmp = readl(port_mmio + PHY_MODE2);
3400
3401 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3402 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3403 }
3404
3405 #undef ZERO
3406 #define ZERO(reg) writel(0, port_mmio + (reg))
3407 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3408 void __iomem *mmio, unsigned int port)
3409 {
3410 void __iomem *port_mmio = mv_port_base(mmio, port);
3411
3412 mv_reset_channel(hpriv, mmio, port);
3413
3414 ZERO(0x028); /* command */
3415 writel(0x101f, port_mmio + EDMA_CFG);
3416 ZERO(0x004); /* timer */
3417 ZERO(0x008); /* irq err cause */
3418 ZERO(0x00c); /* irq err mask */
3419 ZERO(0x010); /* rq bah */
3420 ZERO(0x014); /* rq inp */
3421 ZERO(0x018); /* rq outp */
3422 ZERO(0x01c); /* respq bah */
3423 ZERO(0x024); /* respq outp */
3424 ZERO(0x020); /* respq inp */
3425 ZERO(0x02c); /* test control */
3426 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3427 }
3428
3429 #undef ZERO
3430
3431 #define ZERO(reg) writel(0, hc_mmio + (reg))
3432 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3433 void __iomem *mmio)
3434 {
3435 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3436
3437 ZERO(0x00c);
3438 ZERO(0x010);
3439 ZERO(0x014);
3440
3441 }
3442
3443 #undef ZERO
3444
3445 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3446 void __iomem *mmio, unsigned int n_hc)
3447 {
3448 unsigned int port;
3449
3450 for (port = 0; port < hpriv->n_ports; port++)
3451 mv_soc_reset_hc_port(hpriv, mmio, port);
3452
3453 mv_soc_reset_one_hc(hpriv, mmio);
3454
3455 return 0;
3456 }
3457
3458 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3459 void __iomem *mmio)
3460 {
3461 return;
3462 }
3463
3464 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3465 {
3466 return;
3467 }
3468
3469 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3470 void __iomem *mmio, unsigned int port)
3471 {
3472 void __iomem *port_mmio = mv_port_base(mmio, port);
3473 u32 reg;
3474
3475 reg = readl(port_mmio + PHY_MODE3);
3476 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3477 reg |= (0x1 << 27);
3478 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3479 reg |= (0x1 << 29);
3480 writel(reg, port_mmio + PHY_MODE3);
3481
3482 reg = readl(port_mmio + PHY_MODE4);
3483 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3484 reg |= (0x1 << 16);
3485 writel(reg, port_mmio + PHY_MODE4);
3486
3487 reg = readl(port_mmio + PHY_MODE9_GEN2);
3488 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3489 reg |= 0x8;
3490 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3491 writel(reg, port_mmio + PHY_MODE9_GEN2);
3492
3493 reg = readl(port_mmio + PHY_MODE9_GEN1);
3494 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3495 reg |= 0x8;
3496 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3497 writel(reg, port_mmio + PHY_MODE9_GEN1);
3498 }
3499
3500 /**
3501 * soc_is_65 - check if the soc is 65 nano device
3502 *
3503 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3504 * register, this register should contain non-zero value and it exists only
3505 * in the 65 nano devices, when reading it from older devices we get 0.
3506 */
3507 static bool soc_is_65n(struct mv_host_priv *hpriv)
3508 {
3509 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3510
3511 if (readl(port0_mmio + PHYCFG_OFS))
3512 return true;
3513 return false;
3514 }
3515
3516 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3517 {
3518 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3519
3520 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3521 if (want_gen2i)
3522 ifcfg |= (1 << 7); /* enable gen2i speed */
3523 writelfl(ifcfg, port_mmio + SATA_IFCFG);
3524 }
3525
3526 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3527 unsigned int port_no)
3528 {
3529 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3530
3531 /*
3532 * The datasheet warns against setting EDMA_RESET when EDMA is active
3533 * (but doesn't say what the problem might be). So we first try
3534 * to disable the EDMA engine before doing the EDMA_RESET operation.
3535 */
3536 mv_stop_edma_engine(port_mmio);
3537 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3538
3539 if (!IS_GEN_I(hpriv)) {
3540 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3541 mv_setup_ifcfg(port_mmio, 1);
3542 }
3543 /*
3544 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3545 * link, and physical layers. It resets all SATA interface registers
3546 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3547 */
3548 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3549 udelay(25); /* allow reset propagation */
3550 writelfl(0, port_mmio + EDMA_CMD);
3551
3552 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3553
3554 if (IS_GEN_I(hpriv))
3555 mdelay(1);
3556 }
3557
3558 static void mv_pmp_select(struct ata_port *ap, int pmp)
3559 {
3560 if (sata_pmp_supported(ap)) {
3561 void __iomem *port_mmio = mv_ap_base(ap);
3562 u32 reg = readl(port_mmio + SATA_IFCTL);
3563 int old = reg & 0xf;
3564
3565 if (old != pmp) {
3566 reg = (reg & ~0xf) | pmp;
3567 writelfl(reg, port_mmio + SATA_IFCTL);
3568 }
3569 }
3570 }
3571
3572 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3573 unsigned long deadline)
3574 {
3575 mv_pmp_select(link->ap, sata_srst_pmp(link));
3576 return sata_std_hardreset(link, class, deadline);
3577 }
3578
3579 static int mv_softreset(struct ata_link *link, unsigned int *class,
3580 unsigned long deadline)
3581 {
3582 mv_pmp_select(link->ap, sata_srst_pmp(link));
3583 return ata_sff_softreset(link, class, deadline);
3584 }
3585
3586 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3587 unsigned long deadline)
3588 {
3589 struct ata_port *ap = link->ap;
3590 struct mv_host_priv *hpriv = ap->host->private_data;
3591 struct mv_port_priv *pp = ap->private_data;
3592 void __iomem *mmio = hpriv->base;
3593 int rc, attempts = 0, extra = 0;
3594 u32 sstatus;
3595 bool online;
3596
3597 mv_reset_channel(hpriv, mmio, ap->port_no);
3598 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3599 pp->pp_flags &=
3600 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3601
3602 /* Workaround for errata FEr SATA#10 (part 2) */
3603 do {
3604 const unsigned long *timing =
3605 sata_ehc_deb_timing(&link->eh_context);
3606
3607 rc = sata_link_hardreset(link, timing, deadline + extra,
3608 &online, NULL);
3609 rc = online ? -EAGAIN : rc;
3610 if (rc)
3611 return rc;
3612 sata_scr_read(link, SCR_STATUS, &sstatus);
3613 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3614 /* Force 1.5gb/s link speed and try again */
3615 mv_setup_ifcfg(mv_ap_base(ap), 0);
3616 if (time_after(jiffies + HZ, deadline))
3617 extra = HZ; /* only extend it once, max */
3618 }
3619 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3620 mv_save_cached_regs(ap);
3621 mv_edma_cfg(ap, 0, 0);
3622
3623 return rc;
3624 }
3625
3626 static void mv_eh_freeze(struct ata_port *ap)
3627 {
3628 mv_stop_edma(ap);
3629 mv_enable_port_irqs(ap, 0);
3630 }
3631
3632 static void mv_eh_thaw(struct ata_port *ap)
3633 {
3634 struct mv_host_priv *hpriv = ap->host->private_data;
3635 unsigned int port = ap->port_no;
3636 unsigned int hardport = mv_hardport_from_port(port);
3637 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3638 void __iomem *port_mmio = mv_ap_base(ap);
3639 u32 hc_irq_cause;
3640
3641 /* clear EDMA errors on this port */
3642 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3643
3644 /* clear pending irq events */
3645 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3646 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3647
3648 mv_enable_port_irqs(ap, ERR_IRQ);
3649 }
3650
3651 /**
3652 * mv_port_init - Perform some early initialization on a single port.
3653 * @port: libata data structure storing shadow register addresses
3654 * @port_mmio: base address of the port
3655 *
3656 * Initialize shadow register mmio addresses, clear outstanding
3657 * interrupts on the port, and unmask interrupts for the future
3658 * start of the port.
3659 *
3660 * LOCKING:
3661 * Inherited from caller.
3662 */
3663 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3664 {
3665 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3666
3667 /* PIO related setup
3668 */
3669 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3670 port->error_addr =
3671 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3672 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3673 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3674 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3675 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3676 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3677 port->status_addr =
3678 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3679 /* special case: control/altstatus doesn't have ATA_REG_ address */
3680 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3681
3682 /* unused: */
3683 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3684
3685 /* Clear any currently outstanding port interrupt conditions */
3686 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3687 writelfl(readl(serr), serr);
3688 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3689
3690 /* unmask all non-transient EDMA error interrupts */
3691 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3692
3693 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3694 readl(port_mmio + EDMA_CFG),
3695 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3696 readl(port_mmio + EDMA_ERR_IRQ_MASK));
3697 }
3698
3699 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3700 {
3701 struct mv_host_priv *hpriv = host->private_data;
3702 void __iomem *mmio = hpriv->base;
3703 u32 reg;
3704
3705 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3706 return 0; /* not PCI-X capable */
3707 reg = readl(mmio + MV_PCI_MODE);
3708 if ((reg & MV_PCI_MODE_MASK) == 0)
3709 return 0; /* conventional PCI mode */
3710 return 1; /* chip is in PCI-X mode */
3711 }
3712
3713 static int mv_pci_cut_through_okay(struct ata_host *host)
3714 {
3715 struct mv_host_priv *hpriv = host->private_data;
3716 void __iomem *mmio = hpriv->base;
3717 u32 reg;
3718
3719 if (!mv_in_pcix_mode(host)) {
3720 reg = readl(mmio + MV_PCI_COMMAND);
3721 if (reg & MV_PCI_COMMAND_MRDTRIG)
3722 return 0; /* not okay */
3723 }
3724 return 1; /* okay */
3725 }
3726
3727 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3728 {
3729 struct mv_host_priv *hpriv = host->private_data;
3730 void __iomem *mmio = hpriv->base;
3731
3732 /* workaround for 60x1-B2 errata PCI#7 */
3733 if (mv_in_pcix_mode(host)) {
3734 u32 reg = readl(mmio + MV_PCI_COMMAND);
3735 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3736 }
3737 }
3738
3739 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3740 {
3741 struct pci_dev *pdev = to_pci_dev(host->dev);
3742 struct mv_host_priv *hpriv = host->private_data;
3743 u32 hp_flags = hpriv->hp_flags;
3744
3745 switch (board_idx) {
3746 case chip_5080:
3747 hpriv->ops = &mv5xxx_ops;
3748 hp_flags |= MV_HP_GEN_I;
3749
3750 switch (pdev->revision) {
3751 case 0x1:
3752 hp_flags |= MV_HP_ERRATA_50XXB0;
3753 break;
3754 case 0x3:
3755 hp_flags |= MV_HP_ERRATA_50XXB2;
3756 break;
3757 default:
3758 dev_printk(KERN_WARNING, &pdev->dev,
3759 "Applying 50XXB2 workarounds to unknown rev\n");
3760 hp_flags |= MV_HP_ERRATA_50XXB2;
3761 break;
3762 }
3763 break;
3764
3765 case chip_504x:
3766 case chip_508x:
3767 hpriv->ops = &mv5xxx_ops;
3768 hp_flags |= MV_HP_GEN_I;
3769
3770 switch (pdev->revision) {
3771 case 0x0:
3772 hp_flags |= MV_HP_ERRATA_50XXB0;
3773 break;
3774 case 0x3:
3775 hp_flags |= MV_HP_ERRATA_50XXB2;
3776 break;
3777 default:
3778 dev_printk(KERN_WARNING, &pdev->dev,
3779 "Applying B2 workarounds to unknown rev\n");
3780 hp_flags |= MV_HP_ERRATA_50XXB2;
3781 break;
3782 }
3783 break;
3784
3785 case chip_604x:
3786 case chip_608x:
3787 hpriv->ops = &mv6xxx_ops;
3788 hp_flags |= MV_HP_GEN_II;
3789
3790 switch (pdev->revision) {
3791 case 0x7:
3792 mv_60x1b2_errata_pci7(host);
3793 hp_flags |= MV_HP_ERRATA_60X1B2;
3794 break;
3795 case 0x9:
3796 hp_flags |= MV_HP_ERRATA_60X1C0;
3797 break;
3798 default:
3799 dev_printk(KERN_WARNING, &pdev->dev,
3800 "Applying B2 workarounds to unknown rev\n");
3801 hp_flags |= MV_HP_ERRATA_60X1B2;
3802 break;
3803 }
3804 break;
3805
3806 case chip_7042:
3807 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3808 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3809 (pdev->device == 0x2300 || pdev->device == 0x2310))
3810 {
3811 /*
3812 * Highpoint RocketRAID PCIe 23xx series cards:
3813 *
3814 * Unconfigured drives are treated as "Legacy"
3815 * by the BIOS, and it overwrites sector 8 with
3816 * a "Lgcy" metadata block prior to Linux boot.
3817 *
3818 * Configured drives (RAID or JBOD) leave sector 8
3819 * alone, but instead overwrite a high numbered
3820 * sector for the RAID metadata. This sector can
3821 * be determined exactly, by truncating the physical
3822 * drive capacity to a nice even GB value.
3823 *
3824 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3825 *
3826 * Warn the user, lest they think we're just buggy.
3827 */
3828 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3829 " BIOS CORRUPTS DATA on all attached drives,"
3830 " regardless of if/how they are configured."
3831 " BEWARE!\n");
3832 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3833 " use sectors 8-9 on \"Legacy\" drives,"
3834 " and avoid the final two gigabytes on"
3835 " all RocketRAID BIOS initialized drives.\n");
3836 }
3837 /* drop through */
3838 case chip_6042:
3839 hpriv->ops = &mv6xxx_ops;
3840 hp_flags |= MV_HP_GEN_IIE;
3841 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3842 hp_flags |= MV_HP_CUT_THROUGH;
3843
3844 switch (pdev->revision) {
3845 case 0x2: /* Rev.B0: the first/only public release */
3846 hp_flags |= MV_HP_ERRATA_60X1C0;
3847 break;
3848 default:
3849 dev_printk(KERN_WARNING, &pdev->dev,
3850 "Applying 60X1C0 workarounds to unknown rev\n");
3851 hp_flags |= MV_HP_ERRATA_60X1C0;
3852 break;
3853 }
3854 break;
3855 case chip_soc:
3856 if (soc_is_65n(hpriv))
3857 hpriv->ops = &mv_soc_65n_ops;
3858 else
3859 hpriv->ops = &mv_soc_ops;
3860 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3861 MV_HP_ERRATA_60X1C0;
3862 break;
3863
3864 default:
3865 dev_printk(KERN_ERR, host->dev,
3866 "BUG: invalid board index %u\n", board_idx);
3867 return 1;
3868 }
3869
3870 hpriv->hp_flags = hp_flags;
3871 if (hp_flags & MV_HP_PCIE) {
3872 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3873 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3874 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3875 } else {
3876 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3877 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3878 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3879 }
3880
3881 return 0;
3882 }
3883
3884 /**
3885 * mv_init_host - Perform some early initialization of the host.
3886 * @host: ATA host to initialize
3887 * @board_idx: controller index
3888 *
3889 * If possible, do an early global reset of the host. Then do
3890 * our port init and clear/unmask all/relevant host interrupts.
3891 *
3892 * LOCKING:
3893 * Inherited from caller.
3894 */
3895 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3896 {
3897 int rc = 0, n_hc, port, hc;
3898 struct mv_host_priv *hpriv = host->private_data;
3899 void __iomem *mmio = hpriv->base;
3900
3901 rc = mv_chip_id(host, board_idx);
3902 if (rc)
3903 goto done;
3904
3905 if (IS_SOC(hpriv)) {
3906 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3907 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3908 } else {
3909 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3910 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3911 }
3912
3913 /* initialize shadow irq mask with register's value */
3914 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3915
3916 /* global interrupt mask: 0 == mask everything */
3917 mv_set_main_irq_mask(host, ~0, 0);
3918
3919 n_hc = mv_get_hc_count(host->ports[0]->flags);
3920
3921 for (port = 0; port < host->n_ports; port++)
3922 if (hpriv->ops->read_preamp)
3923 hpriv->ops->read_preamp(hpriv, port, mmio);
3924
3925 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3926 if (rc)
3927 goto done;
3928
3929 hpriv->ops->reset_flash(hpriv, mmio);
3930 hpriv->ops->reset_bus(host, mmio);
3931 hpriv->ops->enable_leds(hpriv, mmio);
3932
3933 for (port = 0; port < host->n_ports; port++) {
3934 struct ata_port *ap = host->ports[port];
3935 void __iomem *port_mmio = mv_port_base(mmio, port);
3936
3937 mv_port_init(&ap->ioaddr, port_mmio);
3938
3939 #ifdef CONFIG_PCI
3940 if (!IS_SOC(hpriv)) {
3941 unsigned int offset = port_mmio - mmio;
3942 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3943 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3944 }
3945 #endif
3946 }
3947
3948 for (hc = 0; hc < n_hc; hc++) {
3949 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3950
3951 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3952 "(before clear)=0x%08x\n", hc,
3953 readl(hc_mmio + HC_CFG),
3954 readl(hc_mmio + HC_IRQ_CAUSE));
3955
3956 /* Clear any currently outstanding hc interrupt conditions */
3957 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3958 }
3959
3960 if (!IS_SOC(hpriv)) {
3961 /* Clear any currently outstanding host interrupt conditions */
3962 writelfl(0, mmio + hpriv->irq_cause_offset);
3963
3964 /* and unmask interrupt generation for host regs */
3965 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3966 }
3967
3968 /*
3969 * enable only global host interrupts for now.
3970 * The per-port interrupts get done later as ports are set up.
3971 */
3972 mv_set_main_irq_mask(host, 0, PCI_ERR);
3973 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3974 irq_coalescing_usecs);
3975 done:
3976 return rc;
3977 }
3978
3979 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3980 {
3981 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3982 MV_CRQB_Q_SZ, 0);
3983 if (!hpriv->crqb_pool)
3984 return -ENOMEM;
3985
3986 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3987 MV_CRPB_Q_SZ, 0);
3988 if (!hpriv->crpb_pool)
3989 return -ENOMEM;
3990
3991 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3992 MV_SG_TBL_SZ, 0);
3993 if (!hpriv->sg_tbl_pool)
3994 return -ENOMEM;
3995
3996 return 0;
3997 }
3998
3999 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
4000 struct mbus_dram_target_info *dram)
4001 {
4002 int i;
4003
4004 for (i = 0; i < 4; i++) {
4005 writel(0, hpriv->base + WINDOW_CTRL(i));
4006 writel(0, hpriv->base + WINDOW_BASE(i));
4007 }
4008
4009 for (i = 0; i < dram->num_cs; i++) {
4010 struct mbus_dram_window *cs = dram->cs + i;
4011
4012 writel(((cs->size - 1) & 0xffff0000) |
4013 (cs->mbus_attr << 8) |
4014 (dram->mbus_dram_target_id << 4) | 1,
4015 hpriv->base + WINDOW_CTRL(i));
4016 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4017 }
4018 }
4019
4020 /**
4021 * mv_platform_probe - handle a positive probe of an soc Marvell
4022 * host
4023 * @pdev: platform device found
4024 *
4025 * LOCKING:
4026 * Inherited from caller.
4027 */
4028 static int mv_platform_probe(struct platform_device *pdev)
4029 {
4030 static int printed_version;
4031 const struct mv_sata_platform_data *mv_platform_data;
4032 const struct ata_port_info *ppi[] =
4033 { &mv_port_info[chip_soc], NULL };
4034 struct ata_host *host;
4035 struct mv_host_priv *hpriv;
4036 struct resource *res;
4037 int n_ports, rc;
4038
4039 if (!printed_version++)
4040 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4041
4042 /*
4043 * Simple resource validation ..
4044 */
4045 if (unlikely(pdev->num_resources != 2)) {
4046 dev_err(&pdev->dev, "invalid number of resources\n");
4047 return -EINVAL;
4048 }
4049
4050 /*
4051 * Get the register base first
4052 */
4053 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4054 if (res == NULL)
4055 return -EINVAL;
4056
4057 /* allocate host */
4058 mv_platform_data = pdev->dev.platform_data;
4059 n_ports = mv_platform_data->n_ports;
4060
4061 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4062 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4063
4064 if (!host || !hpriv)
4065 return -ENOMEM;
4066 host->private_data = hpriv;
4067 hpriv->n_ports = n_ports;
4068
4069 host->iomap = NULL;
4070 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4071 resource_size(res));
4072 hpriv->base -= SATAHC0_REG_BASE;
4073
4074 /*
4075 * (Re-)program MBUS remapping windows if we are asked to.
4076 */
4077 if (mv_platform_data->dram != NULL)
4078 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4079
4080 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4081 if (rc)
4082 return rc;
4083
4084 /* initialize adapter */
4085 rc = mv_init_host(host, chip_soc);
4086 if (rc)
4087 return rc;
4088
4089 dev_printk(KERN_INFO, &pdev->dev,
4090 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4091 host->n_ports);
4092
4093 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4094 IRQF_SHARED, &mv6_sht);
4095 }
4096
4097 /*
4098 *
4099 * mv_platform_remove - unplug a platform interface
4100 * @pdev: platform device
4101 *
4102 * A platform bus SATA device has been unplugged. Perform the needed
4103 * cleanup. Also called on module unload for any active devices.
4104 */
4105 static int __devexit mv_platform_remove(struct platform_device *pdev)
4106 {
4107 struct device *dev = &pdev->dev;
4108 struct ata_host *host = dev_get_drvdata(dev);
4109
4110 ata_host_detach(host);
4111 return 0;
4112 }
4113
4114 static struct platform_driver mv_platform_driver = {
4115 .probe = mv_platform_probe,
4116 .remove = __devexit_p(mv_platform_remove),
4117 .driver = {
4118 .name = DRV_NAME,
4119 .owner = THIS_MODULE,
4120 },
4121 };
4122
4123
4124 #ifdef CONFIG_PCI
4125 static int mv_pci_init_one(struct pci_dev *pdev,
4126 const struct pci_device_id *ent);
4127
4128
4129 static struct pci_driver mv_pci_driver = {
4130 .name = DRV_NAME,
4131 .id_table = mv_pci_tbl,
4132 .probe = mv_pci_init_one,
4133 .remove = ata_pci_remove_one,
4134 };
4135
4136 /* move to PCI layer or libata core? */
4137 static int pci_go_64(struct pci_dev *pdev)
4138 {
4139 int rc;
4140
4141 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4142 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4143 if (rc) {
4144 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4145 if (rc) {
4146 dev_printk(KERN_ERR, &pdev->dev,
4147 "64-bit DMA enable failed\n");
4148 return rc;
4149 }
4150 }
4151 } else {
4152 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4153 if (rc) {
4154 dev_printk(KERN_ERR, &pdev->dev,
4155 "32-bit DMA enable failed\n");
4156 return rc;
4157 }
4158 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4159 if (rc) {
4160 dev_printk(KERN_ERR, &pdev->dev,
4161 "32-bit consistent DMA enable failed\n");
4162 return rc;
4163 }
4164 }
4165
4166 return rc;
4167 }
4168
4169 /**
4170 * mv_print_info - Dump key info to kernel log for perusal.
4171 * @host: ATA host to print info about
4172 *
4173 * FIXME: complete this.
4174 *
4175 * LOCKING:
4176 * Inherited from caller.
4177 */
4178 static void mv_print_info(struct ata_host *host)
4179 {
4180 struct pci_dev *pdev = to_pci_dev(host->dev);
4181 struct mv_host_priv *hpriv = host->private_data;
4182 u8 scc;
4183 const char *scc_s, *gen;
4184
4185 /* Use this to determine the HW stepping of the chip so we know
4186 * what errata to workaround
4187 */
4188 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4189 if (scc == 0)
4190 scc_s = "SCSI";
4191 else if (scc == 0x01)
4192 scc_s = "RAID";
4193 else
4194 scc_s = "?";
4195
4196 if (IS_GEN_I(hpriv))
4197 gen = "I";
4198 else if (IS_GEN_II(hpriv))
4199 gen = "II";
4200 else if (IS_GEN_IIE(hpriv))
4201 gen = "IIE";
4202 else
4203 gen = "?";
4204
4205 dev_printk(KERN_INFO, &pdev->dev,
4206 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4207 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4208 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4209 }
4210
4211 /**
4212 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4213 * @pdev: PCI device found
4214 * @ent: PCI device ID entry for the matched host
4215 *
4216 * LOCKING:
4217 * Inherited from caller.
4218 */
4219 static int mv_pci_init_one(struct pci_dev *pdev,
4220 const struct pci_device_id *ent)
4221 {
4222 static int printed_version;
4223 unsigned int board_idx = (unsigned int)ent->driver_data;
4224 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4225 struct ata_host *host;
4226 struct mv_host_priv *hpriv;
4227 int n_ports, rc;
4228
4229 if (!printed_version++)
4230 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4231
4232 /* allocate host */
4233 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4234
4235 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4236 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4237 if (!host || !hpriv)
4238 return -ENOMEM;
4239 host->private_data = hpriv;
4240 hpriv->n_ports = n_ports;
4241
4242 /* acquire resources */
4243 rc = pcim_enable_device(pdev);
4244 if (rc)
4245 return rc;
4246
4247 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4248 if (rc == -EBUSY)
4249 pcim_pin_device(pdev);
4250 if (rc)
4251 return rc;
4252 host->iomap = pcim_iomap_table(pdev);
4253 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4254
4255 rc = pci_go_64(pdev);
4256 if (rc)
4257 return rc;
4258
4259 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4260 if (rc)
4261 return rc;
4262
4263 /* initialize adapter */
4264 rc = mv_init_host(host, board_idx);
4265 if (rc)
4266 return rc;
4267
4268 /* Enable message-switched interrupts, if requested */
4269 if (msi && pci_enable_msi(pdev) == 0)
4270 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4271
4272 mv_dump_pci_cfg(pdev, 0x68);
4273 mv_print_info(host);
4274
4275 pci_set_master(pdev);
4276 pci_try_set_mwi(pdev);
4277 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4278 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4279 }
4280 #endif
4281
4282 static int mv_platform_probe(struct platform_device *pdev);
4283 static int __devexit mv_platform_remove(struct platform_device *pdev);
4284
4285 static int __init mv_init(void)
4286 {
4287 int rc = -ENODEV;
4288 #ifdef CONFIG_PCI
4289 rc = pci_register_driver(&mv_pci_driver);
4290 if (rc < 0)
4291 return rc;
4292 #endif
4293 rc = platform_driver_register(&mv_platform_driver);
4294
4295 #ifdef CONFIG_PCI
4296 if (rc < 0)
4297 pci_unregister_driver(&mv_pci_driver);
4298 #endif
4299 return rc;
4300 }
4301
4302 static void __exit mv_exit(void)
4303 {
4304 #ifdef CONFIG_PCI
4305 pci_unregister_driver(&mv_pci_driver);
4306 #endif
4307 platform_driver_unregister(&mv_platform_driver);
4308 }
4309
4310 MODULE_AUTHOR("Brett Russ");
4311 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4312 MODULE_LICENSE("GPL");
4313 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4314 MODULE_VERSION(DRV_VERSION);
4315 MODULE_ALIAS("platform:" DRV_NAME);
4316
4317 module_init(mv_init);
4318 module_exit(mv_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree