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Documentation: explain [KMG] parameter suffix
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / pch_gbe / pch_gbe_main.c
blobb99e90aca37dc4afa70cfc58195b5d59c90b7b48
1 /*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include "pch_gbe.h"
22 #include "pch_gbe_api.h"
23
24 #define DRV_VERSION "1.00"
25 const char pch_driver_version[] = DRV_VERSION;
26
27 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
28 #define PCH_GBE_MAR_ENTRIES 16
29 #define PCH_GBE_SHORT_PKT 64
30 #define DSC_INIT16 0xC000
31 #define PCH_GBE_DMA_ALIGN 0
32 #define PCH_GBE_DMA_PADDING 2
33 #define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */
34 #define PCH_GBE_COPYBREAK_DEFAULT 256
35 #define PCH_GBE_PCI_BAR 1
36
37 #define PCH_GBE_TX_WEIGHT 64
38 #define PCH_GBE_RX_WEIGHT 64
39 #define PCH_GBE_RX_BUFFER_WRITE 16
40
41 /* Initialize the wake-on-LAN settings */
42 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
43
44 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
45 PCH_GBE_CHIP_TYPE_INTERNAL | \
46 PCH_GBE_RGMII_MODE_RGMII | \
47 PCH_GBE_CRS_SEL \
48 )
49
50 /* Ethertype field values */
51 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
52 #define PCH_GBE_FRAME_SIZE_2048 2048
53 #define PCH_GBE_FRAME_SIZE_4096 4096
54 #define PCH_GBE_FRAME_SIZE_8192 8192
55
56 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
57 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
58 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
59 #define PCH_GBE_DESC_UNUSED(R) \
60 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
61 (R)->next_to_clean - (R)->next_to_use - 1)
62
63 /* Pause packet value */
64 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
65 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
66 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
67 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
68
69 #define PCH_GBE_ETH_ALEN 6
70
71 /* This defines the bits that are set in the Interrupt Mask
72 * Set/Read Register. Each bit is documented below:
73 * o RXT0 = Receiver Timer Interrupt (ring 0)
74 * o TXDW = Transmit Descriptor Written Back
75 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
76 * o RXSEQ = Receive Sequence Error
77 * o LSC = Link Status Change
78 */
79 #define PCH_GBE_INT_ENABLE_MASK ( \
80 PCH_GBE_INT_RX_DMA_CMPLT | \
81 PCH_GBE_INT_RX_DSC_EMP | \
82 PCH_GBE_INT_WOL_DET | \
83 PCH_GBE_INT_TX_CMPLT \
84 )
85
86
87 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
88
89 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
90 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
91 int data);
92
93 inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
94 {
95 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
96 }
97
98 /**
99 * pch_gbe_mac_read_mac_addr - Read MAC address
100 * @hw: Pointer to the HW structure
101 * Returns
102 * 0: Successful.
103 */
104 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
105 {
106 u32 adr1a, adr1b;
107
108 adr1a = ioread32(&hw->reg->mac_adr[0].high);
109 adr1b = ioread32(&hw->reg->mac_adr[0].low);
110
111 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
112 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
113 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
114 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
115 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
116 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
117
118 pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
119 return 0;
120 }
121
122 /**
123 * pch_gbe_wait_clr_bit - Wait to clear a bit
124 * @reg: Pointer of register
125 * @busy: Busy bit
126 */
127 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
128 {
129 u32 tmp;
130 /* wait busy */
131 tmp = 1000;
132 while ((ioread32(reg) & bit) && --tmp)
133 cpu_relax();
134 if (!tmp)
135 pr_err("Error: busy bit is not cleared\n");
136 }
137 /**
138 * pch_gbe_mac_mar_set - Set MAC address register
139 * @hw: Pointer to the HW structure
140 * @addr: Pointer to the MAC address
141 * @index: MAC address array register
142 */
143 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
144 {
145 u32 mar_low, mar_high, adrmask;
146
147 pr_debug("index : 0x%x\n", index);
148
149 /*
150 * HW expects these in little endian so we reverse the byte order
151 * from network order (big endian) to little endian
152 */
153 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
154 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
155 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
156 /* Stop the MAC Address of index. */
157 adrmask = ioread32(&hw->reg->ADDR_MASK);
158 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
159 /* wait busy */
160 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
161 /* Set the MAC address to the MAC address 1A/1B register */
162 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
163 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
164 /* Start the MAC address of index */
165 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
166 /* wait busy */
167 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
168 }
169
170 /**
171 * pch_gbe_mac_reset_hw - Reset hardware
172 * @hw: Pointer to the HW structure
173 */
174 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
175 {
176 /* Read the MAC address. and store to the private data */
177 pch_gbe_mac_read_mac_addr(hw);
178 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
179 #ifdef PCH_GBE_MAC_IFOP_RGMII
180 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
181 #endif
182 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
183 /* Setup the receive address */
184 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
185 return;
186 }
187
188 /**
189 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
190 * @hw: Pointer to the HW structure
191 * @mar_count: Receive address registers
192 */
193 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
194 {
195 u32 i;
196
197 /* Setup the receive address */
198 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
199
200 /* Zero out the other receive addresses */
201 for (i = 1; i < mar_count; i++) {
202 iowrite32(0, &hw->reg->mac_adr[i].high);
203 iowrite32(0, &hw->reg->mac_adr[i].low);
204 }
205 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
206 /* wait busy */
207 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
208 }
209
210
211 /**
212 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
213 * @hw: Pointer to the HW structure
214 * @mc_addr_list: Array of multicast addresses to program
215 * @mc_addr_count: Number of multicast addresses to program
216 * @mar_used_count: The first MAC Address register free to program
217 * @mar_total_num: Total number of supported MAC Address Registers
218 */
219 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
220 u8 *mc_addr_list, u32 mc_addr_count,
221 u32 mar_used_count, u32 mar_total_num)
222 {
223 u32 i, adrmask;
224
225 /* Load the first set of multicast addresses into the exact
226 * filters (RAR). If there are not enough to fill the RAR
227 * array, clear the filters.
228 */
229 for (i = mar_used_count; i < mar_total_num; i++) {
230 if (mc_addr_count) {
231 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
232 mc_addr_count--;
233 mc_addr_list += PCH_GBE_ETH_ALEN;
234 } else {
235 /* Clear MAC address mask */
236 adrmask = ioread32(&hw->reg->ADDR_MASK);
237 iowrite32((adrmask | (0x0001 << i)),
238 &hw->reg->ADDR_MASK);
239 /* wait busy */
240 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
241 /* Clear MAC address */
242 iowrite32(0, &hw->reg->mac_adr[i].high);
243 iowrite32(0, &hw->reg->mac_adr[i].low);
244 }
245 }
246 }
247
248 /**
249 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
250 * @hw: Pointer to the HW structure
251 * Returns
252 * 0: Successful.
253 * Negative value: Failed.
254 */
255 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
256 {
257 struct pch_gbe_mac_info *mac = &hw->mac;
258 u32 rx_fctrl;
259
260 pr_debug("mac->fc = %u\n", mac->fc);
261
262 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
263
264 switch (mac->fc) {
265 case PCH_GBE_FC_NONE:
266 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
267 mac->tx_fc_enable = false;
268 break;
269 case PCH_GBE_FC_RX_PAUSE:
270 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
271 mac->tx_fc_enable = false;
272 break;
273 case PCH_GBE_FC_TX_PAUSE:
274 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
275 mac->tx_fc_enable = true;
276 break;
277 case PCH_GBE_FC_FULL:
278 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
279 mac->tx_fc_enable = true;
280 break;
281 default:
282 pr_err("Flow control param set incorrectly\n");
283 return -EINVAL;
284 }
285 if (mac->link_duplex == DUPLEX_HALF)
286 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
287 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
288 pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
289 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
290 return 0;
291 }
292
293 /**
294 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
295 * @hw: Pointer to the HW structure
296 * @wu_evt: Wake up event
297 */
298 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
299 {
300 u32 addr_mask;
301
302 pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
303 wu_evt, ioread32(&hw->reg->ADDR_MASK));
304
305 if (wu_evt) {
306 /* Set Wake-On-Lan address mask */
307 addr_mask = ioread32(&hw->reg->ADDR_MASK);
308 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
309 /* wait busy */
310 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
311 iowrite32(0, &hw->reg->WOL_ST);
312 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
313 iowrite32(0x02, &hw->reg->TCPIP_ACC);
314 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
315 } else {
316 iowrite32(0, &hw->reg->WOL_CTRL);
317 iowrite32(0, &hw->reg->WOL_ST);
318 }
319 return;
320 }
321
322 /**
323 * pch_gbe_mac_ctrl_miim - Control MIIM interface
324 * @hw: Pointer to the HW structure
325 * @addr: Address of PHY
326 * @dir: Operetion. (Write or Read)
327 * @reg: Access register of PHY
328 * @data: Write data.
329 *
330 * Returns: Read date.
331 */
332 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
333 u16 data)
334 {
335 u32 data_out = 0;
336 unsigned int i;
337 unsigned long flags;
338
339 spin_lock_irqsave(&hw->miim_lock, flags);
340
341 for (i = 100; i; --i) {
342 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
343 break;
344 udelay(20);
345 }
346 if (i == 0) {
347 pr_err("pch-gbe.miim won't go Ready\n");
348 spin_unlock_irqrestore(&hw->miim_lock, flags);
349 return 0; /* No way to indicate timeout error */
350 }
351 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
352 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
353 dir | data), &hw->reg->MIIM);
354 for (i = 0; i < 100; i++) {
355 udelay(20);
356 data_out = ioread32(&hw->reg->MIIM);
357 if ((data_out & PCH_GBE_MIIM_OPER_READY))
358 break;
359 }
360 spin_unlock_irqrestore(&hw->miim_lock, flags);
361
362 pr_debug("PHY %s: reg=%d, data=0x%04X\n",
363 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
364 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
365 return (u16) data_out;
366 }
367
368 /**
369 * pch_gbe_mac_set_pause_packet - Set pause packet
370 * @hw: Pointer to the HW structure
371 */
372 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
373 {
374 unsigned long tmp2, tmp3;
375
376 /* Set Pause packet */
377 tmp2 = hw->mac.addr[1];
378 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
379 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
380
381 tmp3 = hw->mac.addr[5];
382 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
383 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
384 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
385
386 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
387 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
388 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
389 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
390 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
391
392 /* Transmit Pause Packet */
393 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
394
395 pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
396 ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
397 ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
398 ioread32(&hw->reg->PAUSE_PKT5));
399
400 return;
401 }
402
403
404 /**
405 * pch_gbe_alloc_queues - Allocate memory for all rings
406 * @adapter: Board private structure to initialize
407 * Returns
408 * 0: Successfully
409 * Negative value: Failed
410 */
411 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
412 {
413 int size;
414
415 size = (int)sizeof(struct pch_gbe_tx_ring);
416 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
417 if (!adapter->tx_ring)
418 return -ENOMEM;
419 size = (int)sizeof(struct pch_gbe_rx_ring);
420 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
421 if (!adapter->rx_ring) {
422 kfree(adapter->tx_ring);
423 return -ENOMEM;
424 }
425 return 0;
426 }
427
428 /**
429 * pch_gbe_init_stats - Initialize status
430 * @adapter: Board private structure to initialize
431 */
432 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
433 {
434 memset(&adapter->stats, 0, sizeof(adapter->stats));
435 return;
436 }
437
438 /**
439 * pch_gbe_init_phy - Initialize PHY
440 * @adapter: Board private structure to initialize
441 * Returns
442 * 0: Successfully
443 * Negative value: Failed
444 */
445 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
446 {
447 struct net_device *netdev = adapter->netdev;
448 u32 addr;
449 u16 bmcr, stat;
450
451 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
452 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
453 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
454 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
455 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
456 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
457 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
458 break;
459 }
460 adapter->hw.phy.addr = adapter->mii.phy_id;
461 pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
462 if (addr == 32)
463 return -EAGAIN;
464 /* Selected the phy and isolate the rest */
465 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
466 if (addr != adapter->mii.phy_id) {
467 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
468 BMCR_ISOLATE);
469 } else {
470 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
471 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
472 bmcr & ~BMCR_ISOLATE);
473 }
474 }
475
476 /* MII setup */
477 adapter->mii.phy_id_mask = 0x1F;
478 adapter->mii.reg_num_mask = 0x1F;
479 adapter->mii.dev = adapter->netdev;
480 adapter->mii.mdio_read = pch_gbe_mdio_read;
481 adapter->mii.mdio_write = pch_gbe_mdio_write;
482 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
483 return 0;
484 }
485
486 /**
487 * pch_gbe_mdio_read - The read function for mii
488 * @netdev: Network interface device structure
489 * @addr: Phy ID
490 * @reg: Access location
491 * Returns
492 * 0: Successfully
493 * Negative value: Failed
494 */
495 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
496 {
497 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
498 struct pch_gbe_hw *hw = &adapter->hw;
499
500 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
501 (u16) 0);
502 }
503
504 /**
505 * pch_gbe_mdio_write - The write function for mii
506 * @netdev: Network interface device structure
507 * @addr: Phy ID (not used)
508 * @reg: Access location
509 * @data: Write data
510 */
511 static void pch_gbe_mdio_write(struct net_device *netdev,
512 int addr, int reg, int data)
513 {
514 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
515 struct pch_gbe_hw *hw = &adapter->hw;
516
517 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
518 }
519
520 /**
521 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
522 * @work: Pointer of board private structure
523 */
524 static void pch_gbe_reset_task(struct work_struct *work)
525 {
526 struct pch_gbe_adapter *adapter;
527 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
528
529 rtnl_lock();
530 pch_gbe_reinit_locked(adapter);
531 rtnl_unlock();
532 }
533
534 /**
535 * pch_gbe_reinit_locked- Re-initialization
536 * @adapter: Board private structure
537 */
538 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
539 {
540 pch_gbe_down(adapter);
541 pch_gbe_up(adapter);
542 }
543
544 /**
545 * pch_gbe_reset - Reset GbE
546 * @adapter: Board private structure
547 */
548 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
549 {
550 pch_gbe_mac_reset_hw(&adapter->hw);
551 /* Setup the receive address. */
552 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
553 if (pch_gbe_hal_init_hw(&adapter->hw))
554 pr_err("Hardware Error\n");
555 }
556
557 /**
558 * pch_gbe_free_irq - Free an interrupt
559 * @adapter: Board private structure
560 */
561 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
562 {
563 struct net_device *netdev = adapter->netdev;
564
565 free_irq(adapter->pdev->irq, netdev);
566 if (adapter->have_msi) {
567 pci_disable_msi(adapter->pdev);
568 pr_debug("call pci_disable_msi\n");
569 }
570 }
571
572 /**
573 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
574 * @adapter: Board private structure
575 */
576 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
577 {
578 struct pch_gbe_hw *hw = &adapter->hw;
579
580 atomic_inc(&adapter->irq_sem);
581 iowrite32(0, &hw->reg->INT_EN);
582 ioread32(&hw->reg->INT_ST);
583 synchronize_irq(adapter->pdev->irq);
584
585 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
586 }
587
588 /**
589 * pch_gbe_irq_enable - Enable default interrupt generation settings
590 * @adapter: Board private structure
591 */
592 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
593 {
594 struct pch_gbe_hw *hw = &adapter->hw;
595
596 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
597 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
598 ioread32(&hw->reg->INT_ST);
599 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
600 }
601
602
603
604 /**
605 * pch_gbe_setup_tctl - configure the Transmit control registers
606 * @adapter: Board private structure
607 */
608 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
609 {
610 struct pch_gbe_hw *hw = &adapter->hw;
611 u32 tx_mode, tcpip;
612
613 tx_mode = PCH_GBE_TM_LONG_PKT |
614 PCH_GBE_TM_ST_AND_FD |
615 PCH_GBE_TM_SHORT_PKT |
616 PCH_GBE_TM_TH_TX_STRT_8 |
617 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
618
619 iowrite32(tx_mode, &hw->reg->TX_MODE);
620
621 tcpip = ioread32(&hw->reg->TCPIP_ACC);
622 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
623 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
624 return;
625 }
626
627 /**
628 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
629 * @adapter: Board private structure
630 */
631 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
632 {
633 struct pch_gbe_hw *hw = &adapter->hw;
634 u32 tdba, tdlen, dctrl;
635
636 pr_debug("dma addr = 0x%08llx size = 0x%08x\n",
637 (unsigned long long)adapter->tx_ring->dma,
638 adapter->tx_ring->size);
639
640 /* Setup the HW Tx Head and Tail descriptor pointers */
641 tdba = adapter->tx_ring->dma;
642 tdlen = adapter->tx_ring->size - 0x10;
643 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
644 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
645 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
646
647 /* Enables Transmission DMA */
648 dctrl = ioread32(&hw->reg->DMA_CTRL);
649 dctrl |= PCH_GBE_TX_DMA_EN;
650 iowrite32(dctrl, &hw->reg->DMA_CTRL);
651 }
652
653 /**
654 * pch_gbe_setup_rctl - Configure the receive control registers
655 * @adapter: Board private structure
656 */
657 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
658 {
659 struct pch_gbe_hw *hw = &adapter->hw;
660 u32 rx_mode, tcpip;
661
662 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
663 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
664
665 iowrite32(rx_mode, &hw->reg->RX_MODE);
666
667 tcpip = ioread32(&hw->reg->TCPIP_ACC);
668
669 if (adapter->rx_csum) {
670 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
671 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
672 } else {
673 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
674 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
675 }
676 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
677 return;
678 }
679
680 /**
681 * pch_gbe_configure_rx - Configure Receive Unit after Reset
682 * @adapter: Board private structure
683 */
684 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
685 {
686 struct pch_gbe_hw *hw = &adapter->hw;
687 u32 rdba, rdlen, rctl, rxdma;
688
689 pr_debug("dma adr = 0x%08llx size = 0x%08x\n",
690 (unsigned long long)adapter->rx_ring->dma,
691 adapter->rx_ring->size);
692
693 pch_gbe_mac_force_mac_fc(hw);
694
695 /* Disables Receive MAC */
696 rctl = ioread32(&hw->reg->MAC_RX_EN);
697 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
698
699 /* Disables Receive DMA */
700 rxdma = ioread32(&hw->reg->DMA_CTRL);
701 rxdma &= ~PCH_GBE_RX_DMA_EN;
702 iowrite32(rxdma, &hw->reg->DMA_CTRL);
703
704 pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
705 ioread32(&hw->reg->MAC_RX_EN),
706 ioread32(&hw->reg->DMA_CTRL));
707
708 /* Setup the HW Rx Head and Tail Descriptor Pointers and
709 * the Base and Length of the Rx Descriptor Ring */
710 rdba = adapter->rx_ring->dma;
711 rdlen = adapter->rx_ring->size - 0x10;
712 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
713 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
714 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
715
716 /* Enables Receive DMA */
717 rxdma = ioread32(&hw->reg->DMA_CTRL);
718 rxdma |= PCH_GBE_RX_DMA_EN;
719 iowrite32(rxdma, &hw->reg->DMA_CTRL);
720 /* Enables Receive */
721 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
722 }
723
724 /**
725 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
726 * @adapter: Board private structure
727 * @buffer_info: Buffer information structure
728 */
729 static void pch_gbe_unmap_and_free_tx_resource(
730 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
731 {
732 if (buffer_info->mapped) {
733 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
734 buffer_info->length, DMA_TO_DEVICE);
735 buffer_info->mapped = false;
736 }
737 if (buffer_info->skb) {
738 dev_kfree_skb_any(buffer_info->skb);
739 buffer_info->skb = NULL;
740 }
741 }
742
743 /**
744 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
745 * @adapter: Board private structure
746 * @buffer_info: Buffer information structure
747 */
748 static void pch_gbe_unmap_and_free_rx_resource(
749 struct pch_gbe_adapter *adapter,
750 struct pch_gbe_buffer *buffer_info)
751 {
752 if (buffer_info->mapped) {
753 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
754 buffer_info->length, DMA_FROM_DEVICE);
755 buffer_info->mapped = false;
756 }
757 if (buffer_info->skb) {
758 dev_kfree_skb_any(buffer_info->skb);
759 buffer_info->skb = NULL;
760 }
761 }
762
763 /**
764 * pch_gbe_clean_tx_ring - Free Tx Buffers
765 * @adapter: Board private structure
766 * @tx_ring: Ring to be cleaned
767 */
768 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
769 struct pch_gbe_tx_ring *tx_ring)
770 {
771 struct pch_gbe_hw *hw = &adapter->hw;
772 struct pch_gbe_buffer *buffer_info;
773 unsigned long size;
774 unsigned int i;
775
776 /* Free all the Tx ring sk_buffs */
777 for (i = 0; i < tx_ring->count; i++) {
778 buffer_info = &tx_ring->buffer_info[i];
779 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
780 }
781 pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
782
783 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
784 memset(tx_ring->buffer_info, 0, size);
785
786 /* Zero out the descriptor ring */
787 memset(tx_ring->desc, 0, tx_ring->size);
788 tx_ring->next_to_use = 0;
789 tx_ring->next_to_clean = 0;
790 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
791 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
792 }
793
794 /**
795 * pch_gbe_clean_rx_ring - Free Rx Buffers
796 * @adapter: Board private structure
797 * @rx_ring: Ring to free buffers from
798 */
799 static void
800 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
801 struct pch_gbe_rx_ring *rx_ring)
802 {
803 struct pch_gbe_hw *hw = &adapter->hw;
804 struct pch_gbe_buffer *buffer_info;
805 unsigned long size;
806 unsigned int i;
807
808 /* Free all the Rx ring sk_buffs */
809 for (i = 0; i < rx_ring->count; i++) {
810 buffer_info = &rx_ring->buffer_info[i];
811 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
812 }
813 pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
814 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
815 memset(rx_ring->buffer_info, 0, size);
816
817 /* Zero out the descriptor ring */
818 memset(rx_ring->desc, 0, rx_ring->size);
819 rx_ring->next_to_clean = 0;
820 rx_ring->next_to_use = 0;
821 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
822 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
823 }
824
825 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
826 u16 duplex)
827 {
828 struct pch_gbe_hw *hw = &adapter->hw;
829 unsigned long rgmii = 0;
830
831 /* Set the RGMII control. */
832 #ifdef PCH_GBE_MAC_IFOP_RGMII
833 switch (speed) {
834 case SPEED_10:
835 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
836 PCH_GBE_MAC_RGMII_CTRL_SETTING);
837 break;
838 case SPEED_100:
839 rgmii = (PCH_GBE_RGMII_RATE_25M |
840 PCH_GBE_MAC_RGMII_CTRL_SETTING);
841 break;
842 case SPEED_1000:
843 rgmii = (PCH_GBE_RGMII_RATE_125M |
844 PCH_GBE_MAC_RGMII_CTRL_SETTING);
845 break;
846 }
847 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
848 #else /* GMII */
849 rgmii = 0;
850 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
851 #endif
852 }
853 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
854 u16 duplex)
855 {
856 struct net_device *netdev = adapter->netdev;
857 struct pch_gbe_hw *hw = &adapter->hw;
858 unsigned long mode = 0;
859
860 /* Set the communication mode */
861 switch (speed) {
862 case SPEED_10:
863 mode = PCH_GBE_MODE_MII_ETHER;
864 netdev->tx_queue_len = 10;
865 break;
866 case SPEED_100:
867 mode = PCH_GBE_MODE_MII_ETHER;
868 netdev->tx_queue_len = 100;
869 break;
870 case SPEED_1000:
871 mode = PCH_GBE_MODE_GMII_ETHER;
872 break;
873 }
874 if (duplex == DUPLEX_FULL)
875 mode |= PCH_GBE_MODE_FULL_DUPLEX;
876 else
877 mode |= PCH_GBE_MODE_HALF_DUPLEX;
878 iowrite32(mode, &hw->reg->MODE);
879 }
880
881 /**
882 * pch_gbe_watchdog - Watchdog process
883 * @data: Board private structure
884 */
885 static void pch_gbe_watchdog(unsigned long data)
886 {
887 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
888 struct net_device *netdev = adapter->netdev;
889 struct pch_gbe_hw *hw = &adapter->hw;
890 struct ethtool_cmd cmd;
891
892 pr_debug("right now = %ld\n", jiffies);
893
894 pch_gbe_update_stats(adapter);
895 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
896 netdev->tx_queue_len = adapter->tx_queue_len;
897 /* mii library handles link maintenance tasks */
898 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
899 pr_err("ethtool get setting Error\n");
900 mod_timer(&adapter->watchdog_timer,
901 round_jiffies(jiffies +
902 PCH_GBE_WATCHDOG_PERIOD));
903 return;
904 }
905 hw->mac.link_speed = cmd.speed;
906 hw->mac.link_duplex = cmd.duplex;
907 /* Set the RGMII control. */
908 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
909 hw->mac.link_duplex);
910 /* Set the communication mode */
911 pch_gbe_set_mode(adapter, hw->mac.link_speed,
912 hw->mac.link_duplex);
913 netdev_dbg(netdev,
914 "Link is Up %d Mbps %s-Duplex\n",
915 cmd.speed,
916 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
917 netif_carrier_on(netdev);
918 netif_wake_queue(netdev);
919 } else if ((!mii_link_ok(&adapter->mii)) &&
920 (netif_carrier_ok(netdev))) {
921 netdev_dbg(netdev, "NIC Link is Down\n");
922 hw->mac.link_speed = SPEED_10;
923 hw->mac.link_duplex = DUPLEX_HALF;
924 netif_carrier_off(netdev);
925 netif_stop_queue(netdev);
926 }
927 mod_timer(&adapter->watchdog_timer,
928 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
929 }
930
931 /**
932 * pch_gbe_tx_queue - Carry out queuing of the transmission data
933 * @adapter: Board private structure
934 * @tx_ring: Tx descriptor ring structure
935 * @skb: Sockt buffer structure
936 */
937 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
938 struct pch_gbe_tx_ring *tx_ring,
939 struct sk_buff *skb)
940 {
941 struct pch_gbe_hw *hw = &adapter->hw;
942 struct pch_gbe_tx_desc *tx_desc;
943 struct pch_gbe_buffer *buffer_info;
944 struct sk_buff *tmp_skb;
945 unsigned int frame_ctrl;
946 unsigned int ring_num;
947 unsigned long flags;
948
949 /*-- Set frame control --*/
950 frame_ctrl = 0;
951 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
952 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
953 if (unlikely(!adapter->tx_csum))
954 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
955
956 /* Performs checksum processing */
957 /*
958 * It is because the hardware accelerator does not support a checksum,
959 * when the received data size is less than 64 bytes.
960 */
961 if ((skb->len < PCH_GBE_SHORT_PKT) && (adapter->tx_csum)) {
962 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
963 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
964 if (skb->protocol == htons(ETH_P_IP)) {
965 struct iphdr *iph = ip_hdr(skb);
966 unsigned int offset;
967 iph->check = 0;
968 iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
969 offset = skb_transport_offset(skb);
970 if (iph->protocol == IPPROTO_TCP) {
971 skb->csum = 0;
972 tcp_hdr(skb)->check = 0;
973 skb->csum = skb_checksum(skb, offset,
974 skb->len - offset, 0);
975 tcp_hdr(skb)->check =
976 csum_tcpudp_magic(iph->saddr,
977 iph->daddr,
978 skb->len - offset,
979 IPPROTO_TCP,
980 skb->csum);
981 } else if (iph->protocol == IPPROTO_UDP) {
982 skb->csum = 0;
983 udp_hdr(skb)->check = 0;
984 skb->csum =
985 skb_checksum(skb, offset,
986 skb->len - offset, 0);
987 udp_hdr(skb)->check =
988 csum_tcpudp_magic(iph->saddr,
989 iph->daddr,
990 skb->len - offset,
991 IPPROTO_UDP,
992 skb->csum);
993 }
994 }
995 }
996 spin_lock_irqsave(&tx_ring->tx_lock, flags);
997 ring_num = tx_ring->next_to_use;
998 if (unlikely((ring_num + 1) == tx_ring->count))
999 tx_ring->next_to_use = 0;
1000 else
1001 tx_ring->next_to_use = ring_num + 1;
1002
1003 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1004 buffer_info = &tx_ring->buffer_info[ring_num];
1005 tmp_skb = buffer_info->skb;
1006
1007 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1008 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1009 tmp_skb->data[ETH_HLEN] = 0x00;
1010 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1011 tmp_skb->len = skb->len;
1012 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1013 (skb->len - ETH_HLEN));
1014 /*-- Set Buffer infomation --*/
1015 buffer_info->length = tmp_skb->len;
1016 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1017 buffer_info->length,
1018 DMA_TO_DEVICE);
1019 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1020 pr_err("TX DMA map failed\n");
1021 buffer_info->dma = 0;
1022 buffer_info->time_stamp = 0;
1023 tx_ring->next_to_use = ring_num;
1024 return;
1025 }
1026 buffer_info->mapped = true;
1027 buffer_info->time_stamp = jiffies;
1028
1029 /*-- Set Tx descriptor --*/
1030 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1031 tx_desc->buffer_addr = (buffer_info->dma);
1032 tx_desc->length = (tmp_skb->len);
1033 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1034 tx_desc->tx_frame_ctrl = (frame_ctrl);
1035 tx_desc->gbec_status = (DSC_INIT16);
1036
1037 if (unlikely(++ring_num == tx_ring->count))
1038 ring_num = 0;
1039
1040 /* Update software pointer of TX descriptor */
1041 iowrite32(tx_ring->dma +
1042 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1043 &hw->reg->TX_DSC_SW_P);
1044 dev_kfree_skb_any(skb);
1045 }
1046
1047 /**
1048 * pch_gbe_update_stats - Update the board statistics counters
1049 * @adapter: Board private structure
1050 */
1051 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1052 {
1053 struct net_device *netdev = adapter->netdev;
1054 struct pci_dev *pdev = adapter->pdev;
1055 struct pch_gbe_hw_stats *stats = &adapter->stats;
1056 unsigned long flags;
1057
1058 /*
1059 * Prevent stats update while adapter is being reset, or if the pci
1060 * connection is down.
1061 */
1062 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1063 return;
1064
1065 spin_lock_irqsave(&adapter->stats_lock, flags);
1066
1067 /* Update device status "adapter->stats" */
1068 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1069 stats->tx_errors = stats->tx_length_errors +
1070 stats->tx_aborted_errors +
1071 stats->tx_carrier_errors + stats->tx_timeout_count;
1072
1073 /* Update network device status "adapter->net_stats" */
1074 netdev->stats.rx_packets = stats->rx_packets;
1075 netdev->stats.rx_bytes = stats->rx_bytes;
1076 netdev->stats.rx_dropped = stats->rx_dropped;
1077 netdev->stats.tx_packets = stats->tx_packets;
1078 netdev->stats.tx_bytes = stats->tx_bytes;
1079 netdev->stats.tx_dropped = stats->tx_dropped;
1080 /* Fill out the OS statistics structure */
1081 netdev->stats.multicast = stats->multicast;
1082 netdev->stats.collisions = stats->collisions;
1083 /* Rx Errors */
1084 netdev->stats.rx_errors = stats->rx_errors;
1085 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1086 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1087 /* Tx Errors */
1088 netdev->stats.tx_errors = stats->tx_errors;
1089 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1090 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1091
1092 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1093 }
1094
1095 /**
1096 * pch_gbe_intr - Interrupt Handler
1097 * @irq: Interrupt number
1098 * @data: Pointer to a network interface device structure
1099 * Returns
1100 * - IRQ_HANDLED: Our interrupt
1101 * - IRQ_NONE: Not our interrupt
1102 */
1103 static irqreturn_t pch_gbe_intr(int irq, void *data)
1104 {
1105 struct net_device *netdev = data;
1106 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1107 struct pch_gbe_hw *hw = &adapter->hw;
1108 u32 int_st;
1109 u32 int_en;
1110
1111 /* Check request status */
1112 int_st = ioread32(&hw->reg->INT_ST);
1113 int_st = int_st & ioread32(&hw->reg->INT_EN);
1114 /* When request status is no interruption factor */
1115 if (unlikely(!int_st))
1116 return IRQ_NONE; /* Not our interrupt. End processing. */
1117 pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1118 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1119 adapter->stats.intr_rx_frame_err_count++;
1120 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1121 adapter->stats.intr_rx_fifo_err_count++;
1122 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1123 adapter->stats.intr_rx_dma_err_count++;
1124 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1125 adapter->stats.intr_tx_fifo_err_count++;
1126 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1127 adapter->stats.intr_tx_dma_err_count++;
1128 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1129 adapter->stats.intr_tcpip_err_count++;
1130 /* When Rx descriptor is empty */
1131 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1132 adapter->stats.intr_rx_dsc_empty_count++;
1133 pr_err("Rx descriptor is empty\n");
1134 int_en = ioread32(&hw->reg->INT_EN);
1135 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1136 if (hw->mac.tx_fc_enable) {
1137 /* Set Pause packet */
1138 pch_gbe_mac_set_pause_packet(hw);
1139 }
1140 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1141 == 0) {
1142 return IRQ_HANDLED;
1143 }
1144 }
1145
1146 /* When request status is Receive interruption */
1147 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1148 if (likely(napi_schedule_prep(&adapter->napi))) {
1149 /* Enable only Rx Descriptor empty */
1150 atomic_inc(&adapter->irq_sem);
1151 int_en = ioread32(&hw->reg->INT_EN);
1152 int_en &=
1153 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1154 iowrite32(int_en, &hw->reg->INT_EN);
1155 /* Start polling for NAPI */
1156 __napi_schedule(&adapter->napi);
1157 }
1158 }
1159 pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n",
1160 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1161 return IRQ_HANDLED;
1162 }
1163
1164 /**
1165 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1166 * @adapter: Board private structure
1167 * @rx_ring: Rx descriptor ring
1168 * @cleaned_count: Cleaned count
1169 */
1170 static void
1171 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1172 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1173 {
1174 struct net_device *netdev = adapter->netdev;
1175 struct pci_dev *pdev = adapter->pdev;
1176 struct pch_gbe_hw *hw = &adapter->hw;
1177 struct pch_gbe_rx_desc *rx_desc;
1178 struct pch_gbe_buffer *buffer_info;
1179 struct sk_buff *skb;
1180 unsigned int i;
1181 unsigned int bufsz;
1182
1183 bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1184 i = rx_ring->next_to_use;
1185
1186 while ((cleaned_count--)) {
1187 buffer_info = &rx_ring->buffer_info[i];
1188 skb = buffer_info->skb;
1189 if (skb) {
1190 skb_trim(skb, 0);
1191 } else {
1192 skb = netdev_alloc_skb(netdev, bufsz);
1193 if (unlikely(!skb)) {
1194 /* Better luck next round */
1195 adapter->stats.rx_alloc_buff_failed++;
1196 break;
1197 }
1198 /* 64byte align */
1199 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1200
1201 buffer_info->skb = skb;
1202 buffer_info->length = adapter->rx_buffer_len;
1203 }
1204 buffer_info->dma = dma_map_single(&pdev->dev,
1205 skb->data,
1206 buffer_info->length,
1207 DMA_FROM_DEVICE);
1208 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1209 dev_kfree_skb(skb);
1210 buffer_info->skb = NULL;
1211 buffer_info->dma = 0;
1212 adapter->stats.rx_alloc_buff_failed++;
1213 break; /* while !buffer_info->skb */
1214 }
1215 buffer_info->mapped = true;
1216 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1217 rx_desc->buffer_addr = (buffer_info->dma);
1218 rx_desc->gbec_status = DSC_INIT16;
1219
1220 pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1221 i, (unsigned long long)buffer_info->dma,
1222 buffer_info->length);
1223
1224 if (unlikely(++i == rx_ring->count))
1225 i = 0;
1226 }
1227 if (likely(rx_ring->next_to_use != i)) {
1228 rx_ring->next_to_use = i;
1229 if (unlikely(i-- == 0))
1230 i = (rx_ring->count - 1);
1231 iowrite32(rx_ring->dma +
1232 (int)sizeof(struct pch_gbe_rx_desc) * i,
1233 &hw->reg->RX_DSC_SW_P);
1234 }
1235 return;
1236 }
1237
1238 /**
1239 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1240 * @adapter: Board private structure
1241 * @tx_ring: Tx descriptor ring
1242 */
1243 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1244 struct pch_gbe_tx_ring *tx_ring)
1245 {
1246 struct pch_gbe_buffer *buffer_info;
1247 struct sk_buff *skb;
1248 unsigned int i;
1249 unsigned int bufsz;
1250 struct pch_gbe_tx_desc *tx_desc;
1251
1252 bufsz =
1253 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1254
1255 for (i = 0; i < tx_ring->count; i++) {
1256 buffer_info = &tx_ring->buffer_info[i];
1257 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1258 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1259 buffer_info->skb = skb;
1260 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1261 tx_desc->gbec_status = (DSC_INIT16);
1262 }
1263 return;
1264 }
1265
1266 /**
1267 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1268 * @adapter: Board private structure
1269 * @tx_ring: Tx descriptor ring
1270 * Returns
1271 * true: Cleaned the descriptor
1272 * false: Not cleaned the descriptor
1273 */
1274 static bool
1275 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1276 struct pch_gbe_tx_ring *tx_ring)
1277 {
1278 struct pch_gbe_tx_desc *tx_desc;
1279 struct pch_gbe_buffer *buffer_info;
1280 struct sk_buff *skb;
1281 unsigned int i;
1282 unsigned int cleaned_count = 0;
1283 bool cleaned = false;
1284
1285 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1286
1287 i = tx_ring->next_to_clean;
1288 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1289 pr_debug("gbec_status:0x%04x dma_status:0x%04x\n",
1290 tx_desc->gbec_status, tx_desc->dma_status);
1291
1292 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1293 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1294 cleaned = true;
1295 buffer_info = &tx_ring->buffer_info[i];
1296 skb = buffer_info->skb;
1297
1298 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1299 adapter->stats.tx_aborted_errors++;
1300 pr_err("Transfer Abort Error\n");
1301 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1302 ) {
1303 adapter->stats.tx_carrier_errors++;
1304 pr_err("Transfer Carrier Sense Error\n");
1305 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1306 ) {
1307 adapter->stats.tx_aborted_errors++;
1308 pr_err("Transfer Collision Abort Error\n");
1309 } else if ((tx_desc->gbec_status &
1310 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1311 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1312 adapter->stats.collisions++;
1313 adapter->stats.tx_packets++;
1314 adapter->stats.tx_bytes += skb->len;
1315 pr_debug("Transfer Collision\n");
1316 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1317 ) {
1318 adapter->stats.tx_packets++;
1319 adapter->stats.tx_bytes += skb->len;
1320 }
1321 if (buffer_info->mapped) {
1322 pr_debug("unmap buffer_info->dma : %d\n", i);
1323 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1324 buffer_info->length, DMA_TO_DEVICE);
1325 buffer_info->mapped = false;
1326 }
1327 if (buffer_info->skb) {
1328 pr_debug("trim buffer_info->skb : %d\n", i);
1329 skb_trim(buffer_info->skb, 0);
1330 }
1331 tx_desc->gbec_status = DSC_INIT16;
1332 if (unlikely(++i == tx_ring->count))
1333 i = 0;
1334 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1335
1336 /* weight of a sort for tx, to avoid endless transmit cleanup */
1337 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1338 break;
1339 }
1340 pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1341 cleaned_count);
1342 /* Recover from running out of Tx resources in xmit_frame */
1343 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1344 netif_wake_queue(adapter->netdev);
1345 adapter->stats.tx_restart_count++;
1346 pr_debug("Tx wake queue\n");
1347 }
1348 spin_lock(&adapter->tx_queue_lock);
1349 tx_ring->next_to_clean = i;
1350 spin_unlock(&adapter->tx_queue_lock);
1351 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1352 return cleaned;
1353 }
1354
1355 /**
1356 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1357 * @adapter: Board private structure
1358 * @rx_ring: Rx descriptor ring
1359 * @work_done: Completed count
1360 * @work_to_do: Request count
1361 * Returns
1362 * true: Cleaned the descriptor
1363 * false: Not cleaned the descriptor
1364 */
1365 static bool
1366 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1367 struct pch_gbe_rx_ring *rx_ring,
1368 int *work_done, int work_to_do)
1369 {
1370 struct net_device *netdev = adapter->netdev;
1371 struct pci_dev *pdev = adapter->pdev;
1372 struct pch_gbe_buffer *buffer_info;
1373 struct pch_gbe_rx_desc *rx_desc;
1374 u32 length;
1375 unsigned int i;
1376 unsigned int cleaned_count = 0;
1377 bool cleaned = false;
1378 struct sk_buff *skb, *new_skb;
1379 u8 dma_status;
1380 u16 gbec_status;
1381 u32 tcp_ip_status;
1382
1383 i = rx_ring->next_to_clean;
1384
1385 while (*work_done < work_to_do) {
1386 /* Check Rx descriptor status */
1387 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1388 if (rx_desc->gbec_status == DSC_INIT16)
1389 break;
1390 cleaned = true;
1391 cleaned_count++;
1392
1393 dma_status = rx_desc->dma_status;
1394 gbec_status = rx_desc->gbec_status;
1395 tcp_ip_status = rx_desc->tcp_ip_status;
1396 rx_desc->gbec_status = DSC_INIT16;
1397 buffer_info = &rx_ring->buffer_info[i];
1398 skb = buffer_info->skb;
1399
1400 /* unmap dma */
1401 dma_unmap_single(&pdev->dev, buffer_info->dma,
1402 buffer_info->length, DMA_FROM_DEVICE);
1403 buffer_info->mapped = false;
1404 /* Prefetch the packet */
1405 prefetch(skb->data);
1406
1407 pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x "
1408 "TCP:0x%08x] BufInf = 0x%p\n",
1409 i, dma_status, gbec_status, tcp_ip_status,
1410 buffer_info);
1411 /* Error check */
1412 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1413 adapter->stats.rx_frame_errors++;
1414 pr_err("Receive Not Octal Error\n");
1415 } else if (unlikely(gbec_status &
1416 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1417 adapter->stats.rx_frame_errors++;
1418 pr_err("Receive Nibble Error\n");
1419 } else if (unlikely(gbec_status &
1420 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1421 adapter->stats.rx_crc_errors++;
1422 pr_err("Receive CRC Error\n");
1423 } else {
1424 /* get receive length */
1425 /* length convert[-3] */
1426 length = (rx_desc->rx_words_eob) - 3;
1427
1428 /* Decide the data conversion method */
1429 if (!adapter->rx_csum) {
1430 /* [Header:14][payload] */
1431 if (NET_IP_ALIGN) {
1432 /* Because alignment differs,
1433 * the new_skb is newly allocated,
1434 * and data is copied to new_skb.*/
1435 new_skb = netdev_alloc_skb(netdev,
1436 length + NET_IP_ALIGN);
1437 if (!new_skb) {
1438 /* dorrop error */
1439 pr_err("New skb allocation "
1440 "Error\n");
1441 goto dorrop;
1442 }
1443 skb_reserve(new_skb, NET_IP_ALIGN);
1444 memcpy(new_skb->data, skb->data,
1445 length);
1446 skb = new_skb;
1447 } else {
1448 /* DMA buffer is used as SKB as it is.*/
1449 buffer_info->skb = NULL;
1450 }
1451 } else {
1452 /* [Header:14][padding:2][payload] */
1453 /* The length includes padding length */
1454 length = length - PCH_GBE_DMA_PADDING;
1455 if ((length < copybreak) ||
1456 (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) {
1457 /* Because alignment differs,
1458 * the new_skb is newly allocated,
1459 * and data is copied to new_skb.
1460 * Padding data is deleted
1461 * at the time of a copy.*/
1462 new_skb = netdev_alloc_skb(netdev,
1463 length + NET_IP_ALIGN);
1464 if (!new_skb) {
1465 /* dorrop error */
1466 pr_err("New skb allocation "
1467 "Error\n");
1468 goto dorrop;
1469 }
1470 skb_reserve(new_skb, NET_IP_ALIGN);
1471 memcpy(new_skb->data, skb->data,
1472 ETH_HLEN);
1473 memcpy(&new_skb->data[ETH_HLEN],
1474 &skb->data[ETH_HLEN +
1475 PCH_GBE_DMA_PADDING],
1476 length - ETH_HLEN);
1477 skb = new_skb;
1478 } else {
1479 /* Padding data is deleted
1480 * by moving header data.*/
1481 memmove(&skb->data[PCH_GBE_DMA_PADDING],
1482 &skb->data[0], ETH_HLEN);
1483 skb_reserve(skb, NET_IP_ALIGN);
1484 buffer_info->skb = NULL;
1485 }
1486 }
1487 /* The length includes FCS length */
1488 length = length - ETH_FCS_LEN;
1489 /* update status of driver */
1490 adapter->stats.rx_bytes += length;
1491 adapter->stats.rx_packets++;
1492 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1493 adapter->stats.multicast++;
1494 /* Write meta date of skb */
1495 skb_put(skb, length);
1496 skb->protocol = eth_type_trans(skb, netdev);
1497 if ((tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) ==
1498 PCH_GBE_RXD_ACC_STAT_TCPIPOK) {
1499 skb->ip_summed = CHECKSUM_UNNECESSARY;
1500 } else {
1501 skb->ip_summed = CHECKSUM_NONE;
1502 }
1503 napi_gro_receive(&adapter->napi, skb);
1504 (*work_done)++;
1505 pr_debug("Receive skb->ip_summed: %d length: %d\n",
1506 skb->ip_summed, length);
1507 }
1508 dorrop:
1509 /* return some buffers to hardware, one at a time is too slow */
1510 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1511 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1512 cleaned_count);
1513 cleaned_count = 0;
1514 }
1515 if (++i == rx_ring->count)
1516 i = 0;
1517 }
1518 rx_ring->next_to_clean = i;
1519 if (cleaned_count)
1520 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1521 return cleaned;
1522 }
1523
1524 /**
1525 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1526 * @adapter: Board private structure
1527 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1528 * Returns
1529 * 0: Successfully
1530 * Negative value: Failed
1531 */
1532 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1533 struct pch_gbe_tx_ring *tx_ring)
1534 {
1535 struct pci_dev *pdev = adapter->pdev;
1536 struct pch_gbe_tx_desc *tx_desc;
1537 int size;
1538 int desNo;
1539
1540 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1541 tx_ring->buffer_info = vzalloc(size);
1542 if (!tx_ring->buffer_info) {
1543 pr_err("Unable to allocate memory for the buffer infomation\n");
1544 return -ENOMEM;
1545 }
1546
1547 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1548
1549 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1550 &tx_ring->dma, GFP_KERNEL);
1551 if (!tx_ring->desc) {
1552 vfree(tx_ring->buffer_info);
1553 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1554 return -ENOMEM;
1555 }
1556 memset(tx_ring->desc, 0, tx_ring->size);
1557
1558 tx_ring->next_to_use = 0;
1559 tx_ring->next_to_clean = 0;
1560 spin_lock_init(&tx_ring->tx_lock);
1561
1562 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1563 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1564 tx_desc->gbec_status = DSC_INIT16;
1565 }
1566 pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n"
1567 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1568 tx_ring->desc, (unsigned long long)tx_ring->dma,
1569 tx_ring->next_to_clean, tx_ring->next_to_use);
1570 return 0;
1571 }
1572
1573 /**
1574 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1575 * @adapter: Board private structure
1576 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1577 * Returns
1578 * 0: Successfully
1579 * Negative value: Failed
1580 */
1581 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1582 struct pch_gbe_rx_ring *rx_ring)
1583 {
1584 struct pci_dev *pdev = adapter->pdev;
1585 struct pch_gbe_rx_desc *rx_desc;
1586 int size;
1587 int desNo;
1588
1589 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1590 rx_ring->buffer_info = vzalloc(size);
1591 if (!rx_ring->buffer_info) {
1592 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1593 return -ENOMEM;
1594 }
1595 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1596 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1597 &rx_ring->dma, GFP_KERNEL);
1598
1599 if (!rx_ring->desc) {
1600 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1601 vfree(rx_ring->buffer_info);
1602 return -ENOMEM;
1603 }
1604 memset(rx_ring->desc, 0, rx_ring->size);
1605 rx_ring->next_to_clean = 0;
1606 rx_ring->next_to_use = 0;
1607 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1608 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1609 rx_desc->gbec_status = DSC_INIT16;
1610 }
1611 pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx "
1612 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1613 rx_ring->desc, (unsigned long long)rx_ring->dma,
1614 rx_ring->next_to_clean, rx_ring->next_to_use);
1615 return 0;
1616 }
1617
1618 /**
1619 * pch_gbe_free_tx_resources - Free Tx Resources
1620 * @adapter: Board private structure
1621 * @tx_ring: Tx descriptor ring for a specific queue
1622 */
1623 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1624 struct pch_gbe_tx_ring *tx_ring)
1625 {
1626 struct pci_dev *pdev = adapter->pdev;
1627
1628 pch_gbe_clean_tx_ring(adapter, tx_ring);
1629 vfree(tx_ring->buffer_info);
1630 tx_ring->buffer_info = NULL;
1631 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1632 tx_ring->desc = NULL;
1633 }
1634
1635 /**
1636 * pch_gbe_free_rx_resources - Free Rx Resources
1637 * @adapter: Board private structure
1638 * @rx_ring: Ring to clean the resources from
1639 */
1640 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1641 struct pch_gbe_rx_ring *rx_ring)
1642 {
1643 struct pci_dev *pdev = adapter->pdev;
1644
1645 pch_gbe_clean_rx_ring(adapter, rx_ring);
1646 vfree(rx_ring->buffer_info);
1647 rx_ring->buffer_info = NULL;
1648 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1649 rx_ring->desc = NULL;
1650 }
1651
1652 /**
1653 * pch_gbe_request_irq - Allocate an interrupt line
1654 * @adapter: Board private structure
1655 * Returns
1656 * 0: Successfully
1657 * Negative value: Failed
1658 */
1659 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1660 {
1661 struct net_device *netdev = adapter->netdev;
1662 int err;
1663 int flags;
1664
1665 flags = IRQF_SHARED;
1666 adapter->have_msi = false;
1667 err = pci_enable_msi(adapter->pdev);
1668 pr_debug("call pci_enable_msi\n");
1669 if (err) {
1670 pr_debug("call pci_enable_msi - Error: %d\n", err);
1671 } else {
1672 flags = 0;
1673 adapter->have_msi = true;
1674 }
1675 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1676 flags, netdev->name, netdev);
1677 if (err)
1678 pr_err("Unable to allocate interrupt Error: %d\n", err);
1679 pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1680 adapter->have_msi, flags, err);
1681 return err;
1682 }
1683
1684
1685 static void pch_gbe_set_multi(struct net_device *netdev);
1686 /**
1687 * pch_gbe_up - Up GbE network device
1688 * @adapter: Board private structure
1689 * Returns
1690 * 0: Successfully
1691 * Negative value: Failed
1692 */
1693 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1694 {
1695 struct net_device *netdev = adapter->netdev;
1696 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1697 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1698 int err;
1699
1700 /* hardware has been reset, we need to reload some things */
1701 pch_gbe_set_multi(netdev);
1702
1703 pch_gbe_setup_tctl(adapter);
1704 pch_gbe_configure_tx(adapter);
1705 pch_gbe_setup_rctl(adapter);
1706 pch_gbe_configure_rx(adapter);
1707
1708 err = pch_gbe_request_irq(adapter);
1709 if (err) {
1710 pr_err("Error: can't bring device up\n");
1711 return err;
1712 }
1713 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1714 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1715 adapter->tx_queue_len = netdev->tx_queue_len;
1716
1717 mod_timer(&adapter->watchdog_timer, jiffies);
1718
1719 napi_enable(&adapter->napi);
1720 pch_gbe_irq_enable(adapter);
1721 netif_start_queue(adapter->netdev);
1722
1723 return 0;
1724 }
1725
1726 /**
1727 * pch_gbe_down - Down GbE network device
1728 * @adapter: Board private structure
1729 */
1730 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1731 {
1732 struct net_device *netdev = adapter->netdev;
1733
1734 /* signal that we're down so the interrupt handler does not
1735 * reschedule our watchdog timer */
1736 napi_disable(&adapter->napi);
1737 atomic_set(&adapter->irq_sem, 0);
1738
1739 pch_gbe_irq_disable(adapter);
1740 pch_gbe_free_irq(adapter);
1741
1742 del_timer_sync(&adapter->watchdog_timer);
1743
1744 netdev->tx_queue_len = adapter->tx_queue_len;
1745 netif_carrier_off(netdev);
1746 netif_stop_queue(netdev);
1747
1748 pch_gbe_reset(adapter);
1749 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1750 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1751 }
1752
1753 /**
1754 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1755 * @adapter: Board private structure to initialize
1756 * Returns
1757 * 0: Successfully
1758 * Negative value: Failed
1759 */
1760 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1761 {
1762 struct pch_gbe_hw *hw = &adapter->hw;
1763 struct net_device *netdev = adapter->netdev;
1764
1765 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1766 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1767 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1768
1769 /* Initialize the hardware-specific values */
1770 if (pch_gbe_hal_setup_init_funcs(hw)) {
1771 pr_err("Hardware Initialization Failure\n");
1772 return -EIO;
1773 }
1774 if (pch_gbe_alloc_queues(adapter)) {
1775 pr_err("Unable to allocate memory for queues\n");
1776 return -ENOMEM;
1777 }
1778 spin_lock_init(&adapter->hw.miim_lock);
1779 spin_lock_init(&adapter->tx_queue_lock);
1780 spin_lock_init(&adapter->stats_lock);
1781 spin_lock_init(&adapter->ethtool_lock);
1782 atomic_set(&adapter->irq_sem, 0);
1783 pch_gbe_irq_disable(adapter);
1784
1785 pch_gbe_init_stats(adapter);
1786
1787 pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1788 (u32) adapter->rx_buffer_len,
1789 hw->mac.min_frame_size, hw->mac.max_frame_size);
1790 return 0;
1791 }
1792
1793 /**
1794 * pch_gbe_open - Called when a network interface is made active
1795 * @netdev: Network interface device structure
1796 * Returns
1797 * 0: Successfully
1798 * Negative value: Failed
1799 */
1800 static int pch_gbe_open(struct net_device *netdev)
1801 {
1802 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1803 struct pch_gbe_hw *hw = &adapter->hw;
1804 int err;
1805
1806 /* allocate transmit descriptors */
1807 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1808 if (err)
1809 goto err_setup_tx;
1810 /* allocate receive descriptors */
1811 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1812 if (err)
1813 goto err_setup_rx;
1814 pch_gbe_hal_power_up_phy(hw);
1815 err = pch_gbe_up(adapter);
1816 if (err)
1817 goto err_up;
1818 pr_debug("Success End\n");
1819 return 0;
1820
1821 err_up:
1822 if (!adapter->wake_up_evt)
1823 pch_gbe_hal_power_down_phy(hw);
1824 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1825 err_setup_rx:
1826 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1827 err_setup_tx:
1828 pch_gbe_reset(adapter);
1829 pr_err("Error End\n");
1830 return err;
1831 }
1832
1833 /**
1834 * pch_gbe_stop - Disables a network interface
1835 * @netdev: Network interface device structure
1836 * Returns
1837 * 0: Successfully
1838 */
1839 static int pch_gbe_stop(struct net_device *netdev)
1840 {
1841 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1842 struct pch_gbe_hw *hw = &adapter->hw;
1843
1844 pch_gbe_down(adapter);
1845 if (!adapter->wake_up_evt)
1846 pch_gbe_hal_power_down_phy(hw);
1847 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1848 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1849 return 0;
1850 }
1851
1852 /**
1853 * pch_gbe_xmit_frame - Packet transmitting start
1854 * @skb: Socket buffer structure
1855 * @netdev: Network interface device structure
1856 * Returns
1857 * - NETDEV_TX_OK: Normal end
1858 * - NETDEV_TX_BUSY: Error end
1859 */
1860 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1861 {
1862 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1863 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1864 unsigned long flags;
1865
1866 if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
1867 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1868 skb->len, adapter->hw.mac.max_frame_size);
1869 dev_kfree_skb_any(skb);
1870 adapter->stats.tx_length_errors++;
1871 return NETDEV_TX_OK;
1872 }
1873 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1874 /* Collision - tell upper layer to requeue */
1875 return NETDEV_TX_LOCKED;
1876 }
1877 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1878 netif_stop_queue(netdev);
1879 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1880 pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
1881 tx_ring->next_to_use, tx_ring->next_to_clean);
1882 return NETDEV_TX_BUSY;
1883 }
1884 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1885
1886 /* CRC,ITAG no support */
1887 pch_gbe_tx_queue(adapter, tx_ring, skb);
1888 return NETDEV_TX_OK;
1889 }
1890
1891 /**
1892 * pch_gbe_get_stats - Get System Network Statistics
1893 * @netdev: Network interface device structure
1894 * Returns: The current stats
1895 */
1896 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1897 {
1898 /* only return the current stats */
1899 return &netdev->stats;
1900 }
1901
1902 /**
1903 * pch_gbe_set_multi - Multicast and Promiscuous mode set
1904 * @netdev: Network interface device structure
1905 */
1906 static void pch_gbe_set_multi(struct net_device *netdev)
1907 {
1908 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1909 struct pch_gbe_hw *hw = &adapter->hw;
1910 struct netdev_hw_addr *ha;
1911 u8 *mta_list;
1912 u32 rctl;
1913 int i;
1914 int mc_count;
1915
1916 pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1917
1918 /* Check for Promiscuous and All Multicast modes */
1919 rctl = ioread32(&hw->reg->RX_MODE);
1920 mc_count = netdev_mc_count(netdev);
1921 if ((netdev->flags & IFF_PROMISC)) {
1922 rctl &= ~PCH_GBE_ADD_FIL_EN;
1923 rctl &= ~PCH_GBE_MLT_FIL_EN;
1924 } else if ((netdev->flags & IFF_ALLMULTI)) {
1925 /* all the multicasting receive permissions */
1926 rctl |= PCH_GBE_ADD_FIL_EN;
1927 rctl &= ~PCH_GBE_MLT_FIL_EN;
1928 } else {
1929 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1930 /* all the multicasting receive permissions */
1931 rctl |= PCH_GBE_ADD_FIL_EN;
1932 rctl &= ~PCH_GBE_MLT_FIL_EN;
1933 } else {
1934 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1935 }
1936 }
1937 iowrite32(rctl, &hw->reg->RX_MODE);
1938
1939 if (mc_count >= PCH_GBE_MAR_ENTRIES)
1940 return;
1941 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1942 if (!mta_list)
1943 return;
1944
1945 /* The shared function expects a packed array of only addresses. */
1946 i = 0;
1947 netdev_for_each_mc_addr(ha, netdev) {
1948 if (i == mc_count)
1949 break;
1950 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1951 }
1952 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1953 PCH_GBE_MAR_ENTRIES);
1954 kfree(mta_list);
1955
1956 pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
1957 ioread32(&hw->reg->RX_MODE), mc_count);
1958 }
1959
1960 /**
1961 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1962 * @netdev: Network interface device structure
1963 * @addr: Pointer to an address structure
1964 * Returns
1965 * 0: Successfully
1966 * -EADDRNOTAVAIL: Failed
1967 */
1968 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1969 {
1970 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1971 struct sockaddr *skaddr = addr;
1972 int ret_val;
1973
1974 if (!is_valid_ether_addr(skaddr->sa_data)) {
1975 ret_val = -EADDRNOTAVAIL;
1976 } else {
1977 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1978 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1979 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1980 ret_val = 0;
1981 }
1982 pr_debug("ret_val : 0x%08x\n", ret_val);
1983 pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1984 pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1985 pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1986 ioread32(&adapter->hw.reg->mac_adr[0].high),
1987 ioread32(&adapter->hw.reg->mac_adr[0].low));
1988 return ret_val;
1989 }
1990
1991 /**
1992 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1993 * @netdev: Network interface device structure
1994 * @new_mtu: New value for maximum frame size
1995 * Returns
1996 * 0: Successfully
1997 * -EINVAL: Failed
1998 */
1999 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2000 {
2001 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2002 int max_frame;
2003
2004 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2005 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2006 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2007 pr_err("Invalid MTU setting\n");
2008 return -EINVAL;
2009 }
2010 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2011 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2012 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2013 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2014 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2015 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2016 else
2017 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
2018 netdev->mtu = new_mtu;
2019 adapter->hw.mac.max_frame_size = max_frame;
2020
2021 if (netif_running(netdev))
2022 pch_gbe_reinit_locked(adapter);
2023 else
2024 pch_gbe_reset(adapter);
2025
2026 pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2027 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2028 adapter->hw.mac.max_frame_size);
2029 return 0;
2030 }
2031
2032 /**
2033 * pch_gbe_ioctl - Controls register through a MII interface
2034 * @netdev: Network interface device structure
2035 * @ifr: Pointer to ifr structure
2036 * @cmd: Control command
2037 * Returns
2038 * 0: Successfully
2039 * Negative value: Failed
2040 */
2041 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2042 {
2043 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2044
2045 pr_debug("cmd : 0x%04x\n", cmd);
2046
2047 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2048 }
2049
2050 /**
2051 * pch_gbe_tx_timeout - Respond to a Tx Hang
2052 * @netdev: Network interface device structure
2053 */
2054 static void pch_gbe_tx_timeout(struct net_device *netdev)
2055 {
2056 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2057
2058 /* Do the reset outside of interrupt context */
2059 adapter->stats.tx_timeout_count++;
2060 schedule_work(&adapter->reset_task);
2061 }
2062
2063 /**
2064 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2065 * @napi: Pointer of polling device struct
2066 * @budget: The maximum number of a packet
2067 * Returns
2068 * false: Exit the polling mode
2069 * true: Continue the polling mode
2070 */
2071 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2072 {
2073 struct pch_gbe_adapter *adapter =
2074 container_of(napi, struct pch_gbe_adapter, napi);
2075 struct net_device *netdev = adapter->netdev;
2076 int work_done = 0;
2077 bool poll_end_flag = false;
2078 bool cleaned = false;
2079
2080 pr_debug("budget : %d\n", budget);
2081
2082 /* Keep link state information with original netdev */
2083 if (!netif_carrier_ok(netdev)) {
2084 poll_end_flag = true;
2085 } else {
2086 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2087 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2088
2089 if (cleaned)
2090 work_done = budget;
2091 /* If no Tx and not enough Rx work done,
2092 * exit the polling mode
2093 */
2094 if ((work_done < budget) || !netif_running(netdev))
2095 poll_end_flag = true;
2096 }
2097
2098 if (poll_end_flag) {
2099 napi_complete(napi);
2100 pch_gbe_irq_enable(adapter);
2101 }
2102
2103 pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
2104 poll_end_flag, work_done, budget);
2105
2106 return work_done;
2107 }
2108
2109 #ifdef CONFIG_NET_POLL_CONTROLLER
2110 /**
2111 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2112 * @netdev: Network interface device structure
2113 */
2114 static void pch_gbe_netpoll(struct net_device *netdev)
2115 {
2116 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2117
2118 disable_irq(adapter->pdev->irq);
2119 pch_gbe_intr(adapter->pdev->irq, netdev);
2120 enable_irq(adapter->pdev->irq);
2121 }
2122 #endif
2123
2124 static const struct net_device_ops pch_gbe_netdev_ops = {
2125 .ndo_open = pch_gbe_open,
2126 .ndo_stop = pch_gbe_stop,
2127 .ndo_start_xmit = pch_gbe_xmit_frame,
2128 .ndo_get_stats = pch_gbe_get_stats,
2129 .ndo_set_mac_address = pch_gbe_set_mac,
2130 .ndo_tx_timeout = pch_gbe_tx_timeout,
2131 .ndo_change_mtu = pch_gbe_change_mtu,
2132 .ndo_do_ioctl = pch_gbe_ioctl,
2133 .ndo_set_multicast_list = &pch_gbe_set_multi,
2134 #ifdef CONFIG_NET_POLL_CONTROLLER
2135 .ndo_poll_controller = pch_gbe_netpoll,
2136 #endif
2137 };
2138
2139 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2140 pci_channel_state_t state)
2141 {
2142 struct net_device *netdev = pci_get_drvdata(pdev);
2143 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2144
2145 netif_device_detach(netdev);
2146 if (netif_running(netdev))
2147 pch_gbe_down(adapter);
2148 pci_disable_device(pdev);
2149 /* Request a slot slot reset. */
2150 return PCI_ERS_RESULT_NEED_RESET;
2151 }
2152
2153 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2154 {
2155 struct net_device *netdev = pci_get_drvdata(pdev);
2156 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2157 struct pch_gbe_hw *hw = &adapter->hw;
2158
2159 if (pci_enable_device(pdev)) {
2160 pr_err("Cannot re-enable PCI device after reset\n");
2161 return PCI_ERS_RESULT_DISCONNECT;
2162 }
2163 pci_set_master(pdev);
2164 pci_enable_wake(pdev, PCI_D0, 0);
2165 pch_gbe_hal_power_up_phy(hw);
2166 pch_gbe_reset(adapter);
2167 /* Clear wake up status */
2168 pch_gbe_mac_set_wol_event(hw, 0);
2169
2170 return PCI_ERS_RESULT_RECOVERED;
2171 }
2172
2173 static void pch_gbe_io_resume(struct pci_dev *pdev)
2174 {
2175 struct net_device *netdev = pci_get_drvdata(pdev);
2176 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2177
2178 if (netif_running(netdev)) {
2179 if (pch_gbe_up(adapter)) {
2180 pr_debug("can't bring device back up after reset\n");
2181 return;
2182 }
2183 }
2184 netif_device_attach(netdev);
2185 }
2186
2187 static int __pch_gbe_suspend(struct pci_dev *pdev)
2188 {
2189 struct net_device *netdev = pci_get_drvdata(pdev);
2190 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2191 struct pch_gbe_hw *hw = &adapter->hw;
2192 u32 wufc = adapter->wake_up_evt;
2193 int retval = 0;
2194
2195 netif_device_detach(netdev);
2196 if (netif_running(netdev))
2197 pch_gbe_down(adapter);
2198 if (wufc) {
2199 pch_gbe_set_multi(netdev);
2200 pch_gbe_setup_rctl(adapter);
2201 pch_gbe_configure_rx(adapter);
2202 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2203 hw->mac.link_duplex);
2204 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2205 hw->mac.link_duplex);
2206 pch_gbe_mac_set_wol_event(hw, wufc);
2207 pci_disable_device(pdev);
2208 } else {
2209 pch_gbe_hal_power_down_phy(hw);
2210 pch_gbe_mac_set_wol_event(hw, wufc);
2211 pci_disable_device(pdev);
2212 }
2213 return retval;
2214 }
2215
2216 #ifdef CONFIG_PM
2217 static int pch_gbe_suspend(struct device *device)
2218 {
2219 struct pci_dev *pdev = to_pci_dev(device);
2220
2221 return __pch_gbe_suspend(pdev);
2222 }
2223
2224 static int pch_gbe_resume(struct device *device)
2225 {
2226 struct pci_dev *pdev = to_pci_dev(device);
2227 struct net_device *netdev = pci_get_drvdata(pdev);
2228 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2229 struct pch_gbe_hw *hw = &adapter->hw;
2230 u32 err;
2231
2232 err = pci_enable_device(pdev);
2233 if (err) {
2234 pr_err("Cannot enable PCI device from suspend\n");
2235 return err;
2236 }
2237 pci_set_master(pdev);
2238 pch_gbe_hal_power_up_phy(hw);
2239 pch_gbe_reset(adapter);
2240 /* Clear wake on lan control and status */
2241 pch_gbe_mac_set_wol_event(hw, 0);
2242
2243 if (netif_running(netdev))
2244 pch_gbe_up(adapter);
2245 netif_device_attach(netdev);
2246
2247 return 0;
2248 }
2249 #endif /* CONFIG_PM */
2250
2251 static void pch_gbe_shutdown(struct pci_dev *pdev)
2252 {
2253 __pch_gbe_suspend(pdev);
2254 if (system_state == SYSTEM_POWER_OFF) {
2255 pci_wake_from_d3(pdev, true);
2256 pci_set_power_state(pdev, PCI_D3hot);
2257 }
2258 }
2259
2260 static void pch_gbe_remove(struct pci_dev *pdev)
2261 {
2262 struct net_device *netdev = pci_get_drvdata(pdev);
2263 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2264
2265 cancel_work_sync(&adapter->reset_task);
2266 unregister_netdev(netdev);
2267
2268 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2269
2270 kfree(adapter->tx_ring);
2271 kfree(adapter->rx_ring);
2272
2273 iounmap(adapter->hw.reg);
2274 pci_release_regions(pdev);
2275 free_netdev(netdev);
2276 pci_disable_device(pdev);
2277 }
2278
2279 static int pch_gbe_probe(struct pci_dev *pdev,
2280 const struct pci_device_id *pci_id)
2281 {
2282 struct net_device *netdev;
2283 struct pch_gbe_adapter *adapter;
2284 int ret;
2285
2286 ret = pci_enable_device(pdev);
2287 if (ret)
2288 return ret;
2289
2290 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2291 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2292 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2293 if (ret) {
2294 ret = pci_set_consistent_dma_mask(pdev,
2295 DMA_BIT_MASK(32));
2296 if (ret) {
2297 dev_err(&pdev->dev, "ERR: No usable DMA "
2298 "configuration, aborting\n");
2299 goto err_disable_device;
2300 }
2301 }
2302 }
2303
2304 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2305 if (ret) {
2306 dev_err(&pdev->dev,
2307 "ERR: Can't reserve PCI I/O and memory resources\n");
2308 goto err_disable_device;
2309 }
2310 pci_set_master(pdev);
2311
2312 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2313 if (!netdev) {
2314 ret = -ENOMEM;
2315 dev_err(&pdev->dev,
2316 "ERR: Can't allocate and set up an Ethernet device\n");
2317 goto err_release_pci;
2318 }
2319 SET_NETDEV_DEV(netdev, &pdev->dev);
2320
2321 pci_set_drvdata(pdev, netdev);
2322 adapter = netdev_priv(netdev);
2323 adapter->netdev = netdev;
2324 adapter->pdev = pdev;
2325 adapter->hw.back = adapter;
2326 adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2327 if (!adapter->hw.reg) {
2328 ret = -EIO;
2329 dev_err(&pdev->dev, "Can't ioremap\n");
2330 goto err_free_netdev;
2331 }
2332
2333 netdev->netdev_ops = &pch_gbe_netdev_ops;
2334 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2335 netif_napi_add(netdev, &adapter->napi,
2336 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2337 netdev->features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_GRO;
2338 pch_gbe_set_ethtool_ops(netdev);
2339
2340 pch_gbe_mac_load_mac_addr(&adapter->hw);
2341 pch_gbe_mac_reset_hw(&adapter->hw);
2342
2343 /* setup the private structure */
2344 ret = pch_gbe_sw_init(adapter);
2345 if (ret)
2346 goto err_iounmap;
2347
2348 /* Initialize PHY */
2349 ret = pch_gbe_init_phy(adapter);
2350 if (ret) {
2351 dev_err(&pdev->dev, "PHY initialize error\n");
2352 goto err_free_adapter;
2353 }
2354 pch_gbe_hal_get_bus_info(&adapter->hw);
2355
2356 /* Read the MAC address. and store to the private data */
2357 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2358 if (ret) {
2359 dev_err(&pdev->dev, "MAC address Read Error\n");
2360 goto err_free_adapter;
2361 }
2362
2363 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2364 if (!is_valid_ether_addr(netdev->dev_addr)) {
2365 dev_err(&pdev->dev, "Invalid MAC Address\n");
2366 ret = -EIO;
2367 goto err_free_adapter;
2368 }
2369 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2370 (unsigned long)adapter);
2371
2372 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2373
2374 pch_gbe_check_options(adapter);
2375
2376 if (adapter->tx_csum)
2377 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2378 else
2379 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2380
2381 /* initialize the wol settings based on the eeprom settings */
2382 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2383 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2384
2385 /* reset the hardware with the new settings */
2386 pch_gbe_reset(adapter);
2387
2388 ret = register_netdev(netdev);
2389 if (ret)
2390 goto err_free_adapter;
2391 /* tell the stack to leave us alone until pch_gbe_open() is called */
2392 netif_carrier_off(netdev);
2393 netif_stop_queue(netdev);
2394
2395 dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2396
2397 device_set_wakeup_enable(&pdev->dev, 1);
2398 return 0;
2399
2400 err_free_adapter:
2401 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2402 kfree(adapter->tx_ring);
2403 kfree(adapter->rx_ring);
2404 err_iounmap:
2405 iounmap(adapter->hw.reg);
2406 err_free_netdev:
2407 free_netdev(netdev);
2408 err_release_pci:
2409 pci_release_regions(pdev);
2410 err_disable_device:
2411 pci_disable_device(pdev);
2412 return ret;
2413 }
2414
2415 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2416 {.vendor = PCI_VENDOR_ID_INTEL,
2417 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2418 .subvendor = PCI_ANY_ID,
2419 .subdevice = PCI_ANY_ID,
2420 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2421 .class_mask = (0xFFFF00)
2422 },
2423 /* required last entry */
2424 {0}
2425 };
2426
2427 #ifdef CONFIG_PM
2428 static const struct dev_pm_ops pch_gbe_pm_ops = {
2429 .suspend = pch_gbe_suspend,
2430 .resume = pch_gbe_resume,
2431 .freeze = pch_gbe_suspend,
2432 .thaw = pch_gbe_resume,
2433 .poweroff = pch_gbe_suspend,
2434 .restore = pch_gbe_resume,
2435 };
2436 #endif
2437
2438 static struct pci_error_handlers pch_gbe_err_handler = {
2439 .error_detected = pch_gbe_io_error_detected,
2440 .slot_reset = pch_gbe_io_slot_reset,
2441 .resume = pch_gbe_io_resume
2442 };
2443
2444 static struct pci_driver pch_gbe_pcidev = {
2445 .name = KBUILD_MODNAME,
2446 .id_table = pch_gbe_pcidev_id,
2447 .probe = pch_gbe_probe,
2448 .remove = pch_gbe_remove,
2449 #ifdef CONFIG_PM_OPS
2450 .driver.pm = &pch_gbe_pm_ops,
2451 #endif
2452 .shutdown = pch_gbe_shutdown,
2453 .err_handler = &pch_gbe_err_handler
2454 };
2455
2456
2457 static int __init pch_gbe_init_module(void)
2458 {
2459 int ret;
2460
2461 ret = pci_register_driver(&pch_gbe_pcidev);
2462 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2463 if (copybreak == 0) {
2464 pr_info("copybreak disabled\n");
2465 } else {
2466 pr_info("copybreak enabled for packets <= %u bytes\n",
2467 copybreak);
2468 }
2469 }
2470 return ret;
2471 }
2472
2473 static void __exit pch_gbe_exit_module(void)
2474 {
2475 pci_unregister_driver(&pch_gbe_pcidev);
2476 }
2477
2478 module_init(pch_gbe_init_module);
2479 module_exit(pch_gbe_exit_module);
2480
2481 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2482 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2483 MODULE_LICENSE("GPL");
2484 MODULE_VERSION(DRV_VERSION);
2485 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2486
2487 module_param(copybreak, uint, 0644);
2488 MODULE_PARM_DESC(copybreak,
2489 "Maximum size of packet that is copied to a new buffer on receive");
2490
2491 /* pch_gbe_main.c */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree