arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/cpu.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/current.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/bios.h>
  29 #include <asm/uv/uv.h>
  30 #include <asm/apic.h>
  31 #include <asm/ipi.h>
  32 #include <asm/smp.h>
  33 #include <asm/x86_init.h>
  34
  35 DEFINE_PER_CPU(int, x2apic_extra_bits);
  36
  37 static enum uv_system_type uv_system_type;
  38 static u64 gru_start_paddr, gru_end_paddr;
  39 int uv_min_hub_revision_id;
  40 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  41
  42 static inline bool is_GRU_range(u64 start, u64 end)
  43 {
  44         return start >= gru_start_paddr && end <= gru_end_paddr;
  45 }
  46
  47 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  48 {
  49         return is_ISA_range(start, end) || is_GRU_range(start, end);
  50 }
  51
  52 static int early_get_nodeid(void)
  53 {
  54         union uvh_node_id_u node_id;
  55         unsigned long *mmr;
  56
  57         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
  58         node_id.v = *mmr;
  59         early_iounmap(mmr, sizeof(*mmr));
  60
  61         /* Currently, all blades have same revision number */
  62         uv_min_hub_revision_id = node_id.s.revision;
  63
  64         return node_id.s.node_id;
  65 }
  66
  67 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  68 {
  69         if (!strcmp(oem_id, "SGI")) {
  70                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
  71                 if (!strcmp(oem_table_id, "UVL"))
  72                         uv_system_type = UV_LEGACY_APIC;
  73                 else if (!strcmp(oem_table_id, "UVX"))
  74                         uv_system_type = UV_X2APIC;
  75                 else if (!strcmp(oem_table_id, "UVH")) {
  76                         __get_cpu_var(x2apic_extra_bits) =
  77                                 early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1);
  78                         uv_system_type = UV_NON_UNIQUE_APIC;
  79                         return 1;
  80                 }
  81         }
  82         return 0;
  83 }
  84
  85 enum uv_system_type get_uv_system_type(void)
  86 {
  87         return uv_system_type;
  88 }
  89
  90 int is_uv_system(void)
  91 {
  92         return uv_system_type != UV_NONE;
  93 }
  94 EXPORT_SYMBOL_GPL(is_uv_system);
  95
  96 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  97 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  98
  99 struct uv_blade_info *uv_blade_info;
 100 EXPORT_SYMBOL_GPL(uv_blade_info);
 101
 102 short *uv_node_to_blade;
 103 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 104
 105 short *uv_cpu_to_blade;
 106 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 107
 108 short uv_possible_blades;
 109 EXPORT_SYMBOL_GPL(uv_possible_blades);
 110
 111 unsigned long sn_rtc_cycles_per_second;
 112 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 113
 114 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
 115
 116 static const struct cpumask *uv_target_cpus(void)
 117 {
 118         return cpumask_of(0);
 119 }
 120
 121 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 122 {
 123         cpumask_clear(retmask);
 124         cpumask_set_cpu(cpu, retmask);
 125 }
 126
 127 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 128 {
 129 #ifdef CONFIG_SMP
 130         unsigned long val;
 131         int pnode;
 132
 133         pnode = uv_apicid_to_pnode(phys_apicid);
 134         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 135             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 136             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 137             APIC_DM_INIT;
 138         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 139         mdelay(10);
 140
 141         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 142             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 143             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 144             APIC_DM_STARTUP;
 145         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 146
 147         atomic_set(&init_deasserted, 1);
 148 #endif
 149         return 0;
 150 }
 151
 152 static void uv_send_IPI_one(int cpu, int vector)
 153 {
 154         unsigned long apicid;
 155         int pnode;
 156
 157         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 158         pnode = uv_apicid_to_pnode(apicid);
 159         uv_hub_send_ipi(pnode, apicid, vector);
 160 }
 161
 162 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 163 {
 164         unsigned int cpu;
 165
 166         for_each_cpu(cpu, mask)
 167                 uv_send_IPI_one(cpu, vector);
 168 }
 169
 170 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 171 {
 172         unsigned int this_cpu = smp_processor_id();
 173         unsigned int cpu;
 174
 175         for_each_cpu(cpu, mask) {
 176                 if (cpu != this_cpu)
 177                         uv_send_IPI_one(cpu, vector);
 178         }
 179 }
 180
 181 static void uv_send_IPI_allbutself(int vector)
 182 {
 183         unsigned int this_cpu = smp_processor_id();
 184         unsigned int cpu;
 185
 186         for_each_online_cpu(cpu) {
 187                 if (cpu != this_cpu)
 188                         uv_send_IPI_one(cpu, vector);
 189         }
 190 }
 191
 192 static void uv_send_IPI_all(int vector)
 193 {
 194         uv_send_IPI_mask(cpu_online_mask, vector);
 195 }
 196
 197 static int uv_apic_id_registered(void)
 198 {
 199         return 1;
 200 }
 201
 202 static void uv_init_apic_ldr(void)
 203 {
 204 }
 205
 206 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 207 {
 208         /*
 209          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 210          * May as well be the first.
 211          */
 212         int cpu = cpumask_first(cpumask);
 213
 214         if ((unsigned)cpu < nr_cpu_ids)
 215                 return per_cpu(x86_cpu_to_apicid, cpu);
 216         else
 217                 return BAD_APICID;
 218 }
 219
 220 static unsigned int
 221 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 222                           const struct cpumask *andmask)
 223 {
 224         int cpu;
 225
 226         /*
 227          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 228          * May as well be the first.
 229          */
 230         for_each_cpu_and(cpu, cpumask, andmask) {
 231                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 232                         break;
 233         }
 234         return per_cpu(x86_cpu_to_apicid, cpu);
 235 }
 236
 237 static unsigned int x2apic_get_apic_id(unsigned long x)
 238 {
 239         unsigned int id;
 240
 241         WARN_ON(preemptible() && num_online_cpus() > 1);
 242         id = x | __get_cpu_var(x2apic_extra_bits);
 243
 244         return id;
 245 }
 246
 247 static unsigned long set_apic_id(unsigned int id)
 248 {
 249         unsigned long x;
 250
 251         /* maskout x2apic_extra_bits ? */
 252         x = id;
 253         return x;
 254 }
 255
 256 static unsigned int uv_read_apic_id(void)
 257 {
 258
 259         return x2apic_get_apic_id(apic_read(APIC_ID));
 260 }
 261
 262 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 263 {
 264         return uv_read_apic_id() >> index_msb;
 265 }
 266
 267 static void uv_send_IPI_self(int vector)
 268 {
 269         apic_write(APIC_SELF_IPI, vector);
 270 }
 271
 272 struct apic __refdata apic_x2apic_uv_x = {
 273
 274         .name                           = "UV large system",
 275         .probe                          = NULL,
 276         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 277         .apic_id_registered             = uv_apic_id_registered,
 278
 279         .irq_delivery_mode              = dest_Fixed,
 280         .irq_dest_mode                  = 0, /* physical */
 281
 282         .target_cpus                    = uv_target_cpus,
 283         .disable_esr                    = 0,
 284         .dest_logical                   = APIC_DEST_LOGICAL,
 285         .check_apicid_used              = NULL,
 286         .check_apicid_present           = NULL,
 287
 288         .vector_allocation_domain       = uv_vector_allocation_domain,
 289         .init_apic_ldr                  = uv_init_apic_ldr,
 290
 291         .ioapic_phys_id_map             = NULL,
 292         .setup_apic_routing             = NULL,
 293         .multi_timer_check              = NULL,
 294         .apicid_to_node                 = NULL,
 295         .cpu_to_logical_apicid          = NULL,
 296         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 297         .apicid_to_cpu_present          = NULL,
 298         .setup_portio_remap             = NULL,
 299         .check_phys_apicid_present      = default_check_phys_apicid_present,
 300         .enable_apic_mode               = NULL,
 301         .phys_pkg_id                    = uv_phys_pkg_id,
 302         .mps_oem_check                  = NULL,
 303
 304         .get_apic_id                    = x2apic_get_apic_id,
 305         .set_apic_id                    = set_apic_id,
 306         .apic_id_mask                   = 0xFFFFFFFFu,
 307
 308         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 309         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 310
 311         .send_IPI_mask                  = uv_send_IPI_mask,
 312         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 313         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 314         .send_IPI_all                   = uv_send_IPI_all,
 315         .send_IPI_self                  = uv_send_IPI_self,
 316
 317         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 318         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 319         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 320         .wait_for_init_deassert         = NULL,
 321         .smp_callin_clear_local_apic    = NULL,
 322         .inquire_remote_apic            = NULL,
 323
 324         .read                           = native_apic_msr_read,
 325         .write                          = native_apic_msr_write,
 326         .icr_read                       = native_x2apic_icr_read,
 327         .icr_write                      = native_x2apic_icr_write,
 328         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 329         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 330 };
 331
 332 static __cpuinit void set_x2apic_extra_bits(int pnode)
 333 {
 334         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 335 }
 336
 337 /*
 338  * Called on boot cpu.
 339  */
 340 static __init int boot_pnode_to_blade(int pnode)
 341 {
 342         int blade;
 343
 344         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 345                 if (pnode == uv_blade_info[blade].pnode)
 346                         return blade;
 347         BUG();
 348 }
 349
 350 struct redir_addr {
 351         unsigned long redirect;
 352         unsigned long alias;
 353 };
 354
 355 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 356
 357 static __initdata struct redir_addr redir_addrs[] = {
 358         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 359         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 360         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 361 };
 362
 363 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 364 {
 365         union uvh_si_alias0_overlay_config_u alias;
 366         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 367         int i;
 368
 369         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 370                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 371                 if (alias.s.enable && alias.s.base == 0) {
 372                         *size = (1UL << alias.s.m_alias);
 373                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 374                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 375                         return;
 376                 }
 377         }
 378         *base = *size = 0;
 379 }
 380
 381 enum map_type {map_wb, map_uc};
 382
 383 static __init void map_high(char *id, unsigned long base, int pshift,
 384                         int bshift, int max_pnode, enum map_type map_type)
 385 {
 386         unsigned long bytes, paddr;
 387
 388         paddr = base << pshift;
 389         bytes = (1UL << bshift) * (max_pnode + 1);
 390         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 391                                                 paddr + bytes);
 392         if (map_type == map_uc)
 393                 init_extra_mapping_uc(paddr, bytes);
 394         else
 395                 init_extra_mapping_wb(paddr, bytes);
 396
 397 }
 398 static __init void map_gru_high(int max_pnode)
 399 {
 400         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 401         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 402
 403         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 404         if (gru.s.enable) {
 405                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 406                 gru_start_paddr = ((u64)gru.s.base << shift);
 407                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 408
 409         }
 410 }
 411
 412 static __init void map_mmr_high(int max_pnode)
 413 {
 414         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 415         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 416
 417         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 418         if (mmr.s.enable)
 419                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 420 }
 421
 422 static __init void map_mmioh_high(int max_pnode)
 423 {
 424         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 425         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 426
 427         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 428         if (mmioh.s.enable)
 429                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 430                         max_pnode, map_uc);
 431 }
 432
 433 static __init void map_low_mmrs(void)
 434 {
 435         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 436         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 437 }
 438
 439 static __init void uv_rtc_init(void)
 440 {
 441         long status;
 442         u64 ticks_per_sec;
 443
 444         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 445                                         &ticks_per_sec);
 446         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 447                 printk(KERN_WARNING
 448                         "unable to determine platform RTC clock frequency, "
 449                         "guessing.\n");
 450                 /* BIOS gives wrong value for clock freq. so guess */
 451                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 452         } else
 453                 sn_rtc_cycles_per_second = ticks_per_sec;
 454 }
 455
 456 /*
 457  * percpu heartbeat timer
 458  */
 459 static void uv_heartbeat(unsigned long ignored)
 460 {
 461         struct timer_list *timer = &uv_hub_info->scir.timer;
 462         unsigned char bits = uv_hub_info->scir.state;
 463
 464         /* flip heartbeat bit */
 465         bits ^= SCIR_CPU_HEARTBEAT;
 466
 467         /* is this cpu idle? */
 468         if (idle_cpu(raw_smp_processor_id()))
 469                 bits &= ~SCIR_CPU_ACTIVITY;
 470         else
 471                 bits |= SCIR_CPU_ACTIVITY;
 472
 473         /* update system controller interface reg */
 474         uv_set_scir_bits(bits);
 475
 476         /* enable next timer period */
 477         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 478 }
 479
 480 static void __cpuinit uv_heartbeat_enable(int cpu)
 481 {
 482         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 483                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 484
 485                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 486                 setup_timer(timer, uv_heartbeat, cpu);
 487                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 488                 add_timer_on(timer, cpu);
 489                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 490         }
 491
 492         /* check boot cpu */
 493         if (!uv_cpu_hub_info(0)->scir.enabled)
 494                 uv_heartbeat_enable(0);
 495 }
 496
 497 #ifdef CONFIG_HOTPLUG_CPU
 498 static void __cpuinit uv_heartbeat_disable(int cpu)
 499 {
 500         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 501                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 502                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 503         }
 504         uv_set_cpu_scir_bits(cpu, 0xff);
 505 }
 506
 507 /*
 508  * cpu hotplug notifier
 509  */
 510 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 511                                        unsigned long action, void *hcpu)
 512 {
 513         long cpu = (long)hcpu;
 514
 515         switch (action) {
 516         case CPU_ONLINE:
 517                 uv_heartbeat_enable(cpu);
 518                 break;
 519         case CPU_DOWN_PREPARE:
 520                 uv_heartbeat_disable(cpu);
 521                 break;
 522         default:
 523                 break;
 524         }
 525         return NOTIFY_OK;
 526 }
 527
 528 static __init void uv_scir_register_cpu_notifier(void)
 529 {
 530         hotcpu_notifier(uv_scir_cpu_notify, 0);
 531 }
 532
 533 #else /* !CONFIG_HOTPLUG_CPU */
 534
 535 static __init void uv_scir_register_cpu_notifier(void)
 536 {
 537 }
 538
 539 static __init int uv_init_heartbeat(void)
 540 {
 541         int cpu;
 542
 543         if (is_uv_system())
 544                 for_each_online_cpu(cpu)
 545                         uv_heartbeat_enable(cpu);
 546         return 0;
 547 }
 548
 549 late_initcall(uv_init_heartbeat);
 550
 551 #endif /* !CONFIG_HOTPLUG_CPU */
 552
 553 /*
 554  * Called on each cpu to initialize the per_cpu UV data area.
 555  * FIXME: hotplug not supported yet
 556  */
 557 void __cpuinit uv_cpu_init(void)
 558 {
 559         /* CPU 0 initilization will be done via uv_system_init. */
 560         if (!uv_blade_info)
 561                 return;
 562
 563         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 564
 565         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 566                 set_x2apic_extra_bits(uv_hub_info->pnode);
 567 }
 568
 569
 570 void __init uv_system_init(void)
 571 {
 572         union uvh_si_addr_map_config_u m_n_config;
 573         union uvh_node_id_u node_id;
 574         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 575         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 576         int gnode_extra, max_pnode = 0;
 577         unsigned long mmr_base, present, paddr;
 578         unsigned short pnode_mask;
 579
 580         map_low_mmrs();
 581
 582         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 583         m_val = m_n_config.s.m_skt;
 584         n_val = m_n_config.s.n_skt;
 585         mmr_base =
 586             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 587             ~UV_MMR_ENABLE;
 588         pnode_mask = (1 << n_val) - 1;
 589         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 590         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 591         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 592         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
 593                         n_val, m_val, gnode_upper, gnode_extra);
 594
 595         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 596
 597         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 598                 uv_possible_blades +=
 599                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 600         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 601
 602         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 603         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 604         BUG_ON(!uv_blade_info);
 605         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 606                 uv_blade_info[blade].memory_nid = -1;
 607
 608         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 609
 610         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 611         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 612         BUG_ON(!uv_node_to_blade);
 613         memset(uv_node_to_blade, 255, bytes);
 614
 615         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 616         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 617         BUG_ON(!uv_cpu_to_blade);
 618         memset(uv_cpu_to_blade, 255, bytes);
 619
 620         blade = 0;
 621         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 622                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 623                 for (j = 0; j < 64; j++) {
 624                         if (!test_bit(j, &present))
 625                                 continue;
 626                         uv_blade_info[blade].pnode = (i * 64 + j);
 627                         uv_blade_info[blade].nr_possible_cpus = 0;
 628                         uv_blade_info[blade].nr_online_cpus = 0;
 629                         blade++;
 630                 }
 631         }
 632
 633         uv_bios_init();
 634         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 635                             &sn_coherency_id, &sn_region_size);
 636         uv_rtc_init();
 637
 638         for_each_present_cpu(cpu) {
 639                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 640
 641                 nid = cpu_to_node(cpu);
 642                 pnode = uv_apicid_to_pnode(apicid);
 643                 blade = boot_pnode_to_blade(pnode);
 644                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 645                 uv_blade_info[blade].nr_possible_cpus++;
 646
 647                 /* Any node on the blade, else will contain -1. */
 648                 uv_blade_info[blade].memory_nid = nid;
 649
 650                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 651                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 652                 uv_cpu_hub_info(cpu)->m_val = m_val;
 653                 uv_cpu_hub_info(cpu)->n_val = n_val;
 654                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 655                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 656                 uv_cpu_hub_info(cpu)->pnode = pnode;
 657                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 658                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 659                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 660                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 661                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 662                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 663                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 664                 uv_node_to_blade[nid] = blade;
 665                 uv_cpu_to_blade[cpu] = blade;
 666                 max_pnode = max(pnode, max_pnode);
 667
 668                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, lcpu %d, blade %d\n",
 669                         cpu, apicid, pnode, nid, lcpu, blade);
 670         }
 671
 672         /* Add blade/pnode info for nodes without cpus */
 673         for_each_online_node(nid) {
 674                 if (uv_node_to_blade[nid] >= 0)
 675                         continue;
 676                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 677                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 678                 pnode = (paddr >> m_val) & pnode_mask;
 679                 blade = boot_pnode_to_blade(pnode);
 680                 uv_node_to_blade[nid] = blade;
 681                 max_pnode = max(pnode, max_pnode);
 682         }
 683
 684         map_gru_high(max_pnode);
 685         map_mmr_high(max_pnode);
 686         map_mmioh_high(max_pnode);
 687
 688         uv_cpu_init();
 689         uv_scir_register_cpu_notifier();
 690         proc_mkdir("sgi_uv", NULL);
 691 }