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b43: add missing MMIO defines
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / b43 / main.c
blobfa27c3d97d8b59b817c321cbc2fb90e73ade175c
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
11
12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33 */
34
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/moduleparam.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
47
48 #include "b43.h"
49 #include "main.h"
50 #include "debugfs.h"
51 #include "phy_common.h"
52 #include "phy_g.h"
53 #include "phy_n.h"
54 #include "dma.h"
55 #include "pio.h"
56 #include "sysfs.h"
57 #include "xmit.h"
58 #include "lo.h"
59 #include "pcmcia.h"
60 #include "sdio.h"
61 #include <linux/mmc/sdio_func.h>
62
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
70
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
78
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
107
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
115
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
122 BCMA_CORETABLE_END
123 };
124 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
125 #endif
126
127 #ifdef CONFIG_B43_SSB
128 static const struct ssb_device_id b43_ssb_tbl[] = {
129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
139 SSB_DEVTABLE_END
140 };
141 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
142 #endif
143
144 /* Channel and ratetables are shared for all devices.
145 * They can't be const, because ieee80211 puts some precalculated
146 * data in there. This data is the same for all devices, so we don't
147 * get concurrency issues */
148 #define RATETAB_ENT(_rateid, _flags) \
149 { \
150 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
151 .hw_value = (_rateid), \
152 .flags = (_flags), \
153 }
154
155 /*
156 * NOTE: When changing this, sync with xmit.c's
157 * b43_plcp_get_bitrate_idx_* functions!
158 */
159 static struct ieee80211_rate __b43_ratetable[] = {
160 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
161 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
162 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
163 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
165 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
166 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
172 };
173
174 #define b43_a_ratetable (__b43_ratetable + 4)
175 #define b43_a_ratetable_size 8
176 #define b43_b_ratetable (__b43_ratetable + 0)
177 #define b43_b_ratetable_size 4
178 #define b43_g_ratetable (__b43_ratetable + 0)
179 #define b43_g_ratetable_size 12
180
181 #define CHAN4G(_channel, _freq, _flags) { \
182 .band = IEEE80211_BAND_2GHZ, \
183 .center_freq = (_freq), \
184 .hw_value = (_channel), \
185 .flags = (_flags), \
186 .max_antenna_gain = 0, \
187 .max_power = 30, \
188 }
189 static struct ieee80211_channel b43_2ghz_chantable[] = {
190 CHAN4G(1, 2412, 0),
191 CHAN4G(2, 2417, 0),
192 CHAN4G(3, 2422, 0),
193 CHAN4G(4, 2427, 0),
194 CHAN4G(5, 2432, 0),
195 CHAN4G(6, 2437, 0),
196 CHAN4G(7, 2442, 0),
197 CHAN4G(8, 2447, 0),
198 CHAN4G(9, 2452, 0),
199 CHAN4G(10, 2457, 0),
200 CHAN4G(11, 2462, 0),
201 CHAN4G(12, 2467, 0),
202 CHAN4G(13, 2472, 0),
203 CHAN4G(14, 2484, 0),
204 };
205 #undef CHAN4G
206
207 #define CHAN5G(_channel, _flags) { \
208 .band = IEEE80211_BAND_5GHZ, \
209 .center_freq = 5000 + (5 * (_channel)), \
210 .hw_value = (_channel), \
211 .flags = (_flags), \
212 .max_antenna_gain = 0, \
213 .max_power = 30, \
214 }
215 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
216 CHAN5G(32, 0), CHAN5G(34, 0),
217 CHAN5G(36, 0), CHAN5G(38, 0),
218 CHAN5G(40, 0), CHAN5G(42, 0),
219 CHAN5G(44, 0), CHAN5G(46, 0),
220 CHAN5G(48, 0), CHAN5G(50, 0),
221 CHAN5G(52, 0), CHAN5G(54, 0),
222 CHAN5G(56, 0), CHAN5G(58, 0),
223 CHAN5G(60, 0), CHAN5G(62, 0),
224 CHAN5G(64, 0), CHAN5G(66, 0),
225 CHAN5G(68, 0), CHAN5G(70, 0),
226 CHAN5G(72, 0), CHAN5G(74, 0),
227 CHAN5G(76, 0), CHAN5G(78, 0),
228 CHAN5G(80, 0), CHAN5G(82, 0),
229 CHAN5G(84, 0), CHAN5G(86, 0),
230 CHAN5G(88, 0), CHAN5G(90, 0),
231 CHAN5G(92, 0), CHAN5G(94, 0),
232 CHAN5G(96, 0), CHAN5G(98, 0),
233 CHAN5G(100, 0), CHAN5G(102, 0),
234 CHAN5G(104, 0), CHAN5G(106, 0),
235 CHAN5G(108, 0), CHAN5G(110, 0),
236 CHAN5G(112, 0), CHAN5G(114, 0),
237 CHAN5G(116, 0), CHAN5G(118, 0),
238 CHAN5G(120, 0), CHAN5G(122, 0),
239 CHAN5G(124, 0), CHAN5G(126, 0),
240 CHAN5G(128, 0), CHAN5G(130, 0),
241 CHAN5G(132, 0), CHAN5G(134, 0),
242 CHAN5G(136, 0), CHAN5G(138, 0),
243 CHAN5G(140, 0), CHAN5G(142, 0),
244 CHAN5G(144, 0), CHAN5G(145, 0),
245 CHAN5G(146, 0), CHAN5G(147, 0),
246 CHAN5G(148, 0), CHAN5G(149, 0),
247 CHAN5G(150, 0), CHAN5G(151, 0),
248 CHAN5G(152, 0), CHAN5G(153, 0),
249 CHAN5G(154, 0), CHAN5G(155, 0),
250 CHAN5G(156, 0), CHAN5G(157, 0),
251 CHAN5G(158, 0), CHAN5G(159, 0),
252 CHAN5G(160, 0), CHAN5G(161, 0),
253 CHAN5G(162, 0), CHAN5G(163, 0),
254 CHAN5G(164, 0), CHAN5G(165, 0),
255 CHAN5G(166, 0), CHAN5G(168, 0),
256 CHAN5G(170, 0), CHAN5G(172, 0),
257 CHAN5G(174, 0), CHAN5G(176, 0),
258 CHAN5G(178, 0), CHAN5G(180, 0),
259 CHAN5G(182, 0), CHAN5G(184, 0),
260 CHAN5G(186, 0), CHAN5G(188, 0),
261 CHAN5G(190, 0), CHAN5G(192, 0),
262 CHAN5G(194, 0), CHAN5G(196, 0),
263 CHAN5G(198, 0), CHAN5G(200, 0),
264 CHAN5G(202, 0), CHAN5G(204, 0),
265 CHAN5G(206, 0), CHAN5G(208, 0),
266 CHAN5G(210, 0), CHAN5G(212, 0),
267 CHAN5G(214, 0), CHAN5G(216, 0),
268 CHAN5G(218, 0), CHAN5G(220, 0),
269 CHAN5G(222, 0), CHAN5G(224, 0),
270 CHAN5G(226, 0), CHAN5G(228, 0),
271 };
272
273 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
274 CHAN5G(34, 0), CHAN5G(36, 0),
275 CHAN5G(38, 0), CHAN5G(40, 0),
276 CHAN5G(42, 0), CHAN5G(44, 0),
277 CHAN5G(46, 0), CHAN5G(48, 0),
278 CHAN5G(52, 0), CHAN5G(56, 0),
279 CHAN5G(60, 0), CHAN5G(64, 0),
280 CHAN5G(100, 0), CHAN5G(104, 0),
281 CHAN5G(108, 0), CHAN5G(112, 0),
282 CHAN5G(116, 0), CHAN5G(120, 0),
283 CHAN5G(124, 0), CHAN5G(128, 0),
284 CHAN5G(132, 0), CHAN5G(136, 0),
285 CHAN5G(140, 0), CHAN5G(149, 0),
286 CHAN5G(153, 0), CHAN5G(157, 0),
287 CHAN5G(161, 0), CHAN5G(165, 0),
288 CHAN5G(184, 0), CHAN5G(188, 0),
289 CHAN5G(192, 0), CHAN5G(196, 0),
290 CHAN5G(200, 0), CHAN5G(204, 0),
291 CHAN5G(208, 0), CHAN5G(212, 0),
292 CHAN5G(216, 0),
293 };
294 #undef CHAN5G
295
296 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
297 .band = IEEE80211_BAND_5GHZ,
298 .channels = b43_5ghz_nphy_chantable,
299 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
300 .bitrates = b43_a_ratetable,
301 .n_bitrates = b43_a_ratetable_size,
302 };
303
304 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
305 .band = IEEE80211_BAND_5GHZ,
306 .channels = b43_5ghz_aphy_chantable,
307 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
308 .bitrates = b43_a_ratetable,
309 .n_bitrates = b43_a_ratetable_size,
310 };
311
312 static struct ieee80211_supported_band b43_band_2GHz = {
313 .band = IEEE80211_BAND_2GHZ,
314 .channels = b43_2ghz_chantable,
315 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
316 .bitrates = b43_g_ratetable,
317 .n_bitrates = b43_g_ratetable_size,
318 };
319
320 static void b43_wireless_core_exit(struct b43_wldev *dev);
321 static int b43_wireless_core_init(struct b43_wldev *dev);
322 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
323 static int b43_wireless_core_start(struct b43_wldev *dev);
324 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
325 struct ieee80211_vif *vif,
326 struct ieee80211_bss_conf *conf,
327 u32 changed);
328
329 static int b43_ratelimit(struct b43_wl *wl)
330 {
331 if (!wl || !wl->current_dev)
332 return 1;
333 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
334 return 1;
335 /* We are up and running.
336 * Ratelimit the messages to avoid DoS over the net. */
337 return net_ratelimit();
338 }
339
340 void b43info(struct b43_wl *wl, const char *fmt, ...)
341 {
342 struct va_format vaf;
343 va_list args;
344
345 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
346 return;
347 if (!b43_ratelimit(wl))
348 return;
349
350 va_start(args, fmt);
351
352 vaf.fmt = fmt;
353 vaf.va = &args;
354
355 printk(KERN_INFO "b43-%s: %pV",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
357
358 va_end(args);
359 }
360
361 void b43err(struct b43_wl *wl, const char *fmt, ...)
362 {
363 struct va_format vaf;
364 va_list args;
365
366 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
367 return;
368 if (!b43_ratelimit(wl))
369 return;
370
371 va_start(args, fmt);
372
373 vaf.fmt = fmt;
374 vaf.va = &args;
375
376 printk(KERN_ERR "b43-%s ERROR: %pV",
377 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
378
379 va_end(args);
380 }
381
382 void b43warn(struct b43_wl *wl, const char *fmt, ...)
383 {
384 struct va_format vaf;
385 va_list args;
386
387 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
388 return;
389 if (!b43_ratelimit(wl))
390 return;
391
392 va_start(args, fmt);
393
394 vaf.fmt = fmt;
395 vaf.va = &args;
396
397 printk(KERN_WARNING "b43-%s warning: %pV",
398 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
399
400 va_end(args);
401 }
402
403 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
404 {
405 struct va_format vaf;
406 va_list args;
407
408 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
409 return;
410
411 va_start(args, fmt);
412
413 vaf.fmt = fmt;
414 vaf.va = &args;
415
416 printk(KERN_DEBUG "b43-%s debug: %pV",
417 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
418
419 va_end(args);
420 }
421
422 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
423 {
424 u32 macctl;
425
426 B43_WARN_ON(offset % 4 != 0);
427
428 macctl = b43_read32(dev, B43_MMIO_MACCTL);
429 if (macctl & B43_MACCTL_BE)
430 val = swab32(val);
431
432 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
433 mmiowb();
434 b43_write32(dev, B43_MMIO_RAM_DATA, val);
435 }
436
437 static inline void b43_shm_control_word(struct b43_wldev *dev,
438 u16 routing, u16 offset)
439 {
440 u32 control;
441
442 /* "offset" is the WORD offset. */
443 control = routing;
444 control <<= 16;
445 control |= offset;
446 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
447 }
448
449 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
450 {
451 u32 ret;
452
453 if (routing == B43_SHM_SHARED) {
454 B43_WARN_ON(offset & 0x0001);
455 if (offset & 0x0003) {
456 /* Unaligned access */
457 b43_shm_control_word(dev, routing, offset >> 2);
458 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
459 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
460 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
461
462 goto out;
463 }
464 offset >>= 2;
465 }
466 b43_shm_control_word(dev, routing, offset);
467 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
468 out:
469 return ret;
470 }
471
472 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
473 {
474 u16 ret;
475
476 if (routing == B43_SHM_SHARED) {
477 B43_WARN_ON(offset & 0x0001);
478 if (offset & 0x0003) {
479 /* Unaligned access */
480 b43_shm_control_word(dev, routing, offset >> 2);
481 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
482
483 goto out;
484 }
485 offset >>= 2;
486 }
487 b43_shm_control_word(dev, routing, offset);
488 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
489 out:
490 return ret;
491 }
492
493 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
494 {
495 if (routing == B43_SHM_SHARED) {
496 B43_WARN_ON(offset & 0x0001);
497 if (offset & 0x0003) {
498 /* Unaligned access */
499 b43_shm_control_word(dev, routing, offset >> 2);
500 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
501 value & 0xFFFF);
502 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
503 b43_write16(dev, B43_MMIO_SHM_DATA,
504 (value >> 16) & 0xFFFF);
505 return;
506 }
507 offset >>= 2;
508 }
509 b43_shm_control_word(dev, routing, offset);
510 b43_write32(dev, B43_MMIO_SHM_DATA, value);
511 }
512
513 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
514 {
515 if (routing == B43_SHM_SHARED) {
516 B43_WARN_ON(offset & 0x0001);
517 if (offset & 0x0003) {
518 /* Unaligned access */
519 b43_shm_control_word(dev, routing, offset >> 2);
520 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
521 return;
522 }
523 offset >>= 2;
524 }
525 b43_shm_control_word(dev, routing, offset);
526 b43_write16(dev, B43_MMIO_SHM_DATA, value);
527 }
528
529 /* Read HostFlags */
530 u64 b43_hf_read(struct b43_wldev *dev)
531 {
532 u64 ret;
533
534 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
535 ret <<= 16;
536 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
537 ret <<= 16;
538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
539
540 return ret;
541 }
542
543 /* Write HostFlags */
544 void b43_hf_write(struct b43_wldev *dev, u64 value)
545 {
546 u16 lo, mi, hi;
547
548 lo = (value & 0x00000000FFFFULL);
549 mi = (value & 0x0000FFFF0000ULL) >> 16;
550 hi = (value & 0xFFFF00000000ULL) >> 32;
551 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
552 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
554 }
555
556 /* Read the firmware capabilities bitmask (Opensource firmware only) */
557 static u16 b43_fwcapa_read(struct b43_wldev *dev)
558 {
559 B43_WARN_ON(!dev->fw.opensource);
560 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
561 }
562
563 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
564 {
565 u32 low, high;
566
567 B43_WARN_ON(dev->dev->core_rev < 3);
568
569 /* The hardware guarantees us an atomic read, if we
570 * read the low register first. */
571 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
572 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
573
574 *tsf = high;
575 *tsf <<= 32;
576 *tsf |= low;
577 }
578
579 static void b43_time_lock(struct b43_wldev *dev)
580 {
581 u32 macctl;
582
583 macctl = b43_read32(dev, B43_MMIO_MACCTL);
584 macctl |= B43_MACCTL_TBTTHOLD;
585 b43_write32(dev, B43_MMIO_MACCTL, macctl);
586 /* Commit the write */
587 b43_read32(dev, B43_MMIO_MACCTL);
588 }
589
590 static void b43_time_unlock(struct b43_wldev *dev)
591 {
592 u32 macctl;
593
594 macctl = b43_read32(dev, B43_MMIO_MACCTL);
595 macctl &= ~B43_MACCTL_TBTTHOLD;
596 b43_write32(dev, B43_MMIO_MACCTL, macctl);
597 /* Commit the write */
598 b43_read32(dev, B43_MMIO_MACCTL);
599 }
600
601 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
602 {
603 u32 low, high;
604
605 B43_WARN_ON(dev->dev->core_rev < 3);
606
607 low = tsf;
608 high = (tsf >> 32);
609 /* The hardware guarantees us an atomic write, if we
610 * write the low register first. */
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
612 mmiowb();
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
614 mmiowb();
615 }
616
617 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
618 {
619 b43_time_lock(dev);
620 b43_tsf_write_locked(dev, tsf);
621 b43_time_unlock(dev);
622 }
623
624 static
625 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
626 {
627 static const u8 zero_addr[ETH_ALEN] = { 0 };
628 u16 data;
629
630 if (!mac)
631 mac = zero_addr;
632
633 offset |= 0x0020;
634 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
635
636 data = mac[0];
637 data |= mac[1] << 8;
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
639 data = mac[2];
640 data |= mac[3] << 8;
641 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
642 data = mac[4];
643 data |= mac[5] << 8;
644 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
645 }
646
647 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
648 {
649 const u8 *mac;
650 const u8 *bssid;
651 u8 mac_bssid[ETH_ALEN * 2];
652 int i;
653 u32 tmp;
654
655 bssid = dev->wl->bssid;
656 mac = dev->wl->mac_addr;
657
658 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
659
660 memcpy(mac_bssid, mac, ETH_ALEN);
661 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
662
663 /* Write our MAC address and BSSID to template ram */
664 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
665 tmp = (u32) (mac_bssid[i + 0]);
666 tmp |= (u32) (mac_bssid[i + 1]) << 8;
667 tmp |= (u32) (mac_bssid[i + 2]) << 16;
668 tmp |= (u32) (mac_bssid[i + 3]) << 24;
669 b43_ram_write(dev, 0x20 + i, tmp);
670 }
671 }
672
673 static void b43_upload_card_macaddress(struct b43_wldev *dev)
674 {
675 b43_write_mac_bssid_templates(dev);
676 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
677 }
678
679 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
680 {
681 /* slot_time is in usec. */
682 /* This test used to exit for all but a G PHY. */
683 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
684 return;
685 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
686 /* Shared memory location 0x0010 is the slot time and should be
687 * set to slot_time; however, this register is initially 0 and changing
688 * the value adversely affects the transmit rate for BCM4311
689 * devices. Until this behavior is unterstood, delete this step
690 *
691 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
692 */
693 }
694
695 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
696 {
697 b43_set_slot_time(dev, 9);
698 }
699
700 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
701 {
702 b43_set_slot_time(dev, 20);
703 }
704
705 /* DummyTransmission function, as documented on
706 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
707 */
708 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
709 {
710 struct b43_phy *phy = &dev->phy;
711 unsigned int i, max_loop;
712 u16 value;
713 u32 buffer[5] = {
714 0x00000000,
715 0x00D40000,
716 0x00000000,
717 0x01000000,
718 0x00000000,
719 };
720
721 if (ofdm) {
722 max_loop = 0x1E;
723 buffer[0] = 0x000201CC;
724 } else {
725 max_loop = 0xFA;
726 buffer[0] = 0x000B846E;
727 }
728
729 for (i = 0; i < 5; i++)
730 b43_ram_write(dev, i * 4, buffer[i]);
731
732 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
733
734 if (dev->dev->core_rev < 11)
735 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
736 else
737 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
738
739 value = (ofdm ? 0x41 : 0x40);
740 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
741 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
742 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
743
744 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
745 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
746
747 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
748 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
749 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
750 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
751 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
752 //SPEC TODO
753 }
754
755 switch (phy->type) {
756 case B43_PHYTYPE_N:
757 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
758 break;
759 case B43_PHYTYPE_LP:
760 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
761 break;
762 default:
763 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
764 }
765
766 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
767 b43_radio_write16(dev, 0x0051, 0x0017);
768 for (i = 0x00; i < max_loop; i++) {
769 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
770 if (value & 0x0080)
771 break;
772 udelay(10);
773 }
774 for (i = 0x00; i < 0x0A; i++) {
775 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
776 if (value & 0x0400)
777 break;
778 udelay(10);
779 }
780 for (i = 0x00; i < 0x19; i++) {
781 value = b43_read16(dev, B43_MMIO_IFSSTAT);
782 if (!(value & 0x0100))
783 break;
784 udelay(10);
785 }
786 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
787 b43_radio_write16(dev, 0x0051, 0x0037);
788 }
789
790 static void key_write(struct b43_wldev *dev,
791 u8 index, u8 algorithm, const u8 *key)
792 {
793 unsigned int i;
794 u32 offset;
795 u16 value;
796 u16 kidx;
797
798 /* Key index/algo block */
799 kidx = b43_kidx_to_fw(dev, index);
800 value = ((kidx << 4) | algorithm);
801 b43_shm_write16(dev, B43_SHM_SHARED,
802 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
803
804 /* Write the key to the Key Table Pointer offset */
805 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
806 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
807 value = key[i];
808 value |= (u16) (key[i + 1]) << 8;
809 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
810 }
811 }
812
813 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
814 {
815 u32 addrtmp[2] = { 0, 0, };
816 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
817
818 if (b43_new_kidx_api(dev))
819 pairwise_keys_start = B43_NR_GROUP_KEYS;
820
821 B43_WARN_ON(index < pairwise_keys_start);
822 /* We have four default TX keys and possibly four default RX keys.
823 * Physical mac 0 is mapped to physical key 4 or 8, depending
824 * on the firmware version.
825 * So we must adjust the index here.
826 */
827 index -= pairwise_keys_start;
828 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
829
830 if (addr) {
831 addrtmp[0] = addr[0];
832 addrtmp[0] |= ((u32) (addr[1]) << 8);
833 addrtmp[0] |= ((u32) (addr[2]) << 16);
834 addrtmp[0] |= ((u32) (addr[3]) << 24);
835 addrtmp[1] = addr[4];
836 addrtmp[1] |= ((u32) (addr[5]) << 8);
837 }
838
839 /* Receive match transmitter address (RCMTA) mechanism */
840 b43_shm_write32(dev, B43_SHM_RCMTA,
841 (index * 2) + 0, addrtmp[0]);
842 b43_shm_write16(dev, B43_SHM_RCMTA,
843 (index * 2) + 1, addrtmp[1]);
844 }
845
846 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
847 * When a packet is received, the iv32 is checked.
848 * - if it doesn't the packet is returned without modification (and software
849 * decryption can be done). That's what happen when iv16 wrap.
850 * - if it does, the rc4 key is computed, and decryption is tried.
851 * Either it will success and B43_RX_MAC_DEC is returned,
852 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
853 * and the packet is not usable (it got modified by the ucode).
854 * So in order to never have B43_RX_MAC_DECERR, we should provide
855 * a iv32 and phase1key that match. Because we drop packets in case of
856 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
857 * packets will be lost without higher layer knowing (ie no resync possible
858 * until next wrap).
859 *
860 * NOTE : this should support 50 key like RCMTA because
861 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
862 */
863 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
864 u16 *phase1key)
865 {
866 unsigned int i;
867 u32 offset;
868 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
869
870 if (!modparam_hwtkip)
871 return;
872
873 if (b43_new_kidx_api(dev))
874 pairwise_keys_start = B43_NR_GROUP_KEYS;
875
876 B43_WARN_ON(index < pairwise_keys_start);
877 /* We have four default TX keys and possibly four default RX keys.
878 * Physical mac 0 is mapped to physical key 4 or 8, depending
879 * on the firmware version.
880 * So we must adjust the index here.
881 */
882 index -= pairwise_keys_start;
883 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
884
885 if (b43_debug(dev, B43_DBG_KEYS)) {
886 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
887 index, iv32);
888 }
889 /* Write the key to the RX tkip shared mem */
890 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
891 for (i = 0; i < 10; i += 2) {
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
893 phase1key ? phase1key[i / 2] : 0);
894 }
895 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
896 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
897 }
898
899 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
900 struct ieee80211_vif *vif,
901 struct ieee80211_key_conf *keyconf,
902 struct ieee80211_sta *sta,
903 u32 iv32, u16 *phase1key)
904 {
905 struct b43_wl *wl = hw_to_b43_wl(hw);
906 struct b43_wldev *dev;
907 int index = keyconf->hw_key_idx;
908
909 if (B43_WARN_ON(!modparam_hwtkip))
910 return;
911
912 /* This is only called from the RX path through mac80211, where
913 * our mutex is already locked. */
914 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
915 dev = wl->current_dev;
916 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
917
918 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
919
920 rx_tkip_phase1_write(dev, index, iv32, phase1key);
921 /* only pairwise TKIP keys are supported right now */
922 if (WARN_ON(!sta))
923 return;
924 keymac_write(dev, index, sta->addr);
925 }
926
927 static void do_key_write(struct b43_wldev *dev,
928 u8 index, u8 algorithm,
929 const u8 *key, size_t key_len, const u8 *mac_addr)
930 {
931 u8 buf[B43_SEC_KEYSIZE] = { 0, };
932 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
933
934 if (b43_new_kidx_api(dev))
935 pairwise_keys_start = B43_NR_GROUP_KEYS;
936
937 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
938 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
939
940 if (index >= pairwise_keys_start)
941 keymac_write(dev, index, NULL); /* First zero out mac. */
942 if (algorithm == B43_SEC_ALGO_TKIP) {
943 /*
944 * We should provide an initial iv32, phase1key pair.
945 * We could start with iv32=0 and compute the corresponding
946 * phase1key, but this means calling ieee80211_get_tkip_key
947 * with a fake skb (or export other tkip function).
948 * Because we are lazy we hope iv32 won't start with
949 * 0xffffffff and let's b43_op_update_tkip_key provide a
950 * correct pair.
951 */
952 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
953 } else if (index >= pairwise_keys_start) /* clear it */
954 rx_tkip_phase1_write(dev, index, 0, NULL);
955 if (key)
956 memcpy(buf, key, key_len);
957 key_write(dev, index, algorithm, buf);
958 if (index >= pairwise_keys_start)
959 keymac_write(dev, index, mac_addr);
960
961 dev->key[index].algorithm = algorithm;
962 }
963
964 static int b43_key_write(struct b43_wldev *dev,
965 int index, u8 algorithm,
966 const u8 *key, size_t key_len,
967 const u8 *mac_addr,
968 struct ieee80211_key_conf *keyconf)
969 {
970 int i;
971 int pairwise_keys_start;
972
973 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
974 * - Temporal Encryption Key (128 bits)
975 * - Temporal Authenticator Tx MIC Key (64 bits)
976 * - Temporal Authenticator Rx MIC Key (64 bits)
977 *
978 * Hardware only store TEK
979 */
980 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
981 key_len = 16;
982 if (key_len > B43_SEC_KEYSIZE)
983 return -EINVAL;
984 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
985 /* Check that we don't already have this key. */
986 B43_WARN_ON(dev->key[i].keyconf == keyconf);
987 }
988 if (index < 0) {
989 /* Pairwise key. Get an empty slot for the key. */
990 if (b43_new_kidx_api(dev))
991 pairwise_keys_start = B43_NR_GROUP_KEYS;
992 else
993 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
994 for (i = pairwise_keys_start;
995 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
996 i++) {
997 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
998 if (!dev->key[i].keyconf) {
999 /* found empty */
1000 index = i;
1001 break;
1002 }
1003 }
1004 if (index < 0) {
1005 b43warn(dev->wl, "Out of hardware key memory\n");
1006 return -ENOSPC;
1007 }
1008 } else
1009 B43_WARN_ON(index > 3);
1010
1011 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1012 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1013 /* Default RX key */
1014 B43_WARN_ON(mac_addr);
1015 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1016 }
1017 keyconf->hw_key_idx = index;
1018 dev->key[index].keyconf = keyconf;
1019
1020 return 0;
1021 }
1022
1023 static int b43_key_clear(struct b43_wldev *dev, int index)
1024 {
1025 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1026 return -EINVAL;
1027 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1028 NULL, B43_SEC_KEYSIZE, NULL);
1029 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1030 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1031 NULL, B43_SEC_KEYSIZE, NULL);
1032 }
1033 dev->key[index].keyconf = NULL;
1034
1035 return 0;
1036 }
1037
1038 static void b43_clear_keys(struct b43_wldev *dev)
1039 {
1040 int i, count;
1041
1042 if (b43_new_kidx_api(dev))
1043 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1044 else
1045 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1046 for (i = 0; i < count; i++)
1047 b43_key_clear(dev, i);
1048 }
1049
1050 static void b43_dump_keymemory(struct b43_wldev *dev)
1051 {
1052 unsigned int i, index, count, offset, pairwise_keys_start;
1053 u8 mac[ETH_ALEN];
1054 u16 algo;
1055 u32 rcmta0;
1056 u16 rcmta1;
1057 u64 hf;
1058 struct b43_key *key;
1059
1060 if (!b43_debug(dev, B43_DBG_KEYS))
1061 return;
1062
1063 hf = b43_hf_read(dev);
1064 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1065 !!(hf & B43_HF_USEDEFKEYS));
1066 if (b43_new_kidx_api(dev)) {
1067 pairwise_keys_start = B43_NR_GROUP_KEYS;
1068 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1069 } else {
1070 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1071 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1072 }
1073 for (index = 0; index < count; index++) {
1074 key = &(dev->key[index]);
1075 printk(KERN_DEBUG "Key slot %02u: %s",
1076 index, (key->keyconf == NULL) ? " " : "*");
1077 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1078 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1079 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1080 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1081 }
1082
1083 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1084 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1085 printk(" Algo: %04X/%02X", algo, key->algorithm);
1086
1087 if (index >= pairwise_keys_start) {
1088 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1089 printk(" TKIP: ");
1090 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1091 for (i = 0; i < 14; i += 2) {
1092 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1093 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1094 }
1095 }
1096 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1097 ((index - pairwise_keys_start) * 2) + 0);
1098 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1099 ((index - pairwise_keys_start) * 2) + 1);
1100 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1101 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1102 printk(" MAC: %pM", mac);
1103 } else
1104 printk(" DEFAULT KEY");
1105 printk("\n");
1106 }
1107 }
1108
1109 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1110 {
1111 u32 macctl;
1112 u16 ucstat;
1113 bool hwps;
1114 bool awake;
1115 int i;
1116
1117 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1118 (ps_flags & B43_PS_DISABLED));
1119 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1120
1121 if (ps_flags & B43_PS_ENABLED) {
1122 hwps = 1;
1123 } else if (ps_flags & B43_PS_DISABLED) {
1124 hwps = 0;
1125 } else {
1126 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1127 // and thus is not an AP and we are associated, set bit 25
1128 }
1129 if (ps_flags & B43_PS_AWAKE) {
1130 awake = 1;
1131 } else if (ps_flags & B43_PS_ASLEEP) {
1132 awake = 0;
1133 } else {
1134 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1135 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1136 // successful, set bit26
1137 }
1138
1139 /* FIXME: For now we force awake-on and hwps-off */
1140 hwps = 0;
1141 awake = 1;
1142
1143 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1144 if (hwps)
1145 macctl |= B43_MACCTL_HWPS;
1146 else
1147 macctl &= ~B43_MACCTL_HWPS;
1148 if (awake)
1149 macctl |= B43_MACCTL_AWAKE;
1150 else
1151 macctl &= ~B43_MACCTL_AWAKE;
1152 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1153 /* Commit write */
1154 b43_read32(dev, B43_MMIO_MACCTL);
1155 if (awake && dev->dev->core_rev >= 5) {
1156 /* Wait for the microcode to wake up. */
1157 for (i = 0; i < 100; i++) {
1158 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1159 B43_SHM_SH_UCODESTAT);
1160 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1161 break;
1162 udelay(10);
1163 }
1164 }
1165 }
1166
1167 #ifdef CONFIG_B43_BCMA
1168 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1169 {
1170 u32 flags;
1171
1172 /* Put PHY into reset */
1173 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1174 flags |= B43_BCMA_IOCTL_PHY_RESET;
1175 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1176 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1177 udelay(2);
1178
1179 /* Take PHY out of reset */
1180 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1181 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1182 flags |= BCMA_IOCTL_FGC;
1183 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1184 udelay(1);
1185
1186 /* Do not force clock anymore */
1187 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1188 flags &= ~BCMA_IOCTL_FGC;
1189 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1190 udelay(1);
1191 }
1192
1193 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1194 {
1195 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1196 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1197 b43_bcma_phy_reset(dev);
1198 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1199 }
1200 #endif
1201
1202 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1203 {
1204 struct ssb_device *sdev = dev->dev->sdev;
1205 u32 tmslow;
1206 u32 flags = 0;
1207
1208 if (gmode)
1209 flags |= B43_TMSLOW_GMODE;
1210 flags |= B43_TMSLOW_PHYCLKEN;
1211 flags |= B43_TMSLOW_PHYRESET;
1212 if (dev->phy.type == B43_PHYTYPE_N)
1213 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1214 b43_device_enable(dev, flags);
1215 msleep(2); /* Wait for the PLL to turn on. */
1216
1217 /* Now take the PHY out of Reset again */
1218 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1219 tmslow |= SSB_TMSLOW_FGC;
1220 tmslow &= ~B43_TMSLOW_PHYRESET;
1221 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1222 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1223 msleep(1);
1224 tmslow &= ~SSB_TMSLOW_FGC;
1225 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1226 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1227 msleep(1);
1228 }
1229
1230 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1231 {
1232 u32 macctl;
1233
1234 switch (dev->dev->bus_type) {
1235 #ifdef CONFIG_B43_BCMA
1236 case B43_BUS_BCMA:
1237 b43_bcma_wireless_core_reset(dev, gmode);
1238 break;
1239 #endif
1240 #ifdef CONFIG_B43_SSB
1241 case B43_BUS_SSB:
1242 b43_ssb_wireless_core_reset(dev, gmode);
1243 break;
1244 #endif
1245 }
1246
1247 /* Turn Analog ON, but only if we already know the PHY-type.
1248 * This protects against very early setup where we don't know the
1249 * PHY-type, yet. wireless_core_reset will be called once again later,
1250 * when we know the PHY-type. */
1251 if (dev->phy.ops)
1252 dev->phy.ops->switch_analog(dev, 1);
1253
1254 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1255 macctl &= ~B43_MACCTL_GMODE;
1256 if (gmode)
1257 macctl |= B43_MACCTL_GMODE;
1258 macctl |= B43_MACCTL_IHR_ENABLED;
1259 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1260 }
1261
1262 static void handle_irq_transmit_status(struct b43_wldev *dev)
1263 {
1264 u32 v0, v1;
1265 u16 tmp;
1266 struct b43_txstatus stat;
1267
1268 while (1) {
1269 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1270 if (!(v0 & 0x00000001))
1271 break;
1272 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1273
1274 stat.cookie = (v0 >> 16);
1275 stat.seq = (v1 & 0x0000FFFF);
1276 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1277 tmp = (v0 & 0x0000FFFF);
1278 stat.frame_count = ((tmp & 0xF000) >> 12);
1279 stat.rts_count = ((tmp & 0x0F00) >> 8);
1280 stat.supp_reason = ((tmp & 0x001C) >> 2);
1281 stat.pm_indicated = !!(tmp & 0x0080);
1282 stat.intermediate = !!(tmp & 0x0040);
1283 stat.for_ampdu = !!(tmp & 0x0020);
1284 stat.acked = !!(tmp & 0x0002);
1285
1286 b43_handle_txstatus(dev, &stat);
1287 }
1288 }
1289
1290 static void drain_txstatus_queue(struct b43_wldev *dev)
1291 {
1292 u32 dummy;
1293
1294 if (dev->dev->core_rev < 5)
1295 return;
1296 /* Read all entries from the microcode TXstatus FIFO
1297 * and throw them away.
1298 */
1299 while (1) {
1300 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1301 if (!(dummy & 0x00000001))
1302 break;
1303 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1304 }
1305 }
1306
1307 static u32 b43_jssi_read(struct b43_wldev *dev)
1308 {
1309 u32 val = 0;
1310
1311 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1312 val <<= 16;
1313 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1314
1315 return val;
1316 }
1317
1318 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1319 {
1320 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1321 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1322 }
1323
1324 static void b43_generate_noise_sample(struct b43_wldev *dev)
1325 {
1326 b43_jssi_write(dev, 0x7F7F7F7F);
1327 b43_write32(dev, B43_MMIO_MACCMD,
1328 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1329 }
1330
1331 static void b43_calculate_link_quality(struct b43_wldev *dev)
1332 {
1333 /* Top half of Link Quality calculation. */
1334
1335 if (dev->phy.type != B43_PHYTYPE_G)
1336 return;
1337 if (dev->noisecalc.calculation_running)
1338 return;
1339 dev->noisecalc.calculation_running = 1;
1340 dev->noisecalc.nr_samples = 0;
1341
1342 b43_generate_noise_sample(dev);
1343 }
1344
1345 static void handle_irq_noise(struct b43_wldev *dev)
1346 {
1347 struct b43_phy_g *phy = dev->phy.g;
1348 u16 tmp;
1349 u8 noise[4];
1350 u8 i, j;
1351 s32 average;
1352
1353 /* Bottom half of Link Quality calculation. */
1354
1355 if (dev->phy.type != B43_PHYTYPE_G)
1356 return;
1357
1358 /* Possible race condition: It might be possible that the user
1359 * changed to a different channel in the meantime since we
1360 * started the calculation. We ignore that fact, since it's
1361 * not really that much of a problem. The background noise is
1362 * an estimation only anyway. Slightly wrong results will get damped
1363 * by the averaging of the 8 sample rounds. Additionally the
1364 * value is shortlived. So it will be replaced by the next noise
1365 * calculation round soon. */
1366
1367 B43_WARN_ON(!dev->noisecalc.calculation_running);
1368 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1369 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1370 noise[2] == 0x7F || noise[3] == 0x7F)
1371 goto generate_new;
1372
1373 /* Get the noise samples. */
1374 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1375 i = dev->noisecalc.nr_samples;
1376 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1377 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1378 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1379 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1380 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1381 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1382 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1383 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1384 dev->noisecalc.nr_samples++;
1385 if (dev->noisecalc.nr_samples == 8) {
1386 /* Calculate the Link Quality by the noise samples. */
1387 average = 0;
1388 for (i = 0; i < 8; i++) {
1389 for (j = 0; j < 4; j++)
1390 average += dev->noisecalc.samples[i][j];
1391 }
1392 average /= (8 * 4);
1393 average *= 125;
1394 average += 64;
1395 average /= 128;
1396 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1397 tmp = (tmp / 128) & 0x1F;
1398 if (tmp >= 8)
1399 average += 2;
1400 else
1401 average -= 25;
1402 if (tmp == 8)
1403 average -= 72;
1404 else
1405 average -= 48;
1406
1407 dev->stats.link_noise = average;
1408 dev->noisecalc.calculation_running = 0;
1409 return;
1410 }
1411 generate_new:
1412 b43_generate_noise_sample(dev);
1413 }
1414
1415 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1416 {
1417 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1418 ///TODO: PS TBTT
1419 } else {
1420 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1421 b43_power_saving_ctl_bits(dev, 0);
1422 }
1423 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1424 dev->dfq_valid = 1;
1425 }
1426
1427 static void handle_irq_atim_end(struct b43_wldev *dev)
1428 {
1429 if (dev->dfq_valid) {
1430 b43_write32(dev, B43_MMIO_MACCMD,
1431 b43_read32(dev, B43_MMIO_MACCMD)
1432 | B43_MACCMD_DFQ_VALID);
1433 dev->dfq_valid = 0;
1434 }
1435 }
1436
1437 static void handle_irq_pmq(struct b43_wldev *dev)
1438 {
1439 u32 tmp;
1440
1441 //TODO: AP mode.
1442
1443 while (1) {
1444 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1445 if (!(tmp & 0x00000008))
1446 break;
1447 }
1448 /* 16bit write is odd, but correct. */
1449 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1450 }
1451
1452 static void b43_write_template_common(struct b43_wldev *dev,
1453 const u8 *data, u16 size,
1454 u16 ram_offset,
1455 u16 shm_size_offset, u8 rate)
1456 {
1457 u32 i, tmp;
1458 struct b43_plcp_hdr4 plcp;
1459
1460 plcp.data = 0;
1461 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1462 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1463 ram_offset += sizeof(u32);
1464 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1465 * So leave the first two bytes of the next write blank.
1466 */
1467 tmp = (u32) (data[0]) << 16;
1468 tmp |= (u32) (data[1]) << 24;
1469 b43_ram_write(dev, ram_offset, tmp);
1470 ram_offset += sizeof(u32);
1471 for (i = 2; i < size; i += sizeof(u32)) {
1472 tmp = (u32) (data[i + 0]);
1473 if (i + 1 < size)
1474 tmp |= (u32) (data[i + 1]) << 8;
1475 if (i + 2 < size)
1476 tmp |= (u32) (data[i + 2]) << 16;
1477 if (i + 3 < size)
1478 tmp |= (u32) (data[i + 3]) << 24;
1479 b43_ram_write(dev, ram_offset + i - 2, tmp);
1480 }
1481 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1482 size + sizeof(struct b43_plcp_hdr6));
1483 }
1484
1485 /* Check if the use of the antenna that ieee80211 told us to
1486 * use is possible. This will fall back to DEFAULT.
1487 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1488 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1489 u8 antenna_nr)
1490 {
1491 u8 antenna_mask;
1492
1493 if (antenna_nr == 0) {
1494 /* Zero means "use default antenna". That's always OK. */
1495 return 0;
1496 }
1497
1498 /* Get the mask of available antennas. */
1499 if (dev->phy.gmode)
1500 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1501 else
1502 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1503
1504 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1505 /* This antenna is not available. Fall back to default. */
1506 return 0;
1507 }
1508
1509 return antenna_nr;
1510 }
1511
1512 /* Convert a b43 antenna number value to the PHY TX control value. */
1513 static u16 b43_antenna_to_phyctl(int antenna)
1514 {
1515 switch (antenna) {
1516 case B43_ANTENNA0:
1517 return B43_TXH_PHY_ANT0;
1518 case B43_ANTENNA1:
1519 return B43_TXH_PHY_ANT1;
1520 case B43_ANTENNA2:
1521 return B43_TXH_PHY_ANT2;
1522 case B43_ANTENNA3:
1523 return B43_TXH_PHY_ANT3;
1524 case B43_ANTENNA_AUTO0:
1525 case B43_ANTENNA_AUTO1:
1526 return B43_TXH_PHY_ANT01AUTO;
1527 }
1528 B43_WARN_ON(1);
1529 return 0;
1530 }
1531
1532 static void b43_write_beacon_template(struct b43_wldev *dev,
1533 u16 ram_offset,
1534 u16 shm_size_offset)
1535 {
1536 unsigned int i, len, variable_len;
1537 const struct ieee80211_mgmt *bcn;
1538 const u8 *ie;
1539 bool tim_found = 0;
1540 unsigned int rate;
1541 u16 ctl;
1542 int antenna;
1543 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1544
1545 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1546 len = min((size_t) dev->wl->current_beacon->len,
1547 0x200 - sizeof(struct b43_plcp_hdr6));
1548 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1549
1550 b43_write_template_common(dev, (const u8 *)bcn,
1551 len, ram_offset, shm_size_offset, rate);
1552
1553 /* Write the PHY TX control parameters. */
1554 antenna = B43_ANTENNA_DEFAULT;
1555 antenna = b43_antenna_to_phyctl(antenna);
1556 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1557 /* We can't send beacons with short preamble. Would get PHY errors. */
1558 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1559 ctl &= ~B43_TXH_PHY_ANT;
1560 ctl &= ~B43_TXH_PHY_ENC;
1561 ctl |= antenna;
1562 if (b43_is_cck_rate(rate))
1563 ctl |= B43_TXH_PHY_ENC_CCK;
1564 else
1565 ctl |= B43_TXH_PHY_ENC_OFDM;
1566 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1567
1568 /* Find the position of the TIM and the DTIM_period value
1569 * and write them to SHM. */
1570 ie = bcn->u.beacon.variable;
1571 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1572 for (i = 0; i < variable_len - 2; ) {
1573 uint8_t ie_id, ie_len;
1574
1575 ie_id = ie[i];
1576 ie_len = ie[i + 1];
1577 if (ie_id == 5) {
1578 u16 tim_position;
1579 u16 dtim_period;
1580 /* This is the TIM Information Element */
1581
1582 /* Check whether the ie_len is in the beacon data range. */
1583 if (variable_len < ie_len + 2 + i)
1584 break;
1585 /* A valid TIM is at least 4 bytes long. */
1586 if (ie_len < 4)
1587 break;
1588 tim_found = 1;
1589
1590 tim_position = sizeof(struct b43_plcp_hdr6);
1591 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1592 tim_position += i;
1593
1594 dtim_period = ie[i + 3];
1595
1596 b43_shm_write16(dev, B43_SHM_SHARED,
1597 B43_SHM_SH_TIMBPOS, tim_position);
1598 b43_shm_write16(dev, B43_SHM_SHARED,
1599 B43_SHM_SH_DTIMPER, dtim_period);
1600 break;
1601 }
1602 i += ie_len + 2;
1603 }
1604 if (!tim_found) {
1605 /*
1606 * If ucode wants to modify TIM do it behind the beacon, this
1607 * will happen, for example, when doing mesh networking.
1608 */
1609 b43_shm_write16(dev, B43_SHM_SHARED,
1610 B43_SHM_SH_TIMBPOS,
1611 len + sizeof(struct b43_plcp_hdr6));
1612 b43_shm_write16(dev, B43_SHM_SHARED,
1613 B43_SHM_SH_DTIMPER, 0);
1614 }
1615 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1616 }
1617
1618 static void b43_upload_beacon0(struct b43_wldev *dev)
1619 {
1620 struct b43_wl *wl = dev->wl;
1621
1622 if (wl->beacon0_uploaded)
1623 return;
1624 b43_write_beacon_template(dev, 0x68, 0x18);
1625 wl->beacon0_uploaded = 1;
1626 }
1627
1628 static void b43_upload_beacon1(struct b43_wldev *dev)
1629 {
1630 struct b43_wl *wl = dev->wl;
1631
1632 if (wl->beacon1_uploaded)
1633 return;
1634 b43_write_beacon_template(dev, 0x468, 0x1A);
1635 wl->beacon1_uploaded = 1;
1636 }
1637
1638 static void handle_irq_beacon(struct b43_wldev *dev)
1639 {
1640 struct b43_wl *wl = dev->wl;
1641 u32 cmd, beacon0_valid, beacon1_valid;
1642
1643 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1644 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1645 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1646 return;
1647
1648 /* This is the bottom half of the asynchronous beacon update. */
1649
1650 /* Ignore interrupt in the future. */
1651 dev->irq_mask &= ~B43_IRQ_BEACON;
1652
1653 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1654 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1655 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1656
1657 /* Schedule interrupt manually, if busy. */
1658 if (beacon0_valid && beacon1_valid) {
1659 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1660 dev->irq_mask |= B43_IRQ_BEACON;
1661 return;
1662 }
1663
1664 if (unlikely(wl->beacon_templates_virgin)) {
1665 /* We never uploaded a beacon before.
1666 * Upload both templates now, but only mark one valid. */
1667 wl->beacon_templates_virgin = 0;
1668 b43_upload_beacon0(dev);
1669 b43_upload_beacon1(dev);
1670 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1671 cmd |= B43_MACCMD_BEACON0_VALID;
1672 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1673 } else {
1674 if (!beacon0_valid) {
1675 b43_upload_beacon0(dev);
1676 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1677 cmd |= B43_MACCMD_BEACON0_VALID;
1678 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1679 } else if (!beacon1_valid) {
1680 b43_upload_beacon1(dev);
1681 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1682 cmd |= B43_MACCMD_BEACON1_VALID;
1683 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1684 }
1685 }
1686 }
1687
1688 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1689 {
1690 u32 old_irq_mask = dev->irq_mask;
1691
1692 /* update beacon right away or defer to irq */
1693 handle_irq_beacon(dev);
1694 if (old_irq_mask != dev->irq_mask) {
1695 /* The handler updated the IRQ mask. */
1696 B43_WARN_ON(!dev->irq_mask);
1697 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1698 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1699 } else {
1700 /* Device interrupts are currently disabled. That means
1701 * we just ran the hardirq handler and scheduled the
1702 * IRQ thread. The thread will write the IRQ mask when
1703 * it finished, so there's nothing to do here. Writing
1704 * the mask _here_ would incorrectly re-enable IRQs. */
1705 }
1706 }
1707 }
1708
1709 static void b43_beacon_update_trigger_work(struct work_struct *work)
1710 {
1711 struct b43_wl *wl = container_of(work, struct b43_wl,
1712 beacon_update_trigger);
1713 struct b43_wldev *dev;
1714
1715 mutex_lock(&wl->mutex);
1716 dev = wl->current_dev;
1717 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1718 if (b43_bus_host_is_sdio(dev->dev)) {
1719 /* wl->mutex is enough. */
1720 b43_do_beacon_update_trigger_work(dev);
1721 mmiowb();
1722 } else {
1723 spin_lock_irq(&wl->hardirq_lock);
1724 b43_do_beacon_update_trigger_work(dev);
1725 mmiowb();
1726 spin_unlock_irq(&wl->hardirq_lock);
1727 }
1728 }
1729 mutex_unlock(&wl->mutex);
1730 }
1731
1732 /* Asynchronously update the packet templates in template RAM.
1733 * Locking: Requires wl->mutex to be locked. */
1734 static void b43_update_templates(struct b43_wl *wl)
1735 {
1736 struct sk_buff *beacon;
1737
1738 /* This is the top half of the ansynchronous beacon update.
1739 * The bottom half is the beacon IRQ.
1740 * Beacon update must be asynchronous to avoid sending an
1741 * invalid beacon. This can happen for example, if the firmware
1742 * transmits a beacon while we are updating it. */
1743
1744 /* We could modify the existing beacon and set the aid bit in
1745 * the TIM field, but that would probably require resizing and
1746 * moving of data within the beacon template.
1747 * Simply request a new beacon and let mac80211 do the hard work. */
1748 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1749 if (unlikely(!beacon))
1750 return;
1751
1752 if (wl->current_beacon)
1753 dev_kfree_skb_any(wl->current_beacon);
1754 wl->current_beacon = beacon;
1755 wl->beacon0_uploaded = 0;
1756 wl->beacon1_uploaded = 0;
1757 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1758 }
1759
1760 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1761 {
1762 b43_time_lock(dev);
1763 if (dev->dev->core_rev >= 3) {
1764 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1765 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1766 } else {
1767 b43_write16(dev, 0x606, (beacon_int >> 6));
1768 b43_write16(dev, 0x610, beacon_int);
1769 }
1770 b43_time_unlock(dev);
1771 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1772 }
1773
1774 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1775 {
1776 u16 reason;
1777
1778 /* Read the register that contains the reason code for the panic. */
1779 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1780 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1781
1782 switch (reason) {
1783 default:
1784 b43dbg(dev->wl, "The panic reason is unknown.\n");
1785 /* fallthrough */
1786 case B43_FWPANIC_DIE:
1787 /* Do not restart the controller or firmware.
1788 * The device is nonfunctional from now on.
1789 * Restarting would result in this panic to trigger again,
1790 * so we avoid that recursion. */
1791 break;
1792 case B43_FWPANIC_RESTART:
1793 b43_controller_restart(dev, "Microcode panic");
1794 break;
1795 }
1796 }
1797
1798 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1799 {
1800 unsigned int i, cnt;
1801 u16 reason, marker_id, marker_line;
1802 __le16 *buf;
1803
1804 /* The proprietary firmware doesn't have this IRQ. */
1805 if (!dev->fw.opensource)
1806 return;
1807
1808 /* Read the register that contains the reason code for this IRQ. */
1809 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1810
1811 switch (reason) {
1812 case B43_DEBUGIRQ_PANIC:
1813 b43_handle_firmware_panic(dev);
1814 break;
1815 case B43_DEBUGIRQ_DUMP_SHM:
1816 if (!B43_DEBUG)
1817 break; /* Only with driver debugging enabled. */
1818 buf = kmalloc(4096, GFP_ATOMIC);
1819 if (!buf) {
1820 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1821 goto out;
1822 }
1823 for (i = 0; i < 4096; i += 2) {
1824 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1825 buf[i / 2] = cpu_to_le16(tmp);
1826 }
1827 b43info(dev->wl, "Shared memory dump:\n");
1828 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1829 16, 2, buf, 4096, 1);
1830 kfree(buf);
1831 break;
1832 case B43_DEBUGIRQ_DUMP_REGS:
1833 if (!B43_DEBUG)
1834 break; /* Only with driver debugging enabled. */
1835 b43info(dev->wl, "Microcode register dump:\n");
1836 for (i = 0, cnt = 0; i < 64; i++) {
1837 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1838 if (cnt == 0)
1839 printk(KERN_INFO);
1840 printk("r%02u: 0x%04X ", i, tmp);
1841 cnt++;
1842 if (cnt == 6) {
1843 printk("\n");
1844 cnt = 0;
1845 }
1846 }
1847 printk("\n");
1848 break;
1849 case B43_DEBUGIRQ_MARKER:
1850 if (!B43_DEBUG)
1851 break; /* Only with driver debugging enabled. */
1852 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1853 B43_MARKER_ID_REG);
1854 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1855 B43_MARKER_LINE_REG);
1856 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1857 "at line number %u\n",
1858 marker_id, marker_line);
1859 break;
1860 default:
1861 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1862 reason);
1863 }
1864 out:
1865 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1866 b43_shm_write16(dev, B43_SHM_SCRATCH,
1867 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1868 }
1869
1870 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1871 {
1872 u32 reason;
1873 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1874 u32 merged_dma_reason = 0;
1875 int i;
1876
1877 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1878 return;
1879
1880 reason = dev->irq_reason;
1881 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1882 dma_reason[i] = dev->dma_reason[i];
1883 merged_dma_reason |= dma_reason[i];
1884 }
1885
1886 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1887 b43err(dev->wl, "MAC transmission error\n");
1888
1889 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1890 b43err(dev->wl, "PHY transmission error\n");
1891 rmb();
1892 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1893 atomic_set(&dev->phy.txerr_cnt,
1894 B43_PHY_TX_BADNESS_LIMIT);
1895 b43err(dev->wl, "Too many PHY TX errors, "
1896 "restarting the controller\n");
1897 b43_controller_restart(dev, "PHY TX errors");
1898 }
1899 }
1900
1901 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1902 B43_DMAIRQ_NONFATALMASK))) {
1903 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1904 b43err(dev->wl, "Fatal DMA error: "
1905 "0x%08X, 0x%08X, 0x%08X, "
1906 "0x%08X, 0x%08X, 0x%08X\n",
1907 dma_reason[0], dma_reason[1],
1908 dma_reason[2], dma_reason[3],
1909 dma_reason[4], dma_reason[5]);
1910 b43err(dev->wl, "This device does not support DMA "
1911 "on your system. It will now be switched to PIO.\n");
1912 /* Fall back to PIO transfers if we get fatal DMA errors! */
1913 dev->use_pio = 1;
1914 b43_controller_restart(dev, "DMA error");
1915 return;
1916 }
1917 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1918 b43err(dev->wl, "DMA error: "
1919 "0x%08X, 0x%08X, 0x%08X, "
1920 "0x%08X, 0x%08X, 0x%08X\n",
1921 dma_reason[0], dma_reason[1],
1922 dma_reason[2], dma_reason[3],
1923 dma_reason[4], dma_reason[5]);
1924 }
1925 }
1926
1927 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1928 handle_irq_ucode_debug(dev);
1929 if (reason & B43_IRQ_TBTT_INDI)
1930 handle_irq_tbtt_indication(dev);
1931 if (reason & B43_IRQ_ATIM_END)
1932 handle_irq_atim_end(dev);
1933 if (reason & B43_IRQ_BEACON)
1934 handle_irq_beacon(dev);
1935 if (reason & B43_IRQ_PMQ)
1936 handle_irq_pmq(dev);
1937 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1938 ;/* TODO */
1939 if (reason & B43_IRQ_NOISESAMPLE_OK)
1940 handle_irq_noise(dev);
1941
1942 /* Check the DMA reason registers for received data. */
1943 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1944 if (b43_using_pio_transfers(dev))
1945 b43_pio_rx(dev->pio.rx_queue);
1946 else
1947 b43_dma_rx(dev->dma.rx_ring);
1948 }
1949 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1950 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1951 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1952 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1953 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1954
1955 if (reason & B43_IRQ_TX_OK)
1956 handle_irq_transmit_status(dev);
1957
1958 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1959 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1960
1961 #if B43_DEBUG
1962 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1963 dev->irq_count++;
1964 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1965 if (reason & (1 << i))
1966 dev->irq_bit_count[i]++;
1967 }
1968 }
1969 #endif
1970 }
1971
1972 /* Interrupt thread handler. Handles device interrupts in thread context. */
1973 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1974 {
1975 struct b43_wldev *dev = dev_id;
1976
1977 mutex_lock(&dev->wl->mutex);
1978 b43_do_interrupt_thread(dev);
1979 mmiowb();
1980 mutex_unlock(&dev->wl->mutex);
1981
1982 return IRQ_HANDLED;
1983 }
1984
1985 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1986 {
1987 u32 reason;
1988
1989 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1990 * On SDIO, this runs under wl->mutex. */
1991
1992 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1993 if (reason == 0xffffffff) /* shared IRQ */
1994 return IRQ_NONE;
1995 reason &= dev->irq_mask;
1996 if (!reason)
1997 return IRQ_NONE;
1998
1999 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
2000 & 0x0001DC00;
2001 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2002 & 0x0000DC00;
2003 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2004 & 0x0000DC00;
2005 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2006 & 0x0001DC00;
2007 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2008 & 0x0000DC00;
2009 /* Unused ring
2010 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2011 & 0x0000DC00;
2012 */
2013
2014 /* ACK the interrupt. */
2015 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2016 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2017 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2018 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2019 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2020 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2021 /* Unused ring
2022 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2023 */
2024
2025 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2026 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2027 /* Save the reason bitmasks for the IRQ thread handler. */
2028 dev->irq_reason = reason;
2029
2030 return IRQ_WAKE_THREAD;
2031 }
2032
2033 /* Interrupt handler top-half. This runs with interrupts disabled. */
2034 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2035 {
2036 struct b43_wldev *dev = dev_id;
2037 irqreturn_t ret;
2038
2039 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2040 return IRQ_NONE;
2041
2042 spin_lock(&dev->wl->hardirq_lock);
2043 ret = b43_do_interrupt(dev);
2044 mmiowb();
2045 spin_unlock(&dev->wl->hardirq_lock);
2046
2047 return ret;
2048 }
2049
2050 /* SDIO interrupt handler. This runs in process context. */
2051 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2052 {
2053 struct b43_wl *wl = dev->wl;
2054 irqreturn_t ret;
2055
2056 mutex_lock(&wl->mutex);
2057
2058 ret = b43_do_interrupt(dev);
2059 if (ret == IRQ_WAKE_THREAD)
2060 b43_do_interrupt_thread(dev);
2061
2062 mutex_unlock(&wl->mutex);
2063 }
2064
2065 void b43_do_release_fw(struct b43_firmware_file *fw)
2066 {
2067 release_firmware(fw->data);
2068 fw->data = NULL;
2069 fw->filename = NULL;
2070 }
2071
2072 static void b43_release_firmware(struct b43_wldev *dev)
2073 {
2074 b43_do_release_fw(&dev->fw.ucode);
2075 b43_do_release_fw(&dev->fw.pcm);
2076 b43_do_release_fw(&dev->fw.initvals);
2077 b43_do_release_fw(&dev->fw.initvals_band);
2078 }
2079
2080 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2081 {
2082 const char text[] =
2083 "You must go to " \
2084 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2085 "and download the correct firmware for this driver version. " \
2086 "Please carefully read all instructions on this website.\n";
2087
2088 if (error)
2089 b43err(wl, text);
2090 else
2091 b43warn(wl, text);
2092 }
2093
2094 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2095 const char *name,
2096 struct b43_firmware_file *fw)
2097 {
2098 const struct firmware *blob;
2099 struct b43_fw_header *hdr;
2100 u32 size;
2101 int err;
2102
2103 if (!name) {
2104 /* Don't fetch anything. Free possibly cached firmware. */
2105 /* FIXME: We should probably keep it anyway, to save some headache
2106 * on suspend/resume with multiband devices. */
2107 b43_do_release_fw(fw);
2108 return 0;
2109 }
2110 if (fw->filename) {
2111 if ((fw->type == ctx->req_type) &&
2112 (strcmp(fw->filename, name) == 0))
2113 return 0; /* Already have this fw. */
2114 /* Free the cached firmware first. */
2115 /* FIXME: We should probably do this later after we successfully
2116 * got the new fw. This could reduce headache with multiband devices.
2117 * We could also redesign this to cache the firmware for all possible
2118 * bands all the time. */
2119 b43_do_release_fw(fw);
2120 }
2121
2122 switch (ctx->req_type) {
2123 case B43_FWTYPE_PROPRIETARY:
2124 snprintf(ctx->fwname, sizeof(ctx->fwname),
2125 "b43%s/%s.fw",
2126 modparam_fwpostfix, name);
2127 break;
2128 case B43_FWTYPE_OPENSOURCE:
2129 snprintf(ctx->fwname, sizeof(ctx->fwname),
2130 "b43-open%s/%s.fw",
2131 modparam_fwpostfix, name);
2132 break;
2133 default:
2134 B43_WARN_ON(1);
2135 return -ENOSYS;
2136 }
2137 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2138 if (err == -ENOENT) {
2139 snprintf(ctx->errors[ctx->req_type],
2140 sizeof(ctx->errors[ctx->req_type]),
2141 "Firmware file \"%s\" not found\n", ctx->fwname);
2142 return err;
2143 } else if (err) {
2144 snprintf(ctx->errors[ctx->req_type],
2145 sizeof(ctx->errors[ctx->req_type]),
2146 "Firmware file \"%s\" request failed (err=%d)\n",
2147 ctx->fwname, err);
2148 return err;
2149 }
2150 if (blob->size < sizeof(struct b43_fw_header))
2151 goto err_format;
2152 hdr = (struct b43_fw_header *)(blob->data);
2153 switch (hdr->type) {
2154 case B43_FW_TYPE_UCODE:
2155 case B43_FW_TYPE_PCM:
2156 size = be32_to_cpu(hdr->size);
2157 if (size != blob->size - sizeof(struct b43_fw_header))
2158 goto err_format;
2159 /* fallthrough */
2160 case B43_FW_TYPE_IV:
2161 if (hdr->ver != 1)
2162 goto err_format;
2163 break;
2164 default:
2165 goto err_format;
2166 }
2167
2168 fw->data = blob;
2169 fw->filename = name;
2170 fw->type = ctx->req_type;
2171
2172 return 0;
2173
2174 err_format:
2175 snprintf(ctx->errors[ctx->req_type],
2176 sizeof(ctx->errors[ctx->req_type]),
2177 "Firmware file \"%s\" format error.\n", ctx->fwname);
2178 release_firmware(blob);
2179
2180 return -EPROTO;
2181 }
2182
2183 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2184 {
2185 struct b43_wldev *dev = ctx->dev;
2186 struct b43_firmware *fw = &ctx->dev->fw;
2187 const u8 rev = ctx->dev->dev->core_rev;
2188 const char *filename;
2189 u32 tmshigh;
2190 int err;
2191
2192 /* Files for HT and LCN were found by trying one by one */
2193
2194 /* Get microcode */
2195 if ((rev >= 5) && (rev <= 10)) {
2196 filename = "ucode5";
2197 } else if ((rev >= 11) && (rev <= 12)) {
2198 filename = "ucode11";
2199 } else if (rev == 13) {
2200 filename = "ucode13";
2201 } else if (rev == 14) {
2202 filename = "ucode14";
2203 } else if (rev == 15) {
2204 filename = "ucode15";
2205 } else {
2206 switch (dev->phy.type) {
2207 case B43_PHYTYPE_N:
2208 if (rev >= 16)
2209 filename = "ucode16_mimo";
2210 else
2211 goto err_no_ucode;
2212 break;
2213 case B43_PHYTYPE_HT:
2214 if (rev == 29)
2215 filename = "ucode29_mimo";
2216 else
2217 goto err_no_ucode;
2218 break;
2219 case B43_PHYTYPE_LCN:
2220 if (rev == 24)
2221 filename = "ucode24_mimo";
2222 else
2223 goto err_no_ucode;
2224 break;
2225 default:
2226 goto err_no_ucode;
2227 }
2228 }
2229 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2230 if (err)
2231 goto err_load;
2232
2233 /* Get PCM code */
2234 if ((rev >= 5) && (rev <= 10))
2235 filename = "pcm5";
2236 else if (rev >= 11)
2237 filename = NULL;
2238 else
2239 goto err_no_pcm;
2240 fw->pcm_request_failed = 0;
2241 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2242 if (err == -ENOENT) {
2243 /* We did not find a PCM file? Not fatal, but
2244 * core rev <= 10 must do without hwcrypto then. */
2245 fw->pcm_request_failed = 1;
2246 } else if (err)
2247 goto err_load;
2248
2249 /* Get initvals */
2250 switch (dev->phy.type) {
2251 case B43_PHYTYPE_A:
2252 if ((rev >= 5) && (rev <= 10)) {
2253 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2254 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2255 filename = "a0g1initvals5";
2256 else
2257 filename = "a0g0initvals5";
2258 } else
2259 goto err_no_initvals;
2260 break;
2261 case B43_PHYTYPE_G:
2262 if ((rev >= 5) && (rev <= 10))
2263 filename = "b0g0initvals5";
2264 else if (rev >= 13)
2265 filename = "b0g0initvals13";
2266 else
2267 goto err_no_initvals;
2268 break;
2269 case B43_PHYTYPE_N:
2270 if (rev >= 16)
2271 filename = "n0initvals16";
2272 else if ((rev >= 11) && (rev <= 12))
2273 filename = "n0initvals11";
2274 else
2275 goto err_no_initvals;
2276 break;
2277 case B43_PHYTYPE_LP:
2278 if (rev == 13)
2279 filename = "lp0initvals13";
2280 else if (rev == 14)
2281 filename = "lp0initvals14";
2282 else if (rev >= 15)
2283 filename = "lp0initvals15";
2284 else
2285 goto err_no_initvals;
2286 break;
2287 case B43_PHYTYPE_HT:
2288 if (rev == 29)
2289 filename = "ht0initvals29";
2290 else
2291 goto err_no_initvals;
2292 break;
2293 case B43_PHYTYPE_LCN:
2294 if (rev == 24)
2295 filename = "lcn0initvals24";
2296 else
2297 goto err_no_initvals;
2298 break;
2299 default:
2300 goto err_no_initvals;
2301 }
2302 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2303 if (err)
2304 goto err_load;
2305
2306 /* Get bandswitch initvals */
2307 switch (dev->phy.type) {
2308 case B43_PHYTYPE_A:
2309 if ((rev >= 5) && (rev <= 10)) {
2310 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2311 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2312 filename = "a0g1bsinitvals5";
2313 else
2314 filename = "a0g0bsinitvals5";
2315 } else if (rev >= 11)
2316 filename = NULL;
2317 else
2318 goto err_no_initvals;
2319 break;
2320 case B43_PHYTYPE_G:
2321 if ((rev >= 5) && (rev <= 10))
2322 filename = "b0g0bsinitvals5";
2323 else if (rev >= 11)
2324 filename = NULL;
2325 else
2326 goto err_no_initvals;
2327 break;
2328 case B43_PHYTYPE_N:
2329 if (rev >= 16)
2330 filename = "n0bsinitvals16";
2331 else if ((rev >= 11) && (rev <= 12))
2332 filename = "n0bsinitvals11";
2333 else
2334 goto err_no_initvals;
2335 break;
2336 case B43_PHYTYPE_LP:
2337 if (rev == 13)
2338 filename = "lp0bsinitvals13";
2339 else if (rev == 14)
2340 filename = "lp0bsinitvals14";
2341 else if (rev >= 15)
2342 filename = "lp0bsinitvals15";
2343 else
2344 goto err_no_initvals;
2345 break;
2346 case B43_PHYTYPE_HT:
2347 if (rev == 29)
2348 filename = "ht0bsinitvals29";
2349 else
2350 goto err_no_initvals;
2351 break;
2352 case B43_PHYTYPE_LCN:
2353 if (rev == 24)
2354 filename = "lcn0bsinitvals24";
2355 else
2356 goto err_no_initvals;
2357 break;
2358 default:
2359 goto err_no_initvals;
2360 }
2361 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2362 if (err)
2363 goto err_load;
2364
2365 return 0;
2366
2367 err_no_ucode:
2368 err = ctx->fatal_failure = -EOPNOTSUPP;
2369 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2370 "is required for your device (wl-core rev %u)\n", rev);
2371 goto error;
2372
2373 err_no_pcm:
2374 err = ctx->fatal_failure = -EOPNOTSUPP;
2375 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2376 "is required for your device (wl-core rev %u)\n", rev);
2377 goto error;
2378
2379 err_no_initvals:
2380 err = ctx->fatal_failure = -EOPNOTSUPP;
2381 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2382 "is required for your device (wl-core rev %u)\n", rev);
2383 goto error;
2384
2385 err_load:
2386 /* We failed to load this firmware image. The error message
2387 * already is in ctx->errors. Return and let our caller decide
2388 * what to do. */
2389 goto error;
2390
2391 error:
2392 b43_release_firmware(dev);
2393 return err;
2394 }
2395
2396 static int b43_request_firmware(struct b43_wldev *dev)
2397 {
2398 struct b43_request_fw_context *ctx;
2399 unsigned int i;
2400 int err;
2401 const char *errmsg;
2402
2403 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2404 if (!ctx)
2405 return -ENOMEM;
2406 ctx->dev = dev;
2407
2408 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2409 err = b43_try_request_fw(ctx);
2410 if (!err)
2411 goto out; /* Successfully loaded it. */
2412 err = ctx->fatal_failure;
2413 if (err)
2414 goto out;
2415
2416 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2417 err = b43_try_request_fw(ctx);
2418 if (!err)
2419 goto out; /* Successfully loaded it. */
2420 err = ctx->fatal_failure;
2421 if (err)
2422 goto out;
2423
2424 /* Could not find a usable firmware. Print the errors. */
2425 for (i = 0; i < B43_NR_FWTYPES; i++) {
2426 errmsg = ctx->errors[i];
2427 if (strlen(errmsg))
2428 b43err(dev->wl, errmsg);
2429 }
2430 b43_print_fw_helptext(dev->wl, 1);
2431 err = -ENOENT;
2432
2433 out:
2434 kfree(ctx);
2435 return err;
2436 }
2437
2438 static int b43_upload_microcode(struct b43_wldev *dev)
2439 {
2440 struct wiphy *wiphy = dev->wl->hw->wiphy;
2441 const size_t hdr_len = sizeof(struct b43_fw_header);
2442 const __be32 *data;
2443 unsigned int i, len;
2444 u16 fwrev, fwpatch, fwdate, fwtime;
2445 u32 tmp, macctl;
2446 int err = 0;
2447
2448 /* Jump the microcode PSM to offset 0 */
2449 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2450 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2451 macctl |= B43_MACCTL_PSM_JMP0;
2452 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2453 /* Zero out all microcode PSM registers and shared memory. */
2454 for (i = 0; i < 64; i++)
2455 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2456 for (i = 0; i < 4096; i += 2)
2457 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2458
2459 /* Upload Microcode. */
2460 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2461 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2462 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2463 for (i = 0; i < len; i++) {
2464 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2465 udelay(10);
2466 }
2467
2468 if (dev->fw.pcm.data) {
2469 /* Upload PCM data. */
2470 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2471 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2472 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2473 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2474 /* No need for autoinc bit in SHM_HW */
2475 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2476 for (i = 0; i < len; i++) {
2477 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2478 udelay(10);
2479 }
2480 }
2481
2482 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2483
2484 /* Start the microcode PSM */
2485 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2486 macctl &= ~B43_MACCTL_PSM_JMP0;
2487 macctl |= B43_MACCTL_PSM_RUN;
2488 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2489
2490 /* Wait for the microcode to load and respond */
2491 i = 0;
2492 while (1) {
2493 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2494 if (tmp == B43_IRQ_MAC_SUSPENDED)
2495 break;
2496 i++;
2497 if (i >= 20) {
2498 b43err(dev->wl, "Microcode not responding\n");
2499 b43_print_fw_helptext(dev->wl, 1);
2500 err = -ENODEV;
2501 goto error;
2502 }
2503 msleep(50);
2504 }
2505 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2506
2507 /* Get and check the revisions. */
2508 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2509 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2510 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2511 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2512
2513 if (fwrev <= 0x128) {
2514 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2515 "binary drivers older than version 4.x is unsupported. "
2516 "You must upgrade your firmware files.\n");
2517 b43_print_fw_helptext(dev->wl, 1);
2518 err = -EOPNOTSUPP;
2519 goto error;
2520 }
2521 dev->fw.rev = fwrev;
2522 dev->fw.patch = fwpatch;
2523 if (dev->fw.rev >= 598)
2524 dev->fw.hdr_format = B43_FW_HDR_598;
2525 else if (dev->fw.rev >= 410)
2526 dev->fw.hdr_format = B43_FW_HDR_410;
2527 else
2528 dev->fw.hdr_format = B43_FW_HDR_351;
2529 dev->fw.opensource = (fwdate == 0xFFFF);
2530
2531 /* Default to use-all-queues. */
2532 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2533 dev->qos_enabled = !!modparam_qos;
2534 /* Default to firmware/hardware crypto acceleration. */
2535 dev->hwcrypto_enabled = 1;
2536
2537 if (dev->fw.opensource) {
2538 u16 fwcapa;
2539
2540 /* Patchlevel info is encoded in the "time" field. */
2541 dev->fw.patch = fwtime;
2542 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2543 dev->fw.rev, dev->fw.patch);
2544
2545 fwcapa = b43_fwcapa_read(dev);
2546 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2547 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2548 /* Disable hardware crypto and fall back to software crypto. */
2549 dev->hwcrypto_enabled = 0;
2550 }
2551 if (!(fwcapa & B43_FWCAPA_QOS)) {
2552 b43info(dev->wl, "QoS not supported by firmware\n");
2553 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2554 * ieee80211_unregister to make sure the networking core can
2555 * properly free possible resources. */
2556 dev->wl->hw->queues = 1;
2557 dev->qos_enabled = 0;
2558 }
2559 } else {
2560 b43info(dev->wl, "Loading firmware version %u.%u "
2561 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2562 fwrev, fwpatch,
2563 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2564 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2565 if (dev->fw.pcm_request_failed) {
2566 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2567 "Hardware accelerated cryptography is disabled.\n");
2568 b43_print_fw_helptext(dev->wl, 0);
2569 }
2570 }
2571
2572 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2573 dev->fw.rev, dev->fw.patch);
2574 wiphy->hw_version = dev->dev->core_id;
2575
2576 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2577 /* We're over the deadline, but we keep support for old fw
2578 * until it turns out to be in major conflict with something new. */
2579 b43warn(dev->wl, "You are using an old firmware image. "
2580 "Support for old firmware will be removed soon "
2581 "(official deadline was July 2008).\n");
2582 b43_print_fw_helptext(dev->wl, 0);
2583 }
2584
2585 return 0;
2586
2587 error:
2588 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2589 macctl &= ~B43_MACCTL_PSM_RUN;
2590 macctl |= B43_MACCTL_PSM_JMP0;
2591 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2592
2593 return err;
2594 }
2595
2596 static int b43_write_initvals(struct b43_wldev *dev,
2597 const struct b43_iv *ivals,
2598 size_t count,
2599 size_t array_size)
2600 {
2601 const struct b43_iv *iv;
2602 u16 offset;
2603 size_t i;
2604 bool bit32;
2605
2606 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2607 iv = ivals;
2608 for (i = 0; i < count; i++) {
2609 if (array_size < sizeof(iv->offset_size))
2610 goto err_format;
2611 array_size -= sizeof(iv->offset_size);
2612 offset = be16_to_cpu(iv->offset_size);
2613 bit32 = !!(offset & B43_IV_32BIT);
2614 offset &= B43_IV_OFFSET_MASK;
2615 if (offset >= 0x1000)
2616 goto err_format;
2617 if (bit32) {
2618 u32 value;
2619
2620 if (array_size < sizeof(iv->data.d32))
2621 goto err_format;
2622 array_size -= sizeof(iv->data.d32);
2623
2624 value = get_unaligned_be32(&iv->data.d32);
2625 b43_write32(dev, offset, value);
2626
2627 iv = (const struct b43_iv *)((const uint8_t *)iv +
2628 sizeof(__be16) +
2629 sizeof(__be32));
2630 } else {
2631 u16 value;
2632
2633 if (array_size < sizeof(iv->data.d16))
2634 goto err_format;
2635 array_size -= sizeof(iv->data.d16);
2636
2637 value = be16_to_cpu(iv->data.d16);
2638 b43_write16(dev, offset, value);
2639
2640 iv = (const struct b43_iv *)((const uint8_t *)iv +
2641 sizeof(__be16) +
2642 sizeof(__be16));
2643 }
2644 }
2645 if (array_size)
2646 goto err_format;
2647
2648 return 0;
2649
2650 err_format:
2651 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2652 b43_print_fw_helptext(dev->wl, 1);
2653
2654 return -EPROTO;
2655 }
2656
2657 static int b43_upload_initvals(struct b43_wldev *dev)
2658 {
2659 const size_t hdr_len = sizeof(struct b43_fw_header);
2660 const struct b43_fw_header *hdr;
2661 struct b43_firmware *fw = &dev->fw;
2662 const struct b43_iv *ivals;
2663 size_t count;
2664 int err;
2665
2666 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2667 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2668 count = be32_to_cpu(hdr->size);
2669 err = b43_write_initvals(dev, ivals, count,
2670 fw->initvals.data->size - hdr_len);
2671 if (err)
2672 goto out;
2673 if (fw->initvals_band.data) {
2674 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2675 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2676 count = be32_to_cpu(hdr->size);
2677 err = b43_write_initvals(dev, ivals, count,
2678 fw->initvals_band.data->size - hdr_len);
2679 if (err)
2680 goto out;
2681 }
2682 out:
2683
2684 return err;
2685 }
2686
2687 /* Initialize the GPIOs
2688 * http://bcm-specs.sipsolutions.net/GPIO
2689 */
2690 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2691 {
2692 struct ssb_bus *bus = dev->dev->sdev->bus;
2693
2694 #ifdef CONFIG_SSB_DRIVER_PCICORE
2695 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2696 #else
2697 return bus->chipco.dev;
2698 #endif
2699 }
2700
2701 static int b43_gpio_init(struct b43_wldev *dev)
2702 {
2703 struct ssb_device *gpiodev;
2704 u32 mask, set;
2705
2706 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2707 & ~B43_MACCTL_GPOUTSMSK);
2708
2709 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2710 | 0x000F);
2711
2712 mask = 0x0000001F;
2713 set = 0x0000000F;
2714 if (dev->dev->chip_id == 0x4301) {
2715 mask |= 0x0060;
2716 set |= 0x0060;
2717 }
2718 if (0 /* FIXME: conditional unknown */ ) {
2719 b43_write16(dev, B43_MMIO_GPIO_MASK,
2720 b43_read16(dev, B43_MMIO_GPIO_MASK)
2721 | 0x0100);
2722 mask |= 0x0180;
2723 set |= 0x0180;
2724 }
2725 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2726 b43_write16(dev, B43_MMIO_GPIO_MASK,
2727 b43_read16(dev, B43_MMIO_GPIO_MASK)
2728 | 0x0200);
2729 mask |= 0x0200;
2730 set |= 0x0200;
2731 }
2732 if (dev->dev->core_rev >= 2)
2733 mask |= 0x0010; /* FIXME: This is redundant. */
2734
2735 switch (dev->dev->bus_type) {
2736 #ifdef CONFIG_B43_BCMA
2737 case B43_BUS_BCMA:
2738 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2739 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2740 BCMA_CC_GPIOCTL) & mask) | set);
2741 break;
2742 #endif
2743 #ifdef CONFIG_B43_SSB
2744 case B43_BUS_SSB:
2745 gpiodev = b43_ssb_gpio_dev(dev);
2746 if (gpiodev)
2747 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2748 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2749 & mask) | set);
2750 break;
2751 #endif
2752 }
2753
2754 return 0;
2755 }
2756
2757 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2758 static void b43_gpio_cleanup(struct b43_wldev *dev)
2759 {
2760 struct ssb_device *gpiodev;
2761
2762 switch (dev->dev->bus_type) {
2763 #ifdef CONFIG_B43_BCMA
2764 case B43_BUS_BCMA:
2765 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2766 0);
2767 break;
2768 #endif
2769 #ifdef CONFIG_B43_SSB
2770 case B43_BUS_SSB:
2771 gpiodev = b43_ssb_gpio_dev(dev);
2772 if (gpiodev)
2773 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2774 break;
2775 #endif
2776 }
2777 }
2778
2779 /* http://bcm-specs.sipsolutions.net/EnableMac */
2780 void b43_mac_enable(struct b43_wldev *dev)
2781 {
2782 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2783 u16 fwstate;
2784
2785 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2786 B43_SHM_SH_UCODESTAT);
2787 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2788 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2789 b43err(dev->wl, "b43_mac_enable(): The firmware "
2790 "should be suspended, but current state is %u\n",
2791 fwstate);
2792 }
2793 }
2794
2795 dev->mac_suspended--;
2796 B43_WARN_ON(dev->mac_suspended < 0);
2797 if (dev->mac_suspended == 0) {
2798 b43_write32(dev, B43_MMIO_MACCTL,
2799 b43_read32(dev, B43_MMIO_MACCTL)
2800 | B43_MACCTL_ENABLED);
2801 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2802 B43_IRQ_MAC_SUSPENDED);
2803 /* Commit writes */
2804 b43_read32(dev, B43_MMIO_MACCTL);
2805 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2806 b43_power_saving_ctl_bits(dev, 0);
2807 }
2808 }
2809
2810 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2811 void b43_mac_suspend(struct b43_wldev *dev)
2812 {
2813 int i;
2814 u32 tmp;
2815
2816 might_sleep();
2817 B43_WARN_ON(dev->mac_suspended < 0);
2818
2819 if (dev->mac_suspended == 0) {
2820 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2821 b43_write32(dev, B43_MMIO_MACCTL,
2822 b43_read32(dev, B43_MMIO_MACCTL)
2823 & ~B43_MACCTL_ENABLED);
2824 /* force pci to flush the write */
2825 b43_read32(dev, B43_MMIO_MACCTL);
2826 for (i = 35; i; i--) {
2827 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2828 if (tmp & B43_IRQ_MAC_SUSPENDED)
2829 goto out;
2830 udelay(10);
2831 }
2832 /* Hm, it seems this will take some time. Use msleep(). */
2833 for (i = 40; i; i--) {
2834 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2835 if (tmp & B43_IRQ_MAC_SUSPENDED)
2836 goto out;
2837 msleep(1);
2838 }
2839 b43err(dev->wl, "MAC suspend failed\n");
2840 }
2841 out:
2842 dev->mac_suspended++;
2843 }
2844
2845 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2846 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2847 {
2848 u32 tmp;
2849
2850 switch (dev->dev->bus_type) {
2851 #ifdef CONFIG_B43_BCMA
2852 case B43_BUS_BCMA:
2853 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2854 if (on)
2855 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2856 else
2857 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2858 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2859 break;
2860 #endif
2861 #ifdef CONFIG_B43_SSB
2862 case B43_BUS_SSB:
2863 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2864 if (on)
2865 tmp |= B43_TMSLOW_MACPHYCLKEN;
2866 else
2867 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2868 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2869 break;
2870 #endif
2871 }
2872 }
2873
2874 static void b43_adjust_opmode(struct b43_wldev *dev)
2875 {
2876 struct b43_wl *wl = dev->wl;
2877 u32 ctl;
2878 u16 cfp_pretbtt;
2879
2880 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2881 /* Reset status to STA infrastructure mode. */
2882 ctl &= ~B43_MACCTL_AP;
2883 ctl &= ~B43_MACCTL_KEEP_CTL;
2884 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2885 ctl &= ~B43_MACCTL_KEEP_BAD;
2886 ctl &= ~B43_MACCTL_PROMISC;
2887 ctl &= ~B43_MACCTL_BEACPROMISC;
2888 ctl |= B43_MACCTL_INFRA;
2889
2890 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2891 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2892 ctl |= B43_MACCTL_AP;
2893 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2894 ctl &= ~B43_MACCTL_INFRA;
2895
2896 if (wl->filter_flags & FIF_CONTROL)
2897 ctl |= B43_MACCTL_KEEP_CTL;
2898 if (wl->filter_flags & FIF_FCSFAIL)
2899 ctl |= B43_MACCTL_KEEP_BAD;
2900 if (wl->filter_flags & FIF_PLCPFAIL)
2901 ctl |= B43_MACCTL_KEEP_BADPLCP;
2902 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2903 ctl |= B43_MACCTL_PROMISC;
2904 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2905 ctl |= B43_MACCTL_BEACPROMISC;
2906
2907 /* Workaround: On old hardware the HW-MAC-address-filter
2908 * doesn't work properly, so always run promisc in filter
2909 * it in software. */
2910 if (dev->dev->core_rev <= 4)
2911 ctl |= B43_MACCTL_PROMISC;
2912
2913 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2914
2915 cfp_pretbtt = 2;
2916 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2917 if (dev->dev->chip_id == 0x4306 &&
2918 dev->dev->chip_rev == 3)
2919 cfp_pretbtt = 100;
2920 else
2921 cfp_pretbtt = 50;
2922 }
2923 b43_write16(dev, 0x612, cfp_pretbtt);
2924
2925 /* FIXME: We don't currently implement the PMQ mechanism,
2926 * so always disable it. If we want to implement PMQ,
2927 * we need to enable it here (clear DISCPMQ) in AP mode.
2928 */
2929 if (0 /* ctl & B43_MACCTL_AP */) {
2930 b43_write32(dev, B43_MMIO_MACCTL,
2931 b43_read32(dev, B43_MMIO_MACCTL)
2932 & ~B43_MACCTL_DISCPMQ);
2933 } else {
2934 b43_write32(dev, B43_MMIO_MACCTL,
2935 b43_read32(dev, B43_MMIO_MACCTL)
2936 | B43_MACCTL_DISCPMQ);
2937 }
2938 }
2939
2940 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2941 {
2942 u16 offset;
2943
2944 if (is_ofdm) {
2945 offset = 0x480;
2946 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2947 } else {
2948 offset = 0x4C0;
2949 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2950 }
2951 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2952 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2953 }
2954
2955 static void b43_rate_memory_init(struct b43_wldev *dev)
2956 {
2957 switch (dev->phy.type) {
2958 case B43_PHYTYPE_A:
2959 case B43_PHYTYPE_G:
2960 case B43_PHYTYPE_N:
2961 case B43_PHYTYPE_LP:
2962 case B43_PHYTYPE_HT:
2963 case B43_PHYTYPE_LCN:
2964 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2965 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2966 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2967 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2968 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2969 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2970 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2971 if (dev->phy.type == B43_PHYTYPE_A)
2972 break;
2973 /* fallthrough */
2974 case B43_PHYTYPE_B:
2975 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2976 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2977 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2978 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2979 break;
2980 default:
2981 B43_WARN_ON(1);
2982 }
2983 }
2984
2985 /* Set the default values for the PHY TX Control Words. */
2986 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2987 {
2988 u16 ctl = 0;
2989
2990 ctl |= B43_TXH_PHY_ENC_CCK;
2991 ctl |= B43_TXH_PHY_ANT01AUTO;
2992 ctl |= B43_TXH_PHY_TXPWR;
2993
2994 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2995 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2996 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2997 }
2998
2999 /* Set the TX-Antenna for management frames sent by firmware. */
3000 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3001 {
3002 u16 ant;
3003 u16 tmp;
3004
3005 ant = b43_antenna_to_phyctl(antenna);
3006
3007 /* For ACK/CTS */
3008 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3009 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3010 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3011 /* For Probe Resposes */
3012 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3013 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3014 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3015 }
3016
3017 /* This is the opposite of b43_chip_init() */
3018 static void b43_chip_exit(struct b43_wldev *dev)
3019 {
3020 b43_phy_exit(dev);
3021 b43_gpio_cleanup(dev);
3022 /* firmware is released later */
3023 }
3024
3025 /* Initialize the chip
3026 * http://bcm-specs.sipsolutions.net/ChipInit
3027 */
3028 static int b43_chip_init(struct b43_wldev *dev)
3029 {
3030 struct b43_phy *phy = &dev->phy;
3031 int err;
3032 u32 macctl;
3033 u16 value16;
3034
3035 /* Initialize the MAC control */
3036 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3037 if (dev->phy.gmode)
3038 macctl |= B43_MACCTL_GMODE;
3039 macctl |= B43_MACCTL_INFRA;
3040 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3041
3042 err = b43_request_firmware(dev);
3043 if (err)
3044 goto out;
3045 err = b43_upload_microcode(dev);
3046 if (err)
3047 goto out; /* firmware is released later */
3048
3049 err = b43_gpio_init(dev);
3050 if (err)
3051 goto out; /* firmware is released later */
3052
3053 err = b43_upload_initvals(dev);
3054 if (err)
3055 goto err_gpio_clean;
3056
3057 /* Turn the Analog on and initialize the PHY. */
3058 phy->ops->switch_analog(dev, 1);
3059 err = b43_phy_init(dev);
3060 if (err)
3061 goto err_gpio_clean;
3062
3063 /* Disable Interference Mitigation. */
3064 if (phy->ops->interf_mitigation)
3065 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3066
3067 /* Select the antennae */
3068 if (phy->ops->set_rx_antenna)
3069 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3070 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3071
3072 if (phy->type == B43_PHYTYPE_B) {
3073 value16 = b43_read16(dev, 0x005E);
3074 value16 |= 0x0004;
3075 b43_write16(dev, 0x005E, value16);
3076 }
3077 b43_write32(dev, 0x0100, 0x01000000);
3078 if (dev->dev->core_rev < 5)
3079 b43_write32(dev, 0x010C, 0x01000000);
3080
3081 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3082 & ~B43_MACCTL_INFRA);
3083 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3084 | B43_MACCTL_INFRA);
3085
3086 /* Probe Response Timeout value */
3087 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3088 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3089
3090 /* Initially set the wireless operation mode. */
3091 b43_adjust_opmode(dev);
3092
3093 if (dev->dev->core_rev < 3) {
3094 b43_write16(dev, 0x060E, 0x0000);
3095 b43_write16(dev, 0x0610, 0x8000);
3096 b43_write16(dev, 0x0604, 0x0000);
3097 b43_write16(dev, 0x0606, 0x0200);
3098 } else {
3099 b43_write32(dev, 0x0188, 0x80000000);
3100 b43_write32(dev, 0x018C, 0x02000000);
3101 }
3102 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3103 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3104 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3105 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3106 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3107 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3108 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3109
3110 b43_mac_phy_clock_set(dev, true);
3111
3112 switch (dev->dev->bus_type) {
3113 #ifdef CONFIG_B43_BCMA
3114 case B43_BUS_BCMA:
3115 /* FIXME: 0xE74 is quite common, but should be read from CC */
3116 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3117 break;
3118 #endif
3119 #ifdef CONFIG_B43_SSB
3120 case B43_BUS_SSB:
3121 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3122 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3123 break;
3124 #endif
3125 }
3126
3127 err = 0;
3128 b43dbg(dev->wl, "Chip initialized\n");
3129 out:
3130 return err;
3131
3132 err_gpio_clean:
3133 b43_gpio_cleanup(dev);
3134 return err;
3135 }
3136
3137 static void b43_periodic_every60sec(struct b43_wldev *dev)
3138 {
3139 const struct b43_phy_operations *ops = dev->phy.ops;
3140
3141 if (ops->pwork_60sec)
3142 ops->pwork_60sec(dev);
3143
3144 /* Force check the TX power emission now. */
3145 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3146 }
3147
3148 static void b43_periodic_every30sec(struct b43_wldev *dev)
3149 {
3150 /* Update device statistics. */
3151 b43_calculate_link_quality(dev);
3152 }
3153
3154 static void b43_periodic_every15sec(struct b43_wldev *dev)
3155 {
3156 struct b43_phy *phy = &dev->phy;
3157 u16 wdr;
3158
3159 if (dev->fw.opensource) {
3160 /* Check if the firmware is still alive.
3161 * It will reset the watchdog counter to 0 in its idle loop. */
3162 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3163 if (unlikely(wdr)) {
3164 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3165 b43_controller_restart(dev, "Firmware watchdog");
3166 return;
3167 } else {
3168 b43_shm_write16(dev, B43_SHM_SCRATCH,
3169 B43_WATCHDOG_REG, 1);
3170 }
3171 }
3172
3173 if (phy->ops->pwork_15sec)
3174 phy->ops->pwork_15sec(dev);
3175
3176 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3177 wmb();
3178
3179 #if B43_DEBUG
3180 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3181 unsigned int i;
3182
3183 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3184 dev->irq_count / 15,
3185 dev->tx_count / 15,
3186 dev->rx_count / 15);
3187 dev->irq_count = 0;
3188 dev->tx_count = 0;
3189 dev->rx_count = 0;
3190 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3191 if (dev->irq_bit_count[i]) {
3192 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3193 dev->irq_bit_count[i] / 15, i, (1 << i));
3194 dev->irq_bit_count[i] = 0;
3195 }
3196 }
3197 }
3198 #endif
3199 }
3200
3201 static void do_periodic_work(struct b43_wldev *dev)
3202 {
3203 unsigned int state;
3204
3205 state = dev->periodic_state;
3206 if (state % 4 == 0)
3207 b43_periodic_every60sec(dev);
3208 if (state % 2 == 0)
3209 b43_periodic_every30sec(dev);
3210 b43_periodic_every15sec(dev);
3211 }
3212
3213 /* Periodic work locking policy:
3214 * The whole periodic work handler is protected by
3215 * wl->mutex. If another lock is needed somewhere in the
3216 * pwork callchain, it's acquired in-place, where it's needed.
3217 */
3218 static void b43_periodic_work_handler(struct work_struct *work)
3219 {
3220 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3221 periodic_work.work);
3222 struct b43_wl *wl = dev->wl;
3223 unsigned long delay;
3224
3225 mutex_lock(&wl->mutex);
3226
3227 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3228 goto out;
3229 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3230 goto out_requeue;
3231
3232 do_periodic_work(dev);
3233
3234 dev->periodic_state++;
3235 out_requeue:
3236 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3237 delay = msecs_to_jiffies(50);
3238 else
3239 delay = round_jiffies_relative(HZ * 15);
3240 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3241 out:
3242 mutex_unlock(&wl->mutex);
3243 }
3244
3245 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3246 {
3247 struct delayed_work *work = &dev->periodic_work;
3248
3249 dev->periodic_state = 0;
3250 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3251 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3252 }
3253
3254 /* Check if communication with the device works correctly. */
3255 static int b43_validate_chipaccess(struct b43_wldev *dev)
3256 {
3257 u32 v, backup0, backup4;
3258
3259 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3260 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3261
3262 /* Check for read/write and endianness problems. */
3263 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3264 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3265 goto error;
3266 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3267 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3268 goto error;
3269
3270 /* Check if unaligned 32bit SHM_SHARED access works properly.
3271 * However, don't bail out on failure, because it's noncritical. */
3272 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3273 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3274 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3275 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3276 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3277 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3278 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3279 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3280 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3281 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3282 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3283 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3284
3285 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3286 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3287
3288 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3289 /* The 32bit register shadows the two 16bit registers
3290 * with update sideeffects. Validate this. */
3291 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3292 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3293 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3294 goto error;
3295 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3296 goto error;
3297 }
3298 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3299
3300 v = b43_read32(dev, B43_MMIO_MACCTL);
3301 v |= B43_MACCTL_GMODE;
3302 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3303 goto error;
3304
3305 return 0;
3306 error:
3307 b43err(dev->wl, "Failed to validate the chipaccess\n");
3308 return -ENODEV;
3309 }
3310
3311 static void b43_security_init(struct b43_wldev *dev)
3312 {
3313 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3314 /* KTP is a word address, but we address SHM bytewise.
3315 * So multiply by two.
3316 */
3317 dev->ktp *= 2;
3318 /* Number of RCMTA address slots */
3319 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3320 /* Clear the key memory. */
3321 b43_clear_keys(dev);
3322 }
3323
3324 #ifdef CONFIG_B43_HWRNG
3325 static int b43_rng_read(struct hwrng *rng, u32 *data)
3326 {
3327 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3328 struct b43_wldev *dev;
3329 int count = -ENODEV;
3330
3331 mutex_lock(&wl->mutex);
3332 dev = wl->current_dev;
3333 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3334 *data = b43_read16(dev, B43_MMIO_RNG);
3335 count = sizeof(u16);
3336 }
3337 mutex_unlock(&wl->mutex);
3338
3339 return count;
3340 }
3341 #endif /* CONFIG_B43_HWRNG */
3342
3343 static void b43_rng_exit(struct b43_wl *wl)
3344 {
3345 #ifdef CONFIG_B43_HWRNG
3346 if (wl->rng_initialized)
3347 hwrng_unregister(&wl->rng);
3348 #endif /* CONFIG_B43_HWRNG */
3349 }
3350
3351 static int b43_rng_init(struct b43_wl *wl)
3352 {
3353 int err = 0;
3354
3355 #ifdef CONFIG_B43_HWRNG
3356 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3357 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3358 wl->rng.name = wl->rng_name;
3359 wl->rng.data_read = b43_rng_read;
3360 wl->rng.priv = (unsigned long)wl;
3361 wl->rng_initialized = 1;
3362 err = hwrng_register(&wl->rng);
3363 if (err) {
3364 wl->rng_initialized = 0;
3365 b43err(wl, "Failed to register the random "
3366 "number generator (%d)\n", err);
3367 }
3368 #endif /* CONFIG_B43_HWRNG */
3369
3370 return err;
3371 }
3372
3373 static void b43_tx_work(struct work_struct *work)
3374 {
3375 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3376 struct b43_wldev *dev;
3377 struct sk_buff *skb;
3378 int err = 0;
3379
3380 mutex_lock(&wl->mutex);
3381 dev = wl->current_dev;
3382 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3383 mutex_unlock(&wl->mutex);
3384 return;
3385 }
3386
3387 while (skb_queue_len(&wl->tx_queue)) {
3388 skb = skb_dequeue(&wl->tx_queue);
3389
3390 if (b43_using_pio_transfers(dev))
3391 err = b43_pio_tx(dev, skb);
3392 else
3393 err = b43_dma_tx(dev, skb);
3394 if (unlikely(err))
3395 dev_kfree_skb(skb); /* Drop it */
3396 }
3397
3398 #if B43_DEBUG
3399 dev->tx_count++;
3400 #endif
3401 mutex_unlock(&wl->mutex);
3402 }
3403
3404 static void b43_op_tx(struct ieee80211_hw *hw,
3405 struct sk_buff *skb)
3406 {
3407 struct b43_wl *wl = hw_to_b43_wl(hw);
3408
3409 if (unlikely(skb->len < 2 + 2 + 6)) {
3410 /* Too short, this can't be a valid frame. */
3411 dev_kfree_skb_any(skb);
3412 return;
3413 }
3414 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3415
3416 skb_queue_tail(&wl->tx_queue, skb);
3417 ieee80211_queue_work(wl->hw, &wl->tx_work);
3418 }
3419
3420 static void b43_qos_params_upload(struct b43_wldev *dev,
3421 const struct ieee80211_tx_queue_params *p,
3422 u16 shm_offset)
3423 {
3424 u16 params[B43_NR_QOSPARAMS];
3425 int bslots, tmp;
3426 unsigned int i;
3427
3428 if (!dev->qos_enabled)
3429 return;
3430
3431 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3432
3433 memset(&params, 0, sizeof(params));
3434
3435 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3436 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3437 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3438 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3439 params[B43_QOSPARAM_AIFS] = p->aifs;
3440 params[B43_QOSPARAM_BSLOTS] = bslots;
3441 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3442
3443 for (i = 0; i < ARRAY_SIZE(params); i++) {
3444 if (i == B43_QOSPARAM_STATUS) {
3445 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3446 shm_offset + (i * 2));
3447 /* Mark the parameters as updated. */
3448 tmp |= 0x100;
3449 b43_shm_write16(dev, B43_SHM_SHARED,
3450 shm_offset + (i * 2),
3451 tmp);
3452 } else {
3453 b43_shm_write16(dev, B43_SHM_SHARED,
3454 shm_offset + (i * 2),
3455 params[i]);
3456 }
3457 }
3458 }
3459
3460 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3461 static const u16 b43_qos_shm_offsets[] = {
3462 /* [mac80211-queue-nr] = SHM_OFFSET, */
3463 [0] = B43_QOS_VOICE,
3464 [1] = B43_QOS_VIDEO,
3465 [2] = B43_QOS_BESTEFFORT,
3466 [3] = B43_QOS_BACKGROUND,
3467 };
3468
3469 /* Update all QOS parameters in hardware. */
3470 static void b43_qos_upload_all(struct b43_wldev *dev)
3471 {
3472 struct b43_wl *wl = dev->wl;
3473 struct b43_qos_params *params;
3474 unsigned int i;
3475
3476 if (!dev->qos_enabled)
3477 return;
3478
3479 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3480 ARRAY_SIZE(wl->qos_params));
3481
3482 b43_mac_suspend(dev);
3483 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3484 params = &(wl->qos_params[i]);
3485 b43_qos_params_upload(dev, &(params->p),
3486 b43_qos_shm_offsets[i]);
3487 }
3488 b43_mac_enable(dev);
3489 }
3490
3491 static void b43_qos_clear(struct b43_wl *wl)
3492 {
3493 struct b43_qos_params *params;
3494 unsigned int i;
3495
3496 /* Initialize QoS parameters to sane defaults. */
3497
3498 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3499 ARRAY_SIZE(wl->qos_params));
3500
3501 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3502 params = &(wl->qos_params[i]);
3503
3504 switch (b43_qos_shm_offsets[i]) {
3505 case B43_QOS_VOICE:
3506 params->p.txop = 0;
3507 params->p.aifs = 2;
3508 params->p.cw_min = 0x0001;
3509 params->p.cw_max = 0x0001;
3510 break;
3511 case B43_QOS_VIDEO:
3512 params->p.txop = 0;
3513 params->p.aifs = 2;
3514 params->p.cw_min = 0x0001;
3515 params->p.cw_max = 0x0001;
3516 break;
3517 case B43_QOS_BESTEFFORT:
3518 params->p.txop = 0;
3519 params->p.aifs = 3;
3520 params->p.cw_min = 0x0001;
3521 params->p.cw_max = 0x03FF;
3522 break;
3523 case B43_QOS_BACKGROUND:
3524 params->p.txop = 0;
3525 params->p.aifs = 7;
3526 params->p.cw_min = 0x0001;
3527 params->p.cw_max = 0x03FF;
3528 break;
3529 default:
3530 B43_WARN_ON(1);
3531 }
3532 }
3533 }
3534
3535 /* Initialize the core's QOS capabilities */
3536 static void b43_qos_init(struct b43_wldev *dev)
3537 {
3538 if (!dev->qos_enabled) {
3539 /* Disable QOS support. */
3540 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3541 b43_write16(dev, B43_MMIO_IFSCTL,
3542 b43_read16(dev, B43_MMIO_IFSCTL)
3543 & ~B43_MMIO_IFSCTL_USE_EDCF);
3544 b43dbg(dev->wl, "QoS disabled\n");
3545 return;
3546 }
3547
3548 /* Upload the current QOS parameters. */
3549 b43_qos_upload_all(dev);
3550
3551 /* Enable QOS support. */
3552 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3553 b43_write16(dev, B43_MMIO_IFSCTL,
3554 b43_read16(dev, B43_MMIO_IFSCTL)
3555 | B43_MMIO_IFSCTL_USE_EDCF);
3556 b43dbg(dev->wl, "QoS enabled\n");
3557 }
3558
3559 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3560 const struct ieee80211_tx_queue_params *params)
3561 {
3562 struct b43_wl *wl = hw_to_b43_wl(hw);
3563 struct b43_wldev *dev;
3564 unsigned int queue = (unsigned int)_queue;
3565 int err = -ENODEV;
3566
3567 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3568 /* Queue not available or don't support setting
3569 * params on this queue. Return success to not
3570 * confuse mac80211. */
3571 return 0;
3572 }
3573 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3574 ARRAY_SIZE(wl->qos_params));
3575
3576 mutex_lock(&wl->mutex);
3577 dev = wl->current_dev;
3578 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3579 goto out_unlock;
3580
3581 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3582 b43_mac_suspend(dev);
3583 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3584 b43_qos_shm_offsets[queue]);
3585 b43_mac_enable(dev);
3586 err = 0;
3587
3588 out_unlock:
3589 mutex_unlock(&wl->mutex);
3590
3591 return err;
3592 }
3593
3594 static int b43_op_get_stats(struct ieee80211_hw *hw,
3595 struct ieee80211_low_level_stats *stats)
3596 {
3597 struct b43_wl *wl = hw_to_b43_wl(hw);
3598
3599 mutex_lock(&wl->mutex);
3600 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3601 mutex_unlock(&wl->mutex);
3602
3603 return 0;
3604 }
3605
3606 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3607 {
3608 struct b43_wl *wl = hw_to_b43_wl(hw);
3609 struct b43_wldev *dev;
3610 u64 tsf;
3611
3612 mutex_lock(&wl->mutex);
3613 dev = wl->current_dev;
3614
3615 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3616 b43_tsf_read(dev, &tsf);
3617 else
3618 tsf = 0;
3619
3620 mutex_unlock(&wl->mutex);
3621
3622 return tsf;
3623 }
3624
3625 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3626 struct ieee80211_vif *vif, u64 tsf)
3627 {
3628 struct b43_wl *wl = hw_to_b43_wl(hw);
3629 struct b43_wldev *dev;
3630
3631 mutex_lock(&wl->mutex);
3632 dev = wl->current_dev;
3633
3634 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3635 b43_tsf_write(dev, tsf);
3636
3637 mutex_unlock(&wl->mutex);
3638 }
3639
3640 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3641 {
3642 u32 tmp;
3643
3644 switch (dev->dev->bus_type) {
3645 #ifdef CONFIG_B43_BCMA
3646 case B43_BUS_BCMA:
3647 b43err(dev->wl,
3648 "Putting PHY into reset not supported on BCMA\n");
3649 break;
3650 #endif
3651 #ifdef CONFIG_B43_SSB
3652 case B43_BUS_SSB:
3653 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3654 tmp &= ~B43_TMSLOW_GMODE;
3655 tmp |= B43_TMSLOW_PHYRESET;
3656 tmp |= SSB_TMSLOW_FGC;
3657 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3658 msleep(1);
3659
3660 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3661 tmp &= ~SSB_TMSLOW_FGC;
3662 tmp |= B43_TMSLOW_PHYRESET;
3663 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3664 msleep(1);
3665
3666 break;
3667 #endif
3668 }
3669 }
3670
3671 static const char *band_to_string(enum ieee80211_band band)
3672 {
3673 switch (band) {
3674 case IEEE80211_BAND_5GHZ:
3675 return "5";
3676 case IEEE80211_BAND_2GHZ:
3677 return "2.4";
3678 default:
3679 break;
3680 }
3681 B43_WARN_ON(1);
3682 return "";
3683 }
3684
3685 /* Expects wl->mutex locked */
3686 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3687 {
3688 struct b43_wldev *up_dev = NULL;
3689 struct b43_wldev *down_dev;
3690 struct b43_wldev *d;
3691 int err;
3692 bool uninitialized_var(gmode);
3693 int prev_status;
3694
3695 /* Find a device and PHY which supports the band. */
3696 list_for_each_entry(d, &wl->devlist, list) {
3697 switch (chan->band) {
3698 case IEEE80211_BAND_5GHZ:
3699 if (d->phy.supports_5ghz) {
3700 up_dev = d;
3701 gmode = 0;
3702 }
3703 break;
3704 case IEEE80211_BAND_2GHZ:
3705 if (d->phy.supports_2ghz) {
3706 up_dev = d;
3707 gmode = 1;
3708 }
3709 break;
3710 default:
3711 B43_WARN_ON(1);
3712 return -EINVAL;
3713 }
3714 if (up_dev)
3715 break;
3716 }
3717 if (!up_dev) {
3718 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3719 band_to_string(chan->band));
3720 return -ENODEV;
3721 }
3722 if ((up_dev == wl->current_dev) &&
3723 (!!wl->current_dev->phy.gmode == !!gmode)) {
3724 /* This device is already running. */
3725 return 0;
3726 }
3727 b43dbg(wl, "Switching to %s-GHz band\n",
3728 band_to_string(chan->band));
3729 down_dev = wl->current_dev;
3730
3731 prev_status = b43_status(down_dev);
3732 /* Shutdown the currently running core. */
3733 if (prev_status >= B43_STAT_STARTED)
3734 down_dev = b43_wireless_core_stop(down_dev);
3735 if (prev_status >= B43_STAT_INITIALIZED)
3736 b43_wireless_core_exit(down_dev);
3737
3738 if (down_dev != up_dev) {
3739 /* We switch to a different core, so we put PHY into
3740 * RESET on the old core. */
3741 b43_put_phy_into_reset(down_dev);
3742 }
3743
3744 /* Now start the new core. */
3745 up_dev->phy.gmode = gmode;
3746 if (prev_status >= B43_STAT_INITIALIZED) {
3747 err = b43_wireless_core_init(up_dev);
3748 if (err) {
3749 b43err(wl, "Fatal: Could not initialize device for "
3750 "selected %s-GHz band\n",
3751 band_to_string(chan->band));
3752 goto init_failure;
3753 }
3754 }
3755 if (prev_status >= B43_STAT_STARTED) {
3756 err = b43_wireless_core_start(up_dev);
3757 if (err) {
3758 b43err(wl, "Fatal: Coult not start device for "
3759 "selected %s-GHz band\n",
3760 band_to_string(chan->band));
3761 b43_wireless_core_exit(up_dev);
3762 goto init_failure;
3763 }
3764 }
3765 B43_WARN_ON(b43_status(up_dev) != prev_status);
3766
3767 wl->current_dev = up_dev;
3768
3769 return 0;
3770 init_failure:
3771 /* Whoops, failed to init the new core. No core is operating now. */
3772 wl->current_dev = NULL;
3773 return err;
3774 }
3775
3776 /* Write the short and long frame retry limit values. */
3777 static void b43_set_retry_limits(struct b43_wldev *dev,
3778 unsigned int short_retry,
3779 unsigned int long_retry)
3780 {
3781 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3782 * the chip-internal counter. */
3783 short_retry = min(short_retry, (unsigned int)0xF);
3784 long_retry = min(long_retry, (unsigned int)0xF);
3785
3786 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3787 short_retry);
3788 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3789 long_retry);
3790 }
3791
3792 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3793 {
3794 struct b43_wl *wl = hw_to_b43_wl(hw);
3795 struct b43_wldev *dev;
3796 struct b43_phy *phy;
3797 struct ieee80211_conf *conf = &hw->conf;
3798 int antenna;
3799 int err = 0;
3800 bool reload_bss = false;
3801
3802 mutex_lock(&wl->mutex);
3803
3804 dev = wl->current_dev;
3805
3806 /* Switch the band (if necessary). This might change the active core. */
3807 err = b43_switch_band(wl, conf->channel);
3808 if (err)
3809 goto out_unlock_mutex;
3810
3811 /* Need to reload all settings if the core changed */
3812 if (dev != wl->current_dev) {
3813 dev = wl->current_dev;
3814 changed = ~0;
3815 reload_bss = true;
3816 }
3817
3818 phy = &dev->phy;
3819
3820 if (conf_is_ht(conf))
3821 phy->is_40mhz =
3822 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3823 else
3824 phy->is_40mhz = false;
3825
3826 b43_mac_suspend(dev);
3827
3828 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3829 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3830 conf->long_frame_max_tx_count);
3831 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3832 if (!changed)
3833 goto out_mac_enable;
3834
3835 /* Switch to the requested channel.
3836 * The firmware takes care of races with the TX handler. */
3837 if (conf->channel->hw_value != phy->channel)
3838 b43_switch_channel(dev, conf->channel->hw_value);
3839
3840 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3841
3842 /* Adjust the desired TX power level. */
3843 if (conf->power_level != 0) {
3844 if (conf->power_level != phy->desired_txpower) {
3845 phy->desired_txpower = conf->power_level;
3846 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3847 B43_TXPWR_IGNORE_TSSI);
3848 }
3849 }
3850
3851 /* Antennas for RX and management frame TX. */
3852 antenna = B43_ANTENNA_DEFAULT;
3853 b43_mgmtframe_txantenna(dev, antenna);
3854 antenna = B43_ANTENNA_DEFAULT;
3855 if (phy->ops->set_rx_antenna)
3856 phy->ops->set_rx_antenna(dev, antenna);
3857
3858 if (wl->radio_enabled != phy->radio_on) {
3859 if (wl->radio_enabled) {
3860 b43_software_rfkill(dev, false);
3861 b43info(dev->wl, "Radio turned on by software\n");
3862 if (!dev->radio_hw_enable) {
3863 b43info(dev->wl, "The hardware RF-kill button "
3864 "still turns the radio physically off. "
3865 "Press the button to turn it on.\n");
3866 }
3867 } else {
3868 b43_software_rfkill(dev, true);
3869 b43info(dev->wl, "Radio turned off by software\n");
3870 }
3871 }
3872
3873 out_mac_enable:
3874 b43_mac_enable(dev);
3875 out_unlock_mutex:
3876 mutex_unlock(&wl->mutex);
3877
3878 if (wl->vif && reload_bss)
3879 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3880
3881 return err;
3882 }
3883
3884 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3885 {
3886 struct ieee80211_supported_band *sband =
3887 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3888 struct ieee80211_rate *rate;
3889 int i;
3890 u16 basic, direct, offset, basic_offset, rateptr;
3891
3892 for (i = 0; i < sband->n_bitrates; i++) {
3893 rate = &sband->bitrates[i];
3894
3895 if (b43_is_cck_rate(rate->hw_value)) {
3896 direct = B43_SHM_SH_CCKDIRECT;
3897 basic = B43_SHM_SH_CCKBASIC;
3898 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3899 offset &= 0xF;
3900 } else {
3901 direct = B43_SHM_SH_OFDMDIRECT;
3902 basic = B43_SHM_SH_OFDMBASIC;
3903 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3904 offset &= 0xF;
3905 }
3906
3907 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3908
3909 if (b43_is_cck_rate(rate->hw_value)) {
3910 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3911 basic_offset &= 0xF;
3912 } else {
3913 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3914 basic_offset &= 0xF;
3915 }
3916
3917 /*
3918 * Get the pointer that we need to point to
3919 * from the direct map
3920 */
3921 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3922 direct + 2 * basic_offset);
3923 /* and write it to the basic map */
3924 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3925 rateptr);
3926 }
3927 }
3928
3929 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3930 struct ieee80211_vif *vif,
3931 struct ieee80211_bss_conf *conf,
3932 u32 changed)
3933 {
3934 struct b43_wl *wl = hw_to_b43_wl(hw);
3935 struct b43_wldev *dev;
3936
3937 mutex_lock(&wl->mutex);
3938
3939 dev = wl->current_dev;
3940 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3941 goto out_unlock_mutex;
3942
3943 B43_WARN_ON(wl->vif != vif);
3944
3945 if (changed & BSS_CHANGED_BSSID) {
3946 if (conf->bssid)
3947 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3948 else
3949 memset(wl->bssid, 0, ETH_ALEN);
3950 }
3951
3952 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3953 if (changed & BSS_CHANGED_BEACON &&
3954 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3955 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3956 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3957 b43_update_templates(wl);
3958
3959 if (changed & BSS_CHANGED_BSSID)
3960 b43_write_mac_bssid_templates(dev);
3961 }
3962
3963 b43_mac_suspend(dev);
3964
3965 /* Update templates for AP/mesh mode. */
3966 if (changed & BSS_CHANGED_BEACON_INT &&
3967 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3968 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3969 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3970 conf->beacon_int)
3971 b43_set_beacon_int(dev, conf->beacon_int);
3972
3973 if (changed & BSS_CHANGED_BASIC_RATES)
3974 b43_update_basic_rates(dev, conf->basic_rates);
3975
3976 if (changed & BSS_CHANGED_ERP_SLOT) {
3977 if (conf->use_short_slot)
3978 b43_short_slot_timing_enable(dev);
3979 else
3980 b43_short_slot_timing_disable(dev);
3981 }
3982
3983 b43_mac_enable(dev);
3984 out_unlock_mutex:
3985 mutex_unlock(&wl->mutex);
3986 }
3987
3988 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3989 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3990 struct ieee80211_key_conf *key)
3991 {
3992 struct b43_wl *wl = hw_to_b43_wl(hw);
3993 struct b43_wldev *dev;
3994 u8 algorithm;
3995 u8 index;
3996 int err;
3997 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3998
3999 if (modparam_nohwcrypt)
4000 return -ENOSPC; /* User disabled HW-crypto */
4001
4002 mutex_lock(&wl->mutex);
4003
4004 dev = wl->current_dev;
4005 err = -ENODEV;
4006 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4007 goto out_unlock;
4008
4009 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4010 /* We don't have firmware for the crypto engine.
4011 * Must use software-crypto. */
4012 err = -EOPNOTSUPP;
4013 goto out_unlock;
4014 }
4015
4016 err = -EINVAL;
4017 switch (key->cipher) {
4018 case WLAN_CIPHER_SUITE_WEP40:
4019 algorithm = B43_SEC_ALGO_WEP40;
4020 break;
4021 case WLAN_CIPHER_SUITE_WEP104:
4022 algorithm = B43_SEC_ALGO_WEP104;
4023 break;
4024 case WLAN_CIPHER_SUITE_TKIP:
4025 algorithm = B43_SEC_ALGO_TKIP;
4026 break;
4027 case WLAN_CIPHER_SUITE_CCMP:
4028 algorithm = B43_SEC_ALGO_AES;
4029 break;
4030 default:
4031 B43_WARN_ON(1);
4032 goto out_unlock;
4033 }
4034 index = (u8) (key->keyidx);
4035 if (index > 3)
4036 goto out_unlock;
4037
4038 switch (cmd) {
4039 case SET_KEY:
4040 if (algorithm == B43_SEC_ALGO_TKIP &&
4041 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4042 !modparam_hwtkip)) {
4043 /* We support only pairwise key */
4044 err = -EOPNOTSUPP;
4045 goto out_unlock;
4046 }
4047
4048 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4049 if (WARN_ON(!sta)) {
4050 err = -EOPNOTSUPP;
4051 goto out_unlock;
4052 }
4053 /* Pairwise key with an assigned MAC address. */
4054 err = b43_key_write(dev, -1, algorithm,
4055 key->key, key->keylen,
4056 sta->addr, key);
4057 } else {
4058 /* Group key */
4059 err = b43_key_write(dev, index, algorithm,
4060 key->key, key->keylen, NULL, key);
4061 }
4062 if (err)
4063 goto out_unlock;
4064
4065 if (algorithm == B43_SEC_ALGO_WEP40 ||
4066 algorithm == B43_SEC_ALGO_WEP104) {
4067 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4068 } else {
4069 b43_hf_write(dev,
4070 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4071 }
4072 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4073 if (algorithm == B43_SEC_ALGO_TKIP)
4074 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4075 break;
4076 case DISABLE_KEY: {
4077 err = b43_key_clear(dev, key->hw_key_idx);
4078 if (err)
4079 goto out_unlock;
4080 break;
4081 }
4082 default:
4083 B43_WARN_ON(1);
4084 }
4085
4086 out_unlock:
4087 if (!err) {
4088 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4089 "mac: %pM\n",
4090 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4091 sta ? sta->addr : bcast_addr);
4092 b43_dump_keymemory(dev);
4093 }
4094 mutex_unlock(&wl->mutex);
4095
4096 return err;
4097 }
4098
4099 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4100 unsigned int changed, unsigned int *fflags,
4101 u64 multicast)
4102 {
4103 struct b43_wl *wl = hw_to_b43_wl(hw);
4104 struct b43_wldev *dev;
4105
4106 mutex_lock(&wl->mutex);
4107 dev = wl->current_dev;
4108 if (!dev) {
4109 *fflags = 0;
4110 goto out_unlock;
4111 }
4112
4113 *fflags &= FIF_PROMISC_IN_BSS |
4114 FIF_ALLMULTI |
4115 FIF_FCSFAIL |
4116 FIF_PLCPFAIL |
4117 FIF_CONTROL |
4118 FIF_OTHER_BSS |
4119 FIF_BCN_PRBRESP_PROMISC;
4120
4121 changed &= FIF_PROMISC_IN_BSS |
4122 FIF_ALLMULTI |
4123 FIF_FCSFAIL |
4124 FIF_PLCPFAIL |
4125 FIF_CONTROL |
4126 FIF_OTHER_BSS |
4127 FIF_BCN_PRBRESP_PROMISC;
4128
4129 wl->filter_flags = *fflags;
4130
4131 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4132 b43_adjust_opmode(dev);
4133
4134 out_unlock:
4135 mutex_unlock(&wl->mutex);
4136 }
4137
4138 /* Locking: wl->mutex
4139 * Returns the current dev. This might be different from the passed in dev,
4140 * because the core might be gone away while we unlocked the mutex. */
4141 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4142 {
4143 struct b43_wl *wl;
4144 struct b43_wldev *orig_dev;
4145 u32 mask;
4146
4147 if (!dev)
4148 return NULL;
4149 wl = dev->wl;
4150 redo:
4151 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4152 return dev;
4153
4154 /* Cancel work. Unlock to avoid deadlocks. */
4155 mutex_unlock(&wl->mutex);
4156 cancel_delayed_work_sync(&dev->periodic_work);
4157 cancel_work_sync(&wl->tx_work);
4158 mutex_lock(&wl->mutex);
4159 dev = wl->current_dev;
4160 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4161 /* Whoops, aliens ate up the device while we were unlocked. */
4162 return dev;
4163 }
4164
4165 /* Disable interrupts on the device. */
4166 b43_set_status(dev, B43_STAT_INITIALIZED);
4167 if (b43_bus_host_is_sdio(dev->dev)) {
4168 /* wl->mutex is locked. That is enough. */
4169 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4170 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4171 } else {
4172 spin_lock_irq(&wl->hardirq_lock);
4173 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4174 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4175 spin_unlock_irq(&wl->hardirq_lock);
4176 }
4177 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4178 orig_dev = dev;
4179 mutex_unlock(&wl->mutex);
4180 if (b43_bus_host_is_sdio(dev->dev)) {
4181 b43_sdio_free_irq(dev);
4182 } else {
4183 synchronize_irq(dev->dev->irq);
4184 free_irq(dev->dev->irq, dev);
4185 }
4186 mutex_lock(&wl->mutex);
4187 dev = wl->current_dev;
4188 if (!dev)
4189 return dev;
4190 if (dev != orig_dev) {
4191 if (b43_status(dev) >= B43_STAT_STARTED)
4192 goto redo;
4193 return dev;
4194 }
4195 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4196 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4197
4198 /* Drain the TX queue */
4199 while (skb_queue_len(&wl->tx_queue))
4200 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
4201
4202 b43_mac_suspend(dev);
4203 b43_leds_exit(dev);
4204 b43dbg(wl, "Wireless interface stopped\n");
4205
4206 return dev;
4207 }
4208
4209 /* Locking: wl->mutex */
4210 static int b43_wireless_core_start(struct b43_wldev *dev)
4211 {
4212 int err;
4213
4214 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4215
4216 drain_txstatus_queue(dev);
4217 if (b43_bus_host_is_sdio(dev->dev)) {
4218 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4219 if (err) {
4220 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4221 goto out;
4222 }
4223 } else {
4224 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4225 b43_interrupt_thread_handler,
4226 IRQF_SHARED, KBUILD_MODNAME, dev);
4227 if (err) {
4228 b43err(dev->wl, "Cannot request IRQ-%d\n",
4229 dev->dev->irq);
4230 goto out;
4231 }
4232 }
4233
4234 /* We are ready to run. */
4235 ieee80211_wake_queues(dev->wl->hw);
4236 b43_set_status(dev, B43_STAT_STARTED);
4237
4238 /* Start data flow (TX/RX). */
4239 b43_mac_enable(dev);
4240 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4241
4242 /* Start maintenance work */
4243 b43_periodic_tasks_setup(dev);
4244
4245 b43_leds_init(dev);
4246
4247 b43dbg(dev->wl, "Wireless interface started\n");
4248 out:
4249 return err;
4250 }
4251
4252 /* Get PHY and RADIO versioning numbers */
4253 static int b43_phy_versioning(struct b43_wldev *dev)
4254 {
4255 struct b43_phy *phy = &dev->phy;
4256 u32 tmp;
4257 u8 analog_type;
4258 u8 phy_type;
4259 u8 phy_rev;
4260 u16 radio_manuf;
4261 u16 radio_ver;
4262 u16 radio_rev;
4263 int unsupported = 0;
4264
4265 /* Get PHY versioning */
4266 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4267 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4268 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4269 phy_rev = (tmp & B43_PHYVER_VERSION);
4270 switch (phy_type) {
4271 case B43_PHYTYPE_A:
4272 if (phy_rev >= 4)
4273 unsupported = 1;
4274 break;
4275 case B43_PHYTYPE_B:
4276 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4277 && phy_rev != 7)
4278 unsupported = 1;
4279 break;
4280 case B43_PHYTYPE_G:
4281 if (phy_rev > 9)
4282 unsupported = 1;
4283 break;
4284 #ifdef CONFIG_B43_PHY_N
4285 case B43_PHYTYPE_N:
4286 if (phy_rev > 9)
4287 unsupported = 1;
4288 break;
4289 #endif
4290 #ifdef CONFIG_B43_PHY_LP
4291 case B43_PHYTYPE_LP:
4292 if (phy_rev > 2)
4293 unsupported = 1;
4294 break;
4295 #endif
4296 #ifdef CONFIG_B43_PHY_HT
4297 case B43_PHYTYPE_HT:
4298 if (phy_rev > 1)
4299 unsupported = 1;
4300 break;
4301 #endif
4302 #ifdef CONFIG_B43_PHY_LCN
4303 case B43_PHYTYPE_LCN:
4304 if (phy_rev > 1)
4305 unsupported = 1;
4306 break;
4307 #endif
4308 default:
4309 unsupported = 1;
4310 }
4311 if (unsupported) {
4312 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4313 "(Analog %u, Type %u, Revision %u)\n",
4314 analog_type, phy_type, phy_rev);
4315 return -EOPNOTSUPP;
4316 }
4317 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4318 analog_type, phy_type, phy_rev);
4319
4320 /* Get RADIO versioning */
4321 if (dev->dev->core_rev >= 24) {
4322 u16 radio24[3];
4323
4324 for (tmp = 0; tmp < 3; tmp++) {
4325 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4326 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4327 }
4328
4329 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4330 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4331
4332 radio_manuf = 0x17F;
4333 radio_ver = (radio24[2] << 8) | radio24[1];
4334 radio_rev = (radio24[0] & 0xF);
4335 } else {
4336 if (dev->dev->chip_id == 0x4317) {
4337 if (dev->dev->chip_rev == 0)
4338 tmp = 0x3205017F;
4339 else if (dev->dev->chip_rev == 1)
4340 tmp = 0x4205017F;
4341 else
4342 tmp = 0x5205017F;
4343 } else {
4344 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4345 B43_RADIOCTL_ID);
4346 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4347 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4348 B43_RADIOCTL_ID);
4349 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4350 << 16;
4351 }
4352 radio_manuf = (tmp & 0x00000FFF);
4353 radio_ver = (tmp & 0x0FFFF000) >> 12;
4354 radio_rev = (tmp & 0xF0000000) >> 28;
4355 }
4356
4357 if (radio_manuf != 0x17F /* Broadcom */)
4358 unsupported = 1;
4359 switch (phy_type) {
4360 case B43_PHYTYPE_A:
4361 if (radio_ver != 0x2060)
4362 unsupported = 1;
4363 if (radio_rev != 1)
4364 unsupported = 1;
4365 if (radio_manuf != 0x17F)
4366 unsupported = 1;
4367 break;
4368 case B43_PHYTYPE_B:
4369 if ((radio_ver & 0xFFF0) != 0x2050)
4370 unsupported = 1;
4371 break;
4372 case B43_PHYTYPE_G:
4373 if (radio_ver != 0x2050)
4374 unsupported = 1;
4375 break;
4376 case B43_PHYTYPE_N:
4377 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4378 unsupported = 1;
4379 break;
4380 case B43_PHYTYPE_LP:
4381 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4382 unsupported = 1;
4383 break;
4384 case B43_PHYTYPE_HT:
4385 if (radio_ver != 0x2059)
4386 unsupported = 1;
4387 break;
4388 case B43_PHYTYPE_LCN:
4389 if (radio_ver != 0x2064)
4390 unsupported = 1;
4391 break;
4392 default:
4393 B43_WARN_ON(1);
4394 }
4395 if (unsupported) {
4396 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4397 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4398 radio_manuf, radio_ver, radio_rev);
4399 return -EOPNOTSUPP;
4400 }
4401 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4402 radio_manuf, radio_ver, radio_rev);
4403
4404 phy->radio_manuf = radio_manuf;
4405 phy->radio_ver = radio_ver;
4406 phy->radio_rev = radio_rev;
4407
4408 phy->analog = analog_type;
4409 phy->type = phy_type;
4410 phy->rev = phy_rev;
4411
4412 return 0;
4413 }
4414
4415 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4416 struct b43_phy *phy)
4417 {
4418 phy->hardware_power_control = !!modparam_hwpctl;
4419 phy->next_txpwr_check_time = jiffies;
4420 /* PHY TX errors counter. */
4421 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4422
4423 #if B43_DEBUG
4424 phy->phy_locked = 0;
4425 phy->radio_locked = 0;
4426 #endif
4427 }
4428
4429 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4430 {
4431 dev->dfq_valid = 0;
4432
4433 /* Assume the radio is enabled. If it's not enabled, the state will
4434 * immediately get fixed on the first periodic work run. */
4435 dev->radio_hw_enable = 1;
4436
4437 /* Stats */
4438 memset(&dev->stats, 0, sizeof(dev->stats));
4439
4440 setup_struct_phy_for_init(dev, &dev->phy);
4441
4442 /* IRQ related flags */
4443 dev->irq_reason = 0;
4444 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4445 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4446 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4447 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4448
4449 dev->mac_suspended = 1;
4450
4451 /* Noise calculation context */
4452 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4453 }
4454
4455 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4456 {
4457 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4458 u64 hf;
4459
4460 if (!modparam_btcoex)
4461 return;
4462 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4463 return;
4464 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4465 return;
4466
4467 hf = b43_hf_read(dev);
4468 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4469 hf |= B43_HF_BTCOEXALT;
4470 else
4471 hf |= B43_HF_BTCOEX;
4472 b43_hf_write(dev, hf);
4473 }
4474
4475 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4476 {
4477 if (!modparam_btcoex)
4478 return;
4479 //TODO
4480 }
4481
4482 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4483 {
4484 struct ssb_bus *bus;
4485 u32 tmp;
4486
4487 if (dev->dev->bus_type != B43_BUS_SSB)
4488 return;
4489
4490 bus = dev->dev->sdev->bus;
4491
4492 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4493 (bus->chip_id == 0x4312)) {
4494 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4495 tmp &= ~SSB_IMCFGLO_REQTO;
4496 tmp &= ~SSB_IMCFGLO_SERTO;
4497 tmp |= 0x3;
4498 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4499 ssb_commit_settings(bus);
4500 }
4501 }
4502
4503 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4504 {
4505 u16 pu_delay;
4506
4507 /* The time value is in microseconds. */
4508 if (dev->phy.type == B43_PHYTYPE_A)
4509 pu_delay = 3700;
4510 else
4511 pu_delay = 1050;
4512 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4513 pu_delay = 500;
4514 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4515 pu_delay = max(pu_delay, (u16)2400);
4516
4517 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4518 }
4519
4520 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4521 static void b43_set_pretbtt(struct b43_wldev *dev)
4522 {
4523 u16 pretbtt;
4524
4525 /* The time value is in microseconds. */
4526 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4527 pretbtt = 2;
4528 } else {
4529 if (dev->phy.type == B43_PHYTYPE_A)
4530 pretbtt = 120;
4531 else
4532 pretbtt = 250;
4533 }
4534 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4535 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4536 }
4537
4538 /* Shutdown a wireless core */
4539 /* Locking: wl->mutex */
4540 static void b43_wireless_core_exit(struct b43_wldev *dev)
4541 {
4542 u32 macctl;
4543
4544 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4545 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4546 return;
4547
4548 /* Unregister HW RNG driver */
4549 b43_rng_exit(dev->wl);
4550
4551 b43_set_status(dev, B43_STAT_UNINIT);
4552
4553 /* Stop the microcode PSM. */
4554 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4555 macctl &= ~B43_MACCTL_PSM_RUN;
4556 macctl |= B43_MACCTL_PSM_JMP0;
4557 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4558
4559 b43_dma_free(dev);
4560 b43_pio_free(dev);
4561 b43_chip_exit(dev);
4562 dev->phy.ops->switch_analog(dev, 0);
4563 if (dev->wl->current_beacon) {
4564 dev_kfree_skb_any(dev->wl->current_beacon);
4565 dev->wl->current_beacon = NULL;
4566 }
4567
4568 b43_device_disable(dev, 0);
4569 b43_bus_may_powerdown(dev);
4570 }
4571
4572 /* Initialize a wireless core */
4573 static int b43_wireless_core_init(struct b43_wldev *dev)
4574 {
4575 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4576 struct b43_phy *phy = &dev->phy;
4577 int err;
4578 u64 hf;
4579
4580 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4581
4582 err = b43_bus_powerup(dev, 0);
4583 if (err)
4584 goto out;
4585 if (!b43_device_is_enabled(dev))
4586 b43_wireless_core_reset(dev, phy->gmode);
4587
4588 /* Reset all data structures. */
4589 setup_struct_wldev_for_init(dev);
4590 phy->ops->prepare_structs(dev);
4591
4592 /* Enable IRQ routing to this device. */
4593 switch (dev->dev->bus_type) {
4594 #ifdef CONFIG_B43_BCMA
4595 case B43_BUS_BCMA:
4596 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4597 dev->dev->bdev, true);
4598 break;
4599 #endif
4600 #ifdef CONFIG_B43_SSB
4601 case B43_BUS_SSB:
4602 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4603 dev->dev->sdev);
4604 break;
4605 #endif
4606 }
4607
4608 b43_imcfglo_timeouts_workaround(dev);
4609 b43_bluetooth_coext_disable(dev);
4610 if (phy->ops->prepare_hardware) {
4611 err = phy->ops->prepare_hardware(dev);
4612 if (err)
4613 goto err_busdown;
4614 }
4615 err = b43_chip_init(dev);
4616 if (err)
4617 goto err_busdown;
4618 b43_shm_write16(dev, B43_SHM_SHARED,
4619 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4620 hf = b43_hf_read(dev);
4621 if (phy->type == B43_PHYTYPE_G) {
4622 hf |= B43_HF_SYMW;
4623 if (phy->rev == 1)
4624 hf |= B43_HF_GDCW;
4625 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4626 hf |= B43_HF_OFDMPABOOST;
4627 }
4628 if (phy->radio_ver == 0x2050) {
4629 if (phy->radio_rev == 6)
4630 hf |= B43_HF_4318TSSI;
4631 if (phy->radio_rev < 6)
4632 hf |= B43_HF_VCORECALC;
4633 }
4634 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4635 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4636 #ifdef CONFIG_SSB_DRIVER_PCICORE
4637 if (dev->dev->bus_type == B43_BUS_SSB &&
4638 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4639 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4640 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4641 #endif
4642 hf &= ~B43_HF_SKCFPUP;
4643 b43_hf_write(dev, hf);
4644
4645 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4646 B43_DEFAULT_LONG_RETRY_LIMIT);
4647 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4648 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4649
4650 /* Disable sending probe responses from firmware.
4651 * Setting the MaxTime to one usec will always trigger
4652 * a timeout, so we never send any probe resp.
4653 * A timeout of zero is infinite. */
4654 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4655
4656 b43_rate_memory_init(dev);
4657 b43_set_phytxctl_defaults(dev);
4658
4659 /* Minimum Contention Window */
4660 if (phy->type == B43_PHYTYPE_B)
4661 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4662 else
4663 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4664 /* Maximum Contention Window */
4665 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4666
4667 if (b43_bus_host_is_pcmcia(dev->dev) ||
4668 b43_bus_host_is_sdio(dev->dev)) {
4669 dev->__using_pio_transfers = 1;
4670 err = b43_pio_init(dev);
4671 } else if (dev->use_pio) {
4672 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4673 "This should not be needed and will result in lower "
4674 "performance.\n");
4675 dev->__using_pio_transfers = 1;
4676 err = b43_pio_init(dev);
4677 } else {
4678 dev->__using_pio_transfers = 0;
4679 err = b43_dma_init(dev);
4680 }
4681 if (err)
4682 goto err_chip_exit;
4683 b43_qos_init(dev);
4684 b43_set_synth_pu_delay(dev, 1);
4685 b43_bluetooth_coext_enable(dev);
4686
4687 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4688 b43_upload_card_macaddress(dev);
4689 b43_security_init(dev);
4690
4691 ieee80211_wake_queues(dev->wl->hw);
4692
4693 b43_set_status(dev, B43_STAT_INITIALIZED);
4694
4695 /* Register HW RNG driver */
4696 b43_rng_init(dev->wl);
4697
4698 out:
4699 return err;
4700
4701 err_chip_exit:
4702 b43_chip_exit(dev);
4703 err_busdown:
4704 b43_bus_may_powerdown(dev);
4705 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4706 return err;
4707 }
4708
4709 static int b43_op_add_interface(struct ieee80211_hw *hw,
4710 struct ieee80211_vif *vif)
4711 {
4712 struct b43_wl *wl = hw_to_b43_wl(hw);
4713 struct b43_wldev *dev;
4714 int err = -EOPNOTSUPP;
4715
4716 /* TODO: allow WDS/AP devices to coexist */
4717
4718 if (vif->type != NL80211_IFTYPE_AP &&
4719 vif->type != NL80211_IFTYPE_MESH_POINT &&
4720 vif->type != NL80211_IFTYPE_STATION &&
4721 vif->type != NL80211_IFTYPE_WDS &&
4722 vif->type != NL80211_IFTYPE_ADHOC)
4723 return -EOPNOTSUPP;
4724
4725 mutex_lock(&wl->mutex);
4726 if (wl->operating)
4727 goto out_mutex_unlock;
4728
4729 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4730
4731 dev = wl->current_dev;
4732 wl->operating = 1;
4733 wl->vif = vif;
4734 wl->if_type = vif->type;
4735 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4736
4737 b43_adjust_opmode(dev);
4738 b43_set_pretbtt(dev);
4739 b43_set_synth_pu_delay(dev, 0);
4740 b43_upload_card_macaddress(dev);
4741
4742 err = 0;
4743 out_mutex_unlock:
4744 mutex_unlock(&wl->mutex);
4745
4746 if (err == 0)
4747 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4748
4749 return err;
4750 }
4751
4752 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4753 struct ieee80211_vif *vif)
4754 {
4755 struct b43_wl *wl = hw_to_b43_wl(hw);
4756 struct b43_wldev *dev = wl->current_dev;
4757
4758 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4759
4760 mutex_lock(&wl->mutex);
4761
4762 B43_WARN_ON(!wl->operating);
4763 B43_WARN_ON(wl->vif != vif);
4764 wl->vif = NULL;
4765
4766 wl->operating = 0;
4767
4768 b43_adjust_opmode(dev);
4769 memset(wl->mac_addr, 0, ETH_ALEN);
4770 b43_upload_card_macaddress(dev);
4771
4772 mutex_unlock(&wl->mutex);
4773 }
4774
4775 static int b43_op_start(struct ieee80211_hw *hw)
4776 {
4777 struct b43_wl *wl = hw_to_b43_wl(hw);
4778 struct b43_wldev *dev = wl->current_dev;
4779 int did_init = 0;
4780 int err = 0;
4781
4782 /* Kill all old instance specific information to make sure
4783 * the card won't use it in the short timeframe between start
4784 * and mac80211 reconfiguring it. */
4785 memset(wl->bssid, 0, ETH_ALEN);
4786 memset(wl->mac_addr, 0, ETH_ALEN);
4787 wl->filter_flags = 0;
4788 wl->radiotap_enabled = 0;
4789 b43_qos_clear(wl);
4790 wl->beacon0_uploaded = 0;
4791 wl->beacon1_uploaded = 0;
4792 wl->beacon_templates_virgin = 1;
4793 wl->radio_enabled = 1;
4794
4795 mutex_lock(&wl->mutex);
4796
4797 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4798 err = b43_wireless_core_init(dev);
4799 if (err)
4800 goto out_mutex_unlock;
4801 did_init = 1;
4802 }
4803
4804 if (b43_status(dev) < B43_STAT_STARTED) {
4805 err = b43_wireless_core_start(dev);
4806 if (err) {
4807 if (did_init)
4808 b43_wireless_core_exit(dev);
4809 goto out_mutex_unlock;
4810 }
4811 }
4812
4813 /* XXX: only do if device doesn't support rfkill irq */
4814 wiphy_rfkill_start_polling(hw->wiphy);
4815
4816 out_mutex_unlock:
4817 mutex_unlock(&wl->mutex);
4818
4819 /* reload configuration */
4820 b43_op_config(hw, ~0);
4821
4822 return err;
4823 }
4824
4825 static void b43_op_stop(struct ieee80211_hw *hw)
4826 {
4827 struct b43_wl *wl = hw_to_b43_wl(hw);
4828 struct b43_wldev *dev = wl->current_dev;
4829
4830 cancel_work_sync(&(wl->beacon_update_trigger));
4831
4832 mutex_lock(&wl->mutex);
4833 if (b43_status(dev) >= B43_STAT_STARTED) {
4834 dev = b43_wireless_core_stop(dev);
4835 if (!dev)
4836 goto out_unlock;
4837 }
4838 b43_wireless_core_exit(dev);
4839 wl->radio_enabled = 0;
4840
4841 out_unlock:
4842 mutex_unlock(&wl->mutex);
4843
4844 cancel_work_sync(&(wl->txpower_adjust_work));
4845 }
4846
4847 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4848 struct ieee80211_sta *sta, bool set)
4849 {
4850 struct b43_wl *wl = hw_to_b43_wl(hw);
4851
4852 /* FIXME: add locking */
4853 b43_update_templates(wl);
4854
4855 return 0;
4856 }
4857
4858 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4859 struct ieee80211_vif *vif,
4860 enum sta_notify_cmd notify_cmd,
4861 struct ieee80211_sta *sta)
4862 {
4863 struct b43_wl *wl = hw_to_b43_wl(hw);
4864
4865 B43_WARN_ON(!vif || wl->vif != vif);
4866 }
4867
4868 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4869 {
4870 struct b43_wl *wl = hw_to_b43_wl(hw);
4871 struct b43_wldev *dev;
4872
4873 mutex_lock(&wl->mutex);
4874 dev = wl->current_dev;
4875 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4876 /* Disable CFP update during scan on other channels. */
4877 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4878 }
4879 mutex_unlock(&wl->mutex);
4880 }
4881
4882 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4883 {
4884 struct b43_wl *wl = hw_to_b43_wl(hw);
4885 struct b43_wldev *dev;
4886
4887 mutex_lock(&wl->mutex);
4888 dev = wl->current_dev;
4889 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4890 /* Re-enable CFP update. */
4891 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4892 }
4893 mutex_unlock(&wl->mutex);
4894 }
4895
4896 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4897 struct survey_info *survey)
4898 {
4899 struct b43_wl *wl = hw_to_b43_wl(hw);
4900 struct b43_wldev *dev = wl->current_dev;
4901 struct ieee80211_conf *conf = &hw->conf;
4902
4903 if (idx != 0)
4904 return -ENOENT;
4905
4906 survey->channel = conf->channel;
4907 survey->filled = SURVEY_INFO_NOISE_DBM;
4908 survey->noise = dev->stats.link_noise;
4909
4910 return 0;
4911 }
4912
4913 static const struct ieee80211_ops b43_hw_ops = {
4914 .tx = b43_op_tx,
4915 .conf_tx = b43_op_conf_tx,
4916 .add_interface = b43_op_add_interface,
4917 .remove_interface = b43_op_remove_interface,
4918 .config = b43_op_config,
4919 .bss_info_changed = b43_op_bss_info_changed,
4920 .configure_filter = b43_op_configure_filter,
4921 .set_key = b43_op_set_key,
4922 .update_tkip_key = b43_op_update_tkip_key,
4923 .get_stats = b43_op_get_stats,
4924 .get_tsf = b43_op_get_tsf,
4925 .set_tsf = b43_op_set_tsf,
4926 .start = b43_op_start,
4927 .stop = b43_op_stop,
4928 .set_tim = b43_op_beacon_set_tim,
4929 .sta_notify = b43_op_sta_notify,
4930 .sw_scan_start = b43_op_sw_scan_start_notifier,
4931 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4932 .get_survey = b43_op_get_survey,
4933 .rfkill_poll = b43_rfkill_poll,
4934 };
4935
4936 /* Hard-reset the chip. Do not call this directly.
4937 * Use b43_controller_restart()
4938 */
4939 static void b43_chip_reset(struct work_struct *work)
4940 {
4941 struct b43_wldev *dev =
4942 container_of(work, struct b43_wldev, restart_work);
4943 struct b43_wl *wl = dev->wl;
4944 int err = 0;
4945 int prev_status;
4946
4947 mutex_lock(&wl->mutex);
4948
4949 prev_status = b43_status(dev);
4950 /* Bring the device down... */
4951 if (prev_status >= B43_STAT_STARTED) {
4952 dev = b43_wireless_core_stop(dev);
4953 if (!dev) {
4954 err = -ENODEV;
4955 goto out;
4956 }
4957 }
4958 if (prev_status >= B43_STAT_INITIALIZED)
4959 b43_wireless_core_exit(dev);
4960
4961 /* ...and up again. */
4962 if (prev_status >= B43_STAT_INITIALIZED) {
4963 err = b43_wireless_core_init(dev);
4964 if (err)
4965 goto out;
4966 }
4967 if (prev_status >= B43_STAT_STARTED) {
4968 err = b43_wireless_core_start(dev);
4969 if (err) {
4970 b43_wireless_core_exit(dev);
4971 goto out;
4972 }
4973 }
4974 out:
4975 if (err)
4976 wl->current_dev = NULL; /* Failed to init the dev. */
4977 mutex_unlock(&wl->mutex);
4978
4979 if (err) {
4980 b43err(wl, "Controller restart FAILED\n");
4981 return;
4982 }
4983
4984 /* reload configuration */
4985 b43_op_config(wl->hw, ~0);
4986 if (wl->vif)
4987 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
4988
4989 b43info(wl, "Controller restarted\n");
4990 }
4991
4992 static int b43_setup_bands(struct b43_wldev *dev,
4993 bool have_2ghz_phy, bool have_5ghz_phy)
4994 {
4995 struct ieee80211_hw *hw = dev->wl->hw;
4996
4997 if (have_2ghz_phy)
4998 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4999 if (dev->phy.type == B43_PHYTYPE_N) {
5000 if (have_5ghz_phy)
5001 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5002 } else {
5003 if (have_5ghz_phy)
5004 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5005 }
5006
5007 dev->phy.supports_2ghz = have_2ghz_phy;
5008 dev->phy.supports_5ghz = have_5ghz_phy;
5009
5010 return 0;
5011 }
5012
5013 static void b43_wireless_core_detach(struct b43_wldev *dev)
5014 {
5015 /* We release firmware that late to not be required to re-request
5016 * is all the time when we reinit the core. */
5017 b43_release_firmware(dev);
5018 b43_phy_free(dev);
5019 }
5020
5021 static int b43_wireless_core_attach(struct b43_wldev *dev)
5022 {
5023 struct b43_wl *wl = dev->wl;
5024 struct pci_dev *pdev = NULL;
5025 int err;
5026 u32 tmp;
5027 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
5028
5029 /* Do NOT do any device initialization here.
5030 * Do it in wireless_core_init() instead.
5031 * This function is for gathering basic information about the HW, only.
5032 * Also some structs may be set up here. But most likely you want to have
5033 * that in core_init(), too.
5034 */
5035
5036 #ifdef CONFIG_B43_SSB
5037 if (dev->dev->bus_type == B43_BUS_SSB &&
5038 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5039 pdev = dev->dev->sdev->bus->host_pci;
5040 #endif
5041
5042 err = b43_bus_powerup(dev, 0);
5043 if (err) {
5044 b43err(wl, "Bus powerup failed\n");
5045 goto out;
5046 }
5047
5048 /* Get the PHY type. */
5049 switch (dev->dev->bus_type) {
5050 #ifdef CONFIG_B43_BCMA
5051 case B43_BUS_BCMA:
5052 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5053 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5054 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5055 break;
5056 #endif
5057 #ifdef CONFIG_B43_SSB
5058 case B43_BUS_SSB:
5059 if (dev->dev->core_rev >= 5) {
5060 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5061 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5062 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5063 } else
5064 B43_WARN_ON(1);
5065 break;
5066 #endif
5067 }
5068
5069 dev->phy.gmode = have_2ghz_phy;
5070 dev->phy.radio_on = 1;
5071 b43_wireless_core_reset(dev, dev->phy.gmode);
5072
5073 err = b43_phy_versioning(dev);
5074 if (err)
5075 goto err_powerdown;
5076 /* Check if this device supports multiband. */
5077 if (!pdev ||
5078 (pdev->device != 0x4312 &&
5079 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5080 /* No multiband support. */
5081 have_2ghz_phy = 0;
5082 have_5ghz_phy = 0;
5083 switch (dev->phy.type) {
5084 case B43_PHYTYPE_A:
5085 have_5ghz_phy = 1;
5086 break;
5087 case B43_PHYTYPE_LP: //FIXME not always!
5088 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5089 have_5ghz_phy = 1;
5090 #endif
5091 case B43_PHYTYPE_G:
5092 case B43_PHYTYPE_N:
5093 case B43_PHYTYPE_HT:
5094 case B43_PHYTYPE_LCN:
5095 have_2ghz_phy = 1;
5096 break;
5097 default:
5098 B43_WARN_ON(1);
5099 }
5100 }
5101 if (dev->phy.type == B43_PHYTYPE_A) {
5102 /* FIXME */
5103 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5104 err = -EOPNOTSUPP;
5105 goto err_powerdown;
5106 }
5107 if (1 /* disable A-PHY */) {
5108 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5109 if (dev->phy.type != B43_PHYTYPE_N &&
5110 dev->phy.type != B43_PHYTYPE_LP) {
5111 have_2ghz_phy = 1;
5112 have_5ghz_phy = 0;
5113 }
5114 }
5115
5116 err = b43_phy_allocate(dev);
5117 if (err)
5118 goto err_powerdown;
5119
5120 dev->phy.gmode = have_2ghz_phy;
5121 b43_wireless_core_reset(dev, dev->phy.gmode);
5122
5123 err = b43_validate_chipaccess(dev);
5124 if (err)
5125 goto err_phy_free;
5126 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5127 if (err)
5128 goto err_phy_free;
5129
5130 /* Now set some default "current_dev" */
5131 if (!wl->current_dev)
5132 wl->current_dev = dev;
5133 INIT_WORK(&dev->restart_work, b43_chip_reset);
5134
5135 dev->phy.ops->switch_analog(dev, 0);
5136 b43_device_disable(dev, 0);
5137 b43_bus_may_powerdown(dev);
5138
5139 out:
5140 return err;
5141
5142 err_phy_free:
5143 b43_phy_free(dev);
5144 err_powerdown:
5145 b43_bus_may_powerdown(dev);
5146 return err;
5147 }
5148
5149 static void b43_one_core_detach(struct b43_bus_dev *dev)
5150 {
5151 struct b43_wldev *wldev;
5152 struct b43_wl *wl;
5153
5154 /* Do not cancel ieee80211-workqueue based work here.
5155 * See comment in b43_remove(). */
5156
5157 wldev = b43_bus_get_wldev(dev);
5158 wl = wldev->wl;
5159 b43_debugfs_remove_device(wldev);
5160 b43_wireless_core_detach(wldev);
5161 list_del(&wldev->list);
5162 wl->nr_devs--;
5163 b43_bus_set_wldev(dev, NULL);
5164 kfree(wldev);
5165 }
5166
5167 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5168 {
5169 struct b43_wldev *wldev;
5170 int err = -ENOMEM;
5171
5172 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5173 if (!wldev)
5174 goto out;
5175
5176 wldev->use_pio = b43_modparam_pio;
5177 wldev->dev = dev;
5178 wldev->wl = wl;
5179 b43_set_status(wldev, B43_STAT_UNINIT);
5180 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5181 INIT_LIST_HEAD(&wldev->list);
5182
5183 err = b43_wireless_core_attach(wldev);
5184 if (err)
5185 goto err_kfree_wldev;
5186
5187 list_add(&wldev->list, &wl->devlist);
5188 wl->nr_devs++;
5189 b43_bus_set_wldev(dev, wldev);
5190 b43_debugfs_add_device(wldev);
5191
5192 out:
5193 return err;
5194
5195 err_kfree_wldev:
5196 kfree(wldev);
5197 return err;
5198 }
5199
5200 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5201 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5202 (pdev->device == _device) && \
5203 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5204 (pdev->subsystem_device == _subdevice) )
5205
5206 static void b43_sprom_fixup(struct ssb_bus *bus)
5207 {
5208 struct pci_dev *pdev;
5209
5210 /* boardflags workarounds */
5211 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5212 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
5213 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5214 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5215 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
5216 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5217 if (bus->bustype == SSB_BUSTYPE_PCI) {
5218 pdev = bus->host_pci;
5219 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5220 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5221 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5222 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5223 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5224 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5225 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5226 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5227 }
5228 }
5229
5230 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5231 {
5232 struct ieee80211_hw *hw = wl->hw;
5233
5234 ssb_set_devtypedata(dev->sdev, NULL);
5235 ieee80211_free_hw(hw);
5236 }
5237
5238 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5239 {
5240 struct ssb_sprom *sprom = dev->bus_sprom;
5241 struct ieee80211_hw *hw;
5242 struct b43_wl *wl;
5243 char chip_name[6];
5244
5245 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5246 if (!hw) {
5247 b43err(NULL, "Could not allocate ieee80211 device\n");
5248 return ERR_PTR(-ENOMEM);
5249 }
5250 wl = hw_to_b43_wl(hw);
5251
5252 /* fill hw info */
5253 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5254 IEEE80211_HW_SIGNAL_DBM;
5255
5256 hw->wiphy->interface_modes =
5257 BIT(NL80211_IFTYPE_AP) |
5258 BIT(NL80211_IFTYPE_MESH_POINT) |
5259 BIT(NL80211_IFTYPE_STATION) |
5260 BIT(NL80211_IFTYPE_WDS) |
5261 BIT(NL80211_IFTYPE_ADHOC);
5262
5263 hw->queues = modparam_qos ? 4 : 1;
5264 wl->mac80211_initially_registered_queues = hw->queues;
5265 hw->max_rates = 2;
5266 SET_IEEE80211_DEV(hw, dev->dev);
5267 if (is_valid_ether_addr(sprom->et1mac))
5268 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5269 else
5270 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5271
5272 /* Initialize struct b43_wl */
5273 wl->hw = hw;
5274 mutex_init(&wl->mutex);
5275 spin_lock_init(&wl->hardirq_lock);
5276 INIT_LIST_HEAD(&wl->devlist);
5277 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5278 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5279 INIT_WORK(&wl->tx_work, b43_tx_work);
5280 skb_queue_head_init(&wl->tx_queue);
5281
5282 snprintf(chip_name, ARRAY_SIZE(chip_name),
5283 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5284 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5285 dev->core_rev);
5286 return wl;
5287 }
5288
5289 #ifdef CONFIG_B43_BCMA
5290 static int b43_bcma_probe(struct bcma_device *core)
5291 {
5292 struct b43_bus_dev *dev;
5293 struct b43_wl *wl;
5294 int err;
5295
5296 dev = b43_bus_dev_bcma_init(core);
5297 if (!dev)
5298 return -ENODEV;
5299
5300 wl = b43_wireless_init(dev);
5301 if (IS_ERR(wl)) {
5302 err = PTR_ERR(wl);
5303 goto bcma_out;
5304 }
5305
5306 err = b43_one_core_attach(dev, wl);
5307 if (err)
5308 goto bcma_err_wireless_exit;
5309
5310 err = ieee80211_register_hw(wl->hw);
5311 if (err)
5312 goto bcma_err_one_core_detach;
5313 b43_leds_register(wl->current_dev);
5314
5315 bcma_out:
5316 return err;
5317
5318 bcma_err_one_core_detach:
5319 b43_one_core_detach(dev);
5320 bcma_err_wireless_exit:
5321 ieee80211_free_hw(wl->hw);
5322 return err;
5323 }
5324
5325 static void b43_bcma_remove(struct bcma_device *core)
5326 {
5327 struct b43_wldev *wldev = bcma_get_drvdata(core);
5328 struct b43_wl *wl = wldev->wl;
5329
5330 /* We must cancel any work here before unregistering from ieee80211,
5331 * as the ieee80211 unreg will destroy the workqueue. */
5332 cancel_work_sync(&wldev->restart_work);
5333
5334 /* Restore the queues count before unregistering, because firmware detect
5335 * might have modified it. Restoring is important, so the networking
5336 * stack can properly free resources. */
5337 wl->hw->queues = wl->mac80211_initially_registered_queues;
5338 b43_leds_stop(wldev);
5339 ieee80211_unregister_hw(wl->hw);
5340
5341 b43_one_core_detach(wldev->dev);
5342
5343 b43_leds_unregister(wl);
5344
5345 ieee80211_free_hw(wl->hw);
5346 }
5347
5348 static struct bcma_driver b43_bcma_driver = {
5349 .name = KBUILD_MODNAME,
5350 .id_table = b43_bcma_tbl,
5351 .probe = b43_bcma_probe,
5352 .remove = b43_bcma_remove,
5353 };
5354 #endif
5355
5356 #ifdef CONFIG_B43_SSB
5357 static
5358 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5359 {
5360 struct b43_bus_dev *dev;
5361 struct b43_wl *wl;
5362 int err;
5363 int first = 0;
5364
5365 dev = b43_bus_dev_ssb_init(sdev);
5366 if (!dev)
5367 return -ENOMEM;
5368
5369 wl = ssb_get_devtypedata(sdev);
5370 if (!wl) {
5371 /* Probing the first core. Must setup common struct b43_wl */
5372 first = 1;
5373 b43_sprom_fixup(sdev->bus);
5374 wl = b43_wireless_init(dev);
5375 if (IS_ERR(wl)) {
5376 err = PTR_ERR(wl);
5377 goto out;
5378 }
5379 ssb_set_devtypedata(sdev, wl);
5380 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5381 }
5382 err = b43_one_core_attach(dev, wl);
5383 if (err)
5384 goto err_wireless_exit;
5385
5386 if (first) {
5387 err = ieee80211_register_hw(wl->hw);
5388 if (err)
5389 goto err_one_core_detach;
5390 b43_leds_register(wl->current_dev);
5391 }
5392
5393 out:
5394 return err;
5395
5396 err_one_core_detach:
5397 b43_one_core_detach(dev);
5398 err_wireless_exit:
5399 if (first)
5400 b43_wireless_exit(dev, wl);
5401 return err;
5402 }
5403
5404 static void b43_ssb_remove(struct ssb_device *sdev)
5405 {
5406 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5407 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5408 struct b43_bus_dev *dev = wldev->dev;
5409
5410 /* We must cancel any work here before unregistering from ieee80211,
5411 * as the ieee80211 unreg will destroy the workqueue. */
5412 cancel_work_sync(&wldev->restart_work);
5413
5414 B43_WARN_ON(!wl);
5415 if (wl->current_dev == wldev) {
5416 /* Restore the queues count before unregistering, because firmware detect
5417 * might have modified it. Restoring is important, so the networking
5418 * stack can properly free resources. */
5419 wl->hw->queues = wl->mac80211_initially_registered_queues;
5420 b43_leds_stop(wldev);
5421 ieee80211_unregister_hw(wl->hw);
5422 }
5423
5424 b43_one_core_detach(dev);
5425
5426 if (list_empty(&wl->devlist)) {
5427 b43_leds_unregister(wl);
5428 /* Last core on the chip unregistered.
5429 * We can destroy common struct b43_wl.
5430 */
5431 b43_wireless_exit(dev, wl);
5432 }
5433 }
5434
5435 static struct ssb_driver b43_ssb_driver = {
5436 .name = KBUILD_MODNAME,
5437 .id_table = b43_ssb_tbl,
5438 .probe = b43_ssb_probe,
5439 .remove = b43_ssb_remove,
5440 };
5441 #endif /* CONFIG_B43_SSB */
5442
5443 /* Perform a hardware reset. This can be called from any context. */
5444 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5445 {
5446 /* Must avoid requeueing, if we are in shutdown. */
5447 if (b43_status(dev) < B43_STAT_INITIALIZED)
5448 return;
5449 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5450 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5451 }
5452
5453 static void b43_print_driverinfo(void)
5454 {
5455 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5456 *feat_leds = "", *feat_sdio = "";
5457
5458 #ifdef CONFIG_B43_PCI_AUTOSELECT
5459 feat_pci = "P";
5460 #endif
5461 #ifdef CONFIG_B43_PCMCIA
5462 feat_pcmcia = "M";
5463 #endif
5464 #ifdef CONFIG_B43_PHY_N
5465 feat_nphy = "N";
5466 #endif
5467 #ifdef CONFIG_B43_LEDS
5468 feat_leds = "L";
5469 #endif
5470 #ifdef CONFIG_B43_SDIO
5471 feat_sdio = "S";
5472 #endif
5473 printk(KERN_INFO "Broadcom 43xx driver loaded "
5474 "[ Features: %s%s%s%s%s ]\n",
5475 feat_pci, feat_pcmcia, feat_nphy,
5476 feat_leds, feat_sdio);
5477 }
5478
5479 static int __init b43_init(void)
5480 {
5481 int err;
5482
5483 b43_debugfs_init();
5484 err = b43_pcmcia_init();
5485 if (err)
5486 goto err_dfs_exit;
5487 err = b43_sdio_init();
5488 if (err)
5489 goto err_pcmcia_exit;
5490 #ifdef CONFIG_B43_BCMA
5491 err = bcma_driver_register(&b43_bcma_driver);
5492 if (err)
5493 goto err_sdio_exit;
5494 #endif
5495 #ifdef CONFIG_B43_SSB
5496 err = ssb_driver_register(&b43_ssb_driver);
5497 if (err)
5498 goto err_bcma_driver_exit;
5499 #endif
5500 b43_print_driverinfo();
5501
5502 return err;
5503
5504 #ifdef CONFIG_B43_SSB
5505 err_bcma_driver_exit:
5506 #endif
5507 #ifdef CONFIG_B43_BCMA
5508 bcma_driver_unregister(&b43_bcma_driver);
5509 err_sdio_exit:
5510 #endif
5511 b43_sdio_exit();
5512 err_pcmcia_exit:
5513 b43_pcmcia_exit();
5514 err_dfs_exit:
5515 b43_debugfs_exit();
5516 return err;
5517 }
5518
5519 static void __exit b43_exit(void)
5520 {
5521 #ifdef CONFIG_B43_SSB
5522 ssb_driver_unregister(&b43_ssb_driver);
5523 #endif
5524 #ifdef CONFIG_B43_BCMA
5525 bcma_driver_unregister(&b43_bcma_driver);
5526 #endif
5527 b43_sdio_exit();
5528 b43_pcmcia_exit();
5529 b43_debugfs_exit();
5530 }
5531
5532 module_init(b43_init)
5533 module_exit(b43_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree