drivers/gpu/drm/radeon/radeon_ring.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "atom.h"
  35
  36 int radeon_debugfs_ib_init(struct radeon_device *rdev);
  37 int radeon_debugfs_ring_init(struct radeon_device *rdev);
  38
  39 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  40 {
  41         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  42         u32 pg_idx, pg_offset;
  43         u32 idx_value = 0;
  44         int new_page;
  45
  46         pg_idx = (idx * 4) / PAGE_SIZE;
  47         pg_offset = (idx * 4) % PAGE_SIZE;
  48
  49         if (ibc->kpage_idx[0] == pg_idx)
  50                 return ibc->kpage[0][pg_offset/4];
  51         if (ibc->kpage_idx[1] == pg_idx)
  52                 return ibc->kpage[1][pg_offset/4];
  53
  54         new_page = radeon_cs_update_pages(p, pg_idx);
  55         if (new_page < 0) {
  56                 p->parser_error = new_page;
  57                 return 0;
  58         }
  59
  60         idx_value = ibc->kpage[new_page][pg_offset/4];
  61         return idx_value;
  62 }
  63
  64 void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
  65 {
  66 #if DRM_DEBUG_CODE
  67         if (ring->count_dw <= 0) {
  68                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  69         }
  70 #endif
  71         ring->ring[ring->wptr++] = v;
  72         ring->wptr &= ring->ptr_mask;
  73         ring->count_dw--;
  74         ring->ring_free_dw--;
  75 }
  76
  77 void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
  78 {
  79         struct radeon_ib *ib, *n;
  80
  81         list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) {
  82                 list_del(&ib->list);
  83                 vfree(ib->ptr);
  84                 kfree(ib);
  85         }
  86 }
  87
  88 void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
  89 {
  90         struct radeon_ib *bib;
  91
  92         bib = kmalloc(sizeof(*bib), GFP_KERNEL);
  93         if (bib == NULL)
  94                 return;
  95         bib->ptr = vmalloc(ib->length_dw * 4);
  96         if (bib->ptr == NULL) {
  97                 kfree(bib);
  98                 return;
  99         }
 100         memcpy(bib->ptr, ib->ptr, ib->length_dw * 4);
 101         bib->length_dw = ib->length_dw;
 102         mutex_lock(&rdev->ib_pool.mutex);
 103         list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib);
 104         mutex_unlock(&rdev->ib_pool.mutex);
 105 }
 106
 107 /*
 108  * IB.
 109  */
 110 int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib)
 111 {
 112         struct radeon_fence *fence;
 113         struct radeon_ib *nib;
 114         int r = 0, i, c;
 115
 116         *ib = NULL;
 117         r = radeon_fence_create(rdev, &fence, ring);
 118         if (r) {
 119                 dev_err(rdev->dev, "failed to create fence for new IB\n");
 120                 return r;
 121         }
 122         mutex_lock(&rdev->ib_pool.mutex);
 123         for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
 124                 i &= (RADEON_IB_POOL_SIZE - 1);
 125                 if (rdev->ib_pool.ibs[i].free) {
 126                         nib = &rdev->ib_pool.ibs[i];
 127                         break;
 128                 }
 129         }
 130         if (nib == NULL) {
 131                 /* This should never happen, it means we allocated all
 132                  * IB and haven't scheduled one yet, return EBUSY to
 133                  * userspace hoping that on ioctl recall we get better
 134                  * luck
 135                  */
 136                 dev_err(rdev->dev, "no free indirect buffer !\n");
 137                 mutex_unlock(&rdev->ib_pool.mutex);
 138                 radeon_fence_unref(&fence);
 139                 return -EBUSY;
 140         }
 141         rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
 142         nib->free = false;
 143         if (nib->fence) {
 144                 mutex_unlock(&rdev->ib_pool.mutex);
 145                 r = radeon_fence_wait(nib->fence, false);
 146                 if (r) {
 147                         dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
 148                                 nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
 149                         mutex_lock(&rdev->ib_pool.mutex);
 150                         nib->free = true;
 151                         mutex_unlock(&rdev->ib_pool.mutex);
 152                         radeon_fence_unref(&fence);
 153                         return r;
 154                 }
 155                 mutex_lock(&rdev->ib_pool.mutex);
 156         }
 157         radeon_fence_unref(&nib->fence);
 158         nib->fence = fence;
 159         nib->length_dw = 0;
 160         mutex_unlock(&rdev->ib_pool.mutex);
 161         *ib = nib;
 162         return 0;
 163 }
 164
 165 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
 166 {
 167         struct radeon_ib *tmp = *ib;
 168
 169         *ib = NULL;
 170         if (tmp == NULL) {
 171                 return;
 172         }
 173         if (!tmp->fence->emitted)
 174                 radeon_fence_unref(&tmp->fence);
 175         mutex_lock(&rdev->ib_pool.mutex);
 176         tmp->free = true;
 177         mutex_unlock(&rdev->ib_pool.mutex);
 178 }
 179
 180 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
 181 {
 182         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
 183         int r = 0;
 184
 185         if (!ib->length_dw || !ring->ready) {
 186                 /* TODO: Nothings in the ib we should report. */
 187                 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
 188                 return -EINVAL;
 189         }
 190
 191         /* 64 dwords should be enough for fence too */
 192         r = radeon_ring_lock(rdev, ring, 64);
 193         if (r) {
 194                 DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
 195                 return r;
 196         }
 197         radeon_ring_ib_execute(rdev, ib->fence->ring, ib);
 198         radeon_fence_emit(rdev, ib->fence);
 199         mutex_lock(&rdev->ib_pool.mutex);
 200         /* once scheduled IB is considered free and protected by the fence */
 201         ib->free = true;
 202         mutex_unlock(&rdev->ib_pool.mutex);
 203         radeon_ring_unlock_commit(rdev, ring);
 204         return 0;
 205 }
 206
 207 int radeon_ib_pool_init(struct radeon_device *rdev)
 208 {
 209         void *ptr;
 210         uint64_t gpu_addr;
 211         int i;
 212         int r = 0;
 213
 214         if (rdev->ib_pool.robj)
 215                 return 0;
 216         INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
 217         /* Allocate 1M object buffer */
 218         r = radeon_bo_create(rdev, RADEON_IB_POOL_SIZE*64*1024,
 219                              PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT,
 220                              &rdev->ib_pool.robj);
 221         if (r) {
 222                 DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
 223                 return r;
 224         }
 225         r = radeon_bo_reserve(rdev->ib_pool.robj, false);
 226         if (unlikely(r != 0))
 227                 return r;
 228         r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
 229         if (r) {
 230                 radeon_bo_unreserve(rdev->ib_pool.robj);
 231                 DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
 232                 return r;
 233         }
 234         r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
 235         radeon_bo_unreserve(rdev->ib_pool.robj);
 236         if (r) {
 237                 DRM_ERROR("radeon: failed to map ib pool (%d).\n", r);
 238                 return r;
 239         }
 240         for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
 241                 unsigned offset;
 242
 243                 offset = i * 64 * 1024;
 244                 rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
 245                 rdev->ib_pool.ibs[i].ptr = ptr + offset;
 246                 rdev->ib_pool.ibs[i].idx = i;
 247                 rdev->ib_pool.ibs[i].length_dw = 0;
 248                 rdev->ib_pool.ibs[i].free = true;
 249         }
 250         rdev->ib_pool.head_id = 0;
 251         rdev->ib_pool.ready = true;
 252         DRM_INFO("radeon: ib pool ready.\n");
 253         if (radeon_debugfs_ib_init(rdev)) {
 254                 DRM_ERROR("Failed to register debugfs file for IB !\n");
 255         }
 256         if (radeon_debugfs_ring_init(rdev)) {
 257                 DRM_ERROR("Failed to register debugfs file for rings !\n");
 258         }
 259         return r;
 260 }
 261
 262 void radeon_ib_pool_fini(struct radeon_device *rdev)
 263 {
 264         int r;
 265         struct radeon_bo *robj;
 266
 267         if (!rdev->ib_pool.ready) {
 268                 return;
 269         }
 270         mutex_lock(&rdev->ib_pool.mutex);
 271         radeon_ib_bogus_cleanup(rdev);
 272         robj = rdev->ib_pool.robj;
 273         rdev->ib_pool.robj = NULL;
 274         mutex_unlock(&rdev->ib_pool.mutex);
 275
 276         if (robj) {
 277                 r = radeon_bo_reserve(robj, false);
 278                 if (likely(r == 0)) {
 279                         radeon_bo_kunmap(robj);
 280                         radeon_bo_unpin(robj);
 281                         radeon_bo_unreserve(robj);
 282                 }
 283                 radeon_bo_unref(&robj);
 284         }
 285 }
 286
 287
 288 /*
 289  * Ring.
 290  */
 291 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring)
 292 {
 293         /* r1xx-r5xx only has CP ring */
 294         if (rdev->family < CHIP_R600)
 295                 return RADEON_RING_TYPE_GFX_INDEX;
 296
 297         if (rdev->family >= CHIP_CAYMAN) {
 298                 if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX])
 299                         return CAYMAN_RING_TYPE_CP1_INDEX;
 300                 else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX])
 301                         return CAYMAN_RING_TYPE_CP2_INDEX;
 302         }
 303         return RADEON_RING_TYPE_GFX_INDEX;
 304 }
 305
 306 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
 307 {
 308         u32 rptr;
 309
 310         if (rdev->wb.enabled)
 311                 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
 312         else
 313                 rptr = RREG32(ring->rptr_reg);
 314         ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
 315         /* This works because ring_size is a power of 2 */
 316         ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
 317         ring->ring_free_dw -= ring->wptr;
 318         ring->ring_free_dw &= ring->ptr_mask;
 319         if (!ring->ring_free_dw) {
 320                 ring->ring_free_dw = ring->ring_size / 4;
 321         }
 322 }
 323
 324
 325 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
 326 {
 327         int r;
 328
 329         /* Align requested size with padding so unlock_commit can
 330          * pad safely */
 331         ndw = (ndw + ring->align_mask) & ~ring->align_mask;
 332         while (ndw > (ring->ring_free_dw - 1)) {
 333                 radeon_ring_free_size(rdev, ring);
 334                 if (ndw < ring->ring_free_dw) {
 335                         break;
 336                 }
 337                 r = radeon_fence_wait_next(rdev, radeon_ring_index(rdev, ring));
 338                 if (r)
 339                         return r;
 340         }
 341         ring->count_dw = ndw;
 342         ring->wptr_old = ring->wptr;
 343         return 0;
 344 }
 345
 346 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
 347 {
 348         int r;
 349
 350         mutex_lock(&ring->mutex);
 351         r = radeon_ring_alloc(rdev, ring, ndw);
 352         if (r) {
 353                 mutex_unlock(&ring->mutex);
 354                 return r;
 355         }
 356         return 0;
 357 }
 358
 359 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
 360 {
 361         unsigned count_dw_pad;
 362         unsigned i;
 363
 364         /* We pad to match fetch size */
 365         count_dw_pad = (ring->align_mask + 1) -
 366                        (ring->wptr & ring->align_mask);
 367         for (i = 0; i < count_dw_pad; i++) {
 368                 radeon_ring_write(ring, ring->nop);
 369         }
 370         DRM_MEMORYBARRIER();
 371         WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
 372         (void)RREG32(ring->wptr_reg);
 373 }
 374
 375 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
 376 {
 377         radeon_ring_commit(rdev, ring);
 378         mutex_unlock(&ring->mutex);
 379 }
 380
 381 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
 382 {
 383         ring->wptr = ring->wptr_old;
 384         mutex_unlock(&ring->mutex);
 385 }
 386
 387 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
 388                      unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
 389                      u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
 390 {
 391         int r;
 392
 393         ring->ring_size = ring_size;
 394         ring->rptr_offs = rptr_offs;
 395         ring->rptr_reg = rptr_reg;
 396         ring->wptr_reg = wptr_reg;
 397         ring->ptr_reg_shift = ptr_reg_shift;
 398         ring->ptr_reg_mask = ptr_reg_mask;
 399         ring->nop = nop;
 400         /* Allocate ring buffer */
 401         if (ring->ring_obj == NULL) {
 402                 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
 403                                         RADEON_GEM_DOMAIN_GTT,
 404                                         &ring->ring_obj);
 405                 if (r) {
 406                         dev_err(rdev->dev, "(%d) ring create failed\n", r);
 407                         return r;
 408                 }
 409                 r = radeon_bo_reserve(ring->ring_obj, false);
 410                 if (unlikely(r != 0))
 411                         return r;
 412                 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
 413                                         &ring->gpu_addr);
 414                 if (r) {
 415                         radeon_bo_unreserve(ring->ring_obj);
 416                         dev_err(rdev->dev, "(%d) ring pin failed\n", r);
 417                         return r;
 418                 }
 419                 r = radeon_bo_kmap(ring->ring_obj,
 420                                        (void **)&ring->ring);
 421                 radeon_bo_unreserve(ring->ring_obj);
 422                 if (r) {
 423                         dev_err(rdev->dev, "(%d) ring map failed\n", r);
 424                         return r;
 425                 }
 426         }
 427         ring->ptr_mask = (ring->ring_size / 4) - 1;
 428         ring->ring_free_dw = ring->ring_size / 4;
 429         return 0;
 430 }
 431
 432 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
 433 {
 434         int r;
 435         struct radeon_bo *ring_obj;
 436
 437         mutex_lock(&ring->mutex);
 438         ring_obj = ring->ring_obj;
 439         ring->ring = NULL;
 440         ring->ring_obj = NULL;
 441         mutex_unlock(&ring->mutex);
 442
 443         if (ring_obj) {
 444                 r = radeon_bo_reserve(ring_obj, false);
 445                 if (likely(r == 0)) {
 446                         radeon_bo_kunmap(ring_obj);
 447                         radeon_bo_unpin(ring_obj);
 448                         radeon_bo_unreserve(ring_obj);
 449                 }
 450                 radeon_bo_unref(&ring_obj);
 451         }
 452 }
 453
 454 /*
 455  * Debugfs info
 456  */
 457 #if defined(CONFIG_DEBUG_FS)
 458
 459 static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
 460 {
 461         struct drm_info_node *node = (struct drm_info_node *) m->private;
 462         struct drm_device *dev = node->minor->dev;
 463         struct radeon_device *rdev = dev->dev_private;
 464         int ridx = *(int*)node->info_ent->data;
 465         struct radeon_ring *ring = &rdev->ring[ridx];
 466         unsigned count, i, j;
 467
 468         radeon_ring_free_size(rdev, ring);
 469         count = (ring->ring_size / 4) - ring->ring_free_dw;
 470         seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
 471         seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
 472         seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
 473         seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
 474         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
 475         seq_printf(m, "%u dwords in ring\n", count);
 476         i = ring->rptr;
 477         for (j = 0; j <= count; j++) {
 478                 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
 479                 i = (i + 1) & ring->ptr_mask;
 480         }
 481         return 0;
 482 }
 483
 484 static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
 485 static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
 486 static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
 487
 488 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
 489         {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
 490         {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
 491         {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
 492 };
 493
 494 static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
 495 {
 496         struct drm_info_node *node = (struct drm_info_node *) m->private;
 497         struct radeon_ib *ib = node->info_ent->data;
 498         unsigned i;
 499
 500         if (ib == NULL) {
 501                 return 0;
 502         }
 503         seq_printf(m, "IB %04u\n", ib->idx);
 504         seq_printf(m, "IB fence %p\n", ib->fence);
 505         seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
 506         for (i = 0; i < ib->length_dw; i++) {
 507                 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
 508         }
 509         return 0;
 510 }
 511
 512 static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data)
 513 {
 514         struct drm_info_node *node = (struct drm_info_node *) m->private;
 515         struct radeon_device *rdev = node->info_ent->data;
 516         struct radeon_ib *ib;
 517         unsigned i;
 518
 519         mutex_lock(&rdev->ib_pool.mutex);
 520         if (list_empty(&rdev->ib_pool.bogus_ib)) {
 521                 mutex_unlock(&rdev->ib_pool.mutex);
 522                 seq_printf(m, "no bogus IB recorded\n");
 523                 return 0;
 524         }
 525         ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list);
 526         list_del_init(&ib->list);
 527         mutex_unlock(&rdev->ib_pool.mutex);
 528         seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
 529         for (i = 0; i < ib->length_dw; i++) {
 530                 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
 531         }
 532         vfree(ib->ptr);
 533         kfree(ib);
 534         return 0;
 535 }
 536
 537 static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
 538 static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
 539
 540 static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = {
 541         {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL},
 542 };
 543 #endif
 544
 545 int radeon_debugfs_ring_init(struct radeon_device *rdev)
 546 {
 547 #if defined(CONFIG_DEBUG_FS)
 548         return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list,
 549                                         ARRAY_SIZE(radeon_debugfs_ring_info_list));
 550 #else
 551         return 0;
 552 #endif
 553 }
 554
 555 int radeon_debugfs_ib_init(struct radeon_device *rdev)
 556 {
 557 #if defined(CONFIG_DEBUG_FS)
 558         unsigned i;
 559         int r;
 560
 561         radeon_debugfs_ib_bogus_info_list[0].data = rdev;
 562         r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1);
 563         if (r)
 564                 return r;
 565         for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
 566                 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
 567                 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
 568                 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
 569                 radeon_debugfs_ib_list[i].driver_features = 0;
 570                 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
 571         }
 572         return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
 573                                         RADEON_IB_POOL_SIZE);
 574 #else
 575         return 0;
 576 #endif
 577 }