2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
9 #define LX_NODE_BASE 10
11 #define MIPSCPU_INT_BASE 16
12 #define MIPS_CPU_RTLX_IRQ 0
14 #define RTLX_VERSION 1
15 #define RTLX_xID 0x12345600
16 #define RTLX_ID (RTLX_xID | RTLX_VERSION)
17 #define RTLX_CHANNELS 8
19 #define RTLX_BUFFER_SIZE 1024
24 #define RTLX_STATE_OPENED 1UL
26 /* each channel supports read and write.
27 linux (vpe0) reads lx_buffer and writes rt_buffer
28 SP (vpe1) reads rt_buffer and writes lx_buffer
31 unsigned long lx_state
;
35 /* read and write indexes per buffer */
36 int rt_write
, rt_read
;
39 int lx_write
, lx_read
;
49 struct rtlx_channel channel
[RTLX_CHANNELS
];