1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #define MAX_NOPID ((u32)~0)
41 * Interrupts that are always left unmasked.
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
68 ironlake_enable_graphics_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
70 if ((dev_priv
->gt_irq_mask_reg
& mask
) != 0) {
71 dev_priv
->gt_irq_mask_reg
&= ~mask
;
72 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
73 (void) I915_READ(GTIMR
);
78 ironlake_disable_graphics_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
80 if ((dev_priv
->gt_irq_mask_reg
& mask
) != mask
) {
81 dev_priv
->gt_irq_mask_reg
|= mask
;
82 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
83 (void) I915_READ(GTIMR
);
87 /* For display hotplug interrupt */
89 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
91 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
92 dev_priv
->irq_mask_reg
&= ~mask
;
93 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
94 (void) I915_READ(DEIMR
);
99 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
101 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
102 dev_priv
->irq_mask_reg
|= mask
;
103 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
104 (void) I915_READ(DEIMR
);
109 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
111 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
112 dev_priv
->irq_mask_reg
&= ~mask
;
113 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
114 (void) I915_READ(IMR
);
119 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
121 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
122 dev_priv
->irq_mask_reg
|= mask
;
123 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
124 (void) I915_READ(IMR
);
129 i915_pipestat(int pipe
)
139 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
141 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
142 u32 reg
= i915_pipestat(pipe
);
144 dev_priv
->pipestat
[pipe
] |= mask
;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
147 (void) I915_READ(reg
);
152 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
154 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
155 u32 reg
= i915_pipestat(pipe
);
157 dev_priv
->pipestat
[pipe
] &= ~mask
;
158 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
159 (void) I915_READ(reg
);
164 * intel_enable_asle - enable ASLE interrupt for OpRegion
166 void intel_enable_asle (struct drm_device
*dev
)
168 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
170 if (HAS_PCH_SPLIT(dev
))
171 ironlake_enable_display_irq(dev_priv
, DE_GSE
);
173 i915_enable_pipestat(dev_priv
, 1,
174 PIPE_LEGACY_BLC_EVENT_ENABLE
);
175 if (INTEL_INFO(dev
)->gen
>= 4)
176 i915_enable_pipestat(dev_priv
, 0,
177 PIPE_LEGACY_BLC_EVENT_ENABLE
);
182 * i915_pipe_enabled - check if a pipe is enabled
184 * @pipe: pipe to check
186 * Reading certain registers when the pipe is disabled can hang the chip.
187 * Use this routine to make sure the PLL is running and the pipe is active
188 * before reading such registers if unsure.
191 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
193 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
194 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
197 /* Called from drm generic code, passed a 'crtc', which
198 * we use as a pipe index
200 u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
202 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
203 unsigned long high_frame
;
204 unsigned long low_frame
;
205 u32 high1
, high2
, low
;
207 if (!i915_pipe_enabled(dev
, pipe
)) {
208 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
213 high_frame
= pipe
? PIPEBFRAMEHIGH
: PIPEAFRAMEHIGH
;
214 low_frame
= pipe
? PIPEBFRAMEPIXEL
: PIPEAFRAMEPIXEL
;
217 * High & low register fields aren't synchronized, so make sure
218 * we get a low value that's stable across two reads of the high
222 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
223 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
224 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
225 } while (high1
!= high2
);
227 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
228 low
>>= PIPE_FRAME_LOW_SHIFT
;
229 return (high1
<< 8) | low
;
232 u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
234 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
235 int reg
= pipe
? PIPEB_FRMCOUNT_GM45
: PIPEA_FRMCOUNT_GM45
;
237 if (!i915_pipe_enabled(dev
, pipe
)) {
238 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
243 return I915_READ(reg
);
247 * Handle hotplug events outside the interrupt handler proper.
249 static void i915_hotplug_work_func(struct work_struct
*work
)
251 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
253 struct drm_device
*dev
= dev_priv
->dev
;
254 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
255 struct intel_encoder
*encoder
;
257 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
258 if (encoder
->hot_plug
)
259 encoder
->hot_plug(encoder
);
261 /* Just fire off a uevent and let userspace tell us what to do */
262 drm_helper_hpd_irq_event(dev
);
265 static void i915_handle_rps_change(struct drm_device
*dev
)
267 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
268 u32 busy_up
, busy_down
, max_avg
, min_avg
;
269 u8 new_delay
= dev_priv
->cur_delay
;
271 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
272 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
273 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
274 max_avg
= I915_READ(RCBMAXAVG
);
275 min_avg
= I915_READ(RCBMINAVG
);
277 /* Handle RCS change request from hw */
278 if (busy_up
> max_avg
) {
279 if (dev_priv
->cur_delay
!= dev_priv
->max_delay
)
280 new_delay
= dev_priv
->cur_delay
- 1;
281 if (new_delay
< dev_priv
->max_delay
)
282 new_delay
= dev_priv
->max_delay
;
283 } else if (busy_down
< min_avg
) {
284 if (dev_priv
->cur_delay
!= dev_priv
->min_delay
)
285 new_delay
= dev_priv
->cur_delay
+ 1;
286 if (new_delay
> dev_priv
->min_delay
)
287 new_delay
= dev_priv
->min_delay
;
290 if (ironlake_set_drps(dev
, new_delay
))
291 dev_priv
->cur_delay
= new_delay
;
296 static void notify_ring(struct drm_device
*dev
,
297 struct intel_ring_buffer
*ring
)
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 u32 seqno
= ring
->get_seqno(ring
);
301 ring
->irq_gem_seqno
= seqno
;
302 trace_i915_gem_request_complete(dev
, seqno
);
303 wake_up_all(&ring
->irq_queue
);
304 dev_priv
->hangcheck_count
= 0;
305 mod_timer(&dev_priv
->hangcheck_timer
,
306 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
309 static irqreturn_t
ironlake_irq_handler(struct drm_device
*dev
)
311 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
313 u32 de_iir
, gt_iir
, de_ier
, pch_iir
;
315 struct drm_i915_master_private
*master_priv
;
316 u32 bsd_usr_interrupt
= GT_BSD_USER_INTERRUPT
;
319 bsd_usr_interrupt
= GT_GEN6_BSD_USER_INTERRUPT
;
321 /* disable master interrupt before clearing iir */
322 de_ier
= I915_READ(DEIER
);
323 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
324 (void)I915_READ(DEIER
);
326 de_iir
= I915_READ(DEIIR
);
327 gt_iir
= I915_READ(GTIIR
);
328 pch_iir
= I915_READ(SDEIIR
);
330 if (de_iir
== 0 && gt_iir
== 0 && pch_iir
== 0)
333 if (HAS_PCH_CPT(dev
))
334 hotplug_mask
= SDE_HOTPLUG_MASK_CPT
;
336 hotplug_mask
= SDE_HOTPLUG_MASK
;
340 if (dev
->primary
->master
) {
341 master_priv
= dev
->primary
->master
->driver_priv
;
342 if (master_priv
->sarea_priv
)
343 master_priv
->sarea_priv
->last_dispatch
=
344 READ_BREADCRUMB(dev_priv
);
347 if (gt_iir
& GT_PIPE_NOTIFY
)
348 notify_ring(dev
, &dev_priv
->render_ring
);
349 if (gt_iir
& bsd_usr_interrupt
)
350 notify_ring(dev
, &dev_priv
->bsd_ring
);
351 if (HAS_BLT(dev
) && gt_iir
& GT_BLT_USER_INTERRUPT
)
352 notify_ring(dev
, &dev_priv
->blt_ring
);
355 intel_opregion_gse_intr(dev
);
357 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
358 intel_prepare_page_flip(dev
, 0);
359 intel_finish_page_flip_plane(dev
, 0);
362 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
363 intel_prepare_page_flip(dev
, 1);
364 intel_finish_page_flip_plane(dev
, 1);
367 if (de_iir
& DE_PIPEA_VBLANK
)
368 drm_handle_vblank(dev
, 0);
370 if (de_iir
& DE_PIPEB_VBLANK
)
371 drm_handle_vblank(dev
, 1);
373 /* check event from PCH */
374 if ((de_iir
& DE_PCH_EVENT
) && (pch_iir
& hotplug_mask
))
375 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
377 if (de_iir
& DE_PCU_EVENT
) {
378 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
379 i915_handle_rps_change(dev
);
382 /* should clear PCH hotplug event before clear CPU irq */
383 I915_WRITE(SDEIIR
, pch_iir
);
384 I915_WRITE(GTIIR
, gt_iir
);
385 I915_WRITE(DEIIR
, de_iir
);
388 I915_WRITE(DEIER
, de_ier
);
389 (void)I915_READ(DEIER
);
395 * i915_error_work_func - do process context error handling work
398 * Fire an error uevent so userspace can see that a hang or error
401 static void i915_error_work_func(struct work_struct
*work
)
403 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
405 struct drm_device
*dev
= dev_priv
->dev
;
406 char *error_event
[] = { "ERROR=1", NULL
};
407 char *reset_event
[] = { "RESET=1", NULL
};
408 char *reset_done_event
[] = { "ERROR=0", NULL
};
410 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
412 if (atomic_read(&dev_priv
->mm
.wedged
)) {
413 DRM_DEBUG_DRIVER("resetting chip\n");
414 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_event
);
415 if (!i915_reset(dev
, GRDOM_RENDER
)) {
416 atomic_set(&dev_priv
->mm
.wedged
, 0);
417 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_done_event
);
419 complete_all(&dev_priv
->error_completion
);
423 #ifdef CONFIG_DEBUG_FS
424 static struct drm_i915_error_object
*
425 i915_error_object_create(struct drm_device
*dev
,
426 struct drm_gem_object
*src
)
428 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
429 struct drm_i915_error_object
*dst
;
430 struct drm_i915_gem_object
*src_priv
;
431 int page
, page_count
;
437 src_priv
= to_intel_bo(src
);
438 if (src_priv
->pages
== NULL
)
441 page_count
= src
->size
/ PAGE_SIZE
;
443 dst
= kmalloc(sizeof(*dst
) + page_count
* sizeof (u32
*), GFP_ATOMIC
);
447 reloc_offset
= src_priv
->gtt_offset
;
448 for (page
= 0; page
< page_count
; page
++) {
453 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
457 local_irq_save(flags
);
458 s
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
460 memcpy_fromio(d
, s
, PAGE_SIZE
);
461 io_mapping_unmap_atomic(s
);
462 local_irq_restore(flags
);
464 dst
->pages
[page
] = d
;
466 reloc_offset
+= PAGE_SIZE
;
468 dst
->page_count
= page_count
;
469 dst
->gtt_offset
= src_priv
->gtt_offset
;
475 kfree(dst
->pages
[page
]);
481 i915_error_object_free(struct drm_i915_error_object
*obj
)
488 for (page
= 0; page
< obj
->page_count
; page
++)
489 kfree(obj
->pages
[page
]);
495 i915_error_state_free(struct drm_device
*dev
,
496 struct drm_i915_error_state
*error
)
498 i915_error_object_free(error
->batchbuffer
[0]);
499 i915_error_object_free(error
->batchbuffer
[1]);
500 i915_error_object_free(error
->ringbuffer
);
501 kfree(error
->active_bo
);
502 kfree(error
->overlay
);
507 i915_get_bbaddr(struct drm_device
*dev
, u32
*ring
)
511 if (IS_I830(dev
) || IS_845G(dev
))
512 cmd
= MI_BATCH_BUFFER
;
513 else if (INTEL_INFO(dev
)->gen
>= 4)
514 cmd
= (MI_BATCH_BUFFER_START
| (2 << 6) |
515 MI_BATCH_NON_SECURE_I965
);
517 cmd
= (MI_BATCH_BUFFER_START
| (2 << 6));
519 return ring
[0] == cmd
? ring
[1] : 0;
523 i915_ringbuffer_last_batch(struct drm_device
*dev
)
525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
529 /* Locate the current position in the ringbuffer and walk back
530 * to find the most recently dispatched batch buffer.
533 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
534 ring
= (u32
*)(dev_priv
->render_ring
.virtual_start
+ head
);
536 while (--ring
>= (u32
*)dev_priv
->render_ring
.virtual_start
) {
537 bbaddr
= i915_get_bbaddr(dev
, ring
);
543 ring
= (u32
*)(dev_priv
->render_ring
.virtual_start
544 + dev_priv
->render_ring
.size
);
545 while (--ring
>= (u32
*)dev_priv
->render_ring
.virtual_start
) {
546 bbaddr
= i915_get_bbaddr(dev
, ring
);
556 * i915_capture_error_state - capture an error record for later analysis
559 * Should be called when an error is detected (either a hang or an error
560 * interrupt) to capture error state from the time of the error. Fills
561 * out a structure which becomes available in debugfs for user level tools
564 static void i915_capture_error_state(struct drm_device
*dev
)
566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
567 struct drm_i915_gem_object
*obj_priv
;
568 struct drm_i915_error_state
*error
;
569 struct drm_gem_object
*batchbuffer
[2];
574 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
575 error
= dev_priv
->first_error
;
576 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
580 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
582 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
586 DRM_DEBUG_DRIVER("generating error event\n");
589 dev_priv
->render_ring
.get_seqno(&dev_priv
->render_ring
);
590 error
->eir
= I915_READ(EIR
);
591 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
592 error
->pipeastat
= I915_READ(PIPEASTAT
);
593 error
->pipebstat
= I915_READ(PIPEBSTAT
);
594 error
->instpm
= I915_READ(INSTPM
);
595 if (INTEL_INFO(dev
)->gen
< 4) {
596 error
->ipeir
= I915_READ(IPEIR
);
597 error
->ipehr
= I915_READ(IPEHR
);
598 error
->instdone
= I915_READ(INSTDONE
);
599 error
->acthd
= I915_READ(ACTHD
);
602 error
->ipeir
= I915_READ(IPEIR_I965
);
603 error
->ipehr
= I915_READ(IPEHR_I965
);
604 error
->instdone
= I915_READ(INSTDONE_I965
);
605 error
->instps
= I915_READ(INSTPS
);
606 error
->instdone1
= I915_READ(INSTDONE1
);
607 error
->acthd
= I915_READ(ACTHD_I965
);
608 error
->bbaddr
= I915_READ64(BB_ADDR
);
611 bbaddr
= i915_ringbuffer_last_batch(dev
);
613 /* Grab the current batchbuffer, most likely to have crashed. */
614 batchbuffer
[0] = NULL
;
615 batchbuffer
[1] = NULL
;
617 list_for_each_entry(obj_priv
, &dev_priv
->mm
.active_list
, mm_list
) {
618 struct drm_gem_object
*obj
= &obj_priv
->base
;
620 if (batchbuffer
[0] == NULL
&&
621 bbaddr
>= obj_priv
->gtt_offset
&&
622 bbaddr
< obj_priv
->gtt_offset
+ obj
->size
)
623 batchbuffer
[0] = obj
;
625 if (batchbuffer
[1] == NULL
&&
626 error
->acthd
>= obj_priv
->gtt_offset
&&
627 error
->acthd
< obj_priv
->gtt_offset
+ obj
->size
)
628 batchbuffer
[1] = obj
;
632 /* Scan the other lists for completeness for those bizarre errors. */
633 if (batchbuffer
[0] == NULL
|| batchbuffer
[1] == NULL
) {
634 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, mm_list
) {
635 struct drm_gem_object
*obj
= &obj_priv
->base
;
637 if (batchbuffer
[0] == NULL
&&
638 bbaddr
>= obj_priv
->gtt_offset
&&
639 bbaddr
< obj_priv
->gtt_offset
+ obj
->size
)
640 batchbuffer
[0] = obj
;
642 if (batchbuffer
[1] == NULL
&&
643 error
->acthd
>= obj_priv
->gtt_offset
&&
644 error
->acthd
< obj_priv
->gtt_offset
+ obj
->size
)
645 batchbuffer
[1] = obj
;
647 if (batchbuffer
[0] && batchbuffer
[1])
651 if (batchbuffer
[0] == NULL
|| batchbuffer
[1] == NULL
) {
652 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, mm_list
) {
653 struct drm_gem_object
*obj
= &obj_priv
->base
;
655 if (batchbuffer
[0] == NULL
&&
656 bbaddr
>= obj_priv
->gtt_offset
&&
657 bbaddr
< obj_priv
->gtt_offset
+ obj
->size
)
658 batchbuffer
[0] = obj
;
660 if (batchbuffer
[1] == NULL
&&
661 error
->acthd
>= obj_priv
->gtt_offset
&&
662 error
->acthd
< obj_priv
->gtt_offset
+ obj
->size
)
663 batchbuffer
[1] = obj
;
665 if (batchbuffer
[0] && batchbuffer
[1])
670 /* We need to copy these to an anonymous buffer as the simplest
671 * method to avoid being overwritten by userspace.
673 error
->batchbuffer
[0] = i915_error_object_create(dev
, batchbuffer
[0]);
674 if (batchbuffer
[1] != batchbuffer
[0])
675 error
->batchbuffer
[1] = i915_error_object_create(dev
, batchbuffer
[1]);
677 error
->batchbuffer
[1] = NULL
;
679 /* Record the ringbuffer */
680 error
->ringbuffer
= i915_error_object_create(dev
,
681 dev_priv
->render_ring
.gem_object
);
683 /* Record buffers on the active list. */
684 error
->active_bo
= NULL
;
685 error
->active_bo_count
= 0;
688 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*count
,
691 if (error
->active_bo
) {
693 list_for_each_entry(obj_priv
, &dev_priv
->mm
.active_list
, mm_list
) {
694 struct drm_gem_object
*obj
= &obj_priv
->base
;
696 error
->active_bo
[i
].size
= obj
->size
;
697 error
->active_bo
[i
].name
= obj
->name
;
698 error
->active_bo
[i
].seqno
= obj_priv
->last_rendering_seqno
;
699 error
->active_bo
[i
].gtt_offset
= obj_priv
->gtt_offset
;
700 error
->active_bo
[i
].read_domains
= obj
->read_domains
;
701 error
->active_bo
[i
].write_domain
= obj
->write_domain
;
702 error
->active_bo
[i
].fence_reg
= obj_priv
->fence_reg
;
703 error
->active_bo
[i
].pinned
= 0;
704 if (obj_priv
->pin_count
> 0)
705 error
->active_bo
[i
].pinned
= 1;
706 if (obj_priv
->user_pin_count
> 0)
707 error
->active_bo
[i
].pinned
= -1;
708 error
->active_bo
[i
].tiling
= obj_priv
->tiling_mode
;
709 error
->active_bo
[i
].dirty
= obj_priv
->dirty
;
710 error
->active_bo
[i
].purgeable
= obj_priv
->madv
!= I915_MADV_WILLNEED
;
715 error
->active_bo_count
= i
;
718 do_gettimeofday(&error
->time
);
720 error
->overlay
= intel_overlay_capture_error_state(dev
);
722 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
723 if (dev_priv
->first_error
== NULL
) {
724 dev_priv
->first_error
= error
;
727 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
730 i915_error_state_free(dev
, error
);
733 void i915_destroy_error_state(struct drm_device
*dev
)
735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
736 struct drm_i915_error_state
*error
;
738 spin_lock(&dev_priv
->error_lock
);
739 error
= dev_priv
->first_error
;
740 dev_priv
->first_error
= NULL
;
741 spin_unlock(&dev_priv
->error_lock
);
744 i915_error_state_free(dev
, error
);
747 #define i915_capture_error_state(x)
750 static void i915_report_and_clear_eir(struct drm_device
*dev
)
752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
753 u32 eir
= I915_READ(EIR
);
758 printk(KERN_ERR
"render error detected, EIR: 0x%08x\n",
762 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
763 u32 ipeir
= I915_READ(IPEIR_I965
);
765 printk(KERN_ERR
" IPEIR: 0x%08x\n",
766 I915_READ(IPEIR_I965
));
767 printk(KERN_ERR
" IPEHR: 0x%08x\n",
768 I915_READ(IPEHR_I965
));
769 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
770 I915_READ(INSTDONE_I965
));
771 printk(KERN_ERR
" INSTPS: 0x%08x\n",
773 printk(KERN_ERR
" INSTDONE1: 0x%08x\n",
774 I915_READ(INSTDONE1
));
775 printk(KERN_ERR
" ACTHD: 0x%08x\n",
776 I915_READ(ACTHD_I965
));
777 I915_WRITE(IPEIR_I965
, ipeir
);
778 (void)I915_READ(IPEIR_I965
);
780 if (eir
& GM45_ERROR_PAGE_TABLE
) {
781 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
782 printk(KERN_ERR
"page table error\n");
783 printk(KERN_ERR
" PGTBL_ER: 0x%08x\n",
785 I915_WRITE(PGTBL_ER
, pgtbl_err
);
786 (void)I915_READ(PGTBL_ER
);
791 if (eir
& I915_ERROR_PAGE_TABLE
) {
792 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
793 printk(KERN_ERR
"page table error\n");
794 printk(KERN_ERR
" PGTBL_ER: 0x%08x\n",
796 I915_WRITE(PGTBL_ER
, pgtbl_err
);
797 (void)I915_READ(PGTBL_ER
);
801 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
802 u32 pipea_stats
= I915_READ(PIPEASTAT
);
803 u32 pipeb_stats
= I915_READ(PIPEBSTAT
);
805 printk(KERN_ERR
"memory refresh error\n");
806 printk(KERN_ERR
"PIPEASTAT: 0x%08x\n",
808 printk(KERN_ERR
"PIPEBSTAT: 0x%08x\n",
810 /* pipestat has already been acked */
812 if (eir
& I915_ERROR_INSTRUCTION
) {
813 printk(KERN_ERR
"instruction error\n");
814 printk(KERN_ERR
" INSTPM: 0x%08x\n",
816 if (INTEL_INFO(dev
)->gen
< 4) {
817 u32 ipeir
= I915_READ(IPEIR
);
819 printk(KERN_ERR
" IPEIR: 0x%08x\n",
821 printk(KERN_ERR
" IPEHR: 0x%08x\n",
823 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
824 I915_READ(INSTDONE
));
825 printk(KERN_ERR
" ACTHD: 0x%08x\n",
827 I915_WRITE(IPEIR
, ipeir
);
828 (void)I915_READ(IPEIR
);
830 u32 ipeir
= I915_READ(IPEIR_I965
);
832 printk(KERN_ERR
" IPEIR: 0x%08x\n",
833 I915_READ(IPEIR_I965
));
834 printk(KERN_ERR
" IPEHR: 0x%08x\n",
835 I915_READ(IPEHR_I965
));
836 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
837 I915_READ(INSTDONE_I965
));
838 printk(KERN_ERR
" INSTPS: 0x%08x\n",
840 printk(KERN_ERR
" INSTDONE1: 0x%08x\n",
841 I915_READ(INSTDONE1
));
842 printk(KERN_ERR
" ACTHD: 0x%08x\n",
843 I915_READ(ACTHD_I965
));
844 I915_WRITE(IPEIR_I965
, ipeir
);
845 (void)I915_READ(IPEIR_I965
);
849 I915_WRITE(EIR
, eir
);
850 (void)I915_READ(EIR
);
851 eir
= I915_READ(EIR
);
854 * some errors might have become stuck,
857 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
858 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
859 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
864 * i915_handle_error - handle an error interrupt
867 * Do some basic checking of regsiter state at error interrupt time and
868 * dump it to the syslog. Also call i915_capture_error_state() to make
869 * sure we get a record and make it available in debugfs. Fire a uevent
870 * so userspace knows something bad happened (should trigger collection
871 * of a ring dump etc.).
873 static void i915_handle_error(struct drm_device
*dev
, bool wedged
)
875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
877 i915_capture_error_state(dev
);
878 i915_report_and_clear_eir(dev
);
881 INIT_COMPLETION(dev_priv
->error_completion
);
882 atomic_set(&dev_priv
->mm
.wedged
, 1);
885 * Wakeup waiting processes so they don't hang
887 wake_up_all(&dev_priv
->render_ring
.irq_queue
);
889 wake_up_all(&dev_priv
->bsd_ring
.irq_queue
);
891 wake_up_all(&dev_priv
->blt_ring
.irq_queue
);
894 queue_work(dev_priv
->wq
, &dev_priv
->error_work
);
897 static void i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
899 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
900 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
901 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
902 struct drm_i915_gem_object
*obj_priv
;
903 struct intel_unpin_work
*work
;
907 /* Ignore early vblank irqs */
908 if (intel_crtc
== NULL
)
911 spin_lock_irqsave(&dev
->event_lock
, flags
);
912 work
= intel_crtc
->unpin_work
;
914 if (work
== NULL
|| work
->pending
|| !work
->enable_stall_check
) {
915 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
916 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
920 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
921 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
922 if (INTEL_INFO(dev
)->gen
>= 4) {
923 int dspsurf
= intel_crtc
->plane
== 0 ? DSPASURF
: DSPBSURF
;
924 stall_detected
= I915_READ(dspsurf
) == obj_priv
->gtt_offset
;
926 int dspaddr
= intel_crtc
->plane
== 0 ? DSPAADDR
: DSPBADDR
;
927 stall_detected
= I915_READ(dspaddr
) == (obj_priv
->gtt_offset
+
928 crtc
->y
* crtc
->fb
->pitch
+
929 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
932 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
934 if (stall_detected
) {
935 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
936 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
940 irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
)
942 struct drm_device
*dev
= (struct drm_device
*) arg
;
943 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
944 struct drm_i915_master_private
*master_priv
;
946 u32 pipea_stats
, pipeb_stats
;
949 unsigned long irqflags
;
953 atomic_inc(&dev_priv
->irq_received
);
955 if (HAS_PCH_SPLIT(dev
))
956 return ironlake_irq_handler(dev
);
958 iir
= I915_READ(IIR
);
960 if (INTEL_INFO(dev
)->gen
>= 4)
961 vblank_status
= PIPE_START_VBLANK_INTERRUPT_STATUS
;
963 vblank_status
= PIPE_VBLANK_INTERRUPT_STATUS
;
966 irq_received
= iir
!= 0;
968 /* Can't rely on pipestat interrupt bit in iir as it might
969 * have been cleared after the pipestat interrupt was received.
970 * It doesn't set the bit in iir again, but it still produces
971 * interrupts (for non-MSI).
973 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
974 pipea_stats
= I915_READ(PIPEASTAT
);
975 pipeb_stats
= I915_READ(PIPEBSTAT
);
977 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
978 i915_handle_error(dev
, false);
981 * Clear the PIPE(A|B)STAT regs before the IIR
983 if (pipea_stats
& 0x8000ffff) {
984 if (pipea_stats
& PIPE_FIFO_UNDERRUN_STATUS
)
985 DRM_DEBUG_DRIVER("pipe a underrun\n");
986 I915_WRITE(PIPEASTAT
, pipea_stats
);
990 if (pipeb_stats
& 0x8000ffff) {
991 if (pipeb_stats
& PIPE_FIFO_UNDERRUN_STATUS
)
992 DRM_DEBUG_DRIVER("pipe b underrun\n");
993 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
996 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
1003 /* Consume port. Then clear IIR or we'll miss events */
1004 if ((I915_HAS_HOTPLUG(dev
)) &&
1005 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
1006 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1008 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1010 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
1011 queue_work(dev_priv
->wq
,
1012 &dev_priv
->hotplug_work
);
1014 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1015 I915_READ(PORT_HOTPLUG_STAT
);
1018 I915_WRITE(IIR
, iir
);
1019 new_iir
= I915_READ(IIR
); /* Flush posted writes */
1021 if (dev
->primary
->master
) {
1022 master_priv
= dev
->primary
->master
->driver_priv
;
1023 if (master_priv
->sarea_priv
)
1024 master_priv
->sarea_priv
->last_dispatch
=
1025 READ_BREADCRUMB(dev_priv
);
1028 if (iir
& I915_USER_INTERRUPT
)
1029 notify_ring(dev
, &dev_priv
->render_ring
);
1030 if (HAS_BSD(dev
) && (iir
& I915_BSD_USER_INTERRUPT
))
1031 notify_ring(dev
, &dev_priv
->bsd_ring
);
1033 if (iir
& I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
) {
1034 intel_prepare_page_flip(dev
, 0);
1035 if (dev_priv
->flip_pending_is_done
)
1036 intel_finish_page_flip_plane(dev
, 0);
1039 if (iir
& I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
) {
1040 intel_prepare_page_flip(dev
, 1);
1041 if (dev_priv
->flip_pending_is_done
)
1042 intel_finish_page_flip_plane(dev
, 1);
1045 if (pipea_stats
& vblank_status
) {
1047 drm_handle_vblank(dev
, 0);
1048 if (!dev_priv
->flip_pending_is_done
) {
1049 i915_pageflip_stall_check(dev
, 0);
1050 intel_finish_page_flip(dev
, 0);
1054 if (pipeb_stats
& vblank_status
) {
1056 drm_handle_vblank(dev
, 1);
1057 if (!dev_priv
->flip_pending_is_done
) {
1058 i915_pageflip_stall_check(dev
, 1);
1059 intel_finish_page_flip(dev
, 1);
1063 if ((pipea_stats
& PIPE_LEGACY_BLC_EVENT_STATUS
) ||
1064 (pipeb_stats
& PIPE_LEGACY_BLC_EVENT_STATUS
) ||
1065 (iir
& I915_ASLE_INTERRUPT
))
1066 intel_opregion_asle_intr(dev
);
1068 /* With MSI, interrupts are only generated when iir
1069 * transitions from zero to nonzero. If another bit got
1070 * set while we were handling the existing iir bits, then
1071 * we would never get another interrupt.
1073 * This is fine on non-MSI as well, as if we hit this path
1074 * we avoid exiting the interrupt handler only to generate
1077 * Note that for MSI this could cause a stray interrupt report
1078 * if an interrupt landed in the time between writing IIR and
1079 * the posting read. This should be rare enough to never
1080 * trigger the 99% of 100,000 interrupts test for disabling
1089 static int i915_emit_irq(struct drm_device
* dev
)
1091 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1092 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1094 i915_kernel_lost_context(dev
);
1096 DRM_DEBUG_DRIVER("\n");
1098 dev_priv
->counter
++;
1099 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
1100 dev_priv
->counter
= 1;
1101 if (master_priv
->sarea_priv
)
1102 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
1105 OUT_RING(MI_STORE_DWORD_INDEX
);
1106 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1107 OUT_RING(dev_priv
->counter
);
1108 OUT_RING(MI_USER_INTERRUPT
);
1111 return dev_priv
->counter
;
1114 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
)
1116 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1117 struct intel_ring_buffer
*render_ring
= &dev_priv
->render_ring
;
1119 if (dev_priv
->trace_irq_seqno
== 0)
1120 render_ring
->user_irq_get(render_ring
);
1122 dev_priv
->trace_irq_seqno
= seqno
;
1125 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
1127 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1128 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1130 struct intel_ring_buffer
*render_ring
= &dev_priv
->render_ring
;
1132 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr
,
1133 READ_BREADCRUMB(dev_priv
));
1135 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
1136 if (master_priv
->sarea_priv
)
1137 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
1141 if (master_priv
->sarea_priv
)
1142 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1144 render_ring
->user_irq_get(render_ring
);
1145 DRM_WAIT_ON(ret
, dev_priv
->render_ring
.irq_queue
, 3 * DRM_HZ
,
1146 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
1147 render_ring
->user_irq_put(render_ring
);
1149 if (ret
== -EBUSY
) {
1150 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1151 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
1157 /* Needs the lock as it touches the ring.
1159 int i915_irq_emit(struct drm_device
*dev
, void *data
,
1160 struct drm_file
*file_priv
)
1162 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1163 drm_i915_irq_emit_t
*emit
= data
;
1166 if (!dev_priv
|| !dev_priv
->render_ring
.virtual_start
) {
1167 DRM_ERROR("called with no initialization\n");
1171 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1173 mutex_lock(&dev
->struct_mutex
);
1174 result
= i915_emit_irq(dev
);
1175 mutex_unlock(&dev
->struct_mutex
);
1177 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
1178 DRM_ERROR("copy_to_user\n");
1185 /* Doesn't need the hardware lock.
1187 int i915_irq_wait(struct drm_device
*dev
, void *data
,
1188 struct drm_file
*file_priv
)
1190 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1191 drm_i915_irq_wait_t
*irqwait
= data
;
1194 DRM_ERROR("called with no initialization\n");
1198 return i915_wait_irq(dev
, irqwait
->irq_seq
);
1201 /* Called from drm generic code, passed 'crtc' which
1202 * we use as a pipe index
1204 int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1206 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1207 unsigned long irqflags
;
1209 if (!i915_pipe_enabled(dev
, pipe
))
1212 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
1213 if (HAS_PCH_SPLIT(dev
))
1214 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1215 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1216 else if (INTEL_INFO(dev
)->gen
>= 4)
1217 i915_enable_pipestat(dev_priv
, pipe
,
1218 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1220 i915_enable_pipestat(dev_priv
, pipe
,
1221 PIPE_VBLANK_INTERRUPT_ENABLE
);
1222 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
1226 /* Called from drm generic code, passed 'crtc' which
1227 * we use as a pipe index
1229 void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1231 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1232 unsigned long irqflags
;
1234 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
1235 if (HAS_PCH_SPLIT(dev
))
1236 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1237 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1239 i915_disable_pipestat(dev_priv
, pipe
,
1240 PIPE_VBLANK_INTERRUPT_ENABLE
|
1241 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1242 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
1245 void i915_enable_interrupt (struct drm_device
*dev
)
1247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1249 if (!HAS_PCH_SPLIT(dev
))
1250 intel_opregion_enable_asle(dev
);
1251 dev_priv
->irq_enabled
= 1;
1255 /* Set the vblank monitor pipe
1257 int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
1258 struct drm_file
*file_priv
)
1260 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1263 DRM_ERROR("called with no initialization\n");
1270 int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
1271 struct drm_file
*file_priv
)
1273 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1274 drm_i915_vblank_pipe_t
*pipe
= data
;
1277 DRM_ERROR("called with no initialization\n");
1281 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
1287 * Schedule buffer swap at given vertical blank.
1289 int i915_vblank_swap(struct drm_device
*dev
, void *data
,
1290 struct drm_file
*file_priv
)
1292 /* The delayed swap mechanism was fundamentally racy, and has been
1293 * removed. The model was that the client requested a delayed flip/swap
1294 * from the kernel, then waited for vblank before continuing to perform
1295 * rendering. The problem was that the kernel might wake the client
1296 * up before it dispatched the vblank swap (since the lock has to be
1297 * held while touching the ringbuffer), in which case the client would
1298 * clear and start the next frame before the swap occurred, and
1299 * flicker would occur in addition to likely missing the vblank.
1301 * In the absence of this ioctl, userland falls back to a correct path
1302 * of waiting for a vblank, then dispatching the swap on its own.
1303 * Context switching to userland and back is plenty fast enough for
1304 * meeting the requirements of vblank swapping.
1309 static struct drm_i915_gem_request
*
1310 i915_get_tail_request(struct drm_device
*dev
)
1312 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1313 return list_entry(dev_priv
->render_ring
.request_list
.prev
,
1314 struct drm_i915_gem_request
, list
);
1318 * This is called when the chip hasn't reported back with completed
1319 * batchbuffers in a long time. The first time this is called we simply record
1320 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1321 * again, we assume the chip is wedged and try to fix it.
1323 void i915_hangcheck_elapsed(unsigned long data
)
1325 struct drm_device
*dev
= (struct drm_device
*)data
;
1326 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1327 uint32_t acthd
, instdone
, instdone1
;
1329 if (INTEL_INFO(dev
)->gen
< 4) {
1330 acthd
= I915_READ(ACTHD
);
1331 instdone
= I915_READ(INSTDONE
);
1334 acthd
= I915_READ(ACTHD_I965
);
1335 instdone
= I915_READ(INSTDONE_I965
);
1336 instdone1
= I915_READ(INSTDONE1
);
1339 /* If all work is done then ACTHD clearly hasn't advanced. */
1340 if (list_empty(&dev_priv
->render_ring
.request_list
) ||
1341 i915_seqno_passed(dev_priv
->render_ring
.get_seqno(&dev_priv
->render_ring
),
1342 i915_get_tail_request(dev
)->seqno
)) {
1343 bool missed_wakeup
= false;
1345 dev_priv
->hangcheck_count
= 0;
1347 /* Issue a wake-up to catch stuck h/w. */
1348 if (dev_priv
->render_ring
.waiting_gem_seqno
&&
1349 waitqueue_active(&dev_priv
->render_ring
.irq_queue
)) {
1350 wake_up_all(&dev_priv
->render_ring
.irq_queue
);
1351 missed_wakeup
= true;
1354 if (dev_priv
->bsd_ring
.waiting_gem_seqno
&&
1355 waitqueue_active(&dev_priv
->bsd_ring
.irq_queue
)) {
1356 wake_up_all(&dev_priv
->bsd_ring
.irq_queue
);
1357 missed_wakeup
= true;
1360 if (dev_priv
->blt_ring
.waiting_gem_seqno
&&
1361 waitqueue_active(&dev_priv
->blt_ring
.irq_queue
)) {
1362 wake_up_all(&dev_priv
->blt_ring
.irq_queue
);
1363 missed_wakeup
= true;
1367 DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1371 if (dev_priv
->last_acthd
== acthd
&&
1372 dev_priv
->last_instdone
== instdone
&&
1373 dev_priv
->last_instdone1
== instdone1
) {
1374 if (dev_priv
->hangcheck_count
++ > 1) {
1375 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1377 if (!IS_GEN2(dev
)) {
1378 /* Is the chip hanging on a WAIT_FOR_EVENT?
1379 * If so we can simply poke the RB_WAIT bit
1380 * and break the hang. This should work on
1381 * all but the second generation chipsets.
1383 u32 tmp
= I915_READ(PRB0_CTL
);
1384 if (tmp
& RING_WAIT
) {
1385 I915_WRITE(PRB0_CTL
, tmp
);
1386 POSTING_READ(PRB0_CTL
);
1391 i915_handle_error(dev
, true);
1395 dev_priv
->hangcheck_count
= 0;
1397 dev_priv
->last_acthd
= acthd
;
1398 dev_priv
->last_instdone
= instdone
;
1399 dev_priv
->last_instdone1
= instdone1
;
1403 /* Reset timer case chip hangs without another request being added */
1404 mod_timer(&dev_priv
->hangcheck_timer
,
1405 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1410 static void ironlake_irq_preinstall(struct drm_device
*dev
)
1412 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1414 I915_WRITE(HWSTAM
, 0xeffe);
1416 /* XXX hotplug from PCH */
1418 I915_WRITE(DEIMR
, 0xffffffff);
1419 I915_WRITE(DEIER
, 0x0);
1420 (void) I915_READ(DEIER
);
1423 I915_WRITE(GTIMR
, 0xffffffff);
1424 I915_WRITE(GTIER
, 0x0);
1425 (void) I915_READ(GTIER
);
1427 /* south display irq */
1428 I915_WRITE(SDEIMR
, 0xffffffff);
1429 I915_WRITE(SDEIER
, 0x0);
1430 (void) I915_READ(SDEIER
);
1433 static int ironlake_irq_postinstall(struct drm_device
*dev
)
1435 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1436 /* enable kind of interrupts always enabled */
1437 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
1438 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
;
1439 u32 render_mask
= GT_PIPE_NOTIFY
| GT_BSD_USER_INTERRUPT
;
1442 dev_priv
->irq_mask_reg
= ~display_mask
;
1443 dev_priv
->de_irq_enable_reg
= display_mask
| DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
;
1445 /* should always can generate irq */
1446 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1447 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
1448 I915_WRITE(DEIER
, dev_priv
->de_irq_enable_reg
);
1449 (void) I915_READ(DEIER
);
1454 GT_GEN6_BSD_USER_INTERRUPT
|
1455 GT_BLT_USER_INTERRUPT
;
1458 dev_priv
->gt_irq_mask_reg
= ~render_mask
;
1459 dev_priv
->gt_irq_enable_reg
= render_mask
;
1461 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1462 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
1464 I915_WRITE(GEN6_RENDER_IMR
, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT
);
1465 I915_WRITE(GEN6_BSD_IMR
, ~GEN6_BSD_IMR_USER_INTERRUPT
);
1466 I915_WRITE(GEN6_BLITTER_IMR
, ~GEN6_BLITTER_USER_INTERRUPT
);
1469 I915_WRITE(GTIER
, dev_priv
->gt_irq_enable_reg
);
1470 (void) I915_READ(GTIER
);
1472 if (HAS_PCH_CPT(dev
)) {
1473 hotplug_mask
= SDE_CRT_HOTPLUG_CPT
| SDE_PORTB_HOTPLUG_CPT
|
1474 SDE_PORTC_HOTPLUG_CPT
| SDE_PORTD_HOTPLUG_CPT
;
1476 hotplug_mask
= SDE_CRT_HOTPLUG
| SDE_PORTB_HOTPLUG
|
1477 SDE_PORTC_HOTPLUG
| SDE_PORTD_HOTPLUG
;
1480 dev_priv
->pch_irq_mask_reg
= ~hotplug_mask
;
1481 dev_priv
->pch_irq_enable_reg
= hotplug_mask
;
1483 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1484 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask_reg
);
1485 I915_WRITE(SDEIER
, dev_priv
->pch_irq_enable_reg
);
1486 (void) I915_READ(SDEIER
);
1488 if (IS_IRONLAKE_M(dev
)) {
1489 /* Clear & enable PCU event interrupts */
1490 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
1491 I915_WRITE(DEIER
, I915_READ(DEIER
) | DE_PCU_EVENT
);
1492 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
1498 void i915_driver_irq_preinstall(struct drm_device
* dev
)
1500 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1502 atomic_set(&dev_priv
->irq_received
, 0);
1504 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
1505 INIT_WORK(&dev_priv
->error_work
, i915_error_work_func
);
1507 if (HAS_PCH_SPLIT(dev
)) {
1508 ironlake_irq_preinstall(dev
);
1512 if (I915_HAS_HOTPLUG(dev
)) {
1513 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1514 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1517 I915_WRITE(HWSTAM
, 0xeffe);
1518 I915_WRITE(PIPEASTAT
, 0);
1519 I915_WRITE(PIPEBSTAT
, 0);
1520 I915_WRITE(IMR
, 0xffffffff);
1521 I915_WRITE(IER
, 0x0);
1522 (void) I915_READ(IER
);
1526 * Must be called after intel_modeset_init or hotplug interrupts won't be
1527 * enabled correctly.
1529 int i915_driver_irq_postinstall(struct drm_device
*dev
)
1531 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1532 u32 enable_mask
= I915_INTERRUPT_ENABLE_FIX
| I915_INTERRUPT_ENABLE_VAR
;
1535 DRM_INIT_WAITQUEUE(&dev_priv
->render_ring
.irq_queue
);
1537 DRM_INIT_WAITQUEUE(&dev_priv
->bsd_ring
.irq_queue
);
1539 DRM_INIT_WAITQUEUE(&dev_priv
->blt_ring
.irq_queue
);
1541 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
1543 if (HAS_PCH_SPLIT(dev
))
1544 return ironlake_irq_postinstall(dev
);
1546 /* Unmask the interrupts that we always want on. */
1547 dev_priv
->irq_mask_reg
= ~I915_INTERRUPT_ENABLE_FIX
;
1549 dev_priv
->pipestat
[0] = 0;
1550 dev_priv
->pipestat
[1] = 0;
1552 if (I915_HAS_HOTPLUG(dev
)) {
1553 /* Enable in IER... */
1554 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
1555 /* and unmask in IMR */
1556 dev_priv
->irq_mask_reg
&= ~I915_DISPLAY_PORT_INTERRUPT
;
1560 * Enable some error detection, note the instruction error mask
1561 * bit is reserved, so we leave it masked.
1564 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
1565 GM45_ERROR_MEM_PRIV
|
1566 GM45_ERROR_CP_PRIV
|
1567 I915_ERROR_MEMORY_REFRESH
);
1569 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
1570 I915_ERROR_MEMORY_REFRESH
);
1572 I915_WRITE(EMR
, error_mask
);
1574 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
1575 I915_WRITE(IER
, enable_mask
);
1576 (void) I915_READ(IER
);
1578 if (I915_HAS_HOTPLUG(dev
)) {
1579 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
1581 /* Note HDMI and DP share bits */
1582 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
1583 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
1584 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
1585 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
1586 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
1587 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
1588 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS
)
1589 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
1590 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS
)
1591 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
1592 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
1593 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
1595 /* Programming the CRT detection parameters tends
1596 to generate a spurious hotplug event about three
1597 seconds later. So just do it once.
1600 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
1601 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
1604 /* Ignore TV since it's buggy */
1606 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
1609 intel_opregion_enable_asle(dev
);
1614 static void ironlake_irq_uninstall(struct drm_device
*dev
)
1616 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1617 I915_WRITE(HWSTAM
, 0xffffffff);
1619 I915_WRITE(DEIMR
, 0xffffffff);
1620 I915_WRITE(DEIER
, 0x0);
1621 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1623 I915_WRITE(GTIMR
, 0xffffffff);
1624 I915_WRITE(GTIER
, 0x0);
1625 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1628 void i915_driver_irq_uninstall(struct drm_device
* dev
)
1630 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1635 dev_priv
->vblank_pipe
= 0;
1637 if (HAS_PCH_SPLIT(dev
)) {
1638 ironlake_irq_uninstall(dev
);
1642 if (I915_HAS_HOTPLUG(dev
)) {
1643 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1644 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1647 I915_WRITE(HWSTAM
, 0xffffffff);
1648 I915_WRITE(PIPEASTAT
, 0);
1649 I915_WRITE(PIPEBSTAT
, 0);
1650 I915_WRITE(IMR
, 0xffffffff);
1651 I915_WRITE(IER
, 0x0);
1653 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
1654 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
1655 I915_WRITE(IIR
, I915_READ(IIR
));