2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
17 #include <asm/mach/map.h>
19 #include <mach/dm644x.h>
20 #include <mach/cputype.h>
21 #include <mach/edma.h>
22 #include <mach/irqs.h>
25 #include <mach/time.h>
26 #include <mach/serial.h>
27 #include <mach/common.h>
34 * Device specific clocks
36 #define DM644X_REF_FREQ 27000000
38 static struct pll_data pll1_data
= {
40 .phys_base
= DAVINCI_PLL1_BASE
,
43 static struct pll_data pll2_data
= {
45 .phys_base
= DAVINCI_PLL2_BASE
,
48 static struct clk ref_clk
= {
50 .rate
= DM644X_REF_FREQ
,
53 static struct clk pll1_clk
= {
56 .pll_data
= &pll1_data
,
60 static struct clk pll1_sysclk1
= {
61 .name
= "pll1_sysclk1",
67 static struct clk pll1_sysclk2
= {
68 .name
= "pll1_sysclk2",
74 static struct clk pll1_sysclk3
= {
75 .name
= "pll1_sysclk3",
81 static struct clk pll1_sysclk5
= {
82 .name
= "pll1_sysclk5",
88 static struct clk pll1_aux_clk
= {
89 .name
= "pll1_aux_clk",
91 .flags
= CLK_PLL
| PRE_PLL
,
94 static struct clk pll1_sysclkbp
= {
95 .name
= "pll1_sysclkbp",
97 .flags
= CLK_PLL
| PRE_PLL
,
101 static struct clk pll2_clk
= {
104 .pll_data
= &pll2_data
,
108 static struct clk pll2_sysclk1
= {
109 .name
= "pll2_sysclk1",
115 static struct clk pll2_sysclk2
= {
116 .name
= "pll2_sysclk2",
122 static struct clk pll2_sysclkbp
= {
123 .name
= "pll2_sysclkbp",
125 .flags
= CLK_PLL
| PRE_PLL
,
129 static struct clk dsp_clk
= {
131 .parent
= &pll1_sysclk1
,
132 .lpsc
= DAVINCI_LPSC_GEM
,
134 .usecount
= 1, /* REVISIT how to disable? */
137 static struct clk arm_clk
= {
139 .parent
= &pll1_sysclk2
,
140 .lpsc
= DAVINCI_LPSC_ARM
,
141 .flags
= ALWAYS_ENABLED
,
144 static struct clk vicp_clk
= {
146 .parent
= &pll1_sysclk2
,
147 .lpsc
= DAVINCI_LPSC_IMCOP
,
149 .usecount
= 1, /* REVISIT how to disable? */
152 static struct clk vpss_master_clk
= {
153 .name
= "vpss_master",
154 .parent
= &pll1_sysclk3
,
155 .lpsc
= DAVINCI_LPSC_VPSSMSTR
,
159 static struct clk vpss_slave_clk
= {
160 .name
= "vpss_slave",
161 .parent
= &pll1_sysclk3
,
162 .lpsc
= DAVINCI_LPSC_VPSSSLV
,
165 static struct clk uart0_clk
= {
167 .parent
= &pll1_aux_clk
,
168 .lpsc
= DAVINCI_LPSC_UART0
,
171 static struct clk uart1_clk
= {
173 .parent
= &pll1_aux_clk
,
174 .lpsc
= DAVINCI_LPSC_UART1
,
177 static struct clk uart2_clk
= {
179 .parent
= &pll1_aux_clk
,
180 .lpsc
= DAVINCI_LPSC_UART2
,
183 static struct clk emac_clk
= {
185 .parent
= &pll1_sysclk5
,
186 .lpsc
= DAVINCI_LPSC_EMAC_WRAPPER
,
189 static struct clk i2c_clk
= {
191 .parent
= &pll1_aux_clk
,
192 .lpsc
= DAVINCI_LPSC_I2C
,
195 static struct clk ide_clk
= {
197 .parent
= &pll1_sysclk5
,
198 .lpsc
= DAVINCI_LPSC_ATA
,
201 static struct clk asp_clk
= {
203 .parent
= &pll1_sysclk5
,
204 .lpsc
= DAVINCI_LPSC_McBSP
,
207 static struct clk mmcsd_clk
= {
209 .parent
= &pll1_sysclk5
,
210 .lpsc
= DAVINCI_LPSC_MMC_SD
,
213 static struct clk spi_clk
= {
215 .parent
= &pll1_sysclk5
,
216 .lpsc
= DAVINCI_LPSC_SPI
,
219 static struct clk gpio_clk
= {
221 .parent
= &pll1_sysclk5
,
222 .lpsc
= DAVINCI_LPSC_GPIO
,
225 static struct clk usb_clk
= {
227 .parent
= &pll1_sysclk5
,
228 .lpsc
= DAVINCI_LPSC_USB
,
231 static struct clk vlynq_clk
= {
233 .parent
= &pll1_sysclk5
,
234 .lpsc
= DAVINCI_LPSC_VLYNQ
,
237 static struct clk aemif_clk
= {
239 .parent
= &pll1_sysclk5
,
240 .lpsc
= DAVINCI_LPSC_AEMIF
,
243 static struct clk pwm0_clk
= {
245 .parent
= &pll1_aux_clk
,
246 .lpsc
= DAVINCI_LPSC_PWM0
,
249 static struct clk pwm1_clk
= {
251 .parent
= &pll1_aux_clk
,
252 .lpsc
= DAVINCI_LPSC_PWM1
,
255 static struct clk pwm2_clk
= {
257 .parent
= &pll1_aux_clk
,
258 .lpsc
= DAVINCI_LPSC_PWM2
,
261 static struct clk timer0_clk
= {
263 .parent
= &pll1_aux_clk
,
264 .lpsc
= DAVINCI_LPSC_TIMER0
,
267 static struct clk timer1_clk
= {
269 .parent
= &pll1_aux_clk
,
270 .lpsc
= DAVINCI_LPSC_TIMER1
,
273 static struct clk timer2_clk
= {
275 .parent
= &pll1_aux_clk
,
276 .lpsc
= DAVINCI_LPSC_TIMER2
,
277 .usecount
= 1, /* REVISIT: why cant' this be disabled? */
280 static struct clk_lookup dm644x_clks
[] = {
281 CLK(NULL
, "ref", &ref_clk
),
282 CLK(NULL
, "pll1", &pll1_clk
),
283 CLK(NULL
, "pll1_sysclk1", &pll1_sysclk1
),
284 CLK(NULL
, "pll1_sysclk2", &pll1_sysclk2
),
285 CLK(NULL
, "pll1_sysclk3", &pll1_sysclk3
),
286 CLK(NULL
, "pll1_sysclk5", &pll1_sysclk5
),
287 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
288 CLK(NULL
, "pll1_sysclkbp", &pll1_sysclkbp
),
289 CLK(NULL
, "pll2", &pll2_clk
),
290 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
291 CLK(NULL
, "pll2_sysclk2", &pll2_sysclk2
),
292 CLK(NULL
, "pll2_sysclkbp", &pll2_sysclkbp
),
293 CLK(NULL
, "dsp", &dsp_clk
),
294 CLK(NULL
, "arm", &arm_clk
),
295 CLK(NULL
, "vicp", &vicp_clk
),
296 CLK(NULL
, "vpss_master", &vpss_master_clk
),
297 CLK(NULL
, "vpss_slave", &vpss_slave_clk
),
298 CLK(NULL
, "arm", &arm_clk
),
299 CLK(NULL
, "uart0", &uart0_clk
),
300 CLK(NULL
, "uart1", &uart1_clk
),
301 CLK(NULL
, "uart2", &uart2_clk
),
302 CLK("davinci_emac.1", NULL
, &emac_clk
),
303 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
304 CLK("palm_bk3710", NULL
, &ide_clk
),
305 CLK("davinci-asp", NULL
, &asp_clk
),
306 CLK("davinci_mmc.0", NULL
, &mmcsd_clk
),
307 CLK(NULL
, "spi", &spi_clk
),
308 CLK(NULL
, "gpio", &gpio_clk
),
309 CLK(NULL
, "usb", &usb_clk
),
310 CLK(NULL
, "vlynq", &vlynq_clk
),
311 CLK(NULL
, "aemif", &aemif_clk
),
312 CLK(NULL
, "pwm0", &pwm0_clk
),
313 CLK(NULL
, "pwm1", &pwm1_clk
),
314 CLK(NULL
, "pwm2", &pwm2_clk
),
315 CLK(NULL
, "timer0", &timer0_clk
),
316 CLK(NULL
, "timer1", &timer1_clk
),
317 CLK("watchdog", NULL
, &timer2_clk
),
318 CLK(NULL
, NULL
, NULL
),
321 static struct emac_platform_data dm644x_emac_pdata
= {
322 .ctrl_reg_offset
= DM644X_EMAC_CNTRL_OFFSET
,
323 .ctrl_mod_reg_offset
= DM644X_EMAC_CNTRL_MOD_OFFSET
,
324 .ctrl_ram_offset
= DM644X_EMAC_CNTRL_RAM_OFFSET
,
325 .ctrl_ram_size
= DM644X_EMAC_CNTRL_RAM_SIZE
,
326 .version
= EMAC_VERSION_1
,
329 static struct resource dm644x_emac_resources
[] = {
331 .start
= DM644X_EMAC_BASE
,
332 .end
= DM644X_EMAC_BASE
+ SZ_16K
- 1,
333 .flags
= IORESOURCE_MEM
,
336 .start
= IRQ_EMACINT
,
338 .flags
= IORESOURCE_IRQ
,
342 static struct platform_device dm644x_emac_device
= {
343 .name
= "davinci_emac",
346 .platform_data
= &dm644x_emac_pdata
,
348 .num_resources
= ARRAY_SIZE(dm644x_emac_resources
),
349 .resource
= dm644x_emac_resources
,
352 static struct resource dm644x_mdio_resources
[] = {
354 .start
= DM644X_EMAC_MDIO_BASE
,
355 .end
= DM644X_EMAC_MDIO_BASE
+ SZ_4K
- 1,
356 .flags
= IORESOURCE_MEM
,
360 static struct platform_device dm644x_mdio_device
= {
361 .name
= "davinci_mdio",
363 .num_resources
= ARRAY_SIZE(dm644x_mdio_resources
),
364 .resource
= dm644x_mdio_resources
,
368 * Device specific mux setup
370 * soc description mux mode mode mux dbg
371 * reg offset mask mode
373 static const struct mux_config dm644x_pins
[] = {
374 #ifdef CONFIG_DAVINCI_MUX
375 MUX_CFG(DM644X
, HDIREN
, 0, 16, 1, 1, true)
376 MUX_CFG(DM644X
, ATAEN
, 0, 17, 1, 1, true)
377 MUX_CFG(DM644X
, ATAEN_DISABLE
, 0, 17, 1, 0, true)
379 MUX_CFG(DM644X
, HPIEN_DISABLE
, 0, 29, 1, 0, true)
381 MUX_CFG(DM644X
, AEAW
, 0, 0, 31, 31, true)
382 MUX_CFG(DM644X
, AEAW0
, 0, 0, 1, 0, true)
383 MUX_CFG(DM644X
, AEAW1
, 0, 1, 1, 0, true)
384 MUX_CFG(DM644X
, AEAW2
, 0, 2, 1, 0, true)
385 MUX_CFG(DM644X
, AEAW3
, 0, 3, 1, 0, true)
386 MUX_CFG(DM644X
, AEAW4
, 0, 4, 1, 0, true)
388 MUX_CFG(DM644X
, MSTK
, 1, 9, 1, 0, false)
390 MUX_CFG(DM644X
, I2C
, 1, 7, 1, 1, false)
392 MUX_CFG(DM644X
, MCBSP
, 1, 10, 1, 1, false)
394 MUX_CFG(DM644X
, UART1
, 1, 1, 1, 1, true)
395 MUX_CFG(DM644X
, UART2
, 1, 2, 1, 1, true)
397 MUX_CFG(DM644X
, PWM0
, 1, 4, 1, 1, false)
399 MUX_CFG(DM644X
, PWM1
, 1, 5, 1, 1, false)
401 MUX_CFG(DM644X
, PWM2
, 1, 6, 1, 1, false)
403 MUX_CFG(DM644X
, VLYNQEN
, 0, 15, 1, 1, false)
404 MUX_CFG(DM644X
, VLSCREN
, 0, 14, 1, 1, false)
405 MUX_CFG(DM644X
, VLYNQWD
, 0, 12, 3, 3, false)
407 MUX_CFG(DM644X
, EMACEN
, 0, 31, 1, 1, true)
409 MUX_CFG(DM644X
, GPIO3V
, 0, 31, 1, 0, true)
411 MUX_CFG(DM644X
, GPIO0
, 0, 24, 1, 0, true)
412 MUX_CFG(DM644X
, GPIO3
, 0, 25, 1, 0, false)
413 MUX_CFG(DM644X
, GPIO43_44
, 1, 7, 1, 0, false)
414 MUX_CFG(DM644X
, GPIO46_47
, 0, 22, 1, 0, true)
416 MUX_CFG(DM644X
, RGB666
, 0, 22, 1, 1, true)
418 MUX_CFG(DM644X
, LOEEN
, 0, 24, 1, 1, true)
419 MUX_CFG(DM644X
, LFLDEN
, 0, 25, 1, 1, false)
423 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
424 static u8 dm644x_default_priorities
[DAVINCI_N_AINTC_IRQ
] = {
441 [IRQ_CCINT0
] = 5, /* dma */
442 [IRQ_CCERRINT
] = 5, /* dma */
443 [IRQ_TCERRINT0
] = 5, /* dma */
444 [IRQ_TCERRINT
] = 5, /* dma */
457 [IRQ_TINT0_TINT12
] = 2, /* clockevent */
458 [IRQ_TINT0_TINT34
] = 2, /* clocksource */
459 [IRQ_TINT1_TINT12
] = 7, /* DSP timer */
460 [IRQ_TINT1_TINT34
] = 7, /* system tick */
491 /*----------------------------------------------------------------------*/
494 queue_tc_mapping
[][2] = {
495 /* {event queue no, TC no} */
502 queue_priority_mapping
[][2] = {
503 /* {event queue no, Priority} */
509 static struct edma_soc_info edma_cc0_info
= {
515 .queue_tc_mapping
= queue_tc_mapping
,
516 .queue_priority_mapping
= queue_priority_mapping
,
519 static struct edma_soc_info
*dm644x_edma_info
[EDMA_MAX_CC
] = {
523 static struct resource edma_resources
[] = {
527 .end
= 0x01c00000 + SZ_64K
- 1,
528 .flags
= IORESOURCE_MEM
,
533 .end
= 0x01c10000 + SZ_1K
- 1,
534 .flags
= IORESOURCE_MEM
,
539 .end
= 0x01c10400 + SZ_1K
- 1,
540 .flags
= IORESOURCE_MEM
,
545 .flags
= IORESOURCE_IRQ
,
549 .start
= IRQ_CCERRINT
,
550 .flags
= IORESOURCE_IRQ
,
552 /* not using TC*_ERR */
555 static struct platform_device dm644x_edma_device
= {
558 .dev
.platform_data
= dm644x_edma_info
,
559 .num_resources
= ARRAY_SIZE(edma_resources
),
560 .resource
= edma_resources
,
563 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
564 static struct resource dm644x_asp_resources
[] = {
566 .start
= DAVINCI_ASP0_BASE
,
567 .end
= DAVINCI_ASP0_BASE
+ SZ_8K
- 1,
568 .flags
= IORESOURCE_MEM
,
571 .start
= DAVINCI_DMA_ASP0_TX
,
572 .end
= DAVINCI_DMA_ASP0_TX
,
573 .flags
= IORESOURCE_DMA
,
576 .start
= DAVINCI_DMA_ASP0_RX
,
577 .end
= DAVINCI_DMA_ASP0_RX
,
578 .flags
= IORESOURCE_DMA
,
582 static struct platform_device dm644x_asp_device
= {
583 .name
= "davinci-asp",
585 .num_resources
= ARRAY_SIZE(dm644x_asp_resources
),
586 .resource
= dm644x_asp_resources
,
589 static struct resource dm644x_vpss_resources
[] = {
591 /* VPSS Base address */
594 .end
= 0x01c73400 + 0xff,
595 .flags
= IORESOURCE_MEM
,
599 static struct platform_device dm644x_vpss_device
= {
602 .dev
.platform_data
= "dm644x_vpss",
603 .num_resources
= ARRAY_SIZE(dm644x_vpss_resources
),
604 .resource
= dm644x_vpss_resources
,
607 static struct resource vpfe_resources
[] = {
611 .flags
= IORESOURCE_IRQ
,
616 .flags
= IORESOURCE_IRQ
,
620 static u64 vpfe_capture_dma_mask
= DMA_BIT_MASK(32);
621 static struct resource dm644x_ccdc_resource
[] = {
622 /* CCDC Base address */
625 .end
= 0x01c70400 + 0xff,
626 .flags
= IORESOURCE_MEM
,
630 static struct platform_device dm644x_ccdc_dev
= {
631 .name
= "dm644x_ccdc",
633 .num_resources
= ARRAY_SIZE(dm644x_ccdc_resource
),
634 .resource
= dm644x_ccdc_resource
,
636 .dma_mask
= &vpfe_capture_dma_mask
,
637 .coherent_dma_mask
= DMA_BIT_MASK(32),
641 static struct platform_device vpfe_capture_dev
= {
642 .name
= CAPTURE_DRV_NAME
,
644 .num_resources
= ARRAY_SIZE(vpfe_resources
),
645 .resource
= vpfe_resources
,
647 .dma_mask
= &vpfe_capture_dma_mask
,
648 .coherent_dma_mask
= DMA_BIT_MASK(32),
652 void dm644x_set_vpfe_config(struct vpfe_config
*cfg
)
654 vpfe_capture_dev
.dev
.platform_data
= cfg
;
657 /*----------------------------------------------------------------------*/
659 static struct map_desc dm644x_io_desc
[] = {
662 .pfn
= __phys_to_pfn(IO_PHYS
),
667 .virtual = SRAM_VIRT
,
668 .pfn
= __phys_to_pfn(0x00008000),
670 /* MT_MEMORY_NONCACHED requires supersection alignment */
675 /* Contents of JTAG ID register used to identify exact cpu type */
676 static struct davinci_id dm644x_ids
[] = {
680 .manufacturer
= 0x017,
681 .cpu_id
= DAVINCI_CPU_ID_DM6446
,
687 .manufacturer
= 0x017,
688 .cpu_id
= DAVINCI_CPU_ID_DM6446
,
693 static u32 dm644x_psc_bases
[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE
};
696 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
697 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
698 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
699 * T1_TOP: Timer 1, top : <unused>
701 static struct davinci_timer_info dm644x_timer_info
= {
702 .timers
= davinci_timer_instance
,
703 .clockevent_id
= T0_BOT
,
704 .clocksource_id
= T0_TOP
,
707 static struct plat_serial8250_port dm644x_serial_platform_data
[] = {
709 .mapbase
= DAVINCI_UART0_BASE
,
711 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
717 .mapbase
= DAVINCI_UART1_BASE
,
719 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
725 .mapbase
= DAVINCI_UART2_BASE
,
727 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
737 static struct platform_device dm644x_serial_device
= {
738 .name
= "serial8250",
739 .id
= PLAT8250_DEV_PLATFORM
,
741 .platform_data
= dm644x_serial_platform_data
,
745 static struct davinci_soc_info davinci_soc_info_dm644x
= {
746 .io_desc
= dm644x_io_desc
,
747 .io_desc_num
= ARRAY_SIZE(dm644x_io_desc
),
748 .jtag_id_reg
= 0x01c40028,
750 .ids_num
= ARRAY_SIZE(dm644x_ids
),
751 .cpu_clks
= dm644x_clks
,
752 .psc_bases
= dm644x_psc_bases
,
753 .psc_bases_num
= ARRAY_SIZE(dm644x_psc_bases
),
754 .pinmux_base
= DAVINCI_SYSTEM_MODULE_BASE
,
755 .pinmux_pins
= dm644x_pins
,
756 .pinmux_pins_num
= ARRAY_SIZE(dm644x_pins
),
757 .intc_base
= DAVINCI_ARM_INTC_BASE
,
758 .intc_type
= DAVINCI_INTC_TYPE_AINTC
,
759 .intc_irq_prios
= dm644x_default_priorities
,
760 .intc_irq_num
= DAVINCI_N_AINTC_IRQ
,
761 .timer_info
= &dm644x_timer_info
,
762 .gpio_type
= GPIO_TYPE_DAVINCI
,
763 .gpio_base
= DAVINCI_GPIO_BASE
,
765 .gpio_irq
= IRQ_GPIOBNK0
,
766 .serial_dev
= &dm644x_serial_device
,
767 .emac_pdata
= &dm644x_emac_pdata
,
768 .sram_dma
= 0x00008000,
770 .reset_device
= &davinci_wdt_device
,
773 void __init
dm644x_init_asp(struct snd_platform_data
*pdata
)
775 davinci_cfg_reg(DM644X_MCBSP
);
776 dm644x_asp_device
.dev
.platform_data
= pdata
;
777 platform_device_register(&dm644x_asp_device
);
780 void __init
dm644x_init(void)
782 davinci_common_init(&davinci_soc_info_dm644x
);
785 static int __init
dm644x_init_devices(void)
787 if (!cpu_is_davinci_dm644x())
790 /* Add ccdc clock aliases */
791 clk_add_alias("master", dm644x_ccdc_dev
.name
, "vpss_master", NULL
);
792 clk_add_alias("slave", dm644x_ccdc_dev
.name
, "vpss_slave", NULL
);
793 platform_device_register(&dm644x_edma_device
);
795 platform_device_register(&dm644x_mdio_device
);
796 platform_device_register(&dm644x_emac_device
);
797 clk_add_alias(NULL
, dev_name(&dm644x_mdio_device
.dev
),
798 NULL
, &dm644x_emac_device
.dev
);
800 platform_device_register(&dm644x_vpss_device
);
801 platform_device_register(&dm644x_ccdc_dev
);
802 platform_device_register(&vpfe_capture_dev
);
806 postcore_initcall(dm644x_init_devices
);