arch/mips/pci/ops-au1000.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Alchemy/AMD Au1x00 PCI support.
   4  *
   5  * Copyright 2001-2003, 2007 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc.
   7  *              ppopov@mvista.com or source@mvista.com
   8  *
   9  *  Support for all devices (greater than 16) added by David Gathright.
  10  *
  11  *  This program is free software; you can redistribute  it and/or modify it
  12  *  under  the terms of  the GNU General  Public License as published by the
  13  *  Free Software Foundation;  either version 2 of the  License, or (at your
  14  *  option) any later version.
  15  *
  16  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  17  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  19  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  22  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  24  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  *  You should have received a copy of the  GNU General Public License along
  28  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  29  *  675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31 #include <linux/types.h>
  32 #include <linux/pci.h>
  33 #include <linux/kernel.h>
  34 #include <linux/init.h>
  35 #include <linux/vmalloc.h>
  36
  37 #include <asm/mach-au1x00/au1000.h>
  38
  39 #undef DEBUG
  40 #ifdef DEBUG
  41 #define DBG(x...) printk(x)
  42 #else
  43 #define DBG(x...)
  44 #endif
  45
  46 #define PCI_ACCESS_READ  0
  47 #define PCI_ACCESS_WRITE 1
  48
  49
  50 int (*board_pci_idsel)(unsigned int devsel, int assert);
  51
  52 void mod_wired_entry(int entry, unsigned long entrylo0,
  53                 unsigned long entrylo1, unsigned long entryhi,
  54                 unsigned long pagemask)
  55 {
  56         unsigned long old_pagemask;
  57         unsigned long old_ctx;
  58
  59         /* Save old context and create impossible VPN2 value */
  60         old_ctx = read_c0_entryhi() & 0xff;
  61         old_pagemask = read_c0_pagemask();
  62         write_c0_index(entry);
  63         write_c0_pagemask(pagemask);
  64         write_c0_entryhi(entryhi);
  65         write_c0_entrylo0(entrylo0);
  66         write_c0_entrylo1(entrylo1);
  67         tlb_write_indexed();
  68         write_c0_entryhi(old_ctx);
  69         write_c0_pagemask(old_pagemask);
  70 }
  71
  72 static struct vm_struct *pci_cfg_vm;
  73 static int pci_cfg_wired_entry;
  74 static unsigned long last_entryLo0, last_entryLo1;
  75
  76 /*
  77  * We can't ioremap the entire pci config space because it's too large.
  78  * Nor can we call ioremap dynamically because some device drivers use
  79  * the PCI config routines from within interrupt handlers and that
  80  * becomes a problem in get_vm_area().  We use one wired TLB to handle
  81  * all config accesses for all busses.
  82  */
  83 void __init au1x_pci_cfg_init(void)
  84 {
  85         /* Reserve a wired entry for PCI config accesses */
  86         pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
  87         if (!pci_cfg_vm)
  88                 panic(KERN_ERR "PCI unable to get vm area\n");
  89         pci_cfg_wired_entry = read_c0_wired();
  90         add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
  91         last_entryLo0 = last_entryLo1 = 0xffffffff;
  92 }
  93
  94 static int config_access(unsigned char access_type, struct pci_bus *bus,
  95                          unsigned int dev_fn, unsigned char where,
  96                          u32 * data)
  97 {
  98 #if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 )
  99         unsigned int device = PCI_SLOT(dev_fn);
 100         unsigned int function = PCI_FUNC(dev_fn);
 101         unsigned long offset, status;
 102         unsigned long cfg_base;
 103         unsigned long flags;
 104         int error = PCIBIOS_SUCCESSFUL;
 105         unsigned long entryLo0, entryLo1;
 106
 107         if (device > 19) {
 108                 *data = 0xffffffff;
 109                 return -1;
 110         }
 111
 112         local_irq_save(flags);
 113         au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
 114                         Au1500_PCI_STATCMD);
 115         au_sync_udelay(1);
 116
 117         /* Allow board vendors to implement their own off-chip idsel.
 118          * If it doesn't succeed, may as well bail out at this point.
 119          */
 120         if (board_pci_idsel) {
 121                 if (board_pci_idsel(device, 1) == 0) {
 122                         *data = 0xffffffff;
 123                         local_irq_restore(flags);
 124                         return -1;
 125                 }
 126         }
 127
 128         /* setup the config window */
 129         if (bus->number == 0) {
 130                 cfg_base = ((1<<device)<<11);
 131         } else {
 132                 cfg_base = 0x80000000 | (bus->number<<16) | (device<<11);
 133         }
 134
 135         /* setup the lower bits of the 36 bit address */
 136         offset = (function << 8) | (where & ~0x3);
 137         /* pick up any address that falls below the page mask */
 138         offset |= cfg_base & ~PAGE_MASK;
 139
 140         /* page boundary */
 141         cfg_base = cfg_base & PAGE_MASK;
 142
 143         /*
 144          * To improve performance, if the current device is the same as
 145          * the last device accessed, we don't touch the TLB.
 146          */
 147         entryLo0 = (6 << 26)  | (cfg_base >> 6) | (2 << 3) | 7;
 148         entryLo1 = (6 << 26)  | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
 149         if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
 150                 mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
 151                                 (unsigned long)pci_cfg_vm->addr, PM_4K);
 152                 last_entryLo0 = entryLo0;
 153                 last_entryLo1 = entryLo1;
 154         }
 155
 156         if (access_type == PCI_ACCESS_WRITE) {
 157                 au_writel(*data, (int)(pci_cfg_vm->addr + offset));
 158         } else {
 159                 *data = au_readl((int)(pci_cfg_vm->addr + offset));
 160         }
 161         au_sync_udelay(2);
 162
 163         DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n",
 164                         access_type, bus->number, device, where, *data, offset);
 165
 166         /* check master abort */
 167         status = au_readl(Au1500_PCI_STATCMD);
 168
 169         if (status & (1<<29)) {
 170                 *data = 0xffffffff;
 171                 error = -1;
 172                 DBG("Au1x Master Abort\n");
 173         } else if ((status >> 28) & 0xf) {
 174                 DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf));
 175
 176                 /* clear errors */
 177                 au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
 178
 179                 *data = 0xffffffff;
 180                 error = -1;
 181         }
 182
 183         /* Take away the idsel.
 184         */
 185         if (board_pci_idsel) {
 186                 (void)board_pci_idsel(device, 0);
 187         }
 188
 189         local_irq_restore(flags);
 190         return error;
 191 #endif
 192 }
 193
 194 static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 195                             int where, u8 * val)
 196 {
 197         u32 data;
 198         int ret;
 199
 200         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 201         if (where & 1)
 202                 data >>= 8;
 203         if (where & 2)
 204                 data >>= 16;
 205         *val = data & 0xff;
 206         return ret;
 207 }
 208
 209
 210 static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 211                             int where, u16 * val)
 212 {
 213         u32 data;
 214         int ret;
 215
 216         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 217         if (where & 2)
 218                 data >>= 16;
 219         *val = data & 0xffff;
 220         return ret;
 221 }
 222
 223 static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 224                              int where, u32 * val)
 225 {
 226         int ret;
 227
 228         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
 229         return ret;
 230 }
 231
 232 static int
 233 write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 234                   u8 val)
 235 {
 236         u32 data = 0;
 237
 238         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 239                 return -1;
 240
 241         data = (data & ~(0xff << ((where & 3) << 3))) |
 242             (val << ((where & 3) << 3));
 243
 244         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 245                 return -1;
 246
 247         return PCIBIOS_SUCCESSFUL;
 248 }
 249
 250 static int
 251 write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
 252                   u16 val)
 253 {
 254         u32 data = 0;
 255
 256         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 257                 return -1;
 258
 259         data = (data & ~(0xffff << ((where & 3) << 3))) |
 260             (val << ((where & 3) << 3));
 261
 262         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 263                 return -1;
 264
 265
 266         return PCIBIOS_SUCCESSFUL;
 267 }
 268
 269 static int
 270 write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
 271                    u32 val)
 272 {
 273         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 274                 return -1;
 275
 276         return PCIBIOS_SUCCESSFUL;
 277 }
 278
 279 static int config_read(struct pci_bus *bus, unsigned int devfn,
 280                        int where, int size, u32 * val)
 281 {
 282         switch (size) {
 283         case 1: {
 284                         u8 _val;
 285                         int rc = read_config_byte(bus, devfn, where, &_val);
 286                         *val = _val;
 287                         return rc;
 288                 }
 289        case 2: {
 290                         u16 _val;
 291                         int rc = read_config_word(bus, devfn, where, &_val);
 292                         *val = _val;
 293                         return rc;
 294                 }
 295         default:
 296                 return read_config_dword(bus, devfn, where, val);
 297         }
 298 }
 299
 300 static int config_write(struct pci_bus *bus, unsigned int devfn,
 301                         int where, int size, u32 val)
 302 {
 303         switch (size) {
 304         case 1:
 305                 return write_config_byte(bus, devfn, where, (u8) val);
 306         case 2:
 307                 return write_config_word(bus, devfn, where, (u16) val);
 308         default:
 309                 return write_config_dword(bus, devfn, where, val);
 310         }
 311 }
 312
 313
 314 struct pci_ops au1x_pci_ops = {
 315         config_read,
 316         config_write
 317 };