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spi: davinci: whitespace cleanup
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / spi / davinci_spi.c
blob2fa5bec807ce81320f374a026cafb0feac862a28
1 /*
2 * Copyright (C) 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/err.h>
26 #include <linux/clk.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/slab.h>
31
32 #include <mach/spi.h>
33 #include <mach/edma.h>
34
35 #define SPI_NO_RESOURCE ((resource_size_t)-1)
36
37 #define SPI_MAX_CHIPSELECT 2
38
39 #define CS_DEFAULT 0xFF
40
41 #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
42 #define DAVINCI_DMA_DATA_TYPE_S8 0x01
43 #define DAVINCI_DMA_DATA_TYPE_S16 0x02
44 #define DAVINCI_DMA_DATA_TYPE_S32 0x04
45
46 #define SPIFMT_PHASE_MASK BIT(16)
47 #define SPIFMT_POLARITY_MASK BIT(17)
48 #define SPIFMT_DISTIMER_MASK BIT(18)
49 #define SPIFMT_SHIFTDIR_MASK BIT(20)
50 #define SPIFMT_WAITENA_MASK BIT(21)
51 #define SPIFMT_PARITYENA_MASK BIT(22)
52 #define SPIFMT_ODD_PARITY_MASK BIT(23)
53 #define SPIFMT_WDELAY_MASK 0x3f000000u
54 #define SPIFMT_WDELAY_SHIFT 24
55 #define SPIFMT_CHARLEN_MASK 0x0000001Fu
56
57 /* SPIGCR1 */
58 #define SPIGCR1_SPIENA_MASK 0x01000000u
59
60 /* SPIPC0 */
61 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
62 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
63 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
64 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
65 #define SPIPC0_EN1FUN_MASK BIT(1)
66 #define SPIPC0_EN0FUN_MASK BIT(0)
67
68 #define SPIINT_MASKALL 0x0101035F
69 #define SPI_INTLVL_1 0x000001FFu
70 #define SPI_INTLVL_0 0x00000000u
71
72 /* SPIDAT1 */
73 #define SPIDAT1_CSHOLD_SHIFT 28
74 #define SPIDAT1_CSNR_SHIFT 16
75 #define SPIGCR1_CLKMOD_MASK BIT(1)
76 #define SPIGCR1_MASTER_MASK BIT(0)
77 #define SPIGCR1_LOOPBACK_MASK BIT(16)
78
79 /* SPIBUF */
80 #define SPIBUF_TXFULL_MASK BIT(29)
81 #define SPIBUF_RXEMPTY_MASK BIT(31)
82
83 /* Error Masks */
84 #define SPIFLG_DLEN_ERR_MASK BIT(0)
85 #define SPIFLG_TIMEOUT_MASK BIT(1)
86 #define SPIFLG_PARERR_MASK BIT(2)
87 #define SPIFLG_DESYNC_MASK BIT(3)
88 #define SPIFLG_BITERR_MASK BIT(4)
89 #define SPIFLG_OVRRUN_MASK BIT(6)
90 #define SPIFLG_RX_INTR_MASK BIT(8)
91 #define SPIFLG_TX_INTR_MASK BIT(9)
92 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
93 #define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \
94 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
95 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
96 | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \
97 | SPIFLG_TX_INTR_MASK \
98 | SPIFLG_BUF_INIT_ACTIVE_MASK)
99
100 #define SPIINT_DLEN_ERR_INTR BIT(0)
101 #define SPIINT_TIMEOUT_INTR BIT(1)
102 #define SPIINT_PARERR_INTR BIT(2)
103 #define SPIINT_DESYNC_INTR BIT(3)
104 #define SPIINT_BITERR_INTR BIT(4)
105 #define SPIINT_OVRRUN_INTR BIT(6)
106 #define SPIINT_RX_INTR BIT(8)
107 #define SPIINT_TX_INTR BIT(9)
108 #define SPIINT_DMA_REQ_EN BIT(16)
109 #define SPIINT_ENABLE_HIGHZ BIT(24)
110
111 #define SPI_T2CDELAY_SHIFT 16
112 #define SPI_C2TDELAY_SHIFT 24
113
114 /* SPI Controller registers */
115 #define SPIGCR0 0x00
116 #define SPIGCR1 0x04
117 #define SPIINT 0x08
118 #define SPILVL 0x0c
119 #define SPIFLG 0x10
120 #define SPIPC0 0x14
121 #define SPIPC1 0x18
122 #define SPIPC2 0x1c
123 #define SPIPC3 0x20
124 #define SPIPC4 0x24
125 #define SPIPC5 0x28
126 #define SPIPC6 0x2c
127 #define SPIPC7 0x30
128 #define SPIPC8 0x34
129 #define SPIDAT0 0x38
130 #define SPIDAT1 0x3c
131 #define SPIBUF 0x40
132 #define SPIEMU 0x44
133 #define SPIDELAY 0x48
134 #define SPIDEF 0x4c
135 #define SPIFMT0 0x50
136 #define SPIFMT1 0x54
137 #define SPIFMT2 0x58
138 #define SPIFMT3 0x5c
139 #define TGINTVEC0 0x60
140 #define TGINTVEC1 0x64
141
142 struct davinci_spi_slave {
143 u32 cmd_to_write;
144 u32 clk_ctrl_to_write;
145 u32 bytes_per_word;
146 u8 active_cs;
147 };
148
149 /* We have 2 DMA channels per CS, one for RX and one for TX */
150 struct davinci_spi_dma {
151 int dma_tx_channel;
152 int dma_rx_channel;
153 int dma_tx_sync_dev;
154 int dma_rx_sync_dev;
155 enum dma_event_q eventq;
156
157 struct completion dma_tx_completion;
158 struct completion dma_rx_completion;
159 };
160
161 /* SPI Controller driver's private data. */
162 struct davinci_spi {
163 struct spi_bitbang bitbang;
164 struct clk *clk;
165
166 u8 version;
167 resource_size_t pbase;
168 void __iomem *base;
169 size_t region_size;
170 u32 irq;
171 struct completion done;
172
173 const void *tx;
174 void *rx;
175 u8 *tmp_buf;
176 int count;
177 struct davinci_spi_dma *dma_channels;
178 struct davinci_spi_platform_data *pdata;
179
180 void (*get_rx)(u32 rx_data, struct davinci_spi *);
181 u32 (*get_tx)(struct davinci_spi *);
182
183 struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
184 };
185
186 static unsigned use_dma;
187
188 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
189 {
190 u8 *rx = davinci_spi->rx;
191
192 *rx++ = (u8)data;
193 davinci_spi->rx = rx;
194 }
195
196 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
197 {
198 u16 *rx = davinci_spi->rx;
199
200 *rx++ = (u16)data;
201 davinci_spi->rx = rx;
202 }
203
204 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
205 {
206 u32 data;
207 const u8 *tx = davinci_spi->tx;
208
209 data = *tx++;
210 davinci_spi->tx = tx;
211 return data;
212 }
213
214 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
215 {
216 u32 data;
217 const u16 *tx = davinci_spi->tx;
218
219 data = *tx++;
220 davinci_spi->tx = tx;
221 return data;
222 }
223
224 static inline void set_io_bits(void __iomem *addr, u32 bits)
225 {
226 u32 v = ioread32(addr);
227
228 v |= bits;
229 iowrite32(v, addr);
230 }
231
232 static inline void clear_io_bits(void __iomem *addr, u32 bits)
233 {
234 u32 v = ioread32(addr);
235
236 v &= ~bits;
237 iowrite32(v, addr);
238 }
239
240 static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
241 {
242 set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
243 }
244
245 static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
246 {
247 clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
248 }
249
250 static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
251 {
252 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
253
254 if (enable)
255 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
256 else
257 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
258 }
259
260 /*
261 * Interface to control the chip select signal
262 */
263 static void davinci_spi_chipselect(struct spi_device *spi, int value)
264 {
265 struct davinci_spi *davinci_spi;
266 struct davinci_spi_platform_data *pdata;
267 u32 data1_reg_val = 0;
268
269 davinci_spi = spi_master_get_devdata(spi->master);
270 pdata = davinci_spi->pdata;
271
272 /*
273 * Board specific chip select logic decides the polarity and cs
274 * line for the controller
275 */
276 if (value == BITBANG_CS_INACTIVE) {
277 set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
278
279 data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
280 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
281
282 while ((ioread32(davinci_spi->base + SPIBUF)
283 & SPIBUF_RXEMPTY_MASK) == 0)
284 cpu_relax();
285 }
286 }
287
288 /**
289 * davinci_spi_setup_transfer - This functions will determine transfer method
290 * @spi: spi device on which data transfer to be done
291 * @t: spi transfer in which transfer info is filled
292 *
293 * This function determines data transfer method (8/16/32 bit transfer).
294 * It will also set the SPI Clock Control register according to
295 * SPI slave device freq.
296 */
297 static int davinci_spi_setup_transfer(struct spi_device *spi,
298 struct spi_transfer *t)
299 {
300
301 struct davinci_spi *davinci_spi;
302 struct davinci_spi_platform_data *pdata;
303 u8 bits_per_word = 0;
304 u32 hz = 0, prescale = 0, clkspeed;
305
306 davinci_spi = spi_master_get_devdata(spi->master);
307 pdata = davinci_spi->pdata;
308
309 if (t) {
310 bits_per_word = t->bits_per_word;
311 hz = t->speed_hz;
312 }
313
314 /* if bits_per_word is not set then set it default */
315 if (!bits_per_word)
316 bits_per_word = spi->bits_per_word;
317
318 /*
319 * Assign function pointer to appropriate transfer method
320 * 8bit, 16bit or 32bit transfer
321 */
322 if (bits_per_word <= 8 && bits_per_word >= 2) {
323 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
324 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
325 davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
326 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
327 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
328 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
329 davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
330 } else
331 return -EINVAL;
332
333 if (!hz)
334 hz = spi->max_speed_hz;
335
336 clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
337 spi->chip_select);
338 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
339 spi->chip_select);
340
341 clkspeed = clk_get_rate(davinci_spi->clk);
342 if (hz > clkspeed / 2)
343 prescale = 1 << 8;
344 if (hz < clkspeed / 256)
345 prescale = 255 << 8;
346 if (!prescale)
347 prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
348
349 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
350 set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
351
352 return 0;
353 }
354
355 static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
356 {
357 struct spi_device *spi = (struct spi_device *)data;
358 struct davinci_spi *davinci_spi;
359 struct davinci_spi_dma *davinci_spi_dma;
360 struct davinci_spi_platform_data *pdata;
361
362 davinci_spi = spi_master_get_devdata(spi->master);
363 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
364 pdata = davinci_spi->pdata;
365
366 if (ch_status == DMA_COMPLETE)
367 edma_stop(davinci_spi_dma->dma_rx_channel);
368 else
369 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
370
371 complete(&davinci_spi_dma->dma_rx_completion);
372 /* We must disable the DMA RX request */
373 davinci_spi_set_dma_req(spi, 0);
374 }
375
376 static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
377 {
378 struct spi_device *spi = (struct spi_device *)data;
379 struct davinci_spi *davinci_spi;
380 struct davinci_spi_dma *davinci_spi_dma;
381 struct davinci_spi_platform_data *pdata;
382
383 davinci_spi = spi_master_get_devdata(spi->master);
384 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
385 pdata = davinci_spi->pdata;
386
387 if (ch_status == DMA_COMPLETE)
388 edma_stop(davinci_spi_dma->dma_tx_channel);
389 else
390 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
391
392 complete(&davinci_spi_dma->dma_tx_completion);
393 /* We must disable the DMA TX request */
394 davinci_spi_set_dma_req(spi, 0);
395 }
396
397 static int davinci_spi_request_dma(struct spi_device *spi)
398 {
399 struct davinci_spi *davinci_spi;
400 struct davinci_spi_dma *davinci_spi_dma;
401 struct davinci_spi_platform_data *pdata;
402 struct device *sdev;
403 int r;
404
405 davinci_spi = spi_master_get_devdata(spi->master);
406 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
407 pdata = davinci_spi->pdata;
408 sdev = davinci_spi->bitbang.master->dev.parent;
409
410 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
411 davinci_spi_dma_rx_callback, spi,
412 davinci_spi_dma->eventq);
413 if (r < 0) {
414 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
415 return -EAGAIN;
416 }
417 davinci_spi_dma->dma_rx_channel = r;
418 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
419 davinci_spi_dma_tx_callback, spi,
420 davinci_spi_dma->eventq);
421 if (r < 0) {
422 edma_free_channel(davinci_spi_dma->dma_rx_channel);
423 davinci_spi_dma->dma_rx_channel = -1;
424 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
425 return -EAGAIN;
426 }
427 davinci_spi_dma->dma_tx_channel = r;
428
429 return 0;
430 }
431
432 /**
433 * davinci_spi_setup - This functions will set default transfer method
434 * @spi: spi device on which data transfer to be done
435 *
436 * This functions sets the default transfer method.
437 */
438 static int davinci_spi_setup(struct spi_device *spi)
439 {
440 int retval;
441 struct davinci_spi *davinci_spi;
442 struct davinci_spi_dma *davinci_spi_dma;
443 struct device *sdev;
444
445 davinci_spi = spi_master_get_devdata(spi->master);
446 sdev = davinci_spi->bitbang.master->dev.parent;
447
448 /* if bits per word length is zero then set it default 8 */
449 if (!spi->bits_per_word)
450 spi->bits_per_word = 8;
451
452 davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
453
454 if (use_dma && davinci_spi->dma_channels) {
455 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
456
457 if ((davinci_spi_dma->dma_rx_channel == -1)
458 || (davinci_spi_dma->dma_tx_channel == -1)) {
459 retval = davinci_spi_request_dma(spi);
460 if (retval < 0)
461 return retval;
462 }
463 }
464
465 /*
466 * SPI in DaVinci and DA8xx operate between
467 * 600 KHz and 50 MHz
468 */
469 if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
470 dev_dbg(sdev, "Operating frequency is not in acceptable "
471 "range\n");
472 return -EINVAL;
473 }
474
475 /*
476 * Set up SPIFMTn register, unique to this chipselect.
477 *
478 * NOTE: we could do all of these with one write. Also, some
479 * of the "version 2" features are found in chips that don't
480 * support all of them...
481 */
482 if (spi->mode & SPI_LSB_FIRST)
483 set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
484 spi->chip_select);
485 else
486 clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
487 spi->chip_select);
488
489 if (spi->mode & SPI_CPOL)
490 set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
491 spi->chip_select);
492 else
493 clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
494 spi->chip_select);
495
496 if (!(spi->mode & SPI_CPHA))
497 set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
498 spi->chip_select);
499 else
500 clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
501 spi->chip_select);
502
503 /*
504 * Version 1 hardware supports two basic SPI modes:
505 * - Standard SPI mode uses 4 pins, with chipselect
506 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
507 * (distinct from SPI_3WIRE, with just one data wire;
508 * or similar variants without MOSI or without MISO)
509 *
510 * Version 2 hardware supports an optional handshaking signal,
511 * so it can support two more modes:
512 * - 5 pin SPI variant is standard SPI plus SPI_READY
513 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
514 */
515
516 if (davinci_spi->version == SPI_VERSION_2) {
517 clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
518 spi->chip_select);
519 set_fmt_bits(davinci_spi->base,
520 (davinci_spi->pdata->wdelay
521 << SPIFMT_WDELAY_SHIFT)
522 & SPIFMT_WDELAY_MASK,
523 spi->chip_select);
524
525 if (davinci_spi->pdata->odd_parity)
526 set_fmt_bits(davinci_spi->base,
527 SPIFMT_ODD_PARITY_MASK,
528 spi->chip_select);
529 else
530 clear_fmt_bits(davinci_spi->base,
531 SPIFMT_ODD_PARITY_MASK,
532 spi->chip_select);
533
534 if (davinci_spi->pdata->parity_enable)
535 set_fmt_bits(davinci_spi->base,
536 SPIFMT_PARITYENA_MASK,
537 spi->chip_select);
538 else
539 clear_fmt_bits(davinci_spi->base,
540 SPIFMT_PARITYENA_MASK,
541 spi->chip_select);
542
543 if (davinci_spi->pdata->wait_enable)
544 set_fmt_bits(davinci_spi->base,
545 SPIFMT_WAITENA_MASK,
546 spi->chip_select);
547 else
548 clear_fmt_bits(davinci_spi->base,
549 SPIFMT_WAITENA_MASK,
550 spi->chip_select);
551
552 if (davinci_spi->pdata->timer_disable)
553 set_fmt_bits(davinci_spi->base,
554 SPIFMT_DISTIMER_MASK,
555 spi->chip_select);
556 else
557 clear_fmt_bits(davinci_spi->base,
558 SPIFMT_DISTIMER_MASK,
559 spi->chip_select);
560 }
561
562 retval = davinci_spi_setup_transfer(spi, NULL);
563
564 return retval;
565 }
566
567 static void davinci_spi_cleanup(struct spi_device *spi)
568 {
569 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
570 struct davinci_spi_dma *davinci_spi_dma;
571
572 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
573
574 if (use_dma && davinci_spi->dma_channels) {
575 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
576
577 if ((davinci_spi_dma->dma_rx_channel != -1)
578 && (davinci_spi_dma->dma_tx_channel != -1)) {
579 edma_free_channel(davinci_spi_dma->dma_tx_channel);
580 edma_free_channel(davinci_spi_dma->dma_rx_channel);
581 }
582 }
583 }
584
585 static int davinci_spi_bufs_prep(struct spi_device *spi,
586 struct davinci_spi *davinci_spi)
587 {
588 int op_mode = 0;
589
590 /*
591 * REVISIT unless devices disagree about SPI_LOOP or
592 * SPI_READY (SPI_NO_CS only allows one device!), this
593 * should not need to be done before each message...
594 * optimize for both flags staying cleared.
595 */
596
597 op_mode = SPIPC0_DIFUN_MASK
598 | SPIPC0_DOFUN_MASK
599 | SPIPC0_CLKFUN_MASK;
600 if (!(spi->mode & SPI_NO_CS))
601 op_mode |= 1 << spi->chip_select;
602 if (spi->mode & SPI_READY)
603 op_mode |= SPIPC0_SPIENA_MASK;
604
605 iowrite32(op_mode, davinci_spi->base + SPIPC0);
606
607 if (spi->mode & SPI_LOOP)
608 set_io_bits(davinci_spi->base + SPIGCR1,
609 SPIGCR1_LOOPBACK_MASK);
610 else
611 clear_io_bits(davinci_spi->base + SPIGCR1,
612 SPIGCR1_LOOPBACK_MASK);
613
614 return 0;
615 }
616
617 static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
618 int int_status)
619 {
620 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
621
622 if (int_status & SPIFLG_TIMEOUT_MASK) {
623 dev_dbg(sdev, "SPI Time-out Error\n");
624 return -ETIMEDOUT;
625 }
626 if (int_status & SPIFLG_DESYNC_MASK) {
627 dev_dbg(sdev, "SPI Desynchronization Error\n");
628 return -EIO;
629 }
630 if (int_status & SPIFLG_BITERR_MASK) {
631 dev_dbg(sdev, "SPI Bit error\n");
632 return -EIO;
633 }
634
635 if (davinci_spi->version == SPI_VERSION_2) {
636 if (int_status & SPIFLG_DLEN_ERR_MASK) {
637 dev_dbg(sdev, "SPI Data Length Error\n");
638 return -EIO;
639 }
640 if (int_status & SPIFLG_PARERR_MASK) {
641 dev_dbg(sdev, "SPI Parity Error\n");
642 return -EIO;
643 }
644 if (int_status & SPIFLG_OVRRUN_MASK) {
645 dev_dbg(sdev, "SPI Data Overrun error\n");
646 return -EIO;
647 }
648 if (int_status & SPIFLG_TX_INTR_MASK) {
649 dev_dbg(sdev, "SPI TX intr bit set\n");
650 return -EIO;
651 }
652 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
653 dev_dbg(sdev, "SPI Buffer Init Active\n");
654 return -EBUSY;
655 }
656 }
657
658 return 0;
659 }
660
661 /**
662 * davinci_spi_bufs - functions which will handle transfer data
663 * @spi: spi device on which data transfer to be done
664 * @t: spi transfer in which transfer info is filled
665 *
666 * This function will put data to be transferred into data register
667 * of SPI controller and then wait until the completion will be marked
668 * by the IRQ Handler.
669 */
670 static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
671 {
672 struct davinci_spi *davinci_spi;
673 int int_status, count, ret;
674 u8 conv, tmp;
675 u32 tx_data, data1_reg_val;
676 u32 buf_val, flg_val;
677 struct davinci_spi_platform_data *pdata;
678
679 davinci_spi = spi_master_get_devdata(spi->master);
680 pdata = davinci_spi->pdata;
681
682 davinci_spi->tx = t->tx_buf;
683 davinci_spi->rx = t->rx_buf;
684
685 /* convert len to words based on bits_per_word */
686 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
687 davinci_spi->count = t->len / conv;
688
689 INIT_COMPLETION(davinci_spi->done);
690
691 ret = davinci_spi_bufs_prep(spi, davinci_spi);
692 if (ret)
693 return ret;
694
695 /* Enable SPI */
696 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
697
698 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
699 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
700 davinci_spi->base + SPIDELAY);
701
702 count = davinci_spi->count;
703 data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
704 tmp = ~(0x1 << spi->chip_select);
705
706 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
707
708 data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
709
710 while ((ioread32(davinci_spi->base + SPIBUF)
711 & SPIBUF_RXEMPTY_MASK) == 0)
712 cpu_relax();
713
714 /* Determine the command to execute READ or WRITE */
715 if (t->tx_buf) {
716 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
717
718 while (1) {
719 tx_data = davinci_spi->get_tx(davinci_spi);
720
721 data1_reg_val &= ~(0xFFFF);
722 data1_reg_val |= (0xFFFF & tx_data);
723
724 buf_val = ioread32(davinci_spi->base + SPIBUF);
725 if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
726 iowrite32(data1_reg_val,
727 davinci_spi->base + SPIDAT1);
728
729 count--;
730 }
731 while (ioread32(davinci_spi->base + SPIBUF)
732 & SPIBUF_RXEMPTY_MASK)
733 cpu_relax();
734
735 /* getting the returned byte */
736 if (t->rx_buf) {
737 buf_val = ioread32(davinci_spi->base + SPIBUF);
738 davinci_spi->get_rx(buf_val, davinci_spi);
739 }
740 if (count <= 0)
741 break;
742 }
743 } else {
744 if (pdata->poll_mode) {
745 while (1) {
746 /* keeps the serial clock going */
747 if ((ioread32(davinci_spi->base + SPIBUF)
748 & SPIBUF_TXFULL_MASK) == 0)
749 iowrite32(data1_reg_val,
750 davinci_spi->base + SPIDAT1);
751
752 while (ioread32(davinci_spi->base + SPIBUF) &
753 SPIBUF_RXEMPTY_MASK)
754 cpu_relax();
755
756 flg_val = ioread32(davinci_spi->base + SPIFLG);
757 buf_val = ioread32(davinci_spi->base + SPIBUF);
758
759 davinci_spi->get_rx(buf_val, davinci_spi);
760
761 count--;
762 if (count <= 0)
763 break;
764 }
765 } else { /* Receive in Interrupt mode */
766 int i;
767
768 for (i = 0; i < davinci_spi->count; i++) {
769 set_io_bits(davinci_spi->base + SPIINT,
770 SPIINT_BITERR_INTR
771 | SPIINT_OVRRUN_INTR
772 | SPIINT_RX_INTR);
773
774 iowrite32(data1_reg_val,
775 davinci_spi->base + SPIDAT1);
776
777 while (ioread32(davinci_spi->base + SPIINT) &
778 SPIINT_RX_INTR)
779 cpu_relax();
780 }
781 iowrite32((data1_reg_val & 0x0ffcffff),
782 davinci_spi->base + SPIDAT1);
783 }
784 }
785
786 /*
787 * Check for bit error, desync error,parity error,timeout error and
788 * receive overflow errors
789 */
790 int_status = ioread32(davinci_spi->base + SPIFLG);
791
792 ret = davinci_spi_check_error(davinci_spi, int_status);
793 if (ret != 0)
794 return ret;
795
796 /* SPI Framework maintains the count only in bytes so convert back */
797 davinci_spi->count *= conv;
798
799 return t->len;
800 }
801
802 #define DAVINCI_DMA_DATA_TYPE_S8 0x01
803 #define DAVINCI_DMA_DATA_TYPE_S16 0x02
804 #define DAVINCI_DMA_DATA_TYPE_S32 0x04
805
806 static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
807 {
808 struct davinci_spi *davinci_spi;
809 int int_status = 0;
810 int count, temp_count;
811 u8 conv = 1;
812 u8 tmp;
813 u32 data1_reg_val;
814 struct davinci_spi_dma *davinci_spi_dma;
815 int word_len, data_type, ret;
816 unsigned long tx_reg, rx_reg;
817 struct davinci_spi_platform_data *pdata;
818 struct device *sdev;
819
820 davinci_spi = spi_master_get_devdata(spi->master);
821 pdata = davinci_spi->pdata;
822 sdev = davinci_spi->bitbang.master->dev.parent;
823
824 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
825
826 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
827 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
828
829 davinci_spi->tx = t->tx_buf;
830 davinci_spi->rx = t->rx_buf;
831
832 /* convert len to words based on bits_per_word */
833 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
834 davinci_spi->count = t->len / conv;
835
836 INIT_COMPLETION(davinci_spi->done);
837
838 init_completion(&davinci_spi_dma->dma_rx_completion);
839 init_completion(&davinci_spi_dma->dma_tx_completion);
840
841 word_len = conv * 8;
842
843 if (word_len <= 8)
844 data_type = DAVINCI_DMA_DATA_TYPE_S8;
845 else if (word_len <= 16)
846 data_type = DAVINCI_DMA_DATA_TYPE_S16;
847 else if (word_len <= 32)
848 data_type = DAVINCI_DMA_DATA_TYPE_S32;
849 else
850 return -EINVAL;
851
852 ret = davinci_spi_bufs_prep(spi, davinci_spi);
853 if (ret)
854 return ret;
855
856 /* Put delay val if required */
857 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
858 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
859 davinci_spi->base + SPIDELAY);
860
861 count = davinci_spi->count; /* the number of elements */
862 data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
863
864 /* CS default = 0xFF */
865 tmp = ~(0x1 << spi->chip_select);
866
867 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
868
869 data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
870
871 /* disable all interrupts for dma transfers */
872 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
873 /* Disable SPI to write configuration bits in SPIDAT */
874 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
875 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
876 /* Enable SPI */
877 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
878
879 while ((ioread32(davinci_spi->base + SPIBUF)
880 & SPIBUF_RXEMPTY_MASK) == 0)
881 cpu_relax();
882
883
884 if (t->tx_buf) {
885 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
886 DMA_TO_DEVICE);
887 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
888 dev_dbg(sdev, "Unable to DMA map a %d bytes"
889 " TX buffer\n", count);
890 return -ENOMEM;
891 }
892 temp_count = count;
893 } else {
894 /* We need TX clocking for RX transaction */
895 t->tx_dma = dma_map_single(&spi->dev,
896 (void *)davinci_spi->tmp_buf, count + 1,
897 DMA_TO_DEVICE);
898 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
899 dev_dbg(sdev, "Unable to DMA map a %d bytes"
900 " TX tmp buffer\n", count);
901 return -ENOMEM;
902 }
903 temp_count = count + 1;
904 }
905
906 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
907 data_type, temp_count, 1, 0, ASYNC);
908 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
909 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
910 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
911 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
912
913 if (t->rx_buf) {
914 /* initiate transaction */
915 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
916
917 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
918 DMA_FROM_DEVICE);
919 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
920 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
921 count);
922 if (t->tx_buf != NULL)
923 dma_unmap_single(NULL, t->tx_dma,
924 count, DMA_TO_DEVICE);
925 return -ENOMEM;
926 }
927 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
928 data_type, count, 1, 0, ASYNC);
929 edma_set_src(davinci_spi_dma->dma_rx_channel,
930 rx_reg, INCR, W8BIT);
931 edma_set_dest(davinci_spi_dma->dma_rx_channel,
932 t->rx_dma, INCR, W8BIT);
933 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
934 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
935 data_type, 0);
936 }
937
938 if ((t->tx_buf) || (t->rx_buf))
939 edma_start(davinci_spi_dma->dma_tx_channel);
940
941 if (t->rx_buf)
942 edma_start(davinci_spi_dma->dma_rx_channel);
943
944 if ((t->rx_buf) || (t->tx_buf))
945 davinci_spi_set_dma_req(spi, 1);
946
947 if (t->tx_buf)
948 wait_for_completion_interruptible(
949 &davinci_spi_dma->dma_tx_completion);
950
951 if (t->rx_buf)
952 wait_for_completion_interruptible(
953 &davinci_spi_dma->dma_rx_completion);
954
955 dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
956
957 if (t->rx_buf)
958 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
959
960 /*
961 * Check for bit error, desync error,parity error,timeout error and
962 * receive overflow errors
963 */
964 int_status = ioread32(davinci_spi->base + SPIFLG);
965
966 ret = davinci_spi_check_error(davinci_spi, int_status);
967 if (ret != 0)
968 return ret;
969
970 /* SPI Framework maintains the count only in bytes so convert back */
971 davinci_spi->count *= conv;
972
973 return t->len;
974 }
975
976 /**
977 * davinci_spi_irq - IRQ handler for DaVinci SPI
978 * @irq: IRQ number for this SPI Master
979 * @context_data: structure for SPI Master controller davinci_spi
980 */
981 static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
982 {
983 struct davinci_spi *davinci_spi = context_data;
984 u32 int_status, rx_data = 0;
985 irqreturn_t ret = IRQ_NONE;
986
987 int_status = ioread32(davinci_spi->base + SPIFLG);
988
989 while ((int_status & SPIFLG_RX_INTR_MASK)) {
990 if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
991 ret = IRQ_HANDLED;
992
993 rx_data = ioread32(davinci_spi->base + SPIBUF);
994 davinci_spi->get_rx(rx_data, davinci_spi);
995
996 /* Disable Receive Interrupt */
997 iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
998 davinci_spi->base + SPIINT);
999 } else
1000 (void)davinci_spi_check_error(davinci_spi, int_status);
1001
1002 int_status = ioread32(davinci_spi->base + SPIFLG);
1003 }
1004
1005 return ret;
1006 }
1007
1008 /**
1009 * davinci_spi_probe - probe function for SPI Master Controller
1010 * @pdev: platform_device structure which contains plateform specific data
1011 */
1012 static int davinci_spi_probe(struct platform_device *pdev)
1013 {
1014 struct spi_master *master;
1015 struct davinci_spi *davinci_spi;
1016 struct davinci_spi_platform_data *pdata;
1017 struct resource *r, *mem;
1018 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
1019 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
1020 resource_size_t dma_eventq = SPI_NO_RESOURCE;
1021 int i = 0, ret = 0;
1022
1023 pdata = pdev->dev.platform_data;
1024 if (pdata == NULL) {
1025 ret = -ENODEV;
1026 goto err;
1027 }
1028
1029 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
1030 if (master == NULL) {
1031 ret = -ENOMEM;
1032 goto err;
1033 }
1034
1035 dev_set_drvdata(&pdev->dev, master);
1036
1037 davinci_spi = spi_master_get_devdata(master);
1038 if (davinci_spi == NULL) {
1039 ret = -ENOENT;
1040 goto free_master;
1041 }
1042
1043 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1044 if (r == NULL) {
1045 ret = -ENOENT;
1046 goto free_master;
1047 }
1048
1049 davinci_spi->pbase = r->start;
1050 davinci_spi->region_size = resource_size(r);
1051 davinci_spi->pdata = pdata;
1052
1053 mem = request_mem_region(r->start, davinci_spi->region_size,
1054 pdev->name);
1055 if (mem == NULL) {
1056 ret = -EBUSY;
1057 goto free_master;
1058 }
1059
1060 davinci_spi->base = (struct davinci_spi_reg __iomem *)
1061 ioremap(r->start, davinci_spi->region_size);
1062 if (davinci_spi->base == NULL) {
1063 ret = -ENOMEM;
1064 goto release_region;
1065 }
1066
1067 davinci_spi->irq = platform_get_irq(pdev, 0);
1068 if (davinci_spi->irq <= 0) {
1069 ret = -EINVAL;
1070 goto unmap_io;
1071 }
1072
1073 ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
1074 dev_name(&pdev->dev), davinci_spi);
1075 if (ret)
1076 goto unmap_io;
1077
1078 /* Allocate tmp_buf for tx_buf */
1079 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
1080 if (davinci_spi->tmp_buf == NULL) {
1081 ret = -ENOMEM;
1082 goto irq_free;
1083 }
1084
1085 davinci_spi->bitbang.master = spi_master_get(master);
1086 if (davinci_spi->bitbang.master == NULL) {
1087 ret = -ENODEV;
1088 goto free_tmp_buf;
1089 }
1090
1091 davinci_spi->clk = clk_get(&pdev->dev, NULL);
1092 if (IS_ERR(davinci_spi->clk)) {
1093 ret = -ENODEV;
1094 goto put_master;
1095 }
1096 clk_enable(davinci_spi->clk);
1097
1098 master->bus_num = pdev->id;
1099 master->num_chipselect = pdata->num_chipselect;
1100 master->setup = davinci_spi_setup;
1101 master->cleanup = davinci_spi_cleanup;
1102
1103 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
1104 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
1105
1106 davinci_spi->version = pdata->version;
1107 use_dma = pdata->use_dma;
1108
1109 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1110 if (davinci_spi->version == SPI_VERSION_2)
1111 davinci_spi->bitbang.flags |= SPI_READY;
1112
1113 if (use_dma) {
1114 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1115 if (r)
1116 dma_rx_chan = r->start;
1117 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1118 if (r)
1119 dma_tx_chan = r->start;
1120 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1121 if (r)
1122 dma_eventq = r->start;
1123 }
1124
1125 if (!use_dma ||
1126 dma_rx_chan == SPI_NO_RESOURCE ||
1127 dma_tx_chan == SPI_NO_RESOURCE ||
1128 dma_eventq == SPI_NO_RESOURCE) {
1129 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
1130 use_dma = 0;
1131 } else {
1132 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
1133 davinci_spi->dma_channels = kzalloc(master->num_chipselect
1134 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
1135 if (davinci_spi->dma_channels == NULL) {
1136 ret = -ENOMEM;
1137 goto free_clk;
1138 }
1139
1140 for (i = 0; i < master->num_chipselect; i++) {
1141 davinci_spi->dma_channels[i].dma_rx_channel = -1;
1142 davinci_spi->dma_channels[i].dma_rx_sync_dev =
1143 dma_rx_chan;
1144 davinci_spi->dma_channels[i].dma_tx_channel = -1;
1145 davinci_spi->dma_channels[i].dma_tx_sync_dev =
1146 dma_tx_chan;
1147 davinci_spi->dma_channels[i].eventq = dma_eventq;
1148 }
1149 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
1150 "Using RX channel = %d , TX channel = %d and "
1151 "event queue = %d", dma_rx_chan, dma_tx_chan,
1152 dma_eventq);
1153 }
1154
1155 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1156 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1157
1158 init_completion(&davinci_spi->done);
1159
1160 /* Reset In/OUT SPI module */
1161 iowrite32(0, davinci_spi->base + SPIGCR0);
1162 udelay(100);
1163 iowrite32(1, davinci_spi->base + SPIGCR0);
1164
1165 /* Clock internal */
1166 if (davinci_spi->pdata->clk_internal)
1167 set_io_bits(davinci_spi->base + SPIGCR1,
1168 SPIGCR1_CLKMOD_MASK);
1169 else
1170 clear_io_bits(davinci_spi->base + SPIGCR1,
1171 SPIGCR1_CLKMOD_MASK);
1172
1173 /* master mode default */
1174 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1175
1176 if (davinci_spi->pdata->intr_level)
1177 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1178 else
1179 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1180
1181 ret = spi_bitbang_start(&davinci_spi->bitbang);
1182 if (ret)
1183 goto free_clk;
1184
1185 dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
1186
1187 if (!pdata->poll_mode)
1188 dev_info(&pdev->dev, "Operating in interrupt mode"
1189 " using IRQ %d\n", davinci_spi->irq);
1190
1191 return ret;
1192
1193 free_clk:
1194 clk_disable(davinci_spi->clk);
1195 clk_put(davinci_spi->clk);
1196 put_master:
1197 spi_master_put(master);
1198 free_tmp_buf:
1199 kfree(davinci_spi->tmp_buf);
1200 irq_free:
1201 free_irq(davinci_spi->irq, davinci_spi);
1202 unmap_io:
1203 iounmap(davinci_spi->base);
1204 release_region:
1205 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1206 free_master:
1207 kfree(master);
1208 err:
1209 return ret;
1210 }
1211
1212 /**
1213 * davinci_spi_remove - remove function for SPI Master Controller
1214 * @pdev: platform_device structure which contains plateform specific data
1215 *
1216 * This function will do the reverse action of davinci_spi_probe function
1217 * It will free the IRQ and SPI controller's memory region.
1218 * It will also call spi_bitbang_stop to destroy the work queue which was
1219 * created by spi_bitbang_start.
1220 */
1221 static int __exit davinci_spi_remove(struct platform_device *pdev)
1222 {
1223 struct davinci_spi *davinci_spi;
1224 struct spi_master *master;
1225
1226 master = dev_get_drvdata(&pdev->dev);
1227 davinci_spi = spi_master_get_devdata(master);
1228
1229 spi_bitbang_stop(&davinci_spi->bitbang);
1230
1231 clk_disable(davinci_spi->clk);
1232 clk_put(davinci_spi->clk);
1233 spi_master_put(master);
1234 kfree(davinci_spi->tmp_buf);
1235 free_irq(davinci_spi->irq, davinci_spi);
1236 iounmap(davinci_spi->base);
1237 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1238
1239 return 0;
1240 }
1241
1242 static struct platform_driver davinci_spi_driver = {
1243 .driver.name = "spi_davinci",
1244 .remove = __exit_p(davinci_spi_remove),
1245 };
1246
1247 static int __init davinci_spi_init(void)
1248 {
1249 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1250 }
1251 module_init(davinci_spi_init);
1252
1253 static void __exit davinci_spi_exit(void)
1254 {
1255 platform_driver_unregister(&davinci_spi_driver);
1256 }
1257 module_exit(davinci_spi_exit);
1258
1259 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1260 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree