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[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / linux / pci.h
blobf1b1ca1a09e180bd6cdb7a3b698fa07534127807
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
179 };
180
181 enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
184 };
185
186 typedef unsigned short __bitwise pci_bus_flags_t;
187 enum pci_bus_flags {
188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
190 };
191
192 /* Based on the PCI Hotplug Spec, but some values are made up by us */
193 enum pci_bus_speed {
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
205 AGP_UNKNOWN = 0x0c,
206 AGP_1X = 0x0d,
207 AGP_2X = 0x0e,
208 AGP_4X = 0x0f,
209 AGP_8X = 0x10,
210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
215 PCIE_SPEED_8_0GT = 0x16,
216 PCI_SPEED_UNKNOWN = 0xff,
217 };
218
219 struct pci_cap_saved_data {
220 char cap_nr;
221 unsigned int size;
222 u32 data[0];
223 };
224
225 struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
228 };
229
230 struct pcie_link_state;
231 struct pci_vpd;
232 struct pci_sriov;
233 struct pci_ats;
234
235 /*
236 * The pci_dev structure is used to describe PCI devices.
237 */
238 struct pci_dev {
239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
242
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
245 struct pci_slot *slot; /* Physical slot this device is in */
246
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
253 u8 revision; /* PCI revision, low byte of class word */
254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
255 u8 pcie_cap; /* PCI-E capability offset */
256 u8 pcie_type:4; /* PCI-E device/port type */
257 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
258 u8 rom_base_reg; /* which config register controls the ROM */
259 u8 pin; /* which interrupt pin this device uses */
260
261 struct pci_driver *driver; /* which driver has allocated this device */
262 u64 dma_mask; /* Mask of the bits of bus address this
263 device implements. Normally this is
264 0xffffffff. You only need to change
265 this if your device has broken DMA
266 or supports 64-bit transfers. */
267
268 struct device_dma_parameters dma_parms;
269
270 pci_power_t current_state; /* Current operating state. In ACPI-speak,
271 this is D0-D3, D0 being fully functional,
272 and D3 being off. */
273 int pm_cap; /* PM capability offset in the
274 configuration space */
275 unsigned int pme_support:5; /* Bitmask of states from which PME#
276 can be generated */
277 unsigned int pme_interrupt:1;
278 unsigned int d1_support:1; /* Low power state D1 is supported */
279 unsigned int d2_support:1; /* Low power state D2 is supported */
280 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
281 unsigned int mmio_always_on:1; /* disallow turning off io/mem
282 decoding during bar sizing */
283 unsigned int wakeup_prepared:1;
284 unsigned int d3_delay; /* D3->D0 transition time in ms */
285
286 #ifdef CONFIG_PCIEASPM
287 struct pcie_link_state *link_state; /* ASPM link state. */
288 #endif
289
290 pci_channel_state_t error_state; /* current connectivity state */
291 struct device dev; /* Generic device interface */
292
293 int cfg_size; /* Size of configuration space */
294
295 /*
296 * Instead of touching interrupt line and base address registers
297 * directly, use the values stored here. They might be different!
298 */
299 unsigned int irq;
300 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
301 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
302
303 /* These fields are used by common fixups */
304 unsigned int transparent:1; /* Transparent PCI bridge */
305 unsigned int multifunction:1;/* Part of multi-function device */
306 /* keep track of device state */
307 unsigned int is_added:1;
308 unsigned int is_busmaster:1; /* device is busmaster */
309 unsigned int no_msi:1; /* device may not use msi */
310 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
311 unsigned int broken_parity_status:1; /* Device generates false positive parity */
312 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
313 unsigned int msi_enabled:1;
314 unsigned int msix_enabled:1;
315 unsigned int ari_enabled:1; /* ARI forwarding */
316 unsigned int is_managed:1;
317 unsigned int is_pcie:1; /* Obsolete. Will be removed.
318 Use pci_is_pcie() instead */
319 unsigned int needs_freset:1; /* Dev requires fundamental reset */
320 unsigned int state_saved:1;
321 unsigned int is_physfn:1;
322 unsigned int is_virtfn:1;
323 unsigned int reset_fn:1;
324 unsigned int is_hotplug_bridge:1;
325 unsigned int __aer_firmware_first_valid:1;
326 unsigned int __aer_firmware_first:1;
327 pci_dev_flags_t dev_flags;
328 atomic_t enable_cnt; /* pci_enable_device has been called */
329
330 u32 saved_config_space[16]; /* config space saved at suspend time */
331 struct hlist_head saved_cap_space;
332 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
333 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
334 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
335 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
336 #ifdef CONFIG_PCI_MSI
337 struct list_head msi_list;
338 #endif
339 struct pci_vpd *vpd;
340 #ifdef CONFIG_PCI_IOV
341 union {
342 struct pci_sriov *sriov; /* SR-IOV capability related */
343 struct pci_dev *physfn; /* the PF this VF is associated with */
344 };
345 struct pci_ats *ats; /* Address Translation Service */
346 #endif
347 };
348
349 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
350 {
351 #ifdef CONFIG_PCI_IOV
352 if (dev->is_virtfn)
353 dev = dev->physfn;
354 #endif
355
356 return dev;
357 }
358
359 extern struct pci_dev *alloc_pci_dev(void);
360
361 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
362 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
363 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
364
365 static inline int pci_channel_offline(struct pci_dev *pdev)
366 {
367 return (pdev->error_state != pci_channel_io_normal);
368 }
369
370 static inline struct pci_cap_saved_state *pci_find_saved_cap(
371 struct pci_dev *pci_dev, char cap)
372 {
373 struct pci_cap_saved_state *tmp;
374 struct hlist_node *pos;
375
376 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
377 if (tmp->cap.cap_nr == cap)
378 return tmp;
379 }
380 return NULL;
381 }
382
383 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
384 struct pci_cap_saved_state *new_cap)
385 {
386 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
387 }
388
389 /*
390 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
391 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
392 * buses below host bridges or subtractive decode bridges) go in the list.
393 * Use pci_bus_for_each_resource() to iterate through all the resources.
394 */
395
396 /*
397 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
398 * and there's no way to program the bridge with the details of the window.
399 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
400 * decode bit set, because they are explicit and can be programmed with _SRS.
401 */
402 #define PCI_SUBTRACTIVE_DECODE 0x1
403
404 struct pci_bus_resource {
405 struct list_head list;
406 struct resource *res;
407 unsigned int flags;
408 };
409
410 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
411
412 struct pci_bus {
413 struct list_head node; /* node in list of buses */
414 struct pci_bus *parent; /* parent bus this bridge is on */
415 struct list_head children; /* list of child buses */
416 struct list_head devices; /* list of devices on this bus */
417 struct pci_dev *self; /* bridge device as seen by parent */
418 struct list_head slots; /* list of slots on this bus */
419 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
420 struct list_head resources; /* address space routed to this bus */
421
422 struct pci_ops *ops; /* configuration access functions */
423 void *sysdata; /* hook for sys-specific extension */
424 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
425
426 unsigned char number; /* bus number */
427 unsigned char primary; /* number of primary bridge */
428 unsigned char secondary; /* number of secondary bridge */
429 unsigned char subordinate; /* max number of subordinate buses */
430 unsigned char max_bus_speed; /* enum pci_bus_speed */
431 unsigned char cur_bus_speed; /* enum pci_bus_speed */
432
433 char name[48];
434
435 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
436 pci_bus_flags_t bus_flags; /* Inherited by child busses */
437 struct device *bridge;
438 struct device dev;
439 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
440 struct bin_attribute *legacy_mem; /* legacy mem */
441 unsigned int is_added:1;
442 };
443
444 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
445 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
446
447 /*
448 * Returns true if the pci bus is root (behind host-pci bridge),
449 * false otherwise
450 */
451 static inline bool pci_is_root_bus(struct pci_bus *pbus)
452 {
453 return !(pbus->parent);
454 }
455
456 #ifdef CONFIG_PCI_MSI
457 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
458 {
459 return pci_dev->msi_enabled || pci_dev->msix_enabled;
460 }
461 #else
462 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
463 #endif
464
465 /*
466 * Error values that may be returned by PCI functions.
467 */
468 #define PCIBIOS_SUCCESSFUL 0x00
469 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
470 #define PCIBIOS_BAD_VENDOR_ID 0x83
471 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
472 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
473 #define PCIBIOS_SET_FAILED 0x88
474 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
475
476 /* Low-level architecture-dependent routines */
477
478 struct pci_ops {
479 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
480 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
481 };
482
483 /*
484 * ACPI needs to be able to access PCI config space before we've done a
485 * PCI bus scan and created pci_bus structures.
486 */
487 extern int raw_pci_read(unsigned int domain, unsigned int bus,
488 unsigned int devfn, int reg, int len, u32 *val);
489 extern int raw_pci_write(unsigned int domain, unsigned int bus,
490 unsigned int devfn, int reg, int len, u32 val);
491
492 struct pci_bus_region {
493 resource_size_t start;
494 resource_size_t end;
495 };
496
497 struct pci_dynids {
498 spinlock_t lock; /* protects list, index */
499 struct list_head list; /* for IDs added at runtime */
500 };
501
502 /* ---------------------------------------------------------------- */
503 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
504 * a set of callbacks in struct pci_error_handlers, then that device driver
505 * will be notified of PCI bus errors, and will be driven to recovery
506 * when an error occurs.
507 */
508
509 typedef unsigned int __bitwise pci_ers_result_t;
510
511 enum pci_ers_result {
512 /* no result/none/not supported in device driver */
513 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
514
515 /* Device driver can recover without slot reset */
516 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
517
518 /* Device driver wants slot to be reset. */
519 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
520
521 /* Device has completely failed, is unrecoverable */
522 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
523
524 /* Device driver is fully recovered and operational */
525 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
526 };
527
528 /* PCI bus error event callbacks */
529 struct pci_error_handlers {
530 /* PCI bus error detected on this device */
531 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
532 enum pci_channel_state error);
533
534 /* MMIO has been re-enabled, but not DMA */
535 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
536
537 /* PCI Express link has been reset */
538 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
539
540 /* PCI slot has been reset */
541 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
542
543 /* Device driver may resume normal operations */
544 void (*resume)(struct pci_dev *dev);
545 };
546
547 /* ---------------------------------------------------------------- */
548
549 struct module;
550 struct pci_driver {
551 struct list_head node;
552 const char *name;
553 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
554 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
555 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
556 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
557 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
558 int (*resume_early) (struct pci_dev *dev);
559 int (*resume) (struct pci_dev *dev); /* Device woken up */
560 void (*shutdown) (struct pci_dev *dev);
561 struct pci_error_handlers *err_handler;
562 struct device_driver driver;
563 struct pci_dynids dynids;
564 };
565
566 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
567
568 /**
569 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
570 * @_table: device table name
571 *
572 * This macro is used to create a struct pci_device_id array (a device table)
573 * in a generic manner.
574 */
575 #define DEFINE_PCI_DEVICE_TABLE(_table) \
576 const struct pci_device_id _table[] __devinitconst
577
578 /**
579 * PCI_DEVICE - macro used to describe a specific pci device
580 * @vend: the 16 bit PCI Vendor ID
581 * @dev: the 16 bit PCI Device ID
582 *
583 * This macro is used to create a struct pci_device_id that matches a
584 * specific device. The subvendor and subdevice fields will be set to
585 * PCI_ANY_ID.
586 */
587 #define PCI_DEVICE(vend,dev) \
588 .vendor = (vend), .device = (dev), \
589 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
590
591 /**
592 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
593 * @dev_class: the class, subclass, prog-if triple for this device
594 * @dev_class_mask: the class mask for this device
595 *
596 * This macro is used to create a struct pci_device_id that matches a
597 * specific PCI class. The vendor, device, subvendor, and subdevice
598 * fields will be set to PCI_ANY_ID.
599 */
600 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
601 .class = (dev_class), .class_mask = (dev_class_mask), \
602 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
603 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
604
605 /**
606 * PCI_VDEVICE - macro used to describe a specific pci device in short form
607 * @vendor: the vendor name
608 * @device: the 16 bit PCI Device ID
609 *
610 * This macro is used to create a struct pci_device_id that matches a
611 * specific PCI device. The subvendor, and subdevice fields will be set
612 * to PCI_ANY_ID. The macro allows the next field to follow as the device
613 * private data.
614 */
615
616 #define PCI_VDEVICE(vendor, device) \
617 PCI_VENDOR_ID_##vendor, (device), \
618 PCI_ANY_ID, PCI_ANY_ID, 0, 0
619
620 /* these external functions are only available when PCI support is enabled */
621 #ifdef CONFIG_PCI
622
623 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
624
625 enum pcie_bus_config_types {
626 PCIE_BUS_TUNE_OFF,
627 PCIE_BUS_SAFE,
628 PCIE_BUS_PERFORMANCE,
629 PCIE_BUS_PEER2PEER,
630 };
631
632 extern enum pcie_bus_config_types pcie_bus_config;
633
634 extern struct bus_type pci_bus_type;
635
636 /* Do NOT directly access these two variables, unless you are arch specific pci
637 * code, or pci core code. */
638 extern struct list_head pci_root_buses; /* list of all known PCI buses */
639 /* Some device drivers need know if pci is initiated */
640 extern int no_pci_devices(void);
641
642 void pcibios_fixup_bus(struct pci_bus *);
643 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
644 char *pcibios_setup(char *str);
645
646 /* Used only when drivers/pci/setup.c is used */
647 resource_size_t pcibios_align_resource(void *, const struct resource *,
648 resource_size_t,
649 resource_size_t);
650 void pcibios_update_irq(struct pci_dev *, int irq);
651
652 /* Weak but can be overriden by arch */
653 void pci_fixup_cardbus(struct pci_bus *);
654
655 /* Generic PCI functions used internally */
656
657 void pcibios_scan_specific_bus(int busn);
658 extern struct pci_bus *pci_find_bus(int domain, int busnr);
659 void pci_bus_add_devices(const struct pci_bus *bus);
660 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
661 struct pci_ops *ops, void *sysdata);
662 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
663 void *sysdata)
664 {
665 struct pci_bus *root_bus;
666 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
667 if (root_bus)
668 pci_bus_add_devices(root_bus);
669 return root_bus;
670 }
671 struct pci_bus *pci_create_bus(struct device *parent, int bus,
672 struct pci_ops *ops, void *sysdata);
673 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
674 int busnr);
675 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
676 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
677 const char *name,
678 struct hotplug_slot *hotplug);
679 void pci_destroy_slot(struct pci_slot *slot);
680 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
681 int pci_scan_slot(struct pci_bus *bus, int devfn);
682 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
683 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
684 unsigned int pci_scan_child_bus(struct pci_bus *bus);
685 int __must_check pci_bus_add_device(struct pci_dev *dev);
686 void pci_read_bridge_bases(struct pci_bus *child);
687 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
688 struct resource *res);
689 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
690 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
691 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
692 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
693 extern void pci_dev_put(struct pci_dev *dev);
694 extern void pci_remove_bus(struct pci_bus *b);
695 extern void pci_remove_bus_device(struct pci_dev *dev);
696 extern void pci_stop_bus_device(struct pci_dev *dev);
697 void pci_setup_cardbus(struct pci_bus *bus);
698 extern void pci_sort_breadthfirst(void);
699 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
700 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
701 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
702
703 /* Generic PCI functions exported to card drivers */
704
705 enum pci_lost_interrupt_reason {
706 PCI_LOST_IRQ_NO_INFORMATION = 0,
707 PCI_LOST_IRQ_DISABLE_MSI,
708 PCI_LOST_IRQ_DISABLE_MSIX,
709 PCI_LOST_IRQ_DISABLE_ACPI,
710 };
711 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
712 int pci_find_capability(struct pci_dev *dev, int cap);
713 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
714 int pci_find_ext_capability(struct pci_dev *dev, int cap);
715 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
716 int cap);
717 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
718 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
719 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
720
721 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
722 struct pci_dev *from);
723 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
724 unsigned int ss_vendor, unsigned int ss_device,
725 struct pci_dev *from);
726 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
727 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
728 unsigned int devfn);
729 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
730 unsigned int devfn)
731 {
732 return pci_get_domain_bus_and_slot(0, bus, devfn);
733 }
734 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
735 int pci_dev_present(const struct pci_device_id *ids);
736
737 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
738 int where, u8 *val);
739 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
740 int where, u16 *val);
741 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
742 int where, u32 *val);
743 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
744 int where, u8 val);
745 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
746 int where, u16 val);
747 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
748 int where, u32 val);
749 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
750
751 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
752 {
753 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
754 }
755 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
756 {
757 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
758 }
759 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
760 u32 *val)
761 {
762 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
763 }
764 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
765 {
766 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
767 }
768 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
769 {
770 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
771 }
772 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
773 u32 val)
774 {
775 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
776 }
777
778 int __must_check pci_enable_device(struct pci_dev *dev);
779 int __must_check pci_enable_device_io(struct pci_dev *dev);
780 int __must_check pci_enable_device_mem(struct pci_dev *dev);
781 int __must_check pci_reenable_device(struct pci_dev *);
782 int __must_check pcim_enable_device(struct pci_dev *pdev);
783 void pcim_pin_device(struct pci_dev *pdev);
784
785 static inline int pci_is_enabled(struct pci_dev *pdev)
786 {
787 return (atomic_read(&pdev->enable_cnt) > 0);
788 }
789
790 static inline int pci_is_managed(struct pci_dev *pdev)
791 {
792 return pdev->is_managed;
793 }
794
795 void pci_disable_device(struct pci_dev *dev);
796 void pci_set_master(struct pci_dev *dev);
797 void pci_clear_master(struct pci_dev *dev);
798 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
799 int pci_set_cacheline_size(struct pci_dev *dev);
800 #define HAVE_PCI_SET_MWI
801 int __must_check pci_set_mwi(struct pci_dev *dev);
802 int pci_try_set_mwi(struct pci_dev *dev);
803 void pci_clear_mwi(struct pci_dev *dev);
804 void pci_intx(struct pci_dev *dev, int enable);
805 void pci_msi_off(struct pci_dev *dev);
806 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
807 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
808 int pcix_get_max_mmrbc(struct pci_dev *dev);
809 int pcix_get_mmrbc(struct pci_dev *dev);
810 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
811 int pcie_get_readrq(struct pci_dev *dev);
812 int pcie_set_readrq(struct pci_dev *dev, int rq);
813 int pcie_get_mps(struct pci_dev *dev);
814 int pcie_set_mps(struct pci_dev *dev, int mps);
815 int __pci_reset_function(struct pci_dev *dev);
816 int pci_reset_function(struct pci_dev *dev);
817 void pci_update_resource(struct pci_dev *dev, int resno);
818 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
819 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
820 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
821
822 /* ROM control related routines */
823 int pci_enable_rom(struct pci_dev *pdev);
824 void pci_disable_rom(struct pci_dev *pdev);
825 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
826 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
827 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
828
829 /* Power management related routines */
830 int pci_save_state(struct pci_dev *dev);
831 void pci_restore_state(struct pci_dev *dev);
832 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
833 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
834 int pci_load_and_free_saved_state(struct pci_dev *dev,
835 struct pci_saved_state **state);
836 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
837 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
838 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
839 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
840 void pci_pme_active(struct pci_dev *dev, bool enable);
841 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
842 bool runtime, bool enable);
843 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
844 pci_power_t pci_target_state(struct pci_dev *dev);
845 int pci_prepare_to_sleep(struct pci_dev *dev);
846 int pci_back_from_sleep(struct pci_dev *dev);
847 bool pci_dev_run_wake(struct pci_dev *dev);
848 bool pci_check_pme_status(struct pci_dev *dev);
849 void pci_pme_wakeup_bus(struct pci_bus *bus);
850
851 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
852 bool enable)
853 {
854 return __pci_enable_wake(dev, state, false, enable);
855 }
856
857 #define PCI_EXP_IDO_REQUEST (1<<0)
858 #define PCI_EXP_IDO_COMPLETION (1<<1)
859 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
860 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
861
862 enum pci_obff_signal_type {
863 PCI_EXP_OBFF_SIGNAL_L0 = 0,
864 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
865 };
866 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
867 void pci_disable_obff(struct pci_dev *dev);
868
869 bool pci_ltr_supported(struct pci_dev *dev);
870 int pci_enable_ltr(struct pci_dev *dev);
871 void pci_disable_ltr(struct pci_dev *dev);
872 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
873
874 /* For use by arch with custom probe code */
875 void set_pcie_port_type(struct pci_dev *pdev);
876 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
877
878 /* Functions for PCI Hotplug drivers to use */
879 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
880 #ifdef CONFIG_HOTPLUG
881 unsigned int pci_rescan_bus(struct pci_bus *bus);
882 #endif
883
884 /* Vital product data routines */
885 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
886 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
887 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
888
889 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
890 void pci_bus_assign_resources(const struct pci_bus *bus);
891 void pci_bus_size_bridges(struct pci_bus *bus);
892 int pci_claim_resource(struct pci_dev *, int);
893 void pci_assign_unassigned_resources(void);
894 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
895 void pdev_enable_device(struct pci_dev *);
896 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
897 int pci_enable_resources(struct pci_dev *, int mask);
898 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
899 int (*)(const struct pci_dev *, u8, u8));
900 #define HAVE_PCI_REQ_REGIONS 2
901 int __must_check pci_request_regions(struct pci_dev *, const char *);
902 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
903 void pci_release_regions(struct pci_dev *);
904 int __must_check pci_request_region(struct pci_dev *, int, const char *);
905 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
906 void pci_release_region(struct pci_dev *, int);
907 int pci_request_selected_regions(struct pci_dev *, int, const char *);
908 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
909 void pci_release_selected_regions(struct pci_dev *, int);
910
911 /* drivers/pci/bus.c */
912 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
913 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
914 void pci_bus_remove_resources(struct pci_bus *bus);
915
916 #define pci_bus_for_each_resource(bus, res, i) \
917 for (i = 0; \
918 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
919 i++)
920
921 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
922 struct resource *res, resource_size_t size,
923 resource_size_t align, resource_size_t min,
924 unsigned int type_mask,
925 resource_size_t (*alignf)(void *,
926 const struct resource *,
927 resource_size_t,
928 resource_size_t),
929 void *alignf_data);
930 void pci_enable_bridges(struct pci_bus *bus);
931
932 /* Proper probing supporting hot-pluggable devices */
933 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
934 const char *mod_name);
935
936 /*
937 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
938 */
939 #define pci_register_driver(driver) \
940 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
941
942 void pci_unregister_driver(struct pci_driver *dev);
943 void pci_remove_behind_bridge(struct pci_dev *dev);
944 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
945 int pci_add_dynid(struct pci_driver *drv,
946 unsigned int vendor, unsigned int device,
947 unsigned int subvendor, unsigned int subdevice,
948 unsigned int class, unsigned int class_mask,
949 unsigned long driver_data);
950 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
951 struct pci_dev *dev);
952 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
953 int pass);
954
955 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
956 void *userdata);
957 int pci_cfg_space_size_ext(struct pci_dev *dev);
958 int pci_cfg_space_size(struct pci_dev *dev);
959 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
960
961 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
962 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
963
964 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
965 unsigned int command_bits, u32 flags);
966 /* kmem_cache style wrapper around pci_alloc_consistent() */
967
968 #include <linux/pci-dma.h>
969 #include <linux/dmapool.h>
970
971 #define pci_pool dma_pool
972 #define pci_pool_create(name, pdev, size, align, allocation) \
973 dma_pool_create(name, &pdev->dev, size, align, allocation)
974 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
975 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
976 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
977
978 enum pci_dma_burst_strategy {
979 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
980 strategy_parameter is N/A */
981 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
982 byte boundaries */
983 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
984 strategy_parameter byte boundaries */
985 };
986
987 struct msix_entry {
988 u32 vector; /* kernel uses to write allocated vector */
989 u16 entry; /* driver uses to specify entry, OS writes */
990 };
991
992
993 #ifndef CONFIG_PCI_MSI
994 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
995 {
996 return -1;
997 }
998
999 static inline void pci_msi_shutdown(struct pci_dev *dev)
1000 { }
1001 static inline void pci_disable_msi(struct pci_dev *dev)
1002 { }
1003
1004 static inline int pci_msix_table_size(struct pci_dev *dev)
1005 {
1006 return 0;
1007 }
1008 static inline int pci_enable_msix(struct pci_dev *dev,
1009 struct msix_entry *entries, int nvec)
1010 {
1011 return -1;
1012 }
1013
1014 static inline void pci_msix_shutdown(struct pci_dev *dev)
1015 { }
1016 static inline void pci_disable_msix(struct pci_dev *dev)
1017 { }
1018
1019 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1020 { }
1021
1022 static inline void pci_restore_msi_state(struct pci_dev *dev)
1023 { }
1024 static inline int pci_msi_enabled(void)
1025 {
1026 return 0;
1027 }
1028 #else
1029 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1030 extern void pci_msi_shutdown(struct pci_dev *dev);
1031 extern void pci_disable_msi(struct pci_dev *dev);
1032 extern int pci_msix_table_size(struct pci_dev *dev);
1033 extern int pci_enable_msix(struct pci_dev *dev,
1034 struct msix_entry *entries, int nvec);
1035 extern void pci_msix_shutdown(struct pci_dev *dev);
1036 extern void pci_disable_msix(struct pci_dev *dev);
1037 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1038 extern void pci_restore_msi_state(struct pci_dev *dev);
1039 extern int pci_msi_enabled(void);
1040 #endif
1041
1042 #ifdef CONFIG_PCIEPORTBUS
1043 extern bool pcie_ports_disabled;
1044 extern bool pcie_ports_auto;
1045 #else
1046 #define pcie_ports_disabled true
1047 #define pcie_ports_auto false
1048 #endif
1049
1050 #ifndef CONFIG_PCIEASPM
1051 static inline int pcie_aspm_enabled(void) { return 0; }
1052 static inline bool pcie_aspm_support_enabled(void) { return false; }
1053 #else
1054 extern int pcie_aspm_enabled(void);
1055 extern bool pcie_aspm_support_enabled(void);
1056 #endif
1057
1058 #ifdef CONFIG_PCIEAER
1059 void pci_no_aer(void);
1060 bool pci_aer_available(void);
1061 #else
1062 static inline void pci_no_aer(void) { }
1063 static inline bool pci_aer_available(void) { return false; }
1064 #endif
1065
1066 #ifndef CONFIG_PCIE_ECRC
1067 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1068 {
1069 return;
1070 }
1071 static inline void pcie_ecrc_get_policy(char *str) {};
1072 #else
1073 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1074 extern void pcie_ecrc_get_policy(char *str);
1075 #endif
1076
1077 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1078
1079 #ifdef CONFIG_HT_IRQ
1080 /* The functions a driver should call */
1081 int ht_create_irq(struct pci_dev *dev, int idx);
1082 void ht_destroy_irq(unsigned int irq);
1083 #endif /* CONFIG_HT_IRQ */
1084
1085 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1086 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1087
1088 /*
1089 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1090 * a PCI domain is defined to be a set of PCI busses which share
1091 * configuration space.
1092 */
1093 #ifdef CONFIG_PCI_DOMAINS
1094 extern int pci_domains_supported;
1095 #else
1096 enum { pci_domains_supported = 0 };
1097 static inline int pci_domain_nr(struct pci_bus *bus)
1098 {
1099 return 0;
1100 }
1101
1102 static inline int pci_proc_domain(struct pci_bus *bus)
1103 {
1104 return 0;
1105 }
1106 #endif /* CONFIG_PCI_DOMAINS */
1107
1108 /* some architectures require additional setup to direct VGA traffic */
1109 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1110 unsigned int command_bits, u32 flags);
1111 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1112
1113 #else /* CONFIG_PCI is not enabled */
1114
1115 /*
1116 * If the system does not have PCI, clearly these return errors. Define
1117 * these as simple inline functions to avoid hair in drivers.
1118 */
1119
1120 #define _PCI_NOP(o, s, t) \
1121 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1122 int where, t val) \
1123 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1124
1125 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1126 _PCI_NOP(o, word, u16 x) \
1127 _PCI_NOP(o, dword, u32 x)
1128 _PCI_NOP_ALL(read, *)
1129 _PCI_NOP_ALL(write,)
1130
1131 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1132 unsigned int device,
1133 struct pci_dev *from)
1134 {
1135 return NULL;
1136 }
1137
1138 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1139 unsigned int device,
1140 unsigned int ss_vendor,
1141 unsigned int ss_device,
1142 struct pci_dev *from)
1143 {
1144 return NULL;
1145 }
1146
1147 static inline struct pci_dev *pci_get_class(unsigned int class,
1148 struct pci_dev *from)
1149 {
1150 return NULL;
1151 }
1152
1153 #define pci_dev_present(ids) (0)
1154 #define no_pci_devices() (1)
1155 #define pci_dev_put(dev) do { } while (0)
1156
1157 static inline void pci_set_master(struct pci_dev *dev)
1158 { }
1159
1160 static inline int pci_enable_device(struct pci_dev *dev)
1161 {
1162 return -EIO;
1163 }
1164
1165 static inline void pci_disable_device(struct pci_dev *dev)
1166 { }
1167
1168 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1169 {
1170 return -EIO;
1171 }
1172
1173 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1174 {
1175 return -EIO;
1176 }
1177
1178 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1179 unsigned int size)
1180 {
1181 return -EIO;
1182 }
1183
1184 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1185 unsigned long mask)
1186 {
1187 return -EIO;
1188 }
1189
1190 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1191 {
1192 return -EBUSY;
1193 }
1194
1195 static inline int __pci_register_driver(struct pci_driver *drv,
1196 struct module *owner)
1197 {
1198 return 0;
1199 }
1200
1201 static inline int pci_register_driver(struct pci_driver *drv)
1202 {
1203 return 0;
1204 }
1205
1206 static inline void pci_unregister_driver(struct pci_driver *drv)
1207 { }
1208
1209 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1210 {
1211 return 0;
1212 }
1213
1214 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1215 int cap)
1216 {
1217 return 0;
1218 }
1219
1220 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1221 {
1222 return 0;
1223 }
1224
1225 /* Power management related routines */
1226 static inline int pci_save_state(struct pci_dev *dev)
1227 {
1228 return 0;
1229 }
1230
1231 static inline void pci_restore_state(struct pci_dev *dev)
1232 { }
1233
1234 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1235 {
1236 return 0;
1237 }
1238
1239 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1240 {
1241 return 0;
1242 }
1243
1244 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1245 pm_message_t state)
1246 {
1247 return PCI_D0;
1248 }
1249
1250 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1251 int enable)
1252 {
1253 return 0;
1254 }
1255
1256 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1257 {
1258 }
1259
1260 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1261 {
1262 }
1263
1264 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1265 {
1266 return 0;
1267 }
1268
1269 static inline void pci_disable_obff(struct pci_dev *dev)
1270 {
1271 }
1272
1273 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1274 {
1275 return -EIO;
1276 }
1277
1278 static inline void pci_release_regions(struct pci_dev *dev)
1279 { }
1280
1281 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1282
1283 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1284 { }
1285
1286 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1287 { }
1288
1289 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1290 { return NULL; }
1291
1292 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1293 unsigned int devfn)
1294 { return NULL; }
1295
1296 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1297 unsigned int devfn)
1298 { return NULL; }
1299
1300 static inline int pci_domain_nr(struct pci_bus *bus)
1301 { return 0; }
1302
1303 #define dev_is_pci(d) (false)
1304 #define dev_is_pf(d) (false)
1305 #define dev_num_vf(d) (0)
1306 #endif /* CONFIG_PCI */
1307
1308 /* Include architecture-dependent settings and functions */
1309
1310 #include <asm/pci.h>
1311
1312 #ifndef PCIBIOS_MAX_MEM_32
1313 #define PCIBIOS_MAX_MEM_32 (-1)
1314 #endif
1315
1316 /* these helpers provide future and backwards compatibility
1317 * for accessing popular PCI BAR info */
1318 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1319 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1320 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1321 #define pci_resource_len(dev,bar) \
1322 ((pci_resource_start((dev), (bar)) == 0 && \
1323 pci_resource_end((dev), (bar)) == \
1324 pci_resource_start((dev), (bar))) ? 0 : \
1325 \
1326 (pci_resource_end((dev), (bar)) - \
1327 pci_resource_start((dev), (bar)) + 1))
1328
1329 /* Similar to the helpers above, these manipulate per-pci_dev
1330 * driver-specific data. They are really just a wrapper around
1331 * the generic device structure functions of these calls.
1332 */
1333 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1334 {
1335 return dev_get_drvdata(&pdev->dev);
1336 }
1337
1338 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1339 {
1340 dev_set_drvdata(&pdev->dev, data);
1341 }
1342
1343 /* If you want to know what to call your pci_dev, ask this function.
1344 * Again, it's a wrapper around the generic device.
1345 */
1346 static inline const char *pci_name(const struct pci_dev *pdev)
1347 {
1348 return dev_name(&pdev->dev);
1349 }
1350
1351
1352 /* Some archs don't want to expose struct resource to userland as-is
1353 * in sysfs and /proc
1354 */
1355 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1356 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1357 const struct resource *rsrc, resource_size_t *start,
1358 resource_size_t *end)
1359 {
1360 *start = rsrc->start;
1361 *end = rsrc->end;
1362 }
1363 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1364
1365
1366 /*
1367 * The world is not perfect and supplies us with broken PCI devices.
1368 * For at least a part of these bugs we need a work-around, so both
1369 * generic (drivers/pci/quirks.c) and per-architecture code can define
1370 * fixup hooks to be called for particular buggy devices.
1371 */
1372
1373 struct pci_fixup {
1374 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1375 void (*hook)(struct pci_dev *dev);
1376 };
1377
1378 enum pci_fixup_pass {
1379 pci_fixup_early, /* Before probing BARs */
1380 pci_fixup_header, /* After reading configuration header */
1381 pci_fixup_final, /* Final phase of device fixups */
1382 pci_fixup_enable, /* pci_enable_device() time */
1383 pci_fixup_resume, /* pci_device_resume() */
1384 pci_fixup_suspend, /* pci_device_suspend */
1385 pci_fixup_resume_early, /* pci_device_resume_early() */
1386 };
1387
1388 /* Anonymous variables would be nice... */
1389 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1390 static const struct pci_fixup __pci_fixup_##name __used \
1391 __attribute__((__section__(#section))) = { vendor, device, hook };
1392 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1393 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1394 vendor##device##hook, vendor, device, hook)
1395 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1396 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1397 vendor##device##hook, vendor, device, hook)
1398 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1399 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1400 vendor##device##hook, vendor, device, hook)
1401 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1402 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1403 vendor##device##hook, vendor, device, hook)
1404 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1405 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1406 resume##vendor##device##hook, vendor, device, hook)
1407 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1408 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1409 resume_early##vendor##device##hook, vendor, device, hook)
1410 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1411 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1412 suspend##vendor##device##hook, vendor, device, hook)
1413
1414 #ifdef CONFIG_PCI_QUIRKS
1415 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1416 #else
1417 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1418 struct pci_dev *dev) {}
1419 #endif
1420
1421 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1422 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1423 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1424 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1425 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1426 const char *name);
1427 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1428
1429 extern int pci_pci_problems;
1430 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1431 #define PCIPCI_TRITON 2
1432 #define PCIPCI_NATOMA 4
1433 #define PCIPCI_VIAETBF 8
1434 #define PCIPCI_VSFX 16
1435 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1436 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1437
1438 extern unsigned long pci_cardbus_io_size;
1439 extern unsigned long pci_cardbus_mem_size;
1440 extern u8 __devinitdata pci_dfl_cache_line_size;
1441 extern u8 pci_cache_line_size;
1442
1443 extern unsigned long pci_hotplug_io_size;
1444 extern unsigned long pci_hotplug_mem_size;
1445
1446 int pcibios_add_platform_entries(struct pci_dev *dev);
1447 void pcibios_disable_device(struct pci_dev *dev);
1448 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1449 enum pcie_reset_state state);
1450
1451 #ifdef CONFIG_PCI_MMCONFIG
1452 extern void __init pci_mmcfg_early_init(void);
1453 extern void __init pci_mmcfg_late_init(void);
1454 #else
1455 static inline void pci_mmcfg_early_init(void) { }
1456 static inline void pci_mmcfg_late_init(void) { }
1457 #endif
1458
1459 int pci_ext_cfg_avail(struct pci_dev *dev);
1460
1461 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1462
1463 #ifdef CONFIG_PCI_IOV
1464 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1465 extern void pci_disable_sriov(struct pci_dev *dev);
1466 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1467 extern int pci_num_vf(struct pci_dev *dev);
1468 #else
1469 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1470 {
1471 return -ENODEV;
1472 }
1473 static inline void pci_disable_sriov(struct pci_dev *dev)
1474 {
1475 }
1476 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1477 {
1478 return IRQ_NONE;
1479 }
1480 static inline int pci_num_vf(struct pci_dev *dev)
1481 {
1482 return 0;
1483 }
1484 #endif
1485
1486 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1487 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1488 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1489 #endif
1490
1491 /**
1492 * pci_pcie_cap - get the saved PCIe capability offset
1493 * @dev: PCI device
1494 *
1495 * PCIe capability offset is calculated at PCI device initialization
1496 * time and saved in the data structure. This function returns saved
1497 * PCIe capability offset. Using this instead of pci_find_capability()
1498 * reduces unnecessary search in the PCI configuration space. If you
1499 * need to calculate PCIe capability offset from raw device for some
1500 * reasons, please use pci_find_capability() instead.
1501 */
1502 static inline int pci_pcie_cap(struct pci_dev *dev)
1503 {
1504 return dev->pcie_cap;
1505 }
1506
1507 /**
1508 * pci_is_pcie - check if the PCI device is PCI Express capable
1509 * @dev: PCI device
1510 *
1511 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1512 */
1513 static inline bool pci_is_pcie(struct pci_dev *dev)
1514 {
1515 return !!pci_pcie_cap(dev);
1516 }
1517
1518 void pci_request_acs(void);
1519
1520
1521 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1522 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1523
1524 /* Large Resource Data Type Tag Item Names */
1525 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1526 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1527 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1528
1529 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1530 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1531 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1532
1533 /* Small Resource Data Type Tag Item Names */
1534 #define PCI_VPD_STIN_END 0x78 /* End */
1535
1536 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1537
1538 #define PCI_VPD_SRDT_TIN_MASK 0x78
1539 #define PCI_VPD_SRDT_LEN_MASK 0x07
1540
1541 #define PCI_VPD_LRDT_TAG_SIZE 3
1542 #define PCI_VPD_SRDT_TAG_SIZE 1
1543
1544 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1545
1546 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1547 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1548 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1549 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1550
1551 /**
1552 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1553 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1554 *
1555 * Returns the extracted Large Resource Data Type length.
1556 */
1557 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1558 {
1559 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1560 }
1561
1562 /**
1563 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1564 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1565 *
1566 * Returns the extracted Small Resource Data Type length.
1567 */
1568 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1569 {
1570 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1571 }
1572
1573 /**
1574 * pci_vpd_info_field_size - Extracts the information field length
1575 * @lrdt: Pointer to the beginning of an information field header
1576 *
1577 * Returns the extracted information field length.
1578 */
1579 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1580 {
1581 return info_field[2];
1582 }
1583
1584 /**
1585 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1586 * @buf: Pointer to buffered vpd data
1587 * @off: The offset into the buffer at which to begin the search
1588 * @len: The length of the vpd buffer
1589 * @rdt: The Resource Data Type to search for
1590 *
1591 * Returns the index where the Resource Data Type was found or
1592 * -ENOENT otherwise.
1593 */
1594 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1595
1596 /**
1597 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1598 * @buf: Pointer to buffered vpd data
1599 * @off: The offset into the buffer at which to begin the search
1600 * @len: The length of the buffer area, relative to off, in which to search
1601 * @kw: The keyword to search for
1602 *
1603 * Returns the index where the information field keyword was found or
1604 * -ENOENT otherwise.
1605 */
1606 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1607 unsigned int len, const char *kw);
1608
1609 /* PCI <-> OF binding helpers */
1610 #ifdef CONFIG_OF
1611 struct device_node;
1612 extern void pci_set_of_node(struct pci_dev *dev);
1613 extern void pci_release_of_node(struct pci_dev *dev);
1614 extern void pci_set_bus_of_node(struct pci_bus *bus);
1615 extern void pci_release_bus_of_node(struct pci_bus *bus);
1616
1617 /* Arch may override this (weak) */
1618 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1619
1620 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1621 {
1622 return pdev ? pdev->dev.of_node : NULL;
1623 }
1624
1625 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1626 {
1627 return bus ? bus->dev.of_node : NULL;
1628 }
1629
1630 #else /* CONFIG_OF */
1631 static inline void pci_set_of_node(struct pci_dev *dev) { }
1632 static inline void pci_release_of_node(struct pci_dev *dev) { }
1633 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1634 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1635 #endif /* CONFIG_OF */
1636
1637 /**
1638 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1639 * @pdev: the PCI device
1640 *
1641 * if the device is PCIE, return NULL
1642 * if the device isn't connected to a PCIe bridge (that is its parent is a
1643 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1644 * parent
1645 */
1646 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1647
1648 #endif /* __KERNEL__ */
1649 #endif /* LINUX_PCI_H */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree