drivers/scsi/bfa/bfa_hw_cb.c

   1 /*
   2  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
   3  * All rights reserved
   4  * www.brocade.com
   5  *
   6  * Linux driver for Brocade Fibre Channel Host Bus Adapter.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License (GPL) Version 2 as
  10  * published by the Free Software Foundation
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  */
  17
  18 #include "bfad_drv.h"
  19 #include "bfa_modules.h"
  20 #include "bfi_reg.h"
  21
  22 void
  23 bfa_hwcb_reginit(struct bfa_s *bfa)
  24 {
  25         struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
  26         void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
  27         int     fn = bfa_ioc_pcifn(&bfa->ioc);
  28
  29         if (fn == 0) {
  30                 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
  31                 bfa_regs->intr_mask   = (kva + HOSTFN0_INT_MSK);
  32         } else {
  33                 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
  34                 bfa_regs->intr_mask   = (kva + HOSTFN1_INT_MSK);
  35         }
  36 }
  37
  38 void
  39 bfa_hwcb_reqq_ack(struct bfa_s *bfa, int reqq)
  40 {
  41 }
  42
  43 static void
  44 bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq)
  45 {
  46         writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq),
  47                         bfa->iocfc.bfa_regs.intr_status);
  48 }
  49
  50 void
  51 bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq)
  52 {
  53 }
  54
  55 static void
  56 bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq)
  57 {
  58         writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq),
  59                         bfa->iocfc.bfa_regs.intr_status);
  60 }
  61
  62 void
  63 bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
  64                  u32 *num_vecs, u32 *max_vec_bit)
  65 {
  66 #define __HFN_NUMINTS   13
  67         if (bfa_ioc_pcifn(&bfa->ioc) == 0) {
  68                 *msix_vecs_bmap = (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 |
  69                                    __HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 |
  70                                    __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 |
  71                                    __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 |
  72                                    __HFN_INT_MBOX_LPU0);
  73                 *max_vec_bit = __HFN_INT_MBOX_LPU0;
  74         } else {
  75                 *msix_vecs_bmap = (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 |
  76                                    __HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 |
  77                                    __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 |
  78                                    __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
  79                                    __HFN_INT_MBOX_LPU1);
  80                 *max_vec_bit = __HFN_INT_MBOX_LPU1;
  81         }
  82
  83         *msix_vecs_bmap |= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 |
  84                             __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS);
  85         *num_vecs = __HFN_NUMINTS;
  86 }
  87
  88 /*
  89  * Dummy interrupt handler for handling spurious interrupts.
  90  */
  91 static void
  92 bfa_hwcb_msix_dummy(struct bfa_s *bfa, int vec)
  93 {
  94 }
  95
  96 /*
  97  * No special setup required for crossbow -- vector assignments are implicit.
  98  */
  99 void
 100 bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs)
 101 {
 102         WARN_ON((nvecs != 1) && (nvecs != __HFN_NUMINTS));
 103
 104         bfa->msix.nvecs = nvecs;
 105         bfa_hwcb_msix_uninstall(bfa);
 106 }
 107
 108 void
 109 bfa_hwcb_msix_ctrl_install(struct bfa_s *bfa)
 110 {
 111         int i;
 112
 113         if (bfa->msix.nvecs == 0)
 114                 return;
 115
 116         if (bfa->msix.nvecs == 1) {
 117                 for (i = BFI_MSIX_RME_QMAX_CB+1; i < BFI_MSIX_CB_MAX; i++)
 118                         bfa->msix.handler[i] = bfa_msix_all;
 119                 return;
 120         }
 121
 122         for (i = BFI_MSIX_RME_QMAX_CB+1; i < BFI_MSIX_CB_MAX; i++)
 123                 bfa->msix.handler[i] = bfa_msix_lpu_err;
 124 }
 125
 126 void
 127 bfa_hwcb_msix_queue_install(struct bfa_s *bfa)
 128 {
 129         int i;
 130
 131         if (bfa->msix.nvecs == 0)
 132                 return;
 133
 134         if (bfa->msix.nvecs == 1) {
 135                 for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
 136                         bfa->msix.handler[i] = bfa_msix_all;
 137                 return;
 138         }
 139
 140         for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_CPE_QMAX_CB; i++)
 141                 bfa->msix.handler[i] = bfa_msix_reqq;
 142
 143         for (i = BFI_MSIX_RME_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
 144                 bfa->msix.handler[i] = bfa_msix_rspq;
 145 }
 146
 147 void
 148 bfa_hwcb_msix_uninstall(struct bfa_s *bfa)
 149 {
 150         int i;
 151
 152         for (i = 0; i < BFI_MSIX_CB_MAX; i++)
 153                 bfa->msix.handler[i] = bfa_hwcb_msix_dummy;
 154 }
 155
 156 /*
 157  * No special enable/disable -- vector assignments are implicit.
 158  */
 159 void
 160 bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
 161 {
 162         bfa->iocfc.hwif.hw_reqq_ack = bfa_hwcb_reqq_ack_msix;
 163         bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix;
 164 }
 165
 166 void
 167 bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
 168 {
 169         *start = BFI_MSIX_RME_QMIN_CB;
 170         *end = BFI_MSIX_RME_QMAX_CB;
 171 }