ARM: s3c64xx: convert to MULTI_IRQ_HANDLER
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-s3c64xx / mach-real6410.c
blobdbab49f2713e2c55e52f5b03714c405a3b6cbc00
1 /* linux/arch/arm/mach-s3c64xx/mach-real6410.c
3 * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/fb.h>
18 #include <linux/gpio.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/dm9000.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/platform_device.h>
25 #include <linux/serial_core.h>
26 #include <linux/types.h>
28 #include <asm/hardware/vic.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
33 #include <mach/map.h>
34 #include <mach/regs-gpio.h>
35 #include <mach/regs-modem.h>
36 #include <mach/regs-srom.h>
38 #include <plat/s3c6410.h>
39 #include <plat/adc.h>
40 #include <plat/cpu.h>
41 #include <plat/devs.h>
42 #include <plat/fb.h>
43 #include <plat/nand.h>
44 #include <plat/regs-serial.h>
45 #include <plat/ts.h>
46 #include <plat/regs-fb-v4.h>
48 #include <video/platform_lcd.h>
50 #define UCON S3C2410_UCON_DEFAULT
51 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
52 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
54 static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
55 [0] = {
56 .hwport = 0,
57 .flags = 0,
58 .ucon = UCON,
59 .ulcon = ULCON,
60 .ufcon = UFCON,
62 [1] = {
63 .hwport = 1,
64 .flags = 0,
65 .ucon = UCON,
66 .ulcon = ULCON,
67 .ufcon = UFCON,
69 [2] = {
70 .hwport = 2,
71 .flags = 0,
72 .ucon = UCON,
73 .ulcon = ULCON,
74 .ufcon = UFCON,
76 [3] = {
77 .hwport = 3,
78 .flags = 0,
79 .ucon = UCON,
80 .ulcon = ULCON,
81 .ufcon = UFCON,
85 /* DM9000AEP 10/100 ethernet controller */
87 static struct resource real6410_dm9k_resource[] = {
88 [0] = {
89 .start = S3C64XX_PA_XM0CSN1,
90 .end = S3C64XX_PA_XM0CSN1 + 1,
91 .flags = IORESOURCE_MEM
93 [1] = {
94 .start = S3C64XX_PA_XM0CSN1 + 4,
95 .end = S3C64XX_PA_XM0CSN1 + 5,
96 .flags = IORESOURCE_MEM
98 [2] = {
99 .start = S3C_EINT(7),
100 .end = S3C_EINT(7),
101 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
105 static struct dm9000_plat_data real6410_dm9k_pdata = {
106 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
109 static struct platform_device real6410_device_eth = {
110 .name = "dm9000",
111 .id = -1,
112 .num_resources = ARRAY_SIZE(real6410_dm9k_resource),
113 .resource = real6410_dm9k_resource,
114 .dev = {
115 .platform_data = &real6410_dm9k_pdata,
119 static struct s3c_fb_pd_win real6410_fb_win[] = {
121 .win_mode = { /* 4.3" 480x272 */
122 .left_margin = 3,
123 .right_margin = 2,
124 .upper_margin = 1,
125 .lower_margin = 1,
126 .hsync_len = 40,
127 .vsync_len = 1,
128 .xres = 480,
129 .yres = 272,
131 .max_bpp = 32,
132 .default_bpp = 16,
133 }, {
134 .win_mode = { /* 7.0" 800x480 */
135 .left_margin = 8,
136 .right_margin = 13,
137 .upper_margin = 7,
138 .lower_margin = 5,
139 .hsync_len = 3,
140 .vsync_len = 1,
141 .xres = 800,
142 .yres = 480,
144 .max_bpp = 32,
145 .default_bpp = 16,
149 static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
150 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
151 .win[0] = &real6410_fb_win[0],
152 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
153 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
156 static struct mtd_partition real6410_nand_part[] = {
157 [0] = {
158 .name = "uboot",
159 .size = SZ_1M,
160 .offset = 0,
162 [1] = {
163 .name = "kernel",
164 .size = SZ_2M,
165 .offset = SZ_1M,
167 [2] = {
168 .name = "rootfs",
169 .size = MTDPART_SIZ_FULL,
170 .offset = SZ_1M + SZ_2M,
174 static struct s3c2410_nand_set real6410_nand_sets[] = {
175 [0] = {
176 .name = "nand",
177 .nr_chips = 1,
178 .nr_partitions = ARRAY_SIZE(real6410_nand_part),
179 .partitions = real6410_nand_part,
183 static struct s3c2410_platform_nand real6410_nand_info = {
184 .tacls = 25,
185 .twrph0 = 55,
186 .twrph1 = 40,
187 .nr_sets = ARRAY_SIZE(real6410_nand_sets),
188 .sets = real6410_nand_sets,
191 static struct platform_device *real6410_devices[] __initdata = {
192 &real6410_device_eth,
193 &s3c_device_hsmmc0,
194 &s3c_device_hsmmc1,
195 &s3c_device_fb,
196 &s3c_device_nand,
197 &s3c_device_adc,
198 &s3c_device_ts,
199 &s3c_device_ohci,
202 static void __init real6410_map_io(void)
204 u32 tmp;
206 s3c64xx_init_io(NULL, 0);
207 s3c24xx_init_clocks(12000000);
208 s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
210 /* set the LCD type */
211 tmp = __raw_readl(S3C64XX_SPCON);
212 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
213 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
214 __raw_writel(tmp, S3C64XX_SPCON);
216 /* remove the LCD bypass */
217 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
218 tmp &= ~MIFPCON_LCD_BYPASS;
219 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
223 * real6410_features string
225 * 0-9 LCD configuration
228 static char real6410_features_str[12] __initdata = "0";
230 static int __init real6410_features_setup(char *str)
232 if (str)
233 strlcpy(real6410_features_str, str,
234 sizeof(real6410_features_str));
235 return 1;
238 __setup("real6410=", real6410_features_setup);
240 #define FEATURE_SCREEN (1 << 0)
242 struct real6410_features_t {
243 int done;
244 int lcd_index;
247 static void real6410_parse_features(
248 struct real6410_features_t *features,
249 const char *features_str)
251 const char *fp = features_str;
253 features->done = 0;
254 features->lcd_index = 0;
256 while (*fp) {
257 char f = *fp++;
259 switch (f) {
260 case '0'...'9': /* tft screen */
261 if (features->done & FEATURE_SCREEN) {
262 printk(KERN_INFO "REAL6410: '%c' ignored, "
263 "screen type already set\n", f);
264 } else {
265 int li = f - '0';
266 if (li >= ARRAY_SIZE(real6410_fb_win))
267 printk(KERN_INFO "REAL6410: '%c' out "
268 "of range LCD mode\n", f);
269 else {
270 features->lcd_index = li;
273 features->done |= FEATURE_SCREEN;
274 break;
279 static void __init real6410_machine_init(void)
281 u32 cs1;
282 struct real6410_features_t features = { 0 };
284 printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
285 real6410_features_str);
287 /* Parse the feature string */
288 real6410_parse_features(&features, real6410_features_str);
290 real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
292 printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
293 real6410_lcd_pdata.win[0]->win_mode.xres,
294 real6410_lcd_pdata.win[0]->win_mode.yres);
296 s3c_fb_set_platdata(&real6410_lcd_pdata);
297 s3c_nand_set_platdata(&real6410_nand_info);
298 s3c24xx_ts_set_platdata(NULL);
300 /* configure nCS1 width to 16 bits */
302 cs1 = __raw_readl(S3C64XX_SROM_BW) &
303 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
304 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
305 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
306 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
307 S3C64XX_SROM_BW__NCS1__SHIFT;
308 __raw_writel(cs1, S3C64XX_SROM_BW);
310 /* set timing for nCS1 suitable for ethernet chip */
312 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
313 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
314 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
315 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
316 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
317 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
318 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
320 gpio_request(S3C64XX_GPF(15), "LCD power");
322 platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
325 MACHINE_START(REAL6410, "REAL6410")
326 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
327 .atag_offset = 0x100,
329 .init_irq = s3c6410_init_irq,
330 .handle_irq = vic_handle_irq,
331 .map_io = real6410_map_io,
332 .init_machine = real6410_machine_init,
333 .timer = &s3c24xx_timer,
334 MACHINE_END