drivers/scsi/lpfc/lpfc_hw.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2004-2010 Emulex.  All rights reserved.           *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 #define FDMI_DID        0xfffffaU
  22 #define NameServer_DID  0xfffffcU
  23 #define SCR_DID         0xfffffdU
  24 #define Fabric_DID      0xfffffeU
  25 #define Bcast_DID       0xffffffU
  26 #define Mask_DID        0xffffffU
  27 #define CT_DID_MASK     0xffff00U
  28 #define Fabric_DID_MASK 0xfff000U
  29 #define WELL_KNOWN_DID_MASK 0xfffff0U
  30
  31 #define PT2PT_LocalID   1
  32 #define PT2PT_RemoteID  2
  33
  34 #define FF_DEF_EDTOV          2000      /* Default E_D_TOV (2000ms) */
  35 #define FF_DEF_ALTOV            15      /* Default AL_TIME (15ms) */
  36 #define FF_DEF_RATOV             2      /* Default RA_TOV (2s) */
  37 #define FF_DEF_ARBTOV         1900      /* Default ARB_TOV (1900ms) */
  38
  39 #define LPFC_BUF_RING0        64        /* Number of buffers to post to RING
  40                                            0 */
  41
  42 #define FCELSSIZE             1024      /* maximum ELS transfer size */
  43
  44 #define LPFC_FCP_RING            0      /* ring 0 for FCP initiator commands */
  45 #define LPFC_EXTRA_RING          1      /* ring 1 for other protocols */
  46 #define LPFC_ELS_RING            2      /* ring 2 for ELS commands */
  47 #define LPFC_FCP_NEXT_RING       3
  48
  49 #define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
  50 #define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
  51 #define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 extra command ring entries */
  52 #define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 extra response ring entries */
  53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  55 #define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
  56 #define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
  57 #define SLI2_IOCB_CMD_R3_ENTRIES      0
  58 #define SLI2_IOCB_RSP_R3_ENTRIES      0
  59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  61
  62 #define SLI2_IOCB_CMD_SIZE      32
  63 #define SLI2_IOCB_RSP_SIZE      32
  64 #define SLI3_IOCB_CMD_SIZE      128
  65 #define SLI3_IOCB_RSP_SIZE      64
  66
  67
  68 /* vendor ID used in SCSI netlink calls */
  69 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
  70
  71 /* Common Transport structures and definitions */
  72
  73 union CtRevisionId {
  74         /* Structure is in Big Endian format */
  75         struct {
  76                 uint32_t Revision:8;
  77                 uint32_t InId:24;
  78         } bits;
  79         uint32_t word;
  80 };
  81
  82 union CtCommandResponse {
  83         /* Structure is in Big Endian format */
  84         struct {
  85                 uint32_t CmdRsp:16;
  86                 uint32_t Size:16;
  87         } bits;
  88         uint32_t word;
  89 };
  90
  91 #define FC4_FEATURE_INIT 0x2
  92 #define FC4_FEATURE_TARGET 0x1
  93
  94 struct lpfc_sli_ct_request {
  95         /* Structure is in Big Endian format */
  96         union CtRevisionId RevisionId;
  97         uint8_t FsType;
  98         uint8_t FsSubType;
  99         uint8_t Options;
 100         uint8_t Rsrvd1;
 101         union CtCommandResponse CommandResponse;
 102         uint8_t Rsrvd2;
 103         uint8_t ReasonCode;
 104         uint8_t Explanation;
 105         uint8_t VendorUnique;
 106
 107         union {
 108                 uint32_t PortID;
 109                 struct gid {
 110                         uint8_t PortType;       /* for GID_PT requests */
 111                         uint8_t DomainScope;
 112                         uint8_t AreaScope;
 113                         uint8_t Fc4Type;        /* for GID_FT requests */
 114                 } gid;
 115                 struct rft {
 116                         uint32_t PortId;        /* For RFT_ID requests */
 117
 118 #ifdef __BIG_ENDIAN_BITFIELD
 119                         uint32_t rsvd0:16;
 120                         uint32_t rsvd1:7;
 121                         uint32_t fcpReg:1;      /* Type 8 */
 122                         uint32_t rsvd2:2;
 123                         uint32_t ipReg:1;       /* Type 5 */
 124                         uint32_t rsvd3:5;
 125 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 126                         uint32_t rsvd0:16;
 127                         uint32_t fcpReg:1;      /* Type 8 */
 128                         uint32_t rsvd1:7;
 129                         uint32_t rsvd3:5;
 130                         uint32_t ipReg:1;       /* Type 5 */
 131                         uint32_t rsvd2:2;
 132 #endif
 133
 134                         uint32_t rsvd[7];
 135                 } rft;
 136                 struct rnn {
 137                         uint32_t PortId;        /* For RNN_ID requests */
 138                         uint8_t wwnn[8];
 139                 } rnn;
 140                 struct rsnn {   /* For RSNN_ID requests */
 141                         uint8_t wwnn[8];
 142                         uint8_t len;
 143                         uint8_t symbname[255];
 144                 } rsnn;
 145                 struct da_id { /* For DA_ID requests */
 146                         uint32_t port_id;
 147                 } da_id;
 148                 struct rspn {   /* For RSPN_ID requests */
 149                         uint32_t PortId;
 150                         uint8_t len;
 151                         uint8_t symbname[255];
 152                 } rspn;
 153                 struct gff {
 154                         uint32_t PortId;
 155                 } gff;
 156                 struct gff_acc {
 157                         uint8_t fbits[128];
 158                 } gff_acc;
 159 #define FCP_TYPE_FEATURE_OFFSET 7
 160                 struct rff {
 161                         uint32_t PortId;
 162                         uint8_t reserved[2];
 163                         uint8_t fbits;
 164                         uint8_t type_code;     /* type=8 for FCP */
 165                 } rff;
 166         } un;
 167 };
 168
 169 #define  SLI_CT_REVISION        1
 170 #define  GID_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 171                            sizeof(struct gid))
 172 #define  GFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 173                            sizeof(struct gff))
 174 #define  RFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 175                            sizeof(struct rft))
 176 #define  RFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 177                            sizeof(struct rff))
 178 #define  RNN_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 179                            sizeof(struct rnn))
 180 #define  RSNN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
 181                            sizeof(struct rsnn))
 182 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
 183                           sizeof(struct da_id))
 184 #define  RSPN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
 185                            sizeof(struct rspn))
 186
 187 /*
 188  * FsType Definitions
 189  */
 190
 191 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
 192 #define  SLI_CT_TIME_SERVICE              0xFB
 193 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
 194 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
 195
 196 /*
 197  * Directory Service Subtypes
 198  */
 199
 200 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
 201
 202 /*
 203  * Response Codes
 204  */
 205
 206 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
 207 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
 208
 209 /*
 210  * Reason Codes
 211  */
 212
 213 #define  SLI_CT_NO_ADDITIONAL_EXPL        0x0
 214 #define  SLI_CT_INVALID_COMMAND           0x01
 215 #define  SLI_CT_INVALID_VERSION           0x02
 216 #define  SLI_CT_LOGICAL_ERROR             0x03
 217 #define  SLI_CT_INVALID_IU_SIZE           0x04
 218 #define  SLI_CT_LOGICAL_BUSY              0x05
 219 #define  SLI_CT_PROTOCOL_ERROR            0x07
 220 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
 221 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
 222 #define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
 223 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
 224 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
 225 #define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
 226 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
 227 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
 228 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
 229 #define  SLI_CT_VENDOR_UNIQUE             0xff
 230
 231 /*
 232  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
 233  */
 234
 235 #define  SLI_CT_NO_PORT_ID                0x01
 236 #define  SLI_CT_NO_PORT_NAME              0x02
 237 #define  SLI_CT_NO_NODE_NAME              0x03
 238 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
 239 #define  SLI_CT_NO_IP_ADDRESS             0x05
 240 #define  SLI_CT_NO_IPA                    0x06
 241 #define  SLI_CT_NO_FC4_TYPES              0x07
 242 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
 243 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
 244 #define  SLI_CT_NO_PORT_TYPE              0x0A
 245 #define  SLI_CT_ACCESS_DENIED             0x10
 246 #define  SLI_CT_INVALID_PORT_ID           0x11
 247 #define  SLI_CT_DATABASE_EMPTY            0x12
 248
 249 /*
 250  * Name Server Command Codes
 251  */
 252
 253 #define  SLI_CTNS_GA_NXT      0x0100
 254 #define  SLI_CTNS_GPN_ID      0x0112
 255 #define  SLI_CTNS_GNN_ID      0x0113
 256 #define  SLI_CTNS_GCS_ID      0x0114
 257 #define  SLI_CTNS_GFT_ID      0x0117
 258 #define  SLI_CTNS_GSPN_ID     0x0118
 259 #define  SLI_CTNS_GPT_ID      0x011A
 260 #define  SLI_CTNS_GFF_ID      0x011F
 261 #define  SLI_CTNS_GID_PN      0x0121
 262 #define  SLI_CTNS_GID_NN      0x0131
 263 #define  SLI_CTNS_GIP_NN      0x0135
 264 #define  SLI_CTNS_GIPA_NN     0x0136
 265 #define  SLI_CTNS_GSNN_NN     0x0139
 266 #define  SLI_CTNS_GNN_IP      0x0153
 267 #define  SLI_CTNS_GIPA_IP     0x0156
 268 #define  SLI_CTNS_GID_FT      0x0171
 269 #define  SLI_CTNS_GID_PT      0x01A1
 270 #define  SLI_CTNS_RPN_ID      0x0212
 271 #define  SLI_CTNS_RNN_ID      0x0213
 272 #define  SLI_CTNS_RCS_ID      0x0214
 273 #define  SLI_CTNS_RFT_ID      0x0217
 274 #define  SLI_CTNS_RSPN_ID     0x0218
 275 #define  SLI_CTNS_RPT_ID      0x021A
 276 #define  SLI_CTNS_RFF_ID      0x021F
 277 #define  SLI_CTNS_RIP_NN      0x0235
 278 #define  SLI_CTNS_RIPA_NN     0x0236
 279 #define  SLI_CTNS_RSNN_NN     0x0239
 280 #define  SLI_CTNS_DA_ID       0x0300
 281
 282 /*
 283  * Port Types
 284  */
 285
 286 #define  SLI_CTPT_N_PORT      0x01
 287 #define  SLI_CTPT_NL_PORT     0x02
 288 #define  SLI_CTPT_FNL_PORT    0x03
 289 #define  SLI_CTPT_IP          0x04
 290 #define  SLI_CTPT_FCP         0x08
 291 #define  SLI_CTPT_NX_PORT     0x7F
 292 #define  SLI_CTPT_F_PORT      0x81
 293 #define  SLI_CTPT_FL_PORT     0x82
 294 #define  SLI_CTPT_E_PORT      0x84
 295
 296 #define SLI_CT_LAST_ENTRY     0x80000000
 297
 298 /* Fibre Channel Service Parameter definitions */
 299
 300 #define FC_PH_4_0   6           /* FC-PH version 4.0 */
 301 #define FC_PH_4_1   7           /* FC-PH version 4.1 */
 302 #define FC_PH_4_2   8           /* FC-PH version 4.2 */
 303 #define FC_PH_4_3   9           /* FC-PH version 4.3 */
 304
 305 #define FC_PH_LOW   8           /* Lowest supported FC-PH version */
 306 #define FC_PH_HIGH  9           /* Highest supported FC-PH version */
 307 #define FC_PH3   0x20           /* FC-PH-3 version */
 308
 309 #define FF_FRAME_SIZE     2048
 310
 311 struct lpfc_name {
 312         union {
 313                 struct {
 314 #ifdef __BIG_ENDIAN_BITFIELD
 315                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 316                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 317                                                    8:11 of IEEE ext */
 318 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 319                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 320                                                    8:11 of IEEE ext */
 321                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 322 #endif
 323
 324 #define NAME_IEEE           0x1 /* IEEE name - nameType */
 325 #define NAME_IEEE_EXT       0x2 /* IEEE extended name */
 326 #define NAME_FC_TYPE        0x3 /* FC native name type */
 327 #define NAME_IP_TYPE        0x4 /* IP address */
 328 #define NAME_CCITT_TYPE     0xC
 329 #define NAME_CCITT_GR_TYPE  0xE
 330                         uint8_t IEEEextLsb;     /* FC Word 0, bit 16:23, IEEE
 331                                                    extended Lsb */
 332                         uint8_t IEEE[6];        /* FC IEEE address */
 333                 } s;
 334                 uint8_t wwn[8];
 335         } u;
 336 };
 337
 338 struct csp {
 339         uint8_t fcphHigh;       /* FC Word 0, byte 0 */
 340         uint8_t fcphLow;
 341         uint8_t bbCreditMsb;
 342         uint8_t bbCreditlsb;    /* FC Word 0, byte 3 */
 343
 344 #ifdef __BIG_ENDIAN_BITFIELD
 345         uint16_t request_multiple_Nport:1;      /* FC Word 1, bit 31 */
 346         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 347         uint16_t response_multiple_NPort:1;     /* FC Word 1, bit 29 */
 348         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 349         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 350         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 351         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 352         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 353
 354         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 355         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 356         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 357         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 358         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 359         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 360 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 361         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 362         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 363         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 364         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 365         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 366         uint16_t response_multiple_NPort:1;     /* FC Word 1, bit 29 */
 367         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 368         uint16_t request_multiple_Nport:1;      /* FC Word 1, bit 31 */
 369
 370         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 371         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 372         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 373         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 374         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 375         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 376 #endif
 377
 378         uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
 379         uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
 380         union {
 381                 struct {
 382                         uint8_t word2Reserved1; /* FC Word 2 byte 0 */
 383
 384                         uint8_t totalConcurrSeq;        /* FC Word 2 byte 1 */
 385                         uint8_t roByCategoryMsb;        /* FC Word 2 byte 2 */
 386
 387                         uint8_t roByCategoryLsb;        /* FC Word 2 byte 3 */
 388                 } nPort;
 389                 uint32_t r_a_tov;       /* R_A_TOV must be in B.E. format */
 390         } w2;
 391
 392         uint32_t e_d_tov;       /* E_D_TOV must be in B.E. format */
 393 };
 394
 395 struct class_parms {
 396 #ifdef __BIG_ENDIAN_BITFIELD
 397         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 398         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 399         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 400         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 401         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 402         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 403 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 404         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 405         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 406         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 407         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 408         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 409         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 410
 411 #endif
 412
 413         uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
 414
 415 #ifdef __BIG_ENDIAN_BITFIELD
 416         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 417         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 418         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 419         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 420         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 421 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 422         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 423         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 424         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 425         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 426         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 427 #endif
 428
 429         uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
 430
 431 #ifdef __BIG_ENDIAN_BITFIELD
 432         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 433         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 434         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 435         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 436         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 437         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 438 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 439         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 440         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 441         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 442         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 443         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 444         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 445 #endif
 446
 447         uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
 448         uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
 449         uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
 450
 451         uint8_t concurrentSeqMsb;       /* FC Word 2, bit 24:31 */
 452         uint8_t concurrentSeqLsb;       /* FC Word 2, bit 16:23 */
 453         uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
 454         uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
 455
 456         uint8_t openSeqPerXchgMsb;      /* FC Word 3, bit 24:31 */
 457         uint8_t openSeqPerXchgLsb;      /* FC Word 3, bit 16:23 */
 458         uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
 459         uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
 460 };
 461
 462 struct serv_parm {      /* Structure is in Big Endian format */
 463         struct csp cmn;
 464         struct lpfc_name portName;
 465         struct lpfc_name nodeName;
 466         struct class_parms cls1;
 467         struct class_parms cls2;
 468         struct class_parms cls3;
 469         struct class_parms cls4;
 470         uint8_t vendorVersion[16];
 471 };
 472
 473 /*
 474  * Virtual Fabric Tagging Header
 475  */
 476 struct fc_vft_header {
 477          uint32_t word0;
 478 #define fc_vft_hdr_r_ctl_SHIFT          24
 479 #define fc_vft_hdr_r_ctl_MASK           0xFF
 480 #define fc_vft_hdr_r_ctl_WORD           word0
 481 #define fc_vft_hdr_ver_SHIFT            22
 482 #define fc_vft_hdr_ver_MASK             0x3
 483 #define fc_vft_hdr_ver_WORD             word0
 484 #define fc_vft_hdr_type_SHIFT           18
 485 #define fc_vft_hdr_type_MASK            0xF
 486 #define fc_vft_hdr_type_WORD            word0
 487 #define fc_vft_hdr_e_SHIFT              16
 488 #define fc_vft_hdr_e_MASK               0x1
 489 #define fc_vft_hdr_e_WORD               word0
 490 #define fc_vft_hdr_priority_SHIFT       13
 491 #define fc_vft_hdr_priority_MASK        0x7
 492 #define fc_vft_hdr_priority_WORD        word0
 493 #define fc_vft_hdr_vf_id_SHIFT          1
 494 #define fc_vft_hdr_vf_id_MASK           0xFFF
 495 #define fc_vft_hdr_vf_id_WORD           word0
 496         uint32_t word1;
 497 #define fc_vft_hdr_hopct_SHIFT          24
 498 #define fc_vft_hdr_hopct_MASK           0xFF
 499 #define fc_vft_hdr_hopct_WORD           word1
 500 };
 501
 502 /*
 503  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
 504  */
 505 #ifdef __BIG_ENDIAN_BITFIELD
 506 #define ELS_CMD_MASK      0xffff0000
 507 #define ELS_RSP_MASK      0xff000000
 508 #define ELS_CMD_LS_RJT    0x01000000
 509 #define ELS_CMD_ACC       0x02000000
 510 #define ELS_CMD_PLOGI     0x03000000
 511 #define ELS_CMD_FLOGI     0x04000000
 512 #define ELS_CMD_LOGO      0x05000000
 513 #define ELS_CMD_ABTX      0x06000000
 514 #define ELS_CMD_RCS       0x07000000
 515 #define ELS_CMD_RES       0x08000000
 516 #define ELS_CMD_RSS       0x09000000
 517 #define ELS_CMD_RSI       0x0A000000
 518 #define ELS_CMD_ESTS      0x0B000000
 519 #define ELS_CMD_ESTC      0x0C000000
 520 #define ELS_CMD_ADVC      0x0D000000
 521 #define ELS_CMD_RTV       0x0E000000
 522 #define ELS_CMD_RLS       0x0F000000
 523 #define ELS_CMD_ECHO      0x10000000
 524 #define ELS_CMD_TEST      0x11000000
 525 #define ELS_CMD_RRQ       0x12000000
 526 #define ELS_CMD_PRLI      0x20100014
 527 #define ELS_CMD_PRLO      0x21100014
 528 #define ELS_CMD_PRLO_ACC  0x02100014
 529 #define ELS_CMD_PDISC     0x50000000
 530 #define ELS_CMD_FDISC     0x51000000
 531 #define ELS_CMD_ADISC     0x52000000
 532 #define ELS_CMD_FARP      0x54000000
 533 #define ELS_CMD_FARPR     0x55000000
 534 #define ELS_CMD_RPS       0x56000000
 535 #define ELS_CMD_RPL       0x57000000
 536 #define ELS_CMD_FAN       0x60000000
 537 #define ELS_CMD_RSCN      0x61040000
 538 #define ELS_CMD_SCR       0x62000000
 539 #define ELS_CMD_RNID      0x78000000
 540 #define ELS_CMD_LIRR      0x7A000000
 541 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 542 #define ELS_CMD_MASK      0xffff
 543 #define ELS_RSP_MASK      0xff
 544 #define ELS_CMD_LS_RJT    0x01
 545 #define ELS_CMD_ACC       0x02
 546 #define ELS_CMD_PLOGI     0x03
 547 #define ELS_CMD_FLOGI     0x04
 548 #define ELS_CMD_LOGO      0x05
 549 #define ELS_CMD_ABTX      0x06
 550 #define ELS_CMD_RCS       0x07
 551 #define ELS_CMD_RES       0x08
 552 #define ELS_CMD_RSS       0x09
 553 #define ELS_CMD_RSI       0x0A
 554 #define ELS_CMD_ESTS      0x0B
 555 #define ELS_CMD_ESTC      0x0C
 556 #define ELS_CMD_ADVC      0x0D
 557 #define ELS_CMD_RTV       0x0E
 558 #define ELS_CMD_RLS       0x0F
 559 #define ELS_CMD_ECHO      0x10
 560 #define ELS_CMD_TEST      0x11
 561 #define ELS_CMD_RRQ       0x12
 562 #define ELS_CMD_PRLI      0x14001020
 563 #define ELS_CMD_PRLO      0x14001021
 564 #define ELS_CMD_PRLO_ACC  0x14001002
 565 #define ELS_CMD_PDISC     0x50
 566 #define ELS_CMD_FDISC     0x51
 567 #define ELS_CMD_ADISC     0x52
 568 #define ELS_CMD_FARP      0x54
 569 #define ELS_CMD_FARPR     0x55
 570 #define ELS_CMD_RPS       0x56
 571 #define ELS_CMD_RPL       0x57
 572 #define ELS_CMD_FAN       0x60
 573 #define ELS_CMD_RSCN      0x0461
 574 #define ELS_CMD_SCR       0x62
 575 #define ELS_CMD_RNID      0x78
 576 #define ELS_CMD_LIRR      0x7A
 577 #endif
 578
 579 /*
 580  *  LS_RJT Payload Definition
 581  */
 582
 583 struct ls_rjt { /* Structure is in Big Endian format */
 584         union {
 585                 uint32_t lsRjtError;
 586                 struct {
 587                         uint8_t lsRjtRsvd0;     /* FC Word 0, bit 24:31 */
 588
 589                         uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
 590                         /* LS_RJT reason codes */
 591 #define LSRJT_INVALID_CMD     0x01
 592 #define LSRJT_LOGICAL_ERR     0x03
 593 #define LSRJT_LOGICAL_BSY     0x05
 594 #define LSRJT_PROTOCOL_ERR    0x07
 595 #define LSRJT_UNABLE_TPC      0x09      /* Unable to perform command */
 596 #define LSRJT_CMD_UNSUPPORTED 0x0B
 597 #define LSRJT_VENDOR_UNIQUE   0xFF      /* See Byte 3 */
 598
 599                         uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
 600                         /* LS_RJT reason explanation */
 601 #define LSEXP_NOTHING_MORE      0x00
 602 #define LSEXP_SPARM_OPTIONS     0x01
 603 #define LSEXP_SPARM_ICTL        0x03
 604 #define LSEXP_SPARM_RCTL        0x05
 605 #define LSEXP_SPARM_RCV_SIZE    0x07
 606 #define LSEXP_SPARM_CONCUR_SEQ  0x09
 607 #define LSEXP_SPARM_CREDIT      0x0B
 608 #define LSEXP_INVALID_PNAME     0x0D
 609 #define LSEXP_INVALID_NNAME     0x0E
 610 #define LSEXP_INVALID_CSP       0x0F
 611 #define LSEXP_INVALID_ASSOC_HDR 0x11
 612 #define LSEXP_ASSOC_HDR_REQ     0x13
 613 #define LSEXP_INVALID_O_SID     0x15
 614 #define LSEXP_INVALID_OX_RX     0x17
 615 #define LSEXP_CMD_IN_PROGRESS   0x19
 616 #define LSEXP_PORT_LOGIN_REQ    0x1E
 617 #define LSEXP_INVALID_NPORT_ID  0x1F
 618 #define LSEXP_INVALID_SEQ_ID    0x21
 619 #define LSEXP_INVALID_XCHG      0x23
 620 #define LSEXP_INACTIVE_XCHG     0x25
 621 #define LSEXP_RQ_REQUIRED       0x27
 622 #define LSEXP_OUT_OF_RESOURCE   0x29
 623 #define LSEXP_CANT_GIVE_DATA    0x2A
 624 #define LSEXP_REQ_UNSUPPORTED   0x2C
 625                         uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
 626                 } b;
 627         } un;
 628 };
 629
 630 /*
 631  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
 632  */
 633
 634 typedef struct _LOGO {          /* Structure is in Big Endian format */
 635         union {
 636                 uint32_t nPortId32;     /* Access nPortId as a word */
 637                 struct {
 638                         uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
 639                         uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
 640                         uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
 641                         uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
 642                 } b;
 643         } un;
 644         struct lpfc_name portName;      /* N_port name field */
 645 } LOGO;
 646
 647 /*
 648  *  FCP Login (PRLI Request / ACC) Payload Definition
 649  */
 650
 651 #define PRLX_PAGE_LEN   0x10
 652 #define TPRLO_PAGE_LEN  0x14
 653
 654 typedef struct _PRLI {          /* Structure is in Big Endian format */
 655         uint8_t prliType;       /* FC Parm Word 0, bit 24:31 */
 656
 657 #define PRLI_FCP_TYPE 0x08
 658         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 659
 660 #ifdef __BIG_ENDIAN_BITFIELD
 661         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 662         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 663         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 664
 665         /*    ACC = imagePairEstablished */
 666         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 667         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 668 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 669         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 670         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 671         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 672         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 673         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 674         /*    ACC = imagePairEstablished */
 675 #endif
 676
 677 #define PRLI_REQ_EXECUTED     0x1       /* acceptRspCode */
 678 #define PRLI_NO_RESOURCES     0x2
 679 #define PRLI_INIT_INCOMPLETE  0x3
 680 #define PRLI_NO_SUCH_PA       0x4
 681 #define PRLI_PREDEF_CONFIG    0x5
 682 #define PRLI_PARTIAL_SUCCESS  0x6
 683 #define PRLI_INVALID_PAGE_CNT 0x7
 684         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 685
 686         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 687
 688         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 689
 690         uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
 691         uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
 692
 693 #ifdef __BIG_ENDIAN_BITFIELD
 694         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 695         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 696         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 697         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 698         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 699         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 700         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 701         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 702         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 703         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 704         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 705         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 706         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 707         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 708         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 709         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 710 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 711         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 712         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 713         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 714         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 715         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 716         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 717         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 718         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 719         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 720         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 721         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 722         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 723         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 724         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 725         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 726         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 727 #endif
 728 } PRLI;
 729
 730 /*
 731  *  FCP Logout (PRLO Request / ACC) Payload Definition
 732  */
 733
 734 typedef struct _PRLO {          /* Structure is in Big Endian format */
 735         uint8_t prloType;       /* FC Parm Word 0, bit 24:31 */
 736
 737 #define PRLO_FCP_TYPE  0x08
 738         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 739
 740 #ifdef __BIG_ENDIAN_BITFIELD
 741         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 742         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 743         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 744         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 745 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 746         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 747         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 748         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 749         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 750 #endif
 751
 752 #define PRLO_REQ_EXECUTED     0x1       /* acceptRspCode */
 753 #define PRLO_NO_SUCH_IMAGE    0x4
 754 #define PRLO_INVALID_PAGE_CNT 0x7
 755
 756         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 757
 758         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 759
 760         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 761
 762         uint32_t word3Reserved1;        /* FC Parm Word 3, bit 0:31 */
 763 } PRLO;
 764
 765 typedef struct _ADISC {         /* Structure is in Big Endian format */
 766         uint32_t hardAL_PA;
 767         struct lpfc_name portName;
 768         struct lpfc_name nodeName;
 769         uint32_t DID;
 770 } ADISC;
 771
 772 typedef struct _FARP {          /* Structure is in Big Endian format */
 773         uint32_t Mflags:8;
 774         uint32_t Odid:24;
 775 #define FARP_NO_ACTION          0       /* FARP information enclosed, no
 776                                            action */
 777 #define FARP_MATCH_PORT         0x1     /* Match on Responder Port Name */
 778 #define FARP_MATCH_NODE         0x2     /* Match on Responder Node Name */
 779 #define FARP_MATCH_IP           0x4     /* Match on IP address, not supported */
 780 #define FARP_MATCH_IPV4         0x5     /* Match on IPV4 address, not
 781                                            supported */
 782 #define FARP_MATCH_IPV6         0x6     /* Match on IPV6 address, not
 783                                            supported */
 784         uint32_t Rflags:8;
 785         uint32_t Rdid:24;
 786 #define FARP_REQUEST_PLOGI      0x1     /* Request for PLOGI */
 787 #define FARP_REQUEST_FARPR      0x2     /* Request for FARP Response */
 788         struct lpfc_name OportName;
 789         struct lpfc_name OnodeName;
 790         struct lpfc_name RportName;
 791         struct lpfc_name RnodeName;
 792         uint8_t Oipaddr[16];
 793         uint8_t Ripaddr[16];
 794 } FARP;
 795
 796 typedef struct _FAN {           /* Structure is in Big Endian format */
 797         uint32_t Fdid;
 798         struct lpfc_name FportName;
 799         struct lpfc_name FnodeName;
 800 } FAN;
 801
 802 typedef struct _SCR {           /* Structure is in Big Endian format */
 803         uint8_t resvd1;
 804         uint8_t resvd2;
 805         uint8_t resvd3;
 806         uint8_t Function;
 807 #define  SCR_FUNC_FABRIC     0x01
 808 #define  SCR_FUNC_NPORT      0x02
 809 #define  SCR_FUNC_FULL       0x03
 810 #define  SCR_CLEAR           0xff
 811 } SCR;
 812
 813 typedef struct _RNID_TOP_DISC {
 814         struct lpfc_name portName;
 815         uint8_t resvd[8];
 816         uint32_t unitType;
 817 #define RNID_HBA            0x7
 818 #define RNID_HOST           0xa
 819 #define RNID_DRIVER         0xd
 820         uint32_t physPort;
 821         uint32_t attachedNodes;
 822         uint16_t ipVersion;
 823 #define RNID_IPV4           0x1
 824 #define RNID_IPV6           0x2
 825         uint16_t UDPport;
 826         uint8_t ipAddr[16];
 827         uint16_t resvd1;
 828         uint16_t flags;
 829 #define RNID_TD_SUPPORT     0x1
 830 #define RNID_LP_VALID       0x2
 831 } RNID_TOP_DISC;
 832
 833 typedef struct _RNID {          /* Structure is in Big Endian format */
 834         uint8_t Format;
 835 #define RNID_TOPOLOGY_DISC  0xdf
 836         uint8_t CommonLen;
 837         uint8_t resvd1;
 838         uint8_t SpecificLen;
 839         struct lpfc_name portName;
 840         struct lpfc_name nodeName;
 841         union {
 842                 RNID_TOP_DISC topologyDisc;     /* topology disc (0xdf) */
 843         } un;
 844 } RNID;
 845
 846 typedef struct  _RPS {          /* Structure is in Big Endian format */
 847         union {
 848                 uint32_t portNum;
 849                 struct lpfc_name portName;
 850         } un;
 851 } RPS;
 852
 853 typedef struct  _RPS_RSP {      /* Structure is in Big Endian format */
 854         uint16_t rsvd1;
 855         uint16_t portStatus;
 856         uint32_t linkFailureCnt;
 857         uint32_t lossSyncCnt;
 858         uint32_t lossSignalCnt;
 859         uint32_t primSeqErrCnt;
 860         uint32_t invalidXmitWord;
 861         uint32_t crcCnt;
 862 } RPS_RSP;
 863
 864 struct RLS {                    /* Structure is in Big Endian format */
 865         uint32_t rls;
 866 #define rls_rsvd_SHIFT          24
 867 #define rls_rsvd_MASK           0x000000ff
 868 #define rls_rsvd_WORD           rls
 869 #define rls_did_SHIFT           0
 870 #define rls_did_MASK            0x00ffffff
 871 #define rls_did_WORD            rls
 872 };
 873
 874 struct  RLS_RSP {               /* Structure is in Big Endian format */
 875         uint32_t linkFailureCnt;
 876         uint32_t lossSyncCnt;
 877         uint32_t lossSignalCnt;
 878         uint32_t primSeqErrCnt;
 879         uint32_t invalidXmitWord;
 880         uint32_t crcCnt;
 881 };
 882
 883 struct RTV_RSP {                /* Structure is in Big Endian format */
 884         uint32_t ratov;
 885         uint32_t edtov;
 886         uint32_t qtov;
 887 #define qtov_rsvd0_SHIFT        28
 888 #define qtov_rsvd0_MASK         0x0000000f
 889 #define qtov_rsvd0_WORD         qtov            /* reserved */
 890 #define qtov_edtovres_SHIFT     27
 891 #define qtov_edtovres_MASK      0x00000001
 892 #define qtov_edtovres_WORD      qtov            /* E_D_TOV Resolution */
 893 #define qtov__rsvd1_SHIFT       19
 894 #define qtov_rsvd1_MASK         0x0000003f
 895 #define qtov_rsvd1_WORD         qtov            /* reserved */
 896 #define qtov_rttov_SHIFT        18
 897 #define qtov_rttov_MASK         0x00000001
 898 #define qtov_rttov_WORD         qtov            /* R_T_TOV value */
 899 #define qtov_rsvd2_SHIFT        0
 900 #define qtov_rsvd2_MASK         0x0003ffff
 901 #define qtov_rsvd2_WORD         qtov            /* reserved */
 902 };
 903
 904
 905 typedef struct  _RPL {          /* Structure is in Big Endian format */
 906         uint32_t maxsize;
 907         uint32_t index;
 908 } RPL;
 909
 910 typedef struct  _PORT_NUM_BLK {
 911         uint32_t portNum;
 912         uint32_t portID;
 913         struct lpfc_name portName;
 914 } PORT_NUM_BLK;
 915
 916 typedef struct  _RPL_RSP {      /* Structure is in Big Endian format */
 917         uint32_t listLen;
 918         uint32_t index;
 919         PORT_NUM_BLK port_num_blk;
 920 } RPL_RSP;
 921
 922 /* This is used for RSCN command */
 923 typedef struct _D_ID {          /* Structure is in Big Endian format */
 924         union {
 925                 uint32_t word;
 926                 struct {
 927 #ifdef __BIG_ENDIAN_BITFIELD
 928                         uint8_t resv;
 929                         uint8_t domain;
 930                         uint8_t area;
 931                         uint8_t id;
 932 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 933                         uint8_t id;
 934                         uint8_t area;
 935                         uint8_t domain;
 936                         uint8_t resv;
 937 #endif
 938                 } b;
 939         } un;
 940 } D_ID;
 941
 942 #define RSCN_ADDRESS_FORMAT_PORT        0x0
 943 #define RSCN_ADDRESS_FORMAT_AREA        0x1
 944 #define RSCN_ADDRESS_FORMAT_DOMAIN      0x2
 945 #define RSCN_ADDRESS_FORMAT_FABRIC      0x3
 946 #define RSCN_ADDRESS_FORMAT_MASK        0x3
 947
 948 /*
 949  *  Structure to define all ELS Payload types
 950  */
 951
 952 typedef struct _ELS_PKT {       /* Structure is in Big Endian format */
 953         uint8_t elsCode;        /* FC Word 0, bit 24:31 */
 954         uint8_t elsByte1;
 955         uint8_t elsByte2;
 956         uint8_t elsByte3;
 957         union {
 958                 struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
 959                 struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
 960                 LOGO logo;      /* Payload for PLOGO/FLOGO/ACC */
 961                 PRLI prli;      /* Payload for PRLI/ACC */
 962                 PRLO prlo;      /* Payload for PRLO/ACC */
 963                 ADISC adisc;    /* Payload for ADISC/ACC */
 964                 FARP farp;      /* Payload for FARP/ACC */
 965                 FAN fan;        /* Payload for FAN */
 966                 SCR scr;        /* Payload for SCR/ACC */
 967                 RNID rnid;      /* Payload for RNID */
 968                 uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
 969         } un;
 970 } ELS_PKT;
 971
 972 /*
 973  * FDMI
 974  * HBA MAnagement Operations Command Codes
 975  */
 976 #define  SLI_MGMT_GRHL     0x100        /* Get registered HBA list */
 977 #define  SLI_MGMT_GHAT     0x101        /* Get HBA attributes */
 978 #define  SLI_MGMT_GRPL     0x102        /* Get registered Port list */
 979 #define  SLI_MGMT_GPAT     0x110        /* Get Port attributes */
 980 #define  SLI_MGMT_RHBA     0x200        /* Register HBA */
 981 #define  SLI_MGMT_RHAT     0x201        /* Register HBA atttributes */
 982 #define  SLI_MGMT_RPRT     0x210        /* Register Port */
 983 #define  SLI_MGMT_RPA      0x211        /* Register Port attributes */
 984 #define  SLI_MGMT_DHBA     0x300        /* De-register HBA */
 985 #define  SLI_MGMT_DPRT     0x310        /* De-register Port */
 986
 987 /*
 988  * Management Service Subtypes
 989  */
 990 #define  SLI_CT_FDMI_Subtypes     0x10
 991
 992 /*
 993  * HBA Management Service Reject Code
 994  */
 995 #define  REJECT_CODE             0x9    /* Unable to perform command request */
 996
 997 /*
 998  * HBA Management Service Reject Reason Code
 999  * Please refer to the Reason Codes above
1000  */
1001
1002 /*
1003  * HBA Attribute Types
1004  */
1005 #define  NODE_NAME               0x1
1006 #define  MANUFACTURER            0x2
1007 #define  SERIAL_NUMBER           0x3
1008 #define  MODEL                   0x4
1009 #define  MODEL_DESCRIPTION       0x5
1010 #define  HARDWARE_VERSION        0x6
1011 #define  DRIVER_VERSION          0x7
1012 #define  OPTION_ROM_VERSION      0x8
1013 #define  FIRMWARE_VERSION        0x9
1014 #define  OS_NAME_VERSION         0xa
1015 #define  MAX_CT_PAYLOAD_LEN      0xb
1016
1017 /*
1018  * Port Attrubute Types
1019  */
1020 #define  SUPPORTED_FC4_TYPES     0x1
1021 #define  SUPPORTED_SPEED         0x2
1022 #define  PORT_SPEED              0x3
1023 #define  MAX_FRAME_SIZE          0x4
1024 #define  OS_DEVICE_NAME          0x5
1025 #define  HOST_NAME               0x6
1026
1027 union AttributesDef {
1028         /* Structure is in Big Endian format */
1029         struct {
1030                 uint32_t AttrType:16;
1031                 uint32_t AttrLen:16;
1032         } bits;
1033         uint32_t word;
1034 };
1035
1036
1037 /*
1038  * HBA Attribute Entry (8 - 260 bytes)
1039  */
1040 typedef struct {
1041         union AttributesDef ad;
1042         union {
1043                 uint32_t VendorSpecific;
1044                 uint8_t Manufacturer[64];
1045                 uint8_t SerialNumber[64];
1046                 uint8_t Model[256];
1047                 uint8_t ModelDescription[256];
1048                 uint8_t HardwareVersion[256];
1049                 uint8_t DriverVersion[256];
1050                 uint8_t OptionROMVersion[256];
1051                 uint8_t FirmwareVersion[256];
1052                 struct lpfc_name NodeName;
1053                 uint8_t SupportFC4Types[32];
1054                 uint32_t SupportSpeed;
1055                 uint32_t PortSpeed;
1056                 uint32_t MaxFrameSize;
1057                 uint8_t OsDeviceName[256];
1058                 uint8_t OsNameVersion[256];
1059                 uint32_t MaxCTPayloadLen;
1060                 uint8_t HostName[256];
1061         } un;
1062 } ATTRIBUTE_ENTRY;
1063
1064 /*
1065  * HBA Attribute Block
1066  */
1067 typedef struct {
1068         uint32_t EntryCnt;      /* Number of HBA attribute entries */
1069         ATTRIBUTE_ENTRY Entry;  /* Variable-length array */
1070 } ATTRIBUTE_BLOCK;
1071
1072 /*
1073  * Port Entry
1074  */
1075 typedef struct {
1076         struct lpfc_name PortName;
1077 } PORT_ENTRY;
1078
1079 /*
1080  * HBA Identifier
1081  */
1082 typedef struct {
1083         struct lpfc_name PortName;
1084 } HBA_IDENTIFIER;
1085
1086 /*
1087  * Registered Port List Format
1088  */
1089 typedef struct {
1090         uint32_t EntryCnt;
1091         PORT_ENTRY pe;          /* Variable-length array */
1092 } REG_PORT_LIST;
1093
1094 /*
1095  * Register HBA(RHBA)
1096  */
1097 typedef struct {
1098         HBA_IDENTIFIER hi;
1099         REG_PORT_LIST rpl;      /* variable-length array */
1100 /* ATTRIBUTE_BLOCK   ab; */
1101 } REG_HBA;
1102
1103 /*
1104  * Register HBA Attributes (RHAT)
1105  */
1106 typedef struct {
1107         struct lpfc_name HBA_PortName;
1108         ATTRIBUTE_BLOCK ab;
1109 } REG_HBA_ATTRIBUTE;
1110
1111 /*
1112  * Register Port Attributes (RPA)
1113  */
1114 typedef struct {
1115         struct lpfc_name PortName;
1116         ATTRIBUTE_BLOCK ab;
1117 } REG_PORT_ATTRIBUTE;
1118
1119 /*
1120  * Get Registered HBA List (GRHL) Accept Payload Format
1121  */
1122 typedef struct {
1123         uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1124         struct lpfc_name HBA_PortName;  /* Variable-length array */
1125 } GRHL_ACC_PAYLOAD;
1126
1127 /*
1128  * Get Registered Port List (GRPL) Accept Payload Format
1129  */
1130 typedef struct {
1131         uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1132         PORT_ENTRY Reg_Port_Entry[1];   /* Variable-length array */
1133 } GRPL_ACC_PAYLOAD;
1134
1135 /*
1136  * Get Port Attributes (GPAT) Accept Payload Format
1137  */
1138
1139 typedef struct {
1140         ATTRIBUTE_BLOCK pab;
1141 } GPAT_ACC_PAYLOAD;
1142
1143
1144 /*
1145  *  Begin HBA configuration parameters.
1146  *  The PCI configuration register BAR assignments are:
1147  *  BAR0, offset 0x10 - SLIM base memory address
1148  *  BAR1, offset 0x14 - SLIM base memory high address
1149  *  BAR2, offset 0x18 - REGISTER base memory address
1150  *  BAR3, offset 0x1c - REGISTER base memory high address
1151  *  BAR4, offset 0x20 - BIU I/O registers
1152  *  BAR5, offset 0x24 - REGISTER base io high address
1153  */
1154
1155 /* Number of rings currently used and available. */
1156 #define MAX_CONFIGURED_RINGS     3
1157 #define MAX_RINGS                4
1158
1159 /* IOCB / Mailbox is owned by FireFly */
1160 #define OWN_CHIP        1
1161
1162 /* IOCB / Mailbox is owned by Host */
1163 #define OWN_HOST        0
1164
1165 /* Number of 4-byte words in an IOCB. */
1166 #define IOCB_WORD_SZ    8
1167
1168 /* network headers for Dfctl field */
1169 #define FC_NET_HDR      0x20
1170
1171 /* Start FireFly Register definitions */
1172 #define PCI_VENDOR_ID_EMULEX        0x10df
1173 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1174 #define PCI_DEVICE_ID_PROTEUS_VF    0xe100
1175 #define PCI_DEVICE_ID_BALIUS        0xe131
1176 #define PCI_DEVICE_ID_PROTEUS_PF    0xe180
1177 #define PCI_DEVICE_ID_LANCER_FC     0xe200
1178 #define PCI_DEVICE_ID_LANCER_FCOE   0xe260
1179 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1180 #define PCI_DEVICE_ID_SAT_MID       0xf015
1181 #define PCI_DEVICE_ID_RFLY          0xf095
1182 #define PCI_DEVICE_ID_PFLY          0xf098
1183 #define PCI_DEVICE_ID_LP101         0xf0a1
1184 #define PCI_DEVICE_ID_TFLY          0xf0a5
1185 #define PCI_DEVICE_ID_BSMB          0xf0d1
1186 #define PCI_DEVICE_ID_BMID          0xf0d5
1187 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1188 #define PCI_DEVICE_ID_ZMID          0xf0e5
1189 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1190 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1191 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1192 #define PCI_DEVICE_ID_SAT           0xf100
1193 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1194 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1195 #define PCI_DEVICE_ID_FALCON        0xf180
1196 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1197 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1198 #define PCI_DEVICE_ID_CENTAUR       0xf900
1199 #define PCI_DEVICE_ID_PEGASUS       0xf980
1200 #define PCI_DEVICE_ID_THOR          0xfa00
1201 #define PCI_DEVICE_ID_VIPER         0xfb00
1202 #define PCI_DEVICE_ID_LP10000S      0xfc00
1203 #define PCI_DEVICE_ID_LP11000S      0xfc10
1204 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1205 #define PCI_DEVICE_ID_SAT_S         0xfc40
1206 #define PCI_DEVICE_ID_PROTEUS_S     0xfc50
1207 #define PCI_DEVICE_ID_HELIOS        0xfd00
1208 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1209 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1210 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1211 #define PCI_DEVICE_ID_HORNET        0xfe05
1212 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1213 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1214 #define PCI_VENDOR_ID_SERVERENGINE  0x19a2
1215 #define PCI_DEVICE_ID_TIGERSHARK    0x0704
1216 #define PCI_DEVICE_ID_TOMCAT        0x0714
1217
1218 #define JEDEC_ID_ADDRESS            0x0080001c
1219 #define FIREFLY_JEDEC_ID            0x1ACC
1220 #define SUPERFLY_JEDEC_ID           0x0020
1221 #define DRAGONFLY_JEDEC_ID          0x0021
1222 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1223 #define CENTAUR_2G_JEDEC_ID         0x0026
1224 #define CENTAUR_1G_JEDEC_ID         0x0028
1225 #define PEGASUS_ORION_JEDEC_ID      0x0036
1226 #define PEGASUS_JEDEC_ID            0x0038
1227 #define THOR_JEDEC_ID               0x0012
1228 #define HELIOS_JEDEC_ID             0x0364
1229 #define ZEPHYR_JEDEC_ID             0x0577
1230 #define VIPER_JEDEC_ID              0x4838
1231 #define SATURN_JEDEC_ID             0x1004
1232 #define HORNET_JDEC_ID              0x2057706D
1233
1234 #define JEDEC_ID_MASK               0x0FFFF000
1235 #define JEDEC_ID_SHIFT              12
1236 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1237
1238 typedef struct {                /* FireFly BIU registers */
1239         uint32_t hostAtt;       /* See definitions for Host Attention
1240                                    register */
1241         uint32_t chipAtt;       /* See definitions for Chip Attention
1242                                    register */
1243         uint32_t hostStatus;    /* See definitions for Host Status register */
1244         uint32_t hostControl;   /* See definitions for Host Control register */
1245         uint32_t buiConfig;     /* See definitions for BIU configuration
1246                                    register */
1247 } FF_REGS;
1248
1249 /* IO Register size in bytes */
1250 #define FF_REG_AREA_SIZE       256
1251
1252 /* Host Attention Register */
1253
1254 #define HA_REG_OFFSET  0        /* Byte offset from register base address */
1255
1256 #define HA_R0RE_REQ    0x00000001       /* Bit  0 */
1257 #define HA_R0CE_RSP    0x00000002       /* Bit  1 */
1258 #define HA_R0ATT       0x00000008       /* Bit  3 */
1259 #define HA_R1RE_REQ    0x00000010       /* Bit  4 */
1260 #define HA_R1CE_RSP    0x00000020       /* Bit  5 */
1261 #define HA_R1ATT       0x00000080       /* Bit  7 */
1262 #define HA_R2RE_REQ    0x00000100       /* Bit  8 */
1263 #define HA_R2CE_RSP    0x00000200       /* Bit  9 */
1264 #define HA_R2ATT       0x00000800       /* Bit 11 */
1265 #define HA_R3RE_REQ    0x00001000       /* Bit 12 */
1266 #define HA_R3CE_RSP    0x00002000       /* Bit 13 */
1267 #define HA_R3ATT       0x00008000       /* Bit 15 */
1268 #define HA_LATT        0x20000000       /* Bit 29 */
1269 #define HA_MBATT       0x40000000       /* Bit 30 */
1270 #define HA_ERATT       0x80000000       /* Bit 31 */
1271
1272 #define HA_RXRE_REQ    0x00000001       /* Bit  0 */
1273 #define HA_RXCE_RSP    0x00000002       /* Bit  1 */
1274 #define HA_RXATT       0x00000008       /* Bit  3 */
1275 #define HA_RXMASK      0x0000000f
1276
1277 #define HA_R0_CLR_MSK   (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1278 #define HA_R1_CLR_MSK   (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1279 #define HA_R2_CLR_MSK   (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1280 #define HA_R3_CLR_MSK   (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1281
1282 #define HA_R0_POS       3
1283 #define HA_R1_POS       7
1284 #define HA_R2_POS       11
1285 #define HA_R3_POS       15
1286 #define HA_LE_POS       29
1287 #define HA_MB_POS       30
1288 #define HA_ER_POS       31
1289 /* Chip Attention Register */
1290
1291 #define CA_REG_OFFSET  4        /* Byte offset from register base address */
1292
1293 #define CA_R0CE_REQ    0x00000001       /* Bit  0 */
1294 #define CA_R0RE_RSP    0x00000002       /* Bit  1 */
1295 #define CA_R0ATT       0x00000008       /* Bit  3 */
1296 #define CA_R1CE_REQ    0x00000010       /* Bit  4 */
1297 #define CA_R1RE_RSP    0x00000020       /* Bit  5 */
1298 #define CA_R1ATT       0x00000080       /* Bit  7 */
1299 #define CA_R2CE_REQ    0x00000100       /* Bit  8 */
1300 #define CA_R2RE_RSP    0x00000200       /* Bit  9 */
1301 #define CA_R2ATT       0x00000800       /* Bit 11 */
1302 #define CA_R3CE_REQ    0x00001000       /* Bit 12 */
1303 #define CA_R3RE_RSP    0x00002000       /* Bit 13 */
1304 #define CA_R3ATT       0x00008000       /* Bit 15 */
1305 #define CA_MBATT       0x40000000       /* Bit 30 */
1306
1307 /* Host Status Register */
1308
1309 #define HS_REG_OFFSET  8        /* Byte offset from register base address */
1310
1311 #define HS_MBRDY       0x00400000       /* Bit 22 */
1312 #define HS_FFRDY       0x00800000       /* Bit 23 */
1313 #define HS_FFER8       0x01000000       /* Bit 24 */
1314 #define HS_FFER7       0x02000000       /* Bit 25 */
1315 #define HS_FFER6       0x04000000       /* Bit 26 */
1316 #define HS_FFER5       0x08000000       /* Bit 27 */
1317 #define HS_FFER4       0x10000000       /* Bit 28 */
1318 #define HS_FFER3       0x20000000       /* Bit 29 */
1319 #define HS_FFER2       0x40000000       /* Bit 30 */
1320 #define HS_FFER1       0x80000000       /* Bit 31 */
1321 #define HS_CRIT_TEMP   0x00000100       /* Bit 8  */
1322 #define HS_FFERM       0xFF000100       /* Mask for error bits 31:24 and 8 */
1323
1324 /* Host Control Register */
1325
1326 #define HC_REG_OFFSET  12       /* Byte offset from register base address */
1327
1328 #define HC_MBINT_ENA   0x00000001       /* Bit  0 */
1329 #define HC_R0INT_ENA   0x00000002       /* Bit  1 */
1330 #define HC_R1INT_ENA   0x00000004       /* Bit  2 */
1331 #define HC_R2INT_ENA   0x00000008       /* Bit  3 */
1332 #define HC_R3INT_ENA   0x00000010       /* Bit  4 */
1333 #define HC_INITHBI     0x02000000       /* Bit 25 */
1334 #define HC_INITMB      0x04000000       /* Bit 26 */
1335 #define HC_INITFF      0x08000000       /* Bit 27 */
1336 #define HC_LAINT_ENA   0x20000000       /* Bit 29 */
1337 #define HC_ERINT_ENA   0x80000000       /* Bit 31 */
1338
1339 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1340 #define MSIX_DFLT_ID    0
1341 #define MSIX_RNG0_ID    0
1342 #define MSIX_RNG1_ID    1
1343 #define MSIX_RNG2_ID    2
1344 #define MSIX_RNG3_ID    3
1345
1346 #define MSIX_LINK_ID    4
1347 #define MSIX_MBOX_ID    5
1348
1349 #define MSIX_SPARE0_ID  6
1350 #define MSIX_SPARE1_ID  7
1351
1352 /* Mailbox Commands */
1353 #define MBX_SHUTDOWN        0x00        /* terminate testing */
1354 #define MBX_LOAD_SM         0x01
1355 #define MBX_READ_NV         0x02
1356 #define MBX_WRITE_NV        0x03
1357 #define MBX_RUN_BIU_DIAG    0x04
1358 #define MBX_INIT_LINK       0x05
1359 #define MBX_DOWN_LINK       0x06
1360 #define MBX_CONFIG_LINK     0x07
1361 #define MBX_CONFIG_RING     0x09
1362 #define MBX_RESET_RING      0x0A
1363 #define MBX_READ_CONFIG     0x0B
1364 #define MBX_READ_RCONFIG    0x0C
1365 #define MBX_READ_SPARM      0x0D
1366 #define MBX_READ_STATUS     0x0E
1367 #define MBX_READ_RPI        0x0F
1368 #define MBX_READ_XRI        0x10
1369 #define MBX_READ_REV        0x11
1370 #define MBX_READ_LNK_STAT   0x12
1371 #define MBX_REG_LOGIN       0x13
1372 #define MBX_UNREG_LOGIN     0x14
1373 #define MBX_CLEAR_LA        0x16
1374 #define MBX_DUMP_MEMORY     0x17
1375 #define MBX_DUMP_CONTEXT    0x18
1376 #define MBX_RUN_DIAGS       0x19
1377 #define MBX_RESTART         0x1A
1378 #define MBX_UPDATE_CFG      0x1B
1379 #define MBX_DOWN_LOAD       0x1C
1380 #define MBX_DEL_LD_ENTRY    0x1D
1381 #define MBX_RUN_PROGRAM     0x1E
1382 #define MBX_SET_MASK        0x20
1383 #define MBX_SET_VARIABLE    0x21
1384 #define MBX_UNREG_D_ID      0x23
1385 #define MBX_KILL_BOARD      0x24
1386 #define MBX_CONFIG_FARP     0x25
1387 #define MBX_BEACON          0x2A
1388 #define MBX_CONFIG_MSI      0x30
1389 #define MBX_HEARTBEAT       0x31
1390 #define MBX_WRITE_VPARMS    0x32
1391 #define MBX_ASYNCEVT_ENABLE 0x33
1392 #define MBX_READ_EVENT_LOG_STATUS 0x37
1393 #define MBX_READ_EVENT_LOG  0x38
1394 #define MBX_WRITE_EVENT_LOG 0x39
1395
1396 #define MBX_PORT_CAPABILITIES 0x3B
1397 #define MBX_PORT_IOV_CONTROL 0x3C
1398
1399 #define MBX_CONFIG_HBQ      0x7C
1400 #define MBX_LOAD_AREA       0x81
1401 #define MBX_RUN_BIU_DIAG64  0x84
1402 #define MBX_CONFIG_PORT     0x88
1403 #define MBX_READ_SPARM64    0x8D
1404 #define MBX_READ_RPI64      0x8F
1405 #define MBX_REG_LOGIN64     0x93
1406 #define MBX_READ_TOPOLOGY   0x95
1407 #define MBX_REG_VPI         0x96
1408 #define MBX_UNREG_VPI       0x97
1409
1410 #define MBX_WRITE_WWN       0x98
1411 #define MBX_SET_DEBUG       0x99
1412 #define MBX_LOAD_EXP_ROM    0x9C
1413 #define MBX_SLI4_CONFIG     0x9B
1414 #define MBX_SLI4_REQ_FTRS   0x9D
1415 #define MBX_MAX_CMDS        0x9E
1416 #define MBX_RESUME_RPI      0x9E
1417 #define MBX_SLI2_CMD_MASK   0x80
1418 #define MBX_REG_VFI         0x9F
1419 #define MBX_REG_FCFI        0xA0
1420 #define MBX_UNREG_VFI       0xA1
1421 #define MBX_UNREG_FCFI      0xA2
1422 #define MBX_INIT_VFI        0xA3
1423 #define MBX_INIT_VPI        0xA4
1424
1425 #define MBX_AUTH_PORT       0xF8
1426 #define MBX_SECURITY_MGMT   0xF9
1427
1428 /* IOCB Commands */
1429
1430 #define CMD_RCV_SEQUENCE_CX     0x01
1431 #define CMD_XMIT_SEQUENCE_CR    0x02
1432 #define CMD_XMIT_SEQUENCE_CX    0x03
1433 #define CMD_XMIT_BCAST_CN       0x04
1434 #define CMD_XMIT_BCAST_CX       0x05
1435 #define CMD_QUE_RING_BUF_CN     0x06
1436 #define CMD_QUE_XRI_BUF_CX      0x07
1437 #define CMD_IOCB_CONTINUE_CN    0x08
1438 #define CMD_RET_XRI_BUF_CX      0x09
1439 #define CMD_ELS_REQUEST_CR      0x0A
1440 #define CMD_ELS_REQUEST_CX      0x0B
1441 #define CMD_RCV_ELS_REQ_CX      0x0D
1442 #define CMD_ABORT_XRI_CN        0x0E
1443 #define CMD_ABORT_XRI_CX        0x0F
1444 #define CMD_CLOSE_XRI_CN        0x10
1445 #define CMD_CLOSE_XRI_CX        0x11
1446 #define CMD_CREATE_XRI_CR       0x12
1447 #define CMD_CREATE_XRI_CX       0x13
1448 #define CMD_GET_RPI_CN          0x14
1449 #define CMD_XMIT_ELS_RSP_CX     0x15
1450 #define CMD_GET_RPI_CR          0x16
1451 #define CMD_XRI_ABORTED_CX      0x17
1452 #define CMD_FCP_IWRITE_CR       0x18
1453 #define CMD_FCP_IWRITE_CX       0x19
1454 #define CMD_FCP_IREAD_CR        0x1A
1455 #define CMD_FCP_IREAD_CX        0x1B
1456 #define CMD_FCP_ICMND_CR        0x1C
1457 #define CMD_FCP_ICMND_CX        0x1D
1458 #define CMD_FCP_TSEND_CX        0x1F
1459 #define CMD_FCP_TRECEIVE_CX     0x21
1460 #define CMD_FCP_TRSP_CX         0x23
1461 #define CMD_FCP_AUTO_TRSP_CX    0x29
1462
1463 #define CMD_ADAPTER_MSG         0x20
1464 #define CMD_ADAPTER_DUMP        0x22
1465
1466 /*  SLI_2 IOCB Command Set */
1467
1468 #define CMD_ASYNC_STATUS        0x7C
1469 #define CMD_RCV_SEQUENCE64_CX   0x81
1470 #define CMD_XMIT_SEQUENCE64_CR  0x82
1471 #define CMD_XMIT_SEQUENCE64_CX  0x83
1472 #define CMD_XMIT_BCAST64_CN     0x84
1473 #define CMD_XMIT_BCAST64_CX     0x85
1474 #define CMD_QUE_RING_BUF64_CN   0x86
1475 #define CMD_QUE_XRI_BUF64_CX    0x87
1476 #define CMD_IOCB_CONTINUE64_CN  0x88
1477 #define CMD_RET_XRI_BUF64_CX    0x89
1478 #define CMD_ELS_REQUEST64_CR    0x8A
1479 #define CMD_ELS_REQUEST64_CX    0x8B
1480 #define CMD_ABORT_MXRI64_CN     0x8C
1481 #define CMD_RCV_ELS_REQ64_CX    0x8D
1482 #define CMD_XMIT_ELS_RSP64_CX   0x95
1483 #define CMD_XMIT_BLS_RSP64_CX   0x97
1484 #define CMD_FCP_IWRITE64_CR     0x98
1485 #define CMD_FCP_IWRITE64_CX     0x99
1486 #define CMD_FCP_IREAD64_CR      0x9A
1487 #define CMD_FCP_IREAD64_CX      0x9B
1488 #define CMD_FCP_ICMND64_CR      0x9C
1489 #define CMD_FCP_ICMND64_CX      0x9D
1490 #define CMD_FCP_TSEND64_CX      0x9F
1491 #define CMD_FCP_TRECEIVE64_CX   0xA1
1492 #define CMD_FCP_TRSP64_CX       0xA3
1493
1494 #define CMD_QUE_XRI64_CX        0xB3
1495 #define CMD_IOCB_RCV_SEQ64_CX   0xB5
1496 #define CMD_IOCB_RCV_ELS64_CX   0xB7
1497 #define CMD_IOCB_RET_XRI64_CX   0xB9
1498 #define CMD_IOCB_RCV_CONT64_CX  0xBB
1499
1500 #define CMD_GEN_REQUEST64_CR    0xC2
1501 #define CMD_GEN_REQUEST64_CX    0xC3
1502
1503 /* Unhandled SLI-3 Commands */
1504 #define CMD_IOCB_XMIT_MSEQ64_CR         0xB0
1505 #define CMD_IOCB_XMIT_MSEQ64_CX         0xB1
1506 #define CMD_IOCB_RCV_SEQ_LIST64_CX      0xC1
1507 #define CMD_IOCB_RCV_ELS_LIST64_CX      0xCD
1508 #define CMD_IOCB_CLOSE_EXTENDED_CN      0xB6
1509 #define CMD_IOCB_ABORT_EXTENDED_CN      0xBA
1510 #define CMD_IOCB_RET_HBQE64_CN          0xCA
1511 #define CMD_IOCB_FCP_IBIDIR64_CR        0xAC
1512 #define CMD_IOCB_FCP_IBIDIR64_CX        0xAD
1513 #define CMD_IOCB_FCP_ITASKMGT64_CX      0xAF
1514 #define CMD_IOCB_LOGENTRY_CN            0x94
1515 #define CMD_IOCB_LOGENTRY_ASYNC_CN      0x96
1516
1517 /* Data Security SLI Commands */
1518 #define DSSCMD_IWRITE64_CR              0xF8
1519 #define DSSCMD_IWRITE64_CX              0xF9
1520 #define DSSCMD_IREAD64_CR               0xFA
1521 #define DSSCMD_IREAD64_CX               0xFB
1522
1523 #define CMD_MAX_IOCB_CMD        0xFB
1524 #define CMD_IOCB_MASK           0xff
1525
1526 #define MAX_MSG_DATA            28      /* max msg data in CMD_ADAPTER_MSG
1527                                            iocb */
1528 #define LPFC_MAX_ADPTMSG         32     /* max msg data */
1529 /*
1530  *  Define Status
1531  */
1532 #define MBX_SUCCESS                 0
1533 #define MBXERR_NUM_RINGS            1
1534 #define MBXERR_NUM_IOCBS            2
1535 #define MBXERR_IOCBS_EXCEEDED       3
1536 #define MBXERR_BAD_RING_NUMBER      4
1537 #define MBXERR_MASK_ENTRIES_RANGE   5
1538 #define MBXERR_MASKS_EXCEEDED       6
1539 #define MBXERR_BAD_PROFILE          7
1540 #define MBXERR_BAD_DEF_CLASS        8
1541 #define MBXERR_BAD_MAX_RESPONDER    9
1542 #define MBXERR_BAD_MAX_ORIGINATOR   10
1543 #define MBXERR_RPI_REGISTERED       11
1544 #define MBXERR_RPI_FULL             12
1545 #define MBXERR_NO_RESOURCES         13
1546 #define MBXERR_BAD_RCV_LENGTH       14
1547 #define MBXERR_DMA_ERROR            15
1548 #define MBXERR_ERROR                16
1549 #define MBXERR_LINK_DOWN            0x33
1550 #define MBXERR_SEC_NO_PERMISSION    0xF02
1551 #define MBX_NOT_FINISHED            255
1552
1553 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1554 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1555
1556 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1557
1558 /*
1559  *    Begin Structure Definitions for Mailbox Commands
1560  */
1561
1562 typedef struct {
1563 #ifdef __BIG_ENDIAN_BITFIELD
1564         uint8_t tval;
1565         uint8_t tmask;
1566         uint8_t rval;
1567         uint8_t rmask;
1568 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1569         uint8_t rmask;
1570         uint8_t rval;
1571         uint8_t tmask;
1572         uint8_t tval;
1573 #endif
1574 } RR_REG;
1575
1576 struct ulp_bde {
1577         uint32_t bdeAddress;
1578 #ifdef __BIG_ENDIAN_BITFIELD
1579         uint32_t bdeReserved:4;
1580         uint32_t bdeAddrHigh:4;
1581         uint32_t bdeSize:24;
1582 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1583         uint32_t bdeSize:24;
1584         uint32_t bdeAddrHigh:4;
1585         uint32_t bdeReserved:4;
1586 #endif
1587 };
1588
1589 typedef struct ULP_BDL {        /* SLI-2 */
1590 #ifdef __BIG_ENDIAN_BITFIELD
1591         uint32_t bdeFlags:8;    /* BDL Flags */
1592         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1593 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1594         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1595         uint32_t bdeFlags:8;    /* BDL Flags */
1596 #endif
1597
1598         uint32_t addrLow;       /* Address 0:31 */
1599         uint32_t addrHigh;      /* Address 32:63 */
1600         uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
1601 } ULP_BDL;
1602
1603 /*
1604  * BlockGuard Definitions
1605  */
1606
1607 enum lpfc_protgrp_type {
1608         LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors                  */
1609         LPFC_PG_TYPE_NO_DIF,      /* no DIF data pointed to by prot grp       */
1610         LPFC_PG_TYPE_EMBD_DIF,    /* DIF is embedded (inline) with data       */
1611         LPFC_PG_TYPE_DIF_BUF      /* DIF has its own scatter/gather list      */
1612 };
1613
1614 /* PDE Descriptors */
1615 #define LPFC_PDE5_DESCRIPTOR            0x85
1616 #define LPFC_PDE6_DESCRIPTOR            0x86
1617 #define LPFC_PDE7_DESCRIPTOR            0x87
1618
1619 /* BlockGuard Opcodes */
1620 #define BG_OP_IN_NODIF_OUT_CRC          0x0
1621 #define BG_OP_IN_CRC_OUT_NODIF          0x1
1622 #define BG_OP_IN_NODIF_OUT_CSUM         0x2
1623 #define BG_OP_IN_CSUM_OUT_NODIF         0x3
1624 #define BG_OP_IN_CRC_OUT_CRC            0x4
1625 #define BG_OP_IN_CSUM_OUT_CSUM          0x5
1626 #define BG_OP_IN_CRC_OUT_CSUM           0x6
1627 #define BG_OP_IN_CSUM_OUT_CRC           0x7
1628
1629 struct lpfc_pde5 {
1630         uint32_t word0;
1631 #define pde5_type_SHIFT         24
1632 #define pde5_type_MASK          0x000000ff
1633 #define pde5_type_WORD          word0
1634 #define pde5_rsvd0_SHIFT        0
1635 #define pde5_rsvd0_MASK         0x00ffffff
1636 #define pde5_rsvd0_WORD         word0
1637         uint32_t reftag;        /* Reference Tag Value                  */
1638         uint32_t reftagtr;      /* Reference Tag Translation Value      */
1639 };
1640
1641 struct lpfc_pde6 {
1642         uint32_t word0;
1643 #define pde6_type_SHIFT         24
1644 #define pde6_type_MASK          0x000000ff
1645 #define pde6_type_WORD          word0
1646 #define pde6_rsvd0_SHIFT        0
1647 #define pde6_rsvd0_MASK         0x00ffffff
1648 #define pde6_rsvd0_WORD         word0
1649         uint32_t word1;
1650 #define pde6_rsvd1_SHIFT        26
1651 #define pde6_rsvd1_MASK         0x0000003f
1652 #define pde6_rsvd1_WORD         word1
1653 #define pde6_na_SHIFT           25
1654 #define pde6_na_MASK            0x00000001
1655 #define pde6_na_WORD            word1
1656 #define pde6_rsvd2_SHIFT        16
1657 #define pde6_rsvd2_MASK         0x000001FF
1658 #define pde6_rsvd2_WORD         word1
1659 #define pde6_apptagtr_SHIFT     0
1660 #define pde6_apptagtr_MASK      0x0000ffff
1661 #define pde6_apptagtr_WORD      word1
1662         uint32_t word2;
1663 #define pde6_optx_SHIFT         28
1664 #define pde6_optx_MASK          0x0000000f
1665 #define pde6_optx_WORD          word2
1666 #define pde6_oprx_SHIFT         24
1667 #define pde6_oprx_MASK          0x0000000f
1668 #define pde6_oprx_WORD          word2
1669 #define pde6_nr_SHIFT           23
1670 #define pde6_nr_MASK            0x00000001
1671 #define pde6_nr_WORD            word2
1672 #define pde6_ce_SHIFT           22
1673 #define pde6_ce_MASK            0x00000001
1674 #define pde6_ce_WORD            word2
1675 #define pde6_re_SHIFT           21
1676 #define pde6_re_MASK            0x00000001
1677 #define pde6_re_WORD            word2
1678 #define pde6_ae_SHIFT           20
1679 #define pde6_ae_MASK            0x00000001
1680 #define pde6_ae_WORD            word2
1681 #define pde6_ai_SHIFT           19
1682 #define pde6_ai_MASK            0x00000001
1683 #define pde6_ai_WORD            word2
1684 #define pde6_bs_SHIFT           16
1685 #define pde6_bs_MASK            0x00000007
1686 #define pde6_bs_WORD            word2
1687 #define pde6_apptagval_SHIFT    0
1688 #define pde6_apptagval_MASK     0x0000ffff
1689 #define pde6_apptagval_WORD     word2
1690 };
1691
1692
1693 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1694
1695 typedef struct {
1696 #ifdef __BIG_ENDIAN_BITFIELD
1697         uint32_t rsvd2:25;
1698         uint32_t acknowledgment:1;
1699         uint32_t version:1;
1700         uint32_t erase_or_prog:1;
1701         uint32_t update_flash:1;
1702         uint32_t update_ram:1;
1703         uint32_t method:1;
1704         uint32_t load_cmplt:1;
1705 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1706         uint32_t load_cmplt:1;
1707         uint32_t method:1;
1708         uint32_t update_ram:1;
1709         uint32_t update_flash:1;
1710         uint32_t erase_or_prog:1;
1711         uint32_t version:1;
1712         uint32_t acknowledgment:1;
1713         uint32_t rsvd2:25;
1714 #endif
1715
1716         uint32_t dl_to_adr_low;
1717         uint32_t dl_to_adr_high;
1718         uint32_t dl_len;
1719         union {
1720                 uint32_t dl_from_mbx_offset;
1721                 struct ulp_bde dl_from_bde;
1722                 struct ulp_bde64 dl_from_bde64;
1723         } un;
1724
1725 } LOAD_SM_VAR;
1726
1727 /* Structure for MB Command READ_NVPARM (02) */
1728
1729 typedef struct {
1730         uint32_t rsvd1[3];      /* Read as all one's */
1731         uint32_t rsvd2;         /* Read as all zero's */
1732         uint32_t portname[2];   /* N_PORT name */
1733         uint32_t nodename[2];   /* NODE name */
1734
1735 #ifdef __BIG_ENDIAN_BITFIELD
1736         uint32_t pref_DID:24;
1737         uint32_t hardAL_PA:8;
1738 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1739         uint32_t hardAL_PA:8;
1740         uint32_t pref_DID:24;
1741 #endif
1742
1743         uint32_t rsvd3[21];     /* Read as all one's */
1744 } READ_NV_VAR;
1745
1746 /* Structure for MB Command WRITE_NVPARMS (03) */
1747
1748 typedef struct {
1749         uint32_t rsvd1[3];      /* Must be all one's */
1750         uint32_t rsvd2;         /* Must be all zero's */
1751         uint32_t portname[2];   /* N_PORT name */
1752         uint32_t nodename[2];   /* NODE name */
1753
1754 #ifdef __BIG_ENDIAN_BITFIELD
1755         uint32_t pref_DID:24;
1756         uint32_t hardAL_PA:8;
1757 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1758         uint32_t hardAL_PA:8;
1759         uint32_t pref_DID:24;
1760 #endif
1761
1762         uint32_t rsvd3[21];     /* Must be all one's */
1763 } WRITE_NV_VAR;
1764
1765 /* Structure for MB Command RUN_BIU_DIAG (04) */
1766 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1767
1768 typedef struct {
1769         uint32_t rsvd1;
1770         union {
1771                 struct {
1772                         struct ulp_bde xmit_bde;
1773                         struct ulp_bde rcv_bde;
1774                 } s1;
1775                 struct {
1776                         struct ulp_bde64 xmit_bde64;
1777                         struct ulp_bde64 rcv_bde64;
1778                 } s2;
1779         } un;
1780 } BIU_DIAG_VAR;
1781
1782 /* Structure for MB command READ_EVENT_LOG (0x38) */
1783 struct READ_EVENT_LOG_VAR {
1784         uint32_t word1;
1785 #define lpfc_event_log_SHIFT    29
1786 #define lpfc_event_log_MASK     0x00000001
1787 #define lpfc_event_log_WORD     word1
1788 #define USE_MAILBOX_RESPONSE    1
1789         uint32_t offset;
1790         struct ulp_bde64 rcv_bde64;
1791 };
1792
1793 /* Structure for MB Command INIT_LINK (05) */
1794
1795 typedef struct {
1796 #ifdef __BIG_ENDIAN_BITFIELD
1797         uint32_t rsvd1:24;
1798         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1799 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1800         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1801         uint32_t rsvd1:24;
1802 #endif
1803
1804 #ifdef __BIG_ENDIAN_BITFIELD
1805         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1806         uint8_t rsvd2;
1807         uint16_t link_flags;
1808 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1809         uint16_t link_flags;
1810         uint8_t rsvd2;
1811         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1812 #endif
1813
1814 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
1815 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
1816 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
1817 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
1818 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
1819 #define FLAGS_UNREG_LOGIN_ALL        0x08 /* UNREG_LOGIN all on link down */
1820 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
1821
1822 #define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
1823 #define FLAGS_LINK_SPEED             0x0800     /* Bit 11 */
1824 #define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
1825
1826         uint32_t link_speed;
1827 #define LINK_SPEED_AUTO 0x0     /* Auto selection */
1828 #define LINK_SPEED_1G   0x1     /* 1 Gigabaud */
1829 #define LINK_SPEED_2G   0x2     /* 2 Gigabaud */
1830 #define LINK_SPEED_4G   0x4     /* 4 Gigabaud */
1831 #define LINK_SPEED_8G   0x8     /* 8 Gigabaud */
1832 #define LINK_SPEED_10G  0x10    /* 10 Gigabaud */
1833 #define LINK_SPEED_16G  0x11    /* 16 Gigabaud */
1834
1835 } INIT_LINK_VAR;
1836
1837 /* Structure for MB Command DOWN_LINK (06) */
1838
1839 typedef struct {
1840         uint32_t rsvd1;
1841 } DOWN_LINK_VAR;
1842
1843 /* Structure for MB Command CONFIG_LINK (07) */
1844
1845 typedef struct {
1846 #ifdef __BIG_ENDIAN_BITFIELD
1847         uint32_t cr:1;
1848         uint32_t ci:1;
1849         uint32_t cr_delay:6;
1850         uint32_t cr_count:8;
1851         uint32_t rsvd1:8;
1852         uint32_t MaxBBC:8;
1853 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1854         uint32_t MaxBBC:8;
1855         uint32_t rsvd1:8;
1856         uint32_t cr_count:8;
1857         uint32_t cr_delay:6;
1858         uint32_t ci:1;
1859         uint32_t cr:1;
1860 #endif
1861
1862         uint32_t myId;
1863         uint32_t rsvd2;
1864         uint32_t edtov;
1865         uint32_t arbtov;
1866         uint32_t ratov;
1867         uint32_t rttov;
1868         uint32_t altov;
1869         uint32_t crtov;
1870         uint32_t citov;
1871 #ifdef __BIG_ENDIAN_BITFIELD
1872         uint32_t rrq_enable:1;
1873         uint32_t rrq_immed:1;
1874         uint32_t rsvd4:29;
1875         uint32_t ack0_enable:1;
1876 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1877         uint32_t ack0_enable:1;
1878         uint32_t rsvd4:29;
1879         uint32_t rrq_immed:1;
1880         uint32_t rrq_enable:1;
1881 #endif
1882 } CONFIG_LINK;
1883
1884 /* Structure for MB Command PART_SLIM (08)
1885  * will be removed since SLI1 is no longer supported!
1886  */
1887 typedef struct {
1888 #ifdef __BIG_ENDIAN_BITFIELD
1889         uint16_t offCiocb;
1890         uint16_t numCiocb;
1891         uint16_t offRiocb;
1892         uint16_t numRiocb;
1893 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1894         uint16_t numCiocb;
1895         uint16_t offCiocb;
1896         uint16_t numRiocb;
1897         uint16_t offRiocb;
1898 #endif
1899 } RING_DEF;
1900
1901 typedef struct {
1902 #ifdef __BIG_ENDIAN_BITFIELD
1903         uint32_t unused1:24;
1904         uint32_t numRing:8;
1905 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1906         uint32_t numRing:8;
1907         uint32_t unused1:24;
1908 #endif
1909
1910         RING_DEF ringdef[4];
1911         uint32_t hbainit;
1912 } PART_SLIM_VAR;
1913
1914 /* Structure for MB Command CONFIG_RING (09) */
1915
1916 typedef struct {
1917 #ifdef __BIG_ENDIAN_BITFIELD
1918         uint32_t unused2:6;
1919         uint32_t recvSeq:1;
1920         uint32_t recvNotify:1;
1921         uint32_t numMask:8;
1922         uint32_t profile:8;
1923         uint32_t unused1:4;
1924         uint32_t ring:4;
1925 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1926         uint32_t ring:4;
1927         uint32_t unused1:4;
1928         uint32_t profile:8;
1929         uint32_t numMask:8;
1930         uint32_t recvNotify:1;
1931         uint32_t recvSeq:1;
1932         uint32_t unused2:6;
1933 #endif
1934
1935 #ifdef __BIG_ENDIAN_BITFIELD
1936         uint16_t maxRespXchg;
1937         uint16_t maxOrigXchg;
1938 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1939         uint16_t maxOrigXchg;
1940         uint16_t maxRespXchg;
1941 #endif
1942
1943         RR_REG rrRegs[6];
1944 } CONFIG_RING_VAR;
1945
1946 /* Structure for MB Command RESET_RING (10) */
1947
1948 typedef struct {
1949         uint32_t ring_no;
1950 } RESET_RING_VAR;
1951
1952 /* Structure for MB Command READ_CONFIG (11) */
1953
1954 typedef struct {
1955 #ifdef __BIG_ENDIAN_BITFIELD
1956         uint32_t cr:1;
1957         uint32_t ci:1;
1958         uint32_t cr_delay:6;
1959         uint32_t cr_count:8;
1960         uint32_t InitBBC:8;
1961         uint32_t MaxBBC:8;
1962 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1963         uint32_t MaxBBC:8;
1964         uint32_t InitBBC:8;
1965         uint32_t cr_count:8;
1966         uint32_t cr_delay:6;
1967         uint32_t ci:1;
1968         uint32_t cr:1;
1969 #endif
1970
1971 #ifdef __BIG_ENDIAN_BITFIELD
1972         uint32_t topology:8;
1973         uint32_t myDid:24;
1974 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1975         uint32_t myDid:24;
1976         uint32_t topology:8;
1977 #endif
1978
1979         /* Defines for topology (defined previously) */
1980 #ifdef __BIG_ENDIAN_BITFIELD
1981         uint32_t AR:1;
1982         uint32_t IR:1;
1983         uint32_t rsvd1:29;
1984         uint32_t ack0:1;
1985 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1986         uint32_t ack0:1;
1987         uint32_t rsvd1:29;
1988         uint32_t IR:1;
1989         uint32_t AR:1;
1990 #endif
1991
1992         uint32_t edtov;
1993         uint32_t arbtov;
1994         uint32_t ratov;
1995         uint32_t rttov;
1996         uint32_t altov;
1997         uint32_t lmt;
1998 #define LMT_RESERVED  0x000    /* Not used */
1999 #define LMT_1Gb       0x004
2000 #define LMT_2Gb       0x008
2001 #define LMT_4Gb       0x040
2002 #define LMT_8Gb       0x080
2003 #define LMT_10Gb      0x100
2004 #define LMT_16Gb      0x200
2005         uint32_t rsvd2;
2006         uint32_t rsvd3;
2007         uint32_t max_xri;
2008         uint32_t max_iocb;
2009         uint32_t max_rpi;
2010         uint32_t avail_xri;
2011         uint32_t avail_iocb;
2012         uint32_t avail_rpi;
2013         uint32_t max_vpi;
2014         uint32_t rsvd4;
2015         uint32_t rsvd5;
2016         uint32_t avail_vpi;
2017 } READ_CONFIG_VAR;
2018
2019 /* Structure for MB Command READ_RCONFIG (12) */
2020
2021 typedef struct {
2022 #ifdef __BIG_ENDIAN_BITFIELD
2023         uint32_t rsvd2:7;
2024         uint32_t recvNotify:1;
2025         uint32_t numMask:8;
2026         uint32_t profile:8;
2027         uint32_t rsvd1:4;
2028         uint32_t ring:4;
2029 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2030         uint32_t ring:4;
2031         uint32_t rsvd1:4;
2032         uint32_t profile:8;
2033         uint32_t numMask:8;
2034         uint32_t recvNotify:1;
2035         uint32_t rsvd2:7;
2036 #endif
2037
2038 #ifdef __BIG_ENDIAN_BITFIELD
2039         uint16_t maxResp;
2040         uint16_t maxOrig;
2041 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2042         uint16_t maxOrig;
2043         uint16_t maxResp;
2044 #endif
2045
2046         RR_REG rrRegs[6];
2047
2048 #ifdef __BIG_ENDIAN_BITFIELD
2049         uint16_t cmdRingOffset;
2050         uint16_t cmdEntryCnt;
2051         uint16_t rspRingOffset;
2052         uint16_t rspEntryCnt;
2053         uint16_t nextCmdOffset;
2054         uint16_t rsvd3;
2055         uint16_t nextRspOffset;
2056         uint16_t rsvd4;
2057 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2058         uint16_t cmdEntryCnt;
2059         uint16_t cmdRingOffset;
2060         uint16_t rspEntryCnt;
2061         uint16_t rspRingOffset;
2062         uint16_t rsvd3;
2063         uint16_t nextCmdOffset;
2064         uint16_t rsvd4;
2065         uint16_t nextRspOffset;
2066 #endif
2067 } READ_RCONF_VAR;
2068
2069 /* Structure for MB Command READ_SPARM (13) */
2070 /* Structure for MB Command READ_SPARM64 (0x8D) */
2071
2072 typedef struct {
2073         uint32_t rsvd1;
2074         uint32_t rsvd2;
2075         union {
2076                 struct ulp_bde sp; /* This BDE points to struct serv_parm
2077                                       structure */
2078                 struct ulp_bde64 sp64;
2079         } un;
2080 #ifdef __BIG_ENDIAN_BITFIELD
2081         uint16_t rsvd3;
2082         uint16_t vpi;
2083 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2084         uint16_t vpi;
2085         uint16_t rsvd3;
2086 #endif
2087 } READ_SPARM_VAR;
2088
2089 /* Structure for MB Command READ_STATUS (14) */
2090
2091 typedef struct {
2092 #ifdef __BIG_ENDIAN_BITFIELD
2093         uint32_t rsvd1:31;
2094         uint32_t clrCounters:1;
2095         uint16_t activeXriCnt;
2096         uint16_t activeRpiCnt;
2097 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2098         uint32_t clrCounters:1;
2099         uint32_t rsvd1:31;
2100         uint16_t activeRpiCnt;
2101         uint16_t activeXriCnt;
2102 #endif
2103
2104         uint32_t xmitByteCnt;
2105         uint32_t rcvByteCnt;
2106         uint32_t xmitFrameCnt;
2107         uint32_t rcvFrameCnt;
2108         uint32_t xmitSeqCnt;
2109         uint32_t rcvSeqCnt;
2110         uint32_t totalOrigExchanges;
2111         uint32_t totalRespExchanges;
2112         uint32_t rcvPbsyCnt;
2113         uint32_t rcvFbsyCnt;
2114 } READ_STATUS_VAR;
2115
2116 /* Structure for MB Command READ_RPI (15) */
2117 /* Structure for MB Command READ_RPI64 (0x8F) */
2118
2119 typedef struct {
2120 #ifdef __BIG_ENDIAN_BITFIELD
2121         uint16_t nextRpi;
2122         uint16_t reqRpi;
2123         uint32_t rsvd2:8;
2124         uint32_t DID:24;
2125 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2126         uint16_t reqRpi;
2127         uint16_t nextRpi;
2128         uint32_t DID:24;
2129         uint32_t rsvd2:8;
2130 #endif
2131
2132         union {
2133                 struct ulp_bde sp;
2134                 struct ulp_bde64 sp64;
2135         } un;
2136
2137 } READ_RPI_VAR;
2138
2139 /* Structure for MB Command READ_XRI (16) */
2140
2141 typedef struct {
2142 #ifdef __BIG_ENDIAN_BITFIELD
2143         uint16_t nextXri;
2144         uint16_t reqXri;
2145         uint16_t rsvd1;
2146         uint16_t rpi;
2147         uint32_t rsvd2:8;
2148         uint32_t DID:24;
2149         uint32_t rsvd3:8;
2150         uint32_t SID:24;
2151         uint32_t rsvd4;
2152         uint8_t seqId;
2153         uint8_t rsvd5;
2154         uint16_t seqCount;
2155         uint16_t oxId;
2156         uint16_t rxId;
2157         uint32_t rsvd6:30;
2158         uint32_t si:1;
2159         uint32_t exchOrig:1;
2160 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2161         uint16_t reqXri;
2162         uint16_t nextXri;
2163         uint16_t rpi;
2164         uint16_t rsvd1;
2165         uint32_t DID:24;
2166         uint32_t rsvd2:8;
2167         uint32_t SID:24;
2168         uint32_t rsvd3:8;
2169         uint32_t rsvd4;
2170         uint16_t seqCount;
2171         uint8_t rsvd5;
2172         uint8_t seqId;
2173         uint16_t rxId;
2174         uint16_t oxId;
2175         uint32_t exchOrig:1;
2176         uint32_t si:1;
2177         uint32_t rsvd6:30;
2178 #endif
2179 } READ_XRI_VAR;
2180
2181 /* Structure for MB Command READ_REV (17) */
2182
2183 typedef struct {
2184 #ifdef __BIG_ENDIAN_BITFIELD
2185         uint32_t cv:1;
2186         uint32_t rr:1;
2187         uint32_t rsvd2:2;
2188         uint32_t v3req:1;
2189         uint32_t v3rsp:1;
2190         uint32_t rsvd1:25;
2191         uint32_t rv:1;
2192 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2193         uint32_t rv:1;
2194         uint32_t rsvd1:25;
2195         uint32_t v3rsp:1;
2196         uint32_t v3req:1;
2197         uint32_t rsvd2:2;
2198         uint32_t rr:1;
2199         uint32_t cv:1;
2200 #endif
2201
2202         uint32_t biuRev;
2203         uint32_t smRev;
2204         union {
2205                 uint32_t smFwRev;
2206                 struct {
2207 #ifdef __BIG_ENDIAN_BITFIELD
2208                         uint8_t ProgType;
2209                         uint8_t ProgId;
2210                         uint16_t ProgVer:4;
2211                         uint16_t ProgRev:4;
2212                         uint16_t ProgFixLvl:2;
2213                         uint16_t ProgDistType:2;
2214                         uint16_t DistCnt:4;
2215 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2216                         uint16_t DistCnt:4;
2217                         uint16_t ProgDistType:2;
2218                         uint16_t ProgFixLvl:2;
2219                         uint16_t ProgRev:4;
2220                         uint16_t ProgVer:4;
2221                         uint8_t ProgId;
2222                         uint8_t ProgType;
2223 #endif
2224
2225                 } b;
2226         } un;
2227         uint32_t endecRev;
2228 #ifdef __BIG_ENDIAN_BITFIELD
2229         uint8_t feaLevelHigh;
2230         uint8_t feaLevelLow;
2231         uint8_t fcphHigh;
2232         uint8_t fcphLow;
2233 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2234         uint8_t fcphLow;
2235         uint8_t fcphHigh;
2236         uint8_t feaLevelLow;
2237         uint8_t feaLevelHigh;
2238 #endif
2239
2240         uint32_t postKernRev;
2241         uint32_t opFwRev;
2242         uint8_t opFwName[16];
2243         uint32_t sli1FwRev;
2244         uint8_t sli1FwName[16];
2245         uint32_t sli2FwRev;
2246         uint8_t sli2FwName[16];
2247         uint32_t sli3Feat;
2248         uint32_t RandomData[6];
2249 } READ_REV_VAR;
2250
2251 /* Structure for MB Command READ_LINK_STAT (18) */
2252
2253 typedef struct {
2254         uint32_t rsvd1;
2255         uint32_t linkFailureCnt;
2256         uint32_t lossSyncCnt;
2257
2258         uint32_t lossSignalCnt;
2259         uint32_t primSeqErrCnt;
2260         uint32_t invalidXmitWord;
2261         uint32_t crcCnt;
2262         uint32_t primSeqTimeout;
2263         uint32_t elasticOverrun;
2264         uint32_t arbTimeout;
2265 } READ_LNK_VAR;
2266
2267 /* Structure for MB Command REG_LOGIN (19) */
2268 /* Structure for MB Command REG_LOGIN64 (0x93) */
2269
2270 typedef struct {
2271 #ifdef __BIG_ENDIAN_BITFIELD
2272         uint16_t rsvd1;
2273         uint16_t rpi;
2274         uint32_t rsvd2:8;
2275         uint32_t did:24;
2276 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2277         uint16_t rpi;
2278         uint16_t rsvd1;
2279         uint32_t did:24;
2280         uint32_t rsvd2:8;
2281 #endif
2282
2283         union {
2284                 struct ulp_bde sp;
2285                 struct ulp_bde64 sp64;
2286         } un;
2287
2288 #ifdef __BIG_ENDIAN_BITFIELD
2289         uint16_t rsvd6;
2290         uint16_t vpi;
2291 #else /* __LITTLE_ENDIAN_BITFIELD */
2292         uint16_t vpi;
2293         uint16_t rsvd6;
2294 #endif
2295
2296 } REG_LOGIN_VAR;
2297
2298 /* Word 30 contents for REG_LOGIN */
2299 typedef union {
2300         struct {
2301 #ifdef __BIG_ENDIAN_BITFIELD
2302                 uint16_t rsvd1:12;
2303                 uint16_t wd30_class:4;
2304                 uint16_t xri;
2305 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2306                 uint16_t xri;
2307                 uint16_t wd30_class:4;
2308                 uint16_t rsvd1:12;
2309 #endif
2310         } f;
2311         uint32_t word;
2312 } REG_WD30;
2313
2314 /* Structure for MB Command UNREG_LOGIN (20) */
2315
2316 typedef struct {
2317 #ifdef __BIG_ENDIAN_BITFIELD
2318         uint16_t rsvd1;
2319         uint16_t rpi;
2320         uint32_t rsvd2;
2321         uint32_t rsvd3;
2322         uint32_t rsvd4;
2323         uint32_t rsvd5;
2324         uint16_t rsvd6;
2325         uint16_t vpi;
2326 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2327         uint16_t rpi;
2328         uint16_t rsvd1;
2329         uint32_t rsvd2;
2330         uint32_t rsvd3;
2331         uint32_t rsvd4;
2332         uint32_t rsvd5;
2333         uint16_t vpi;
2334         uint16_t rsvd6;
2335 #endif
2336 } UNREG_LOGIN_VAR;
2337
2338 /* Structure for MB Command REG_VPI (0x96) */
2339 typedef struct {
2340 #ifdef __BIG_ENDIAN_BITFIELD
2341         uint32_t rsvd1;
2342         uint32_t rsvd2:7;
2343         uint32_t upd:1;
2344         uint32_t sid:24;
2345         uint32_t wwn[2];
2346         uint32_t rsvd5;
2347         uint16_t vfi;
2348         uint16_t vpi;
2349 #else   /*  __LITTLE_ENDIAN */
2350         uint32_t rsvd1;
2351         uint32_t sid:24;
2352         uint32_t upd:1;
2353         uint32_t rsvd2:7;
2354         uint32_t wwn[2];
2355         uint32_t rsvd5;
2356         uint16_t vpi;
2357         uint16_t vfi;
2358 #endif
2359 } REG_VPI_VAR;
2360
2361 /* Structure for MB Command UNREG_VPI (0x97) */
2362 typedef struct {
2363         uint32_t rsvd1;
2364 #ifdef __BIG_ENDIAN_BITFIELD
2365         uint16_t rsvd2;
2366         uint16_t sli4_vpi;
2367 #else   /*  __LITTLE_ENDIAN */
2368         uint16_t sli4_vpi;
2369         uint16_t rsvd2;
2370 #endif
2371         uint32_t rsvd3;
2372         uint32_t rsvd4;
2373         uint32_t rsvd5;
2374 #ifdef __BIG_ENDIAN_BITFIELD
2375         uint16_t rsvd6;
2376         uint16_t vpi;
2377 #else   /*  __LITTLE_ENDIAN */
2378         uint16_t vpi;
2379         uint16_t rsvd6;
2380 #endif
2381 } UNREG_VPI_VAR;
2382
2383 /* Structure for MB Command UNREG_D_ID (0x23) */
2384
2385 typedef struct {
2386         uint32_t did;
2387         uint32_t rsvd2;
2388         uint32_t rsvd3;
2389         uint32_t rsvd4;
2390         uint32_t rsvd5;
2391 #ifdef __BIG_ENDIAN_BITFIELD
2392         uint16_t rsvd6;
2393         uint16_t vpi;
2394 #else
2395         uint16_t vpi;
2396         uint16_t rsvd6;
2397 #endif
2398 } UNREG_D_ID_VAR;
2399
2400 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2401 struct lpfc_mbx_read_top {
2402         uint32_t eventTag;      /* Event tag */
2403         uint32_t word2;
2404 #define lpfc_mbx_read_top_fa_SHIFT              12
2405 #define lpfc_mbx_read_top_fa_MASK               0x00000001
2406 #define lpfc_mbx_read_top_fa_WORD               word2
2407 #define lpfc_mbx_read_top_mm_SHIFT              11
2408 #define lpfc_mbx_read_top_mm_MASK               0x00000001
2409 #define lpfc_mbx_read_top_mm_WORD               word2
2410 #define lpfc_mbx_read_top_pb_SHIFT              9
2411 #define lpfc_mbx_read_top_pb_MASK               0X00000001
2412 #define lpfc_mbx_read_top_pb_WORD               word2
2413 #define lpfc_mbx_read_top_il_SHIFT              8
2414 #define lpfc_mbx_read_top_il_MASK               0x00000001
2415 #define lpfc_mbx_read_top_il_WORD               word2
2416 #define lpfc_mbx_read_top_att_type_SHIFT        0
2417 #define lpfc_mbx_read_top_att_type_MASK         0x000000FF
2418 #define lpfc_mbx_read_top_att_type_WORD         word2
2419 #define LPFC_ATT_RESERVED    0x00       /* Reserved - attType */
2420 #define LPFC_ATT_LINK_UP     0x01       /* Link is up */
2421 #define LPFC_ATT_LINK_DOWN   0x02       /* Link is down */
2422         uint32_t word3;
2423 #define lpfc_mbx_read_top_alpa_granted_SHIFT    24
2424 #define lpfc_mbx_read_top_alpa_granted_MASK     0x000000FF
2425 #define lpfc_mbx_read_top_alpa_granted_WORD     word3
2426 #define lpfc_mbx_read_top_lip_alps_SHIFT        16
2427 #define lpfc_mbx_read_top_lip_alps_MASK         0x000000FF
2428 #define lpfc_mbx_read_top_lip_alps_WORD         word3
2429 #define lpfc_mbx_read_top_lip_type_SHIFT        8
2430 #define lpfc_mbx_read_top_lip_type_MASK         0x000000FF
2431 #define lpfc_mbx_read_top_lip_type_WORD         word3
2432 #define lpfc_mbx_read_top_topology_SHIFT        0
2433 #define lpfc_mbx_read_top_topology_MASK         0x000000FF
2434 #define lpfc_mbx_read_top_topology_WORD         word3
2435 #define LPFC_TOPOLOGY_PT_PT 0x01        /* Topology is pt-pt / pt-fabric */
2436 #define LPFC_TOPOLOGY_LOOP  0x02        /* Topology is FC-AL */
2437 #define LPFC_TOPOLOGY_MM    0x05        /* maint mode zephtr to menlo */
2438         /* store the LILP AL_PA position map into */
2439         struct ulp_bde64 lilpBde64;
2440 #define LPFC_ALPA_MAP_SIZE      128
2441         uint32_t word7;
2442 #define lpfc_mbx_read_top_ld_lu_SHIFT           31
2443 #define lpfc_mbx_read_top_ld_lu_MASK            0x00000001
2444 #define lpfc_mbx_read_top_ld_lu_WORD            word7
2445 #define lpfc_mbx_read_top_ld_tf_SHIFT           30
2446 #define lpfc_mbx_read_top_ld_tf_MASK            0x00000001
2447 #define lpfc_mbx_read_top_ld_tf_WORD            word7
2448 #define lpfc_mbx_read_top_ld_link_spd_SHIFT     8
2449 #define lpfc_mbx_read_top_ld_link_spd_MASK      0x000000FF
2450 #define lpfc_mbx_read_top_ld_link_spd_WORD      word7
2451 #define lpfc_mbx_read_top_ld_nl_port_SHIFT      4
2452 #define lpfc_mbx_read_top_ld_nl_port_MASK       0x0000000F
2453 #define lpfc_mbx_read_top_ld_nl_port_WORD       word7
2454 #define lpfc_mbx_read_top_ld_tx_SHIFT           2
2455 #define lpfc_mbx_read_top_ld_tx_MASK            0x00000003
2456 #define lpfc_mbx_read_top_ld_tx_WORD            word7
2457 #define lpfc_mbx_read_top_ld_rx_SHIFT           0
2458 #define lpfc_mbx_read_top_ld_rx_MASK            0x00000003
2459 #define lpfc_mbx_read_top_ld_rx_WORD            word7
2460         uint32_t word8;
2461 #define lpfc_mbx_read_top_lu_SHIFT              31
2462 #define lpfc_mbx_read_top_lu_MASK               0x00000001
2463 #define lpfc_mbx_read_top_lu_WORD               word8
2464 #define lpfc_mbx_read_top_tf_SHIFT              30
2465 #define lpfc_mbx_read_top_tf_MASK               0x00000001
2466 #define lpfc_mbx_read_top_tf_WORD               word8
2467 #define lpfc_mbx_read_top_link_spd_SHIFT        8
2468 #define lpfc_mbx_read_top_link_spd_MASK         0x000000FF
2469 #define lpfc_mbx_read_top_link_spd_WORD         word8
2470 #define lpfc_mbx_read_top_nl_port_SHIFT         4
2471 #define lpfc_mbx_read_top_nl_port_MASK          0x0000000F
2472 #define lpfc_mbx_read_top_nl_port_WORD          word8
2473 #define lpfc_mbx_read_top_tx_SHIFT              2
2474 #define lpfc_mbx_read_top_tx_MASK               0x00000003
2475 #define lpfc_mbx_read_top_tx_WORD               word8
2476 #define lpfc_mbx_read_top_rx_SHIFT              0
2477 #define lpfc_mbx_read_top_rx_MASK               0x00000003
2478 #define lpfc_mbx_read_top_rx_WORD               word8
2479 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2480 #define LPFC_LINK_SPEED_1GHZ    0x04
2481 #define LPFC_LINK_SPEED_2GHZ    0x08
2482 #define LPFC_LINK_SPEED_4GHZ    0x10
2483 #define LPFC_LINK_SPEED_8GHZ    0x20
2484 #define LPFC_LINK_SPEED_10GHZ   0x40
2485 #define LPFC_LINK_SPEED_16GHZ   0x80
2486 };
2487
2488 /* Structure for MB Command CLEAR_LA (22) */
2489
2490 typedef struct {
2491         uint32_t eventTag;      /* Event tag */
2492         uint32_t rsvd1;
2493 } CLEAR_LA_VAR;
2494
2495 /* Structure for MB Command DUMP */
2496
2497 typedef struct {
2498 #ifdef __BIG_ENDIAN_BITFIELD
2499         uint32_t rsvd:25;
2500         uint32_t ra:1;
2501         uint32_t co:1;
2502         uint32_t cv:1;
2503         uint32_t type:4;
2504         uint32_t entry_index:16;
2505         uint32_t region_id:16;
2506 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2507         uint32_t type:4;
2508         uint32_t cv:1;
2509         uint32_t co:1;
2510         uint32_t ra:1;
2511         uint32_t rsvd:25;
2512         uint32_t region_id:16;
2513         uint32_t entry_index:16;
2514 #endif
2515
2516         uint32_t sli4_length;
2517         uint32_t word_cnt;
2518         uint32_t resp_offset;
2519 } DUMP_VAR;
2520
2521 #define  DMP_MEM_REG             0x1
2522 #define  DMP_NV_PARAMS           0x2
2523
2524 #define  DMP_REGION_VPD          0xe
2525 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
2526 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
2527 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
2528
2529 #define  DMP_REGION_VPORT        0x16   /* VPort info region */
2530 #define  DMP_VPORT_REGION_SIZE   0x200
2531 #define  DMP_MBOX_OFFSET_WORD    0x5
2532
2533 #define  DMP_REGION_23           0x17   /* fcoe param  and port state region */
2534 #define  DMP_RGN23_SIZE          0x400
2535
2536 #define  WAKE_UP_PARMS_REGION_ID    4
2537 #define  WAKE_UP_PARMS_WORD_SIZE   15
2538
2539 struct vport_rec {
2540         uint8_t wwpn[8];
2541         uint8_t wwnn[8];
2542 };
2543
2544 #define VPORT_INFO_SIG 0x32324752
2545 #define VPORT_INFO_REV_MASK 0xff
2546 #define VPORT_INFO_REV 0x1
2547 #define MAX_STATIC_VPORT_COUNT 16
2548 struct static_vport_info {
2549         uint32_t                signature;
2550         uint32_t                rev;
2551         struct vport_rec        vport_list[MAX_STATIC_VPORT_COUNT];
2552         uint32_t                resvd[66];
2553 };
2554
2555 /* Option rom version structure */
2556 struct prog_id {
2557 #ifdef __BIG_ENDIAN_BITFIELD
2558         uint8_t  type;
2559         uint8_t  id;
2560         uint32_t ver:4;  /* Major Version */
2561         uint32_t rev:4;  /* Revision */
2562         uint32_t lev:2;  /* Level */
2563         uint32_t dist:2; /* Dist Type */
2564         uint32_t num:4;  /* number after dist type */
2565 #else /*  __LITTLE_ENDIAN_BITFIELD */
2566         uint32_t num:4;  /* number after dist type */
2567         uint32_t dist:2; /* Dist Type */
2568         uint32_t lev:2;  /* Level */
2569         uint32_t rev:4;  /* Revision */
2570         uint32_t ver:4;  /* Major Version */
2571         uint8_t  id;
2572         uint8_t  type;
2573 #endif
2574 };
2575
2576 /* Structure for MB Command UPDATE_CFG (0x1B) */
2577
2578 struct update_cfg_var {
2579 #ifdef __BIG_ENDIAN_BITFIELD
2580         uint32_t rsvd2:16;
2581         uint32_t type:8;
2582         uint32_t rsvd:1;
2583         uint32_t ra:1;
2584         uint32_t co:1;
2585         uint32_t cv:1;
2586         uint32_t req:4;
2587         uint32_t entry_length:16;
2588         uint32_t region_id:16;
2589 #else  /*  __LITTLE_ENDIAN_BITFIELD */
2590         uint32_t req:4;
2591         uint32_t cv:1;
2592         uint32_t co:1;
2593         uint32_t ra:1;
2594         uint32_t rsvd:1;
2595         uint32_t type:8;
2596         uint32_t rsvd2:16;
2597         uint32_t region_id:16;
2598         uint32_t entry_length:16;
2599 #endif
2600
2601         uint32_t resp_info;
2602         uint32_t byte_cnt;
2603         uint32_t data_offset;
2604 };
2605
2606 struct hbq_mask {
2607 #ifdef __BIG_ENDIAN_BITFIELD
2608         uint8_t tmatch;
2609         uint8_t tmask;
2610         uint8_t rctlmatch;
2611         uint8_t rctlmask;
2612 #else   /*  __LITTLE_ENDIAN */
2613         uint8_t rctlmask;
2614         uint8_t rctlmatch;
2615         uint8_t tmask;
2616         uint8_t tmatch;
2617 #endif
2618 };
2619
2620
2621 /* Structure for MB Command CONFIG_HBQ (7c) */
2622
2623 struct config_hbq_var {
2624 #ifdef __BIG_ENDIAN_BITFIELD
2625         uint32_t rsvd1      :7;
2626         uint32_t recvNotify :1;     /* Receive Notification */
2627         uint32_t numMask    :8;     /* # Mask Entries       */
2628         uint32_t profile    :8;     /* Selection Profile    */
2629         uint32_t rsvd2      :8;
2630 #else   /*  __LITTLE_ENDIAN */
2631         uint32_t rsvd2      :8;
2632         uint32_t profile    :8;     /* Selection Profile    */
2633         uint32_t numMask    :8;     /* # Mask Entries       */
2634         uint32_t recvNotify :1;     /* Receive Notification */
2635         uint32_t rsvd1      :7;
2636 #endif
2637
2638 #ifdef __BIG_ENDIAN_BITFIELD
2639         uint32_t hbqId      :16;
2640         uint32_t rsvd3      :12;
2641         uint32_t ringMask   :4;
2642 #else   /*  __LITTLE_ENDIAN */
2643         uint32_t ringMask   :4;
2644         uint32_t rsvd3      :12;
2645         uint32_t hbqId      :16;
2646 #endif
2647
2648 #ifdef __BIG_ENDIAN_BITFIELD
2649         uint32_t entry_count :16;
2650         uint32_t rsvd4        :8;
2651         uint32_t headerLen    :8;
2652 #else   /*  __LITTLE_ENDIAN */
2653         uint32_t headerLen    :8;
2654         uint32_t rsvd4        :8;
2655         uint32_t entry_count :16;
2656 #endif
2657
2658         uint32_t hbqaddrLow;
2659         uint32_t hbqaddrHigh;
2660
2661 #ifdef __BIG_ENDIAN_BITFIELD
2662         uint32_t rsvd5      :31;
2663         uint32_t logEntry   :1;
2664 #else   /*  __LITTLE_ENDIAN */
2665         uint32_t logEntry   :1;
2666         uint32_t rsvd5      :31;
2667 #endif
2668
2669         uint32_t rsvd6;    /* w7 */
2670         uint32_t rsvd7;    /* w8 */
2671         uint32_t rsvd8;    /* w9 */
2672
2673         struct hbq_mask hbqMasks[6];
2674
2675
2676         union {
2677                 uint32_t allprofiles[12];
2678
2679                 struct {
2680                         #ifdef __BIG_ENDIAN_BITFIELD
2681                                 uint32_t        seqlenoff       :16;
2682                                 uint32_t        maxlen          :16;
2683                         #else   /*  __LITTLE_ENDIAN */
2684                                 uint32_t        maxlen          :16;
2685                                 uint32_t        seqlenoff       :16;
2686                         #endif
2687                         #ifdef __BIG_ENDIAN_BITFIELD
2688                                 uint32_t        rsvd1           :28;
2689                                 uint32_t        seqlenbcnt      :4;
2690                         #else   /*  __LITTLE_ENDIAN */
2691                                 uint32_t        seqlenbcnt      :4;
2692                                 uint32_t        rsvd1           :28;
2693                         #endif
2694                         uint32_t rsvd[10];
2695                 } profile2;
2696
2697                 struct {
2698                         #ifdef __BIG_ENDIAN_BITFIELD
2699                                 uint32_t        seqlenoff       :16;
2700                                 uint32_t        maxlen          :16;
2701                         #else   /*  __LITTLE_ENDIAN */
2702                                 uint32_t        maxlen          :16;
2703                                 uint32_t        seqlenoff       :16;
2704                         #endif
2705                         #ifdef __BIG_ENDIAN_BITFIELD
2706                                 uint32_t        cmdcodeoff      :28;
2707                                 uint32_t        rsvd1           :12;
2708                                 uint32_t        seqlenbcnt      :4;
2709                         #else   /*  __LITTLE_ENDIAN */
2710                                 uint32_t        seqlenbcnt      :4;
2711                                 uint32_t        rsvd1           :12;
2712                                 uint32_t        cmdcodeoff      :28;
2713                         #endif
2714                         uint32_t cmdmatch[8];
2715
2716                         uint32_t rsvd[2];
2717                 } profile3;
2718
2719                 struct {
2720                         #ifdef __BIG_ENDIAN_BITFIELD
2721                                 uint32_t        seqlenoff       :16;
2722                                 uint32_t        maxlen          :16;
2723                         #else   /*  __LITTLE_ENDIAN */
2724                                 uint32_t        maxlen          :16;
2725                                 uint32_t        seqlenoff       :16;
2726                         #endif
2727                         #ifdef __BIG_ENDIAN_BITFIELD
2728                                 uint32_t        cmdcodeoff      :28;
2729                                 uint32_t        rsvd1           :12;
2730                                 uint32_t        seqlenbcnt      :4;
2731                         #else   /*  __LITTLE_ENDIAN */
2732                                 uint32_t        seqlenbcnt      :4;
2733                                 uint32_t        rsvd1           :12;
2734                                 uint32_t        cmdcodeoff      :28;
2735                         #endif
2736                         uint32_t cmdmatch[8];
2737
2738                         uint32_t rsvd[2];
2739                 } profile5;
2740
2741         } profiles;
2742
2743 };
2744
2745
2746
2747 /* Structure for MB Command CONFIG_PORT (0x88) */
2748 typedef struct {
2749 #ifdef __BIG_ENDIAN_BITFIELD
2750         uint32_t cBE       :  1;
2751         uint32_t cET       :  1;
2752         uint32_t cHpcb     :  1;
2753         uint32_t cMA       :  1;
2754         uint32_t sli_mode  :  4;
2755         uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
2756                                         * config block */
2757 #else   /*  __LITTLE_ENDIAN */
2758         uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
2759                                         * config block */
2760         uint32_t sli_mode  :  4;
2761         uint32_t cMA       :  1;
2762         uint32_t cHpcb     :  1;
2763         uint32_t cET       :  1;
2764         uint32_t cBE       :  1;
2765 #endif
2766
2767         uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
2768         uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
2769         uint32_t hbainit[5];
2770 #ifdef __BIG_ENDIAN_BITFIELD
2771         uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
2772         uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
2773 #else   /*  __LITTLE_ENDIAN */
2774         uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
2775         uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
2776 #endif
2777
2778 #ifdef __BIG_ENDIAN_BITFIELD
2779         uint32_t rsvd1     : 19;  /* Reserved                             */
2780         uint32_t cdss      :  1;  /* Configure Data Security SLI          */
2781         uint32_t rsvd2     :  3;  /* Reserved                             */
2782         uint32_t cbg       :  1;  /* Configure BlockGuard                 */
2783         uint32_t cmv       :  1;  /* Configure Max VPIs                   */
2784         uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
2785         uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
2786         uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
2787         uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
2788         uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
2789         uint32_t cmx       :  1;  /* Configure Max XRIs                   */
2790         uint32_t cmr       :  1;  /* Configure Max RPIs                   */
2791 #else   /*  __LITTLE_ENDIAN */
2792         uint32_t cmr       :  1;  /* Configure Max RPIs                   */
2793         uint32_t cmx       :  1;  /* Configure Max XRIs                   */
2794         uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
2795         uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
2796         uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
2797         uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
2798         uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
2799         uint32_t cmv       :  1;  /* Configure Max VPIs                   */
2800         uint32_t cbg       :  1;  /* Configure BlockGuard                 */
2801         uint32_t rsvd2     :  3;  /* Reserved                             */
2802         uint32_t cdss      :  1;  /* Configure Data Security SLI          */
2803         uint32_t rsvd1     : 19;  /* Reserved                             */
2804 #endif
2805 #ifdef __BIG_ENDIAN_BITFIELD
2806         uint32_t rsvd3     : 19;  /* Reserved                             */
2807         uint32_t gdss      :  1;  /* Configure Data Security SLI          */
2808         uint32_t rsvd4     :  3;  /* Reserved                             */
2809         uint32_t gbg       :  1;  /* Grant BlockGuard                     */
2810         uint32_t gmv       :  1;  /* Grant Max VPIs                       */
2811         uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
2812         uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
2813         uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
2814         uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
2815         uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
2816         uint32_t gmx       :  1;  /* Grant Max XRIs                       */
2817         uint32_t gmr       :  1;  /* Grant Max RPIs                       */
2818 #else   /*  __LITTLE_ENDIAN */
2819         uint32_t gmr       :  1;  /* Grant Max RPIs                       */
2820         uint32_t gmx       :  1;  /* Grant Max XRIs                       */
2821         uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
2822         uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
2823         uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
2824         uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
2825         uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
2826         uint32_t gmv       :  1;  /* Grant Max VPIs                       */
2827         uint32_t gbg       :  1;  /* Grant BlockGuard                     */
2828         uint32_t rsvd4     :  3;  /* Reserved                             */
2829         uint32_t gdss      :  1;  /* Configure Data Security SLI          */
2830         uint32_t rsvd3     : 19;  /* Reserved                             */
2831 #endif
2832
2833 #ifdef __BIG_ENDIAN_BITFIELD
2834         uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
2835         uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
2836 #else   /*  __LITTLE_ENDIAN */
2837         uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
2838         uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
2839 #endif
2840
2841 #ifdef __BIG_ENDIAN_BITFIELD
2842         uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
2843         uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
2844 #else   /*  __LITTLE_ENDIAN */
2845         uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
2846         uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
2847 #endif
2848
2849         uint32_t rsvd6;           /* Reserved                             */
2850
2851 #ifdef __BIG_ENDIAN_BITFIELD
2852         uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
2853         uint32_t fips_level : 4;   /* FIPS Level                           */
2854         uint32_t sec_err    : 9;   /* security crypto error                */
2855         uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
2856 #else   /*  __LITTLE_ENDIAN */
2857         uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
2858         uint32_t sec_err    : 9;   /* security crypto error                */
2859         uint32_t fips_level : 4;   /* FIPS Level                           */
2860         uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
2861 #endif
2862
2863 } CONFIG_PORT_VAR;
2864
2865 /* Structure for MB Command CONFIG_MSI (0x30) */
2866 struct config_msi_var {
2867 #ifdef __BIG_ENDIAN_BITFIELD
2868         uint32_t dfltMsgNum:8;  /* Default message number            */
2869         uint32_t rsvd1:11;      /* Reserved                          */
2870         uint32_t NID:5;         /* Number of secondary attention IDs */
2871         uint32_t rsvd2:5;       /* Reserved                          */
2872         uint32_t dfltPresent:1; /* Default message number present    */
2873         uint32_t addFlag:1;     /* Add association flag              */
2874         uint32_t reportFlag:1;  /* Report association flag           */
2875 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2876         uint32_t reportFlag:1;  /* Report association flag           */
2877         uint32_t addFlag:1;     /* Add association flag              */
2878         uint32_t dfltPresent:1; /* Default message number present    */
2879         uint32_t rsvd2:5;       /* Reserved                          */
2880         uint32_t NID:5;         /* Number of secondary attention IDs */
2881         uint32_t rsvd1:11;      /* Reserved                          */
2882         uint32_t dfltMsgNum:8;  /* Default message number            */
2883 #endif
2884         uint32_t attentionConditions[2];
2885         uint8_t  attentionId[16];
2886         uint8_t  messageNumberByHA[64];
2887         uint8_t  messageNumberByID[16];
2888         uint32_t autoClearHA[2];
2889 #ifdef __BIG_ENDIAN_BITFIELD
2890         uint32_t rsvd3:16;
2891         uint32_t autoClearID:16;
2892 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2893         uint32_t autoClearID:16;
2894         uint32_t rsvd3:16;
2895 #endif
2896         uint32_t rsvd4;
2897 };
2898
2899 /* SLI-2 Port Control Block */
2900
2901 /* SLIM POINTER */
2902 #define SLIMOFF 0x30            /* WORD */
2903
2904 typedef struct _SLI2_RDSC {
2905         uint32_t cmdEntries;
2906         uint32_t cmdAddrLow;
2907         uint32_t cmdAddrHigh;
2908
2909         uint32_t rspEntries;
2910         uint32_t rspAddrLow;
2911         uint32_t rspAddrHigh;
2912 } SLI2_RDSC;
2913
2914 typedef struct _PCB {
2915 #ifdef __BIG_ENDIAN_BITFIELD
2916         uint32_t type:8;
2917 #define TYPE_NATIVE_SLI2       0x01;
2918         uint32_t feature:8;
2919 #define FEATURE_INITIAL_SLI2   0x01;
2920         uint32_t rsvd:12;
2921         uint32_t maxRing:4;
2922 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2923         uint32_t maxRing:4;
2924         uint32_t rsvd:12;
2925         uint32_t feature:8;
2926 #define FEATURE_INITIAL_SLI2   0x01;
2927         uint32_t type:8;
2928 #define TYPE_NATIVE_SLI2       0x01;
2929 #endif
2930
2931         uint32_t mailBoxSize;
2932         uint32_t mbAddrLow;
2933         uint32_t mbAddrHigh;
2934
2935         uint32_t hgpAddrLow;
2936         uint32_t hgpAddrHigh;
2937
2938         uint32_t pgpAddrLow;
2939         uint32_t pgpAddrHigh;
2940         SLI2_RDSC rdsc[MAX_RINGS];
2941 } PCB_t;
2942
2943 /* NEW_FEATURE */
2944 typedef struct {
2945 #ifdef __BIG_ENDIAN_BITFIELD
2946         uint32_t rsvd0:27;
2947         uint32_t discardFarp:1;
2948         uint32_t IPEnable:1;
2949         uint32_t nodeName:1;
2950         uint32_t portName:1;
2951         uint32_t filterEnable:1;
2952 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2953         uint32_t filterEnable:1;
2954         uint32_t portName:1;
2955         uint32_t nodeName:1;
2956         uint32_t IPEnable:1;
2957         uint32_t discardFarp:1;
2958         uint32_t rsvd:27;
2959 #endif
2960
2961         uint8_t portname[8];    /* Used to be struct lpfc_name */
2962         uint8_t nodename[8];
2963         uint32_t rsvd1;
2964         uint32_t rsvd2;
2965         uint32_t rsvd3;
2966         uint32_t IPAddress;
2967 } CONFIG_FARP_VAR;
2968
2969 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
2970
2971 typedef struct {
2972 #ifdef __BIG_ENDIAN_BITFIELD
2973         uint32_t rsvd:30;
2974         uint32_t ring:2;        /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2975 #else /*  __LITTLE_ENDIAN */
2976         uint32_t ring:2;        /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2977         uint32_t rsvd:30;
2978 #endif
2979 } ASYNCEVT_ENABLE_VAR;
2980
2981 /* Union of all Mailbox Command types */
2982 #define MAILBOX_CMD_WSIZE       32
2983 #define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2984 /* ext_wsize times 4 bytes should not be greater than max xmit size */
2985 #define MAILBOX_EXT_WSIZE       512
2986 #define MAILBOX_EXT_SIZE        (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
2987 #define MAILBOX_HBA_EXT_OFFSET  0x100
2988 /* max mbox xmit size is a page size for sysfs IO operations */
2989 #define MAILBOX_MAX_XMIT_SIZE   PAGE_SIZE
2990
2991 typedef union {
2992         uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2993                                                     * feature/max ring number
2994                                                     */
2995         LOAD_SM_VAR varLdSM;            /* cmd =  1 (LOAD_SM)        */
2996         READ_NV_VAR varRDnvp;           /* cmd =  2 (READ_NVPARMS)   */
2997         WRITE_NV_VAR varWTnvp;          /* cmd =  3 (WRITE_NVPARMS)  */
2998         BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
2999         INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
3000         DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
3001         CONFIG_LINK varCfgLnk;          /* cmd =  7 (CONFIG_LINK)    */
3002         PART_SLIM_VAR varSlim;          /* cmd =  8 (PART_SLIM)      */
3003         CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
3004         RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
3005         READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
3006         READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
3007         READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
3008         READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
3009         READ_RPI_VAR varRdRPI;          /* cmd = 15 (READ_RPI(64))   */
3010         READ_XRI_VAR varRdXRI;          /* cmd = 16 (READ_XRI)       */
3011         READ_REV_VAR varRdRev;          /* cmd = 17 (READ_REV)       */
3012         READ_LNK_VAR varRdLnk;          /* cmd = 18 (READ_LNK_STAT)  */
3013         REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
3014         UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
3015         CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
3016         DUMP_VAR varDmp;                /* Warm Start DUMP mbx cmd   */
3017         UNREG_D_ID_VAR varUnregDID;     /* cmd = 0x23 (UNREG_D_ID)   */
3018         CONFIG_FARP_VAR varCfgFarp;     /* cmd = 0x25 (CONFIG_FARP)
3019                                          * NEW_FEATURE
3020                                          */
3021         struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
3022         struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3023         CONFIG_PORT_VAR varCfgPort;     /* cmd = 0x88 (CONFIG_PORT)  */
3024         struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3025         REG_VPI_VAR varRegVpi;          /* cmd = 0x96 (REG_VPI) */
3026         UNREG_VPI_VAR varUnregVpi;      /* cmd = 0x97 (UNREG_VPI) */
3027         ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3028         struct READ_EVENT_LOG_VAR varRdEventLog;        /* cmd = 0x38
3029                                                          * (READ_EVENT_LOG)
3030                                                          */
3031         struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI)     */
3032 } MAILVARIANTS;
3033
3034 /*
3035  * SLI-2 specific structures
3036  */
3037
3038 struct lpfc_hgp {
3039         __le32 cmdPutInx;
3040         __le32 rspGetInx;
3041 };
3042
3043 struct lpfc_pgp {
3044         __le32 cmdGetInx;
3045         __le32 rspPutInx;
3046 };
3047
3048 struct sli2_desc {
3049         uint32_t unused1[16];
3050         struct lpfc_hgp host[MAX_RINGS];
3051         struct lpfc_pgp port[MAX_RINGS];
3052 };
3053
3054 struct sli3_desc {
3055         struct lpfc_hgp host[MAX_RINGS];
3056         uint32_t reserved[8];
3057         uint32_t hbq_put[16];
3058 };
3059
3060 struct sli3_pgp {
3061         struct lpfc_pgp port[MAX_RINGS];
3062         uint32_t hbq_get[16];
3063 };
3064
3065 union sli_var {
3066         struct sli2_desc        s2;
3067         struct sli3_desc        s3;
3068         struct sli3_pgp         s3_pgp;
3069 };
3070
3071 typedef struct {
3072 #ifdef __BIG_ENDIAN_BITFIELD
3073         uint16_t mbxStatus;
3074         uint8_t mbxCommand;
3075         uint8_t mbxReserved:6;
3076         uint8_t mbxHc:1;
3077         uint8_t mbxOwner:1;     /* Low order bit first word */
3078 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3079         uint8_t mbxOwner:1;     /* Low order bit first word */
3080         uint8_t mbxHc:1;
3081         uint8_t mbxReserved:6;
3082         uint8_t mbxCommand;
3083         uint16_t mbxStatus;
3084 #endif
3085
3086         MAILVARIANTS un;
3087         union sli_var us;
3088 } MAILBOX_t;
3089
3090 /*
3091  *    Begin Structure Definitions for IOCB Commands
3092  */
3093
3094 typedef struct {
3095 #ifdef __BIG_ENDIAN_BITFIELD
3096         uint8_t statAction;
3097         uint8_t statRsn;
3098         uint8_t statBaExp;
3099         uint8_t statLocalError;
3100 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3101         uint8_t statLocalError;
3102         uint8_t statBaExp;
3103         uint8_t statRsn;
3104         uint8_t statAction;
3105 #endif
3106         /* statRsn  P/F_RJT reason codes */
3107 #define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
3108 #define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
3109 #define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
3110 #define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
3111 #define RJT_UNSUP_CLASS    0x05 /* Class not supported */
3112 #define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
3113 #define RJT_UNSUP_TYPE     0x07 /* Type not supported */
3114 #define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
3115 #define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
3116 #define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
3117 #define RJT_BAD_OXID       0x0B /* OX_ID invalid */
3118 #define RJT_BAD_RXID       0x0C /* RX_ID invalid */
3119 #define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
3120 #define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
3121 #define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
3122 #define RJT_BAD_PARM       0x10 /* Param. field invalid */
3123 #define RJT_XCHG_ERR       0x11 /* Exchange error */
3124 #define RJT_PROT_ERR       0x12 /* Protocol error */
3125 #define RJT_BAD_LENGTH     0x13 /* Invalid Length */
3126 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3127 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3128 #define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
3129 #define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
3130 #define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
3131 #define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
3132 #define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
3133
3134 #define IOERR_SUCCESS                 0x00      /* statLocalError */
3135 #define IOERR_MISSING_CONTINUE        0x01
3136 #define IOERR_SEQUENCE_TIMEOUT        0x02
3137 #define IOERR_INTERNAL_ERROR          0x03
3138 #define IOERR_INVALID_RPI             0x04
3139 #define IOERR_NO_XRI                  0x05
3140 #define IOERR_ILLEGAL_COMMAND         0x06
3141 #define IOERR_XCHG_DROPPED            0x07
3142 #define IOERR_ILLEGAL_FIELD           0x08
3143 #define IOERR_BAD_CONTINUE            0x09
3144 #define IOERR_TOO_MANY_BUFFERS        0x0A
3145 #define IOERR_RCV_BUFFER_WAITING      0x0B
3146 #define IOERR_NO_CONNECTION           0x0C
3147 #define IOERR_TX_DMA_FAILED           0x0D
3148 #define IOERR_RX_DMA_FAILED           0x0E
3149 #define IOERR_ILLEGAL_FRAME           0x0F
3150 #define IOERR_EXTRA_DATA              0x10
3151 #define IOERR_NO_RESOURCES            0x11
3152 #define IOERR_RESERVED                0x12
3153 #define IOERR_ILLEGAL_LENGTH          0x13
3154 #define IOERR_UNSUPPORTED_FEATURE     0x14
3155 #define IOERR_ABORT_IN_PROGRESS       0x15
3156 #define IOERR_ABORT_REQUESTED         0x16
3157 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
3158 #define IOERR_LOOP_OPEN_FAILURE       0x18
3159 #define IOERR_RING_RESET              0x19
3160 #define IOERR_LINK_DOWN               0x1A
3161 #define IOERR_CORRUPTED_DATA          0x1B
3162 #define IOERR_CORRUPTED_RPI           0x1C
3163 #define IOERR_OUT_OF_ORDER_DATA       0x1D
3164 #define IOERR_OUT_OF_ORDER_ACK        0x1E
3165 #define IOERR_DUP_FRAME               0x1F
3166 #define IOERR_LINK_CONTROL_FRAME      0x20      /* ACK_N received */
3167 #define IOERR_BAD_HOST_ADDRESS        0x21
3168 #define IOERR_RCV_HDRBUF_WAITING      0x22
3169 #define IOERR_MISSING_HDR_BUFFER      0x23
3170 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
3171 #define IOERR_ABORTMULT_REQUESTED     0x25
3172 #define IOERR_BUFFER_SHORTAGE         0x28
3173 #define IOERR_DEFAULT                 0x29
3174 #define IOERR_CNT                     0x2A
3175 #define IOERR_SLER_FAILURE            0x46
3176 #define IOERR_SLER_CMD_RCV_FAILURE    0x47
3177 #define IOERR_SLER_REC_RJT_ERR        0x48
3178 #define IOERR_SLER_REC_SRR_RETRY_ERR  0x49
3179 #define IOERR_SLER_SRR_RJT_ERR        0x4A
3180 #define IOERR_SLER_RRQ_RJT_ERR        0x4C
3181 #define IOERR_SLER_RRQ_RETRY_ERR      0x4D
3182 #define IOERR_SLER_ABTS_ERR           0x4E
3183
3184 #define IOERR_DRVR_MASK               0x100
3185 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
3186 #define IOERR_SLI_BRESET              0x102
3187 #define IOERR_SLI_ABORTED             0x103
3188 } PARM_ERR;
3189
3190 typedef union {
3191         struct {
3192 #ifdef __BIG_ENDIAN_BITFIELD
3193                 uint8_t Rctl;   /* R_CTL field */
3194                 uint8_t Type;   /* TYPE field */
3195                 uint8_t Dfctl;  /* DF_CTL field */
3196                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3197 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3198                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3199                 uint8_t Dfctl;  /* DF_CTL field */
3200                 uint8_t Type;   /* TYPE field */
3201                 uint8_t Rctl;   /* R_CTL field */
3202 #endif
3203
3204 #define BC      0x02            /* Broadcast Received  - Fctl */
3205 #define SI      0x04            /* Sequence Initiative */
3206 #define LA      0x08            /* Ignore Link Attention state */
3207 #define LS      0x80            /* Last Sequence */
3208         } hcsw;
3209         uint32_t reserved;
3210 } WORD5;
3211
3212 /* IOCB Command template for a generic response */
3213 typedef struct {
3214         uint32_t reserved[4];
3215         PARM_ERR perr;
3216 } GENERIC_RSP;
3217
3218 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3219 typedef struct {
3220         struct ulp_bde xrsqbde[2];
3221         uint32_t xrsqRo;        /* Starting Relative Offset */
3222         WORD5 w5;               /* Header control/status word */
3223 } XR_SEQ_FIELDS;
3224
3225 /* IOCB Command template for ELS_REQUEST */
3226 typedef struct {
3227         struct ulp_bde elsReq;
3228         struct ulp_bde elsRsp;
3229
3230 #ifdef __BIG_ENDIAN_BITFIELD
3231         uint32_t word4Rsvd:7;
3232         uint32_t fl:1;
3233         uint32_t myID:24;
3234         uint32_t word5Rsvd:8;
3235         uint32_t remoteID:24;
3236 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3237         uint32_t myID:24;
3238         uint32_t fl:1;
3239         uint32_t word4Rsvd:7;
3240         uint32_t remoteID:24;
3241         uint32_t word5Rsvd:8;
3242 #endif
3243 } ELS_REQUEST;
3244
3245 /* IOCB Command template for RCV_ELS_REQ */
3246 typedef struct {
3247         struct ulp_bde elsReq[2];
3248         uint32_t parmRo;
3249
3250 #ifdef __BIG_ENDIAN_BITFIELD
3251         uint32_t word5Rsvd:8;
3252         uint32_t remoteID:24;
3253 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3254         uint32_t remoteID:24;
3255         uint32_t word5Rsvd:8;
3256 #endif
3257 } RCV_ELS_REQ;
3258
3259 /* IOCB Command template for ABORT / CLOSE_XRI */
3260 typedef struct {
3261         uint32_t rsvd[3];
3262         uint32_t abortType;
3263 #define ABORT_TYPE_ABTX  0x00000000
3264 #define ABORT_TYPE_ABTS  0x00000001
3265         uint32_t parm;
3266 #ifdef __BIG_ENDIAN_BITFIELD
3267         uint16_t abortContextTag; /* ulpContext from command to abort/close */
3268         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3269 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3270         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3271         uint16_t abortContextTag; /* ulpContext from command to abort/close */
3272 #endif
3273 } AC_XRI;
3274
3275 /* IOCB Command template for ABORT_MXRI64 */
3276 typedef struct {
3277         uint32_t rsvd[3];
3278         uint32_t abortType;
3279         uint32_t parm;
3280         uint32_t iotag32;
3281 } A_MXRI64;
3282
3283 /* IOCB Command template for GET_RPI */
3284 typedef struct {
3285         uint32_t rsvd[4];
3286         uint32_t parmRo;
3287 #ifdef __BIG_ENDIAN_BITFIELD
3288         uint32_t word5Rsvd:8;
3289         uint32_t remoteID:24;
3290 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3291         uint32_t remoteID:24;
3292         uint32_t word5Rsvd:8;
3293 #endif
3294 } GET_RPI;
3295
3296 /* IOCB Command template for all FCP Initiator commands */
3297 typedef struct {
3298         struct ulp_bde fcpi_cmnd;       /* FCP_CMND payload descriptor */
3299         struct ulp_bde fcpi_rsp;        /* Rcv buffer */
3300         uint32_t fcpi_parm;
3301         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
3302 } FCPI_FIELDS;
3303
3304 /* IOCB Command template for all FCP Target commands */
3305 typedef struct {
3306         struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
3307         uint32_t fcpt_Offset;
3308         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
3309 } FCPT_FIELDS;
3310
3311 /* SLI-2 IOCB structure definitions */
3312
3313 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3314 typedef struct {
3315         ULP_BDL bdl;
3316         uint32_t xrsqRo;        /* Starting Relative Offset */
3317         WORD5 w5;               /* Header control/status word */
3318 } XMT_SEQ_FIELDS64;
3319
3320 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3321 typedef struct {
3322         struct ulp_bde64 rcvBde;
3323         uint32_t rsvd1;
3324         uint32_t xrsqRo;        /* Starting Relative Offset */
3325         WORD5 w5;               /* Header control/status word */
3326 } RCV_SEQ_FIELDS64;
3327
3328 /* IOCB Command template for ELS_REQUEST64 */
3329 typedef struct {
3330         ULP_BDL bdl;
3331 #ifdef __BIG_ENDIAN_BITFIELD
3332         uint32_t word4Rsvd:7;
3333         uint32_t fl:1;
3334         uint32_t myID:24;
3335         uint32_t word5Rsvd:8;
3336         uint32_t remoteID:24;
3337 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3338         uint32_t myID:24;
3339         uint32_t fl:1;
3340         uint32_t word4Rsvd:7;
3341         uint32_t remoteID:24;
3342         uint32_t word5Rsvd:8;
3343 #endif
3344 } ELS_REQUEST64;
3345
3346 /* IOCB Command template for GEN_REQUEST64 */
3347 typedef struct {
3348         ULP_BDL bdl;
3349         uint32_t xrsqRo;        /* Starting Relative Offset */
3350         WORD5 w5;               /* Header control/status word */
3351 } GEN_REQUEST64;
3352
3353 /* IOCB Command template for RCV_ELS_REQ64 */
3354 typedef struct {
3355         struct ulp_bde64 elsReq;
3356         uint32_t rcvd1;
3357         uint32_t parmRo;
3358
3359 #ifdef __BIG_ENDIAN_BITFIELD
3360         uint32_t word5Rsvd:8;
3361         uint32_t remoteID:24;
3362 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3363         uint32_t remoteID:24;
3364         uint32_t word5Rsvd:8;
3365 #endif
3366 } RCV_ELS_REQ64;
3367
3368 /* IOCB Command template for RCV_SEQ64 */
3369 struct rcv_seq64 {
3370         struct ulp_bde64 elsReq;
3371         uint32_t hbq_1;
3372         uint32_t parmRo;
3373 #ifdef __BIG_ENDIAN_BITFIELD
3374         uint32_t rctl:8;
3375         uint32_t type:8;
3376         uint32_t dfctl:8;
3377         uint32_t ls:1;
3378         uint32_t fs:1;
3379         uint32_t rsvd2:3;
3380         uint32_t si:1;
3381         uint32_t bc:1;
3382         uint32_t rsvd3:1;
3383 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3384         uint32_t rsvd3:1;
3385         uint32_t bc:1;
3386         uint32_t si:1;
3387         uint32_t rsvd2:3;
3388         uint32_t fs:1;
3389         uint32_t ls:1;
3390         uint32_t dfctl:8;
3391         uint32_t type:8;
3392         uint32_t rctl:8;
3393 #endif
3394 };
3395
3396 /* IOCB Command template for all 64 bit FCP Initiator commands */
3397 typedef struct {
3398         ULP_BDL bdl;
3399         uint32_t fcpi_parm;
3400         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
3401 } FCPI_FIELDS64;
3402
3403 /* IOCB Command template for all 64 bit FCP Target commands */
3404 typedef struct {
3405         ULP_BDL bdl;
3406         uint32_t fcpt_Offset;
3407         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
3408 } FCPT_FIELDS64;
3409
3410 /* IOCB Command template for Async Status iocb commands */
3411 typedef struct {
3412         uint32_t rsvd[4];
3413         uint32_t param;
3414 #ifdef __BIG_ENDIAN_BITFIELD
3415         uint16_t evt_code;              /* High order bits word 5 */
3416         uint16_t sub_ctxt_tag;          /* Low  order bits word 5 */
3417 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3418         uint16_t sub_ctxt_tag;          /* High order bits word 5 */
3419         uint16_t evt_code;              /* Low  order bits word 5 */
3420 #endif
3421 } ASYNCSTAT_FIELDS;
3422 #define ASYNC_TEMP_WARN         0x100
3423 #define ASYNC_TEMP_SAFE         0x101
3424
3425 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3426    or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3427
3428 struct rcv_sli3 {
3429         uint32_t word8Rsvd;
3430 #ifdef __BIG_ENDIAN_BITFIELD
3431         uint16_t vpi;
3432         uint16_t word9Rsvd;
3433 #else  /*  __LITTLE_ENDIAN */
3434         uint16_t word9Rsvd;
3435         uint16_t vpi;
3436 #endif
3437         uint32_t word10Rsvd;
3438         uint32_t acc_len;      /* accumulated length */
3439         struct ulp_bde64 bde2;
3440 };
3441
3442 /* Structure used for a single HBQ entry */
3443 struct lpfc_hbq_entry {
3444         struct ulp_bde64 bde;
3445         uint32_t buffer_tag;
3446 };
3447
3448 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3449 typedef struct {
3450         struct lpfc_hbq_entry   buff;
3451         uint32_t                rsvd;
3452         uint32_t                rsvd1;
3453 } QUE_XRI64_CX_FIELDS;
3454
3455 struct que_xri64cx_ext_fields {
3456         uint32_t        iotag64_low;
3457         uint32_t        iotag64_high;
3458         uint32_t        ebde_count;
3459         uint32_t        rsvd;
3460         struct lpfc_hbq_entry   buff[5];
3461 };
3462
3463 struct sli3_bg_fields {
3464         uint32_t filler[6];     /* word 8-13 in IOCB */
3465         uint32_t bghm;          /* word 14 - BlockGuard High Water Mark */
3466 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3467 #define BGS_BIDIR_BG_PROF_MASK          0xff000000
3468 #define BGS_BIDIR_BG_PROF_SHIFT         24
3469 #define BGS_BIDIR_ERR_COND_FLAGS_MASK   0x003f0000
3470 #define BGS_BIDIR_ERR_COND_SHIFT        16
3471 #define BGS_BG_PROFILE_MASK             0x0000ff00
3472 #define BGS_BG_PROFILE_SHIFT            8
3473 #define BGS_INVALID_PROF_MASK           0x00000020
3474 #define BGS_INVALID_PROF_SHIFT          5
3475 #define BGS_UNINIT_DIF_BLOCK_MASK       0x00000010
3476 #define BGS_UNINIT_DIF_BLOCK_SHIFT      4
3477 #define BGS_HI_WATER_MARK_PRESENT_MASK  0x00000008
3478 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3479 #define BGS_REFTAG_ERR_MASK             0x00000004
3480 #define BGS_REFTAG_ERR_SHIFT            2
3481 #define BGS_APPTAG_ERR_MASK             0x00000002
3482 #define BGS_APPTAG_ERR_SHIFT            1
3483 #define BGS_GUARD_ERR_MASK              0x00000001
3484 #define BGS_GUARD_ERR_SHIFT             0
3485         uint32_t bgstat;        /* word 15 - BlockGuard Status */
3486 };
3487
3488 static inline uint32_t
3489 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3490 {
3491         return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3492                                 BGS_BIDIR_BG_PROF_SHIFT;
3493 }
3494
3495 static inline uint32_t
3496 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3497 {
3498         return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3499                                 BGS_BIDIR_ERR_COND_SHIFT;
3500 }
3501
3502 static inline uint32_t
3503 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3504 {
3505         return (bgstat & BGS_BG_PROFILE_MASK) >>
3506                                 BGS_BG_PROFILE_SHIFT;
3507 }
3508
3509 static inline uint32_t
3510 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3511 {
3512         return (bgstat & BGS_INVALID_PROF_MASK) >>
3513                                 BGS_INVALID_PROF_SHIFT;
3514 }
3515
3516 static inline uint32_t
3517 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3518 {
3519         return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3520                                 BGS_UNINIT_DIF_BLOCK_SHIFT;
3521 }
3522
3523 static inline uint32_t
3524 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3525 {
3526         return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3527                                 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3528 }
3529
3530 static inline uint32_t
3531 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3532 {
3533         return (bgstat & BGS_REFTAG_ERR_MASK) >>
3534                                 BGS_REFTAG_ERR_SHIFT;
3535 }
3536
3537 static inline uint32_t
3538 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3539 {
3540         return (bgstat & BGS_APPTAG_ERR_MASK) >>
3541                                 BGS_APPTAG_ERR_SHIFT;
3542 }
3543
3544 static inline uint32_t
3545 lpfc_bgs_get_guard_err(uint32_t bgstat)
3546 {
3547         return (bgstat & BGS_GUARD_ERR_MASK) >>
3548                                 BGS_GUARD_ERR_SHIFT;
3549 }
3550
3551 #define LPFC_EXT_DATA_BDE_COUNT 3
3552 struct fcp_irw_ext {
3553         uint32_t        io_tag64_low;
3554         uint32_t        io_tag64_high;
3555 #ifdef __BIG_ENDIAN_BITFIELD
3556         uint8_t         reserved1;
3557         uint8_t         reserved2;
3558         uint8_t         reserved3;
3559         uint8_t         ebde_count;
3560 #else  /* __LITTLE_ENDIAN */
3561         uint8_t         ebde_count;
3562         uint8_t         reserved3;
3563         uint8_t         reserved2;
3564         uint8_t         reserved1;
3565 #endif
3566         uint32_t        reserved4;
3567         struct ulp_bde64 rbde;          /* response bde */
3568         struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3569         uint8_t icd[32];                /* immediate command data (32 bytes) */
3570 };
3571
3572 typedef struct _IOCB {  /* IOCB structure */
3573         union {
3574                 GENERIC_RSP grsp;       /* Generic response */
3575                 XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
3576                 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3577                 RCV_ELS_REQ rcvels;     /* RCV_ELS_REQ template */
3578                 AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
3579                 A_MXRI64 amxri; /* abort multiple xri command overlay */
3580                 GET_RPI getrpi; /* GET_RPI template */
3581                 FCPI_FIELDS fcpi;       /* FCP Initiator template */
3582                 FCPT_FIELDS fcpt;       /* FCP target template */
3583
3584                 /* SLI-2 structures */
3585
3586                 struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
3587                                               * bde_64s */
3588                 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3589                 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3590                 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3591                 XMT_SEQ_FIELDS64 xseq64;        /* XMIT / BCAST cmd */
3592                 FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
3593                 FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
3594                 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3595                 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3596                 struct rcv_seq64 rcvseq64;      /* RCV_SEQ64 and RCV_CONT64 */
3597                 struct sli4_bls_acc bls_acc; /* UNSOL ABTS BLS_ACC params */
3598                 uint32_t ulpWord[IOCB_WORD_SZ - 2];     /* generic 6 'words' */
3599         } un;
3600         union {
3601                 struct {
3602 #ifdef __BIG_ENDIAN_BITFIELD
3603                         uint16_t ulpContext;    /* High order bits word 6 */
3604                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
3605 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3606                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
3607                         uint16_t ulpContext;    /* High order bits word 6 */
3608 #endif
3609                 } t1;
3610                 struct {
3611 #ifdef __BIG_ENDIAN_BITFIELD
3612                         uint16_t ulpContext;    /* High order bits word 6 */
3613                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
3614                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
3615 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3616                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
3617                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
3618                         uint16_t ulpContext;    /* High order bits word 6 */
3619 #endif
3620                 } t2;
3621         } un1;
3622 #define ulpContext un1.t1.ulpContext
3623 #define ulpIoTag   un1.t1.ulpIoTag
3624 #define ulpIoTag0  un1.t2.ulpIoTag0
3625
3626 #ifdef __BIG_ENDIAN_BITFIELD
3627         uint32_t ulpTimeout:8;
3628         uint32_t ulpXS:1;
3629         uint32_t ulpFCP2Rcvy:1;
3630         uint32_t ulpPU:2;
3631         uint32_t ulpIr:1;
3632         uint32_t ulpClass:3;
3633         uint32_t ulpCommand:8;
3634         uint32_t ulpStatus:4;
3635         uint32_t ulpBdeCount:2;
3636         uint32_t ulpLe:1;
3637         uint32_t ulpOwner:1;    /* Low order bit word 7 */
3638 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3639         uint32_t ulpOwner:1;    /* Low order bit word 7 */
3640         uint32_t ulpLe:1;
3641         uint32_t ulpBdeCount:2;
3642         uint32_t ulpStatus:4;
3643         uint32_t ulpCommand:8;
3644         uint32_t ulpClass:3;
3645         uint32_t ulpIr:1;
3646         uint32_t ulpPU:2;
3647         uint32_t ulpFCP2Rcvy:1;
3648         uint32_t ulpXS:1;
3649         uint32_t ulpTimeout:8;
3650 #endif
3651
3652         union {
3653                 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3654
3655                 /* words 8-31 used for que_xri_cx iocb */
3656                 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3657                 struct fcp_irw_ext fcp_ext;
3658                 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3659
3660                 /* words 8-15 for BlockGuard */
3661                 struct sli3_bg_fields sli3_bg;
3662         } unsli3;
3663
3664 #define ulpCt_h ulpXS
3665 #define ulpCt_l ulpFCP2Rcvy
3666
3667 #define IOCB_FCP           1    /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3668 #define IOCB_IP            2    /* IOCB is used for IP ELS cmds */
3669 #define PARM_UNUSED        0    /* PU field (Word 4) not used */
3670 #define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
3671 #define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
3672 #define PARM_NPIV_DID      3
3673 #define CLASS1             0    /* Class 1 */
3674 #define CLASS2             1    /* Class 2 */
3675 #define CLASS3             2    /* Class 3 */
3676 #define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
3677
3678 #define IOSTAT_SUCCESS         0x0      /* ulpStatus  - HBA defined */
3679 #define IOSTAT_FCP_RSP_ERROR   0x1
3680 #define IOSTAT_REMOTE_STOP     0x2
3681 #define IOSTAT_LOCAL_REJECT    0x3
3682 #define IOSTAT_NPORT_RJT       0x4
3683 #define IOSTAT_FABRIC_RJT      0x5
3684 #define IOSTAT_NPORT_BSY       0x6
3685 #define IOSTAT_FABRIC_BSY      0x7
3686 #define IOSTAT_INTERMED_RSP    0x8
3687 #define IOSTAT_LS_RJT          0x9
3688 #define IOSTAT_BA_RJT          0xA
3689 #define IOSTAT_RSVD1           0xB
3690 #define IOSTAT_RSVD2           0xC
3691 #define IOSTAT_RSVD3           0xD
3692 #define IOSTAT_RSVD4           0xE
3693 #define IOSTAT_NEED_BUFFER     0xF
3694 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
3695 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
3696 #define IOSTAT_CNT             0x11
3697
3698 } IOCB_t;
3699
3700
3701 #define SLI1_SLIM_SIZE   (4 * 1024)
3702
3703 /* Up to 498 IOCBs will fit into 16k
3704  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3705  */
3706 #define SLI2_SLIM_SIZE   (64 * 1024)
3707
3708 /* Maximum IOCBs that will fit in SLI2 slim */
3709 #define MAX_SLI2_IOCB    498
3710 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3711                             (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3712                             sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3713
3714 /* HBQ entries are 4 words each = 4k */
3715 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
3716                              lpfc_sli_hbq_count())
3717
3718 struct lpfc_sli2_slim {
3719         MAILBOX_t mbx;
3720         uint32_t  mbx_ext_words[MAILBOX_EXT_WSIZE];
3721         PCB_t pcb;
3722         IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3723 };
3724
3725 /*
3726  * This function checks PCI device to allow special handling for LC HBAs.
3727  *
3728  * Parameters:
3729  * device : struct pci_dev 's device field
3730  *
3731  * return 1 => TRUE
3732  *        0 => FALSE
3733  */
3734 static inline int
3735 lpfc_is_LC_HBA(unsigned short device)
3736 {
3737         if ((device == PCI_DEVICE_ID_TFLY) ||
3738             (device == PCI_DEVICE_ID_PFLY) ||
3739             (device == PCI_DEVICE_ID_LP101) ||
3740             (device == PCI_DEVICE_ID_BMID) ||
3741             (device == PCI_DEVICE_ID_BSMB) ||
3742             (device == PCI_DEVICE_ID_ZMID) ||
3743             (device == PCI_DEVICE_ID_ZSMB) ||
3744             (device == PCI_DEVICE_ID_SAT_MID) ||
3745             (device == PCI_DEVICE_ID_SAT_SMB) ||
3746             (device == PCI_DEVICE_ID_RFLY))
3747                 return 1;
3748         else
3749                 return 0;
3750 }
3751
3752 /*
3753  * Determine if an IOCB failed because of a link event or firmware reset.
3754  */
3755
3756 static inline int
3757 lpfc_error_lost_link(IOCB_t *iocbp)
3758 {
3759         return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3760                 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3761                  iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3762                  iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3763 }
3764
3765 #define MENLO_TRANSPORT_TYPE 0xfe
3766 #define MENLO_CONTEXT 0
3767 #define MENLO_PU 3
3768 #define MENLO_TIMEOUT 30
3769 #define SETVAR_MLOMNT 0x103107
3770 #define SETVAR_MLORST 0x103007
3771
3772 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */