drivers/usb/host/ohci-hcd.c

   1 /*
   2  * Open Host Controller Interface (OHCI) driver for USB.
   3  *
   4  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
   5  *
   6  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   7  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   8  *
   9  * [ Initialisation is based on Linus'  ]
  10  * [ uhci code and gregs ohci fragments ]
  11  * [ (C) Copyright 1999 Linus Torvalds  ]
  12  * [ (C) Copyright 1999 Gregory P. Smith]
  13  *
  14  *
  15  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  16  * interfaces (though some non-x86 Intel chips use it).  It supports
  17  * smarter hardware than UHCI.  A download link for the spec available
  18  * through the http://www.usb.org website.
  19  *
  20  * This file is licenced under the GPL.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/pci.h>
  26 #include <linux/kernel.h>
  27 #include <linux/delay.h>
  28 #include <linux/ioport.h>
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/errno.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/list.h>
  35 #include <linux/usb.h>
  36 #include <linux/usb/otg.h>
  37 #include <linux/usb/hcd.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/dmapool.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/debugfs.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/irq.h>
  45 #include <asm/system.h>
  46 #include <asm/unaligned.h>
  47 #include <asm/byteorder.h>
  48
  49
  50 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  51 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  52
  53 /*-------------------------------------------------------------------------*/
  54
  55 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
  56
  57 /* For initializing controller (mask in an HCFS mode too) */
  58 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  59 #define OHCI_INTR_INIT \
  60                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  61                 | OHCI_INTR_RD | OHCI_INTR_WDH)
  62
  63 #ifdef __hppa__
  64 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  65 #define IR_DISABLE
  66 #endif
  67
  68 #ifdef CONFIG_ARCH_OMAP
  69 /* OMAP doesn't support IR (no SMM; not needed) */
  70 #define IR_DISABLE
  71 #endif
  72
  73 /*-------------------------------------------------------------------------*/
  74
  75 static const char       hcd_name [] = "ohci_hcd";
  76
  77 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  78
  79 #include "ohci.h"
  80 #include "pci-quirks.h"
  81
  82 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
  83 static int ohci_init (struct ohci_hcd *ohci);
  84 static void ohci_stop (struct usb_hcd *hcd);
  85
  86 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
  87 static int ohci_restart (struct ohci_hcd *ohci);
  88 #endif
  89
  90 #ifdef CONFIG_PCI
  91 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
  92 #else
  93 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
  94 {
  95         return;
  96 }
  97 #endif
  98
  99
 100 #include "ohci-hub.c"
 101 #include "ohci-dbg.c"
 102 #include "ohci-mem.c"
 103 #include "ohci-q.c"
 104
 105
 106 /*
 107  * On architectures with edge-triggered interrupts we must never return
 108  * IRQ_NONE.
 109  */
 110 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
 111 #define IRQ_NOTMINE     IRQ_HANDLED
 112 #else
 113 #define IRQ_NOTMINE     IRQ_NONE
 114 #endif
 115
 116
 117 /* Some boards misreport power switching/overcurrent */
 118 static int distrust_firmware = 1;
 119 module_param (distrust_firmware, bool, 0);
 120 MODULE_PARM_DESC (distrust_firmware,
 121         "true to distrust firmware power/overcurrent setup");
 122
 123 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
 124 static int no_handshake = 0;
 125 module_param (no_handshake, bool, 0);
 126 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
 127
 128 /*-------------------------------------------------------------------------*/
 129
 130 /*
 131  * queue up an urb for anything except the root hub
 132  */
 133 static int ohci_urb_enqueue (
 134         struct usb_hcd  *hcd,
 135         struct urb      *urb,
 136         gfp_t           mem_flags
 137 ) {
 138         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 139         struct ed       *ed;
 140         urb_priv_t      *urb_priv;
 141         unsigned int    pipe = urb->pipe;
 142         int             i, size = 0;
 143         unsigned long   flags;
 144         int             retval = 0;
 145
 146 #ifdef OHCI_VERBOSE_DEBUG
 147         urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
 148 #endif
 149
 150         /* every endpoint has a ed, locate and maybe (re)initialize it */
 151         if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
 152                 return -ENOMEM;
 153
 154         /* for the private part of the URB we need the number of TDs (size) */
 155         switch (ed->type) {
 156                 case PIPE_CONTROL:
 157                         /* td_submit_urb() doesn't yet handle these */
 158                         if (urb->transfer_buffer_length > 4096)
 159                                 return -EMSGSIZE;
 160
 161                         /* 1 TD for setup, 1 for ACK, plus ... */
 162                         size = 2;
 163                         /* FALLTHROUGH */
 164                 // case PIPE_INTERRUPT:
 165                 // case PIPE_BULK:
 166                 default:
 167                         /* one TD for every 4096 Bytes (can be up to 8K) */
 168                         size += urb->transfer_buffer_length / 4096;
 169                         /* ... and for any remaining bytes ... */
 170                         if ((urb->transfer_buffer_length % 4096) != 0)
 171                                 size++;
 172                         /* ... and maybe a zero length packet to wrap it up */
 173                         if (size == 0)
 174                                 size++;
 175                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 176                                 && (urb->transfer_buffer_length
 177                                         % usb_maxpacket (urb->dev, pipe,
 178                                                 usb_pipeout (pipe))) == 0)
 179                                 size++;
 180                         break;
 181                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
 182                         size = urb->number_of_packets;
 183                         break;
 184         }
 185
 186         /* allocate the private part of the URB */
 187         urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
 188                         mem_flags);
 189         if (!urb_priv)
 190                 return -ENOMEM;
 191         INIT_LIST_HEAD (&urb_priv->pending);
 192         urb_priv->length = size;
 193         urb_priv->ed = ed;
 194
 195         /* allocate the TDs (deferring hash chain updates) */
 196         for (i = 0; i < size; i++) {
 197                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
 198                 if (!urb_priv->td [i]) {
 199                         urb_priv->length = i;
 200                         urb_free_priv (ohci, urb_priv);
 201                         return -ENOMEM;
 202                 }
 203         }
 204
 205         spin_lock_irqsave (&ohci->lock, flags);
 206
 207         /* don't submit to a dead HC */
 208         if (!HCD_HW_ACCESSIBLE(hcd)) {
 209                 retval = -ENODEV;
 210                 goto fail;
 211         }
 212         if (!HC_IS_RUNNING(hcd->state)) {
 213                 retval = -ENODEV;
 214                 goto fail;
 215         }
 216         retval = usb_hcd_link_urb_to_ep(hcd, urb);
 217         if (retval)
 218                 goto fail;
 219
 220         /* schedule the ed if needed */
 221         if (ed->state == ED_IDLE) {
 222                 retval = ed_schedule (ohci, ed);
 223                 if (retval < 0) {
 224                         usb_hcd_unlink_urb_from_ep(hcd, urb);
 225                         goto fail;
 226                 }
 227                 if (ed->type == PIPE_ISOCHRONOUS) {
 228                         u16     frame = ohci_frame_no(ohci);
 229
 230                         /* delay a few frames before the first TD */
 231                         frame += max_t (u16, 8, ed->interval);
 232                         frame &= ~(ed->interval - 1);
 233                         frame |= ed->branch;
 234                         urb->start_frame = frame;
 235
 236                         /* yes, only URB_ISO_ASAP is supported, and
 237                          * urb->start_frame is never used as input.
 238                          */
 239                 }
 240         } else if (ed->type == PIPE_ISOCHRONOUS)
 241                 urb->start_frame = ed->last_iso + ed->interval;
 242
 243         /* fill the TDs and link them to the ed; and
 244          * enable that part of the schedule, if needed
 245          * and update count of queued periodic urbs
 246          */
 247         urb->hcpriv = urb_priv;
 248         td_submit_urb (ohci, urb);
 249
 250 fail:
 251         if (retval)
 252                 urb_free_priv (ohci, urb_priv);
 253         spin_unlock_irqrestore (&ohci->lock, flags);
 254         return retval;
 255 }
 256
 257 /*
 258  * decouple the URB from the HC queues (TDs, urb_priv).
 259  * reporting is always done
 260  * asynchronously, and we might be dealing with an urb that's
 261  * partially transferred, or an ED with other urbs being unlinked.
 262  */
 263 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 264 {
 265         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 266         unsigned long           flags;
 267         int                     rc;
 268
 269 #ifdef OHCI_VERBOSE_DEBUG
 270         urb_print(urb, "UNLINK", 1, status);
 271 #endif
 272
 273         spin_lock_irqsave (&ohci->lock, flags);
 274         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 275         if (rc) {
 276                 ;       /* Do nothing */
 277         } else if (HC_IS_RUNNING(hcd->state)) {
 278                 urb_priv_t  *urb_priv;
 279
 280                 /* Unless an IRQ completed the unlink while it was being
 281                  * handed to us, flag it for unlink and giveback, and force
 282                  * some upcoming INTR_SF to call finish_unlinks()
 283                  */
 284                 urb_priv = urb->hcpriv;
 285                 if (urb_priv) {
 286                         if (urb_priv->ed->state == ED_OPER)
 287                                 start_ed_unlink (ohci, urb_priv->ed);
 288                 }
 289         } else {
 290                 /*
 291                  * with HC dead, we won't respect hc queue pointers
 292                  * any more ... just clean up every urb's memory.
 293                  */
 294                 if (urb->hcpriv)
 295                         finish_urb(ohci, urb, status);
 296         }
 297         spin_unlock_irqrestore (&ohci->lock, flags);
 298         return rc;
 299 }
 300
 301 /*-------------------------------------------------------------------------*/
 302
 303 /* frees config/altsetting state for endpoints,
 304  * including ED memory, dummy TD, and bulk/intr data toggle
 305  */
 306
 307 static void
 308 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 309 {
 310         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 311         unsigned long           flags;
 312         struct ed               *ed = ep->hcpriv;
 313         unsigned                limit = 1000;
 314
 315         /* ASSERT:  any requests/urbs are being unlinked */
 316         /* ASSERT:  nobody can be submitting urbs for this any more */
 317
 318         if (!ed)
 319                 return;
 320
 321 rescan:
 322         spin_lock_irqsave (&ohci->lock, flags);
 323
 324         if (!HC_IS_RUNNING (hcd->state)) {
 325 sanitize:
 326                 ed->state = ED_IDLE;
 327                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
 328                         ohci->eds_scheduled--;
 329                 finish_unlinks (ohci, 0);
 330         }
 331
 332         switch (ed->state) {
 333         case ED_UNLINK:         /* wait for hw to finish? */
 334                 /* major IRQ delivery trouble loses INTR_SF too... */
 335                 if (limit-- == 0) {
 336                         ohci_warn(ohci, "ED unlink timeout\n");
 337                         if (quirk_zfmicro(ohci)) {
 338                                 ohci_warn(ohci, "Attempting ZF TD recovery\n");
 339                                 ohci->ed_to_check = ed;
 340                                 ohci->zf_delay = 2;
 341                         }
 342                         goto sanitize;
 343                 }
 344                 spin_unlock_irqrestore (&ohci->lock, flags);
 345                 schedule_timeout_uninterruptible(1);
 346                 goto rescan;
 347         case ED_IDLE:           /* fully unlinked */
 348                 if (list_empty (&ed->td_list)) {
 349                         td_free (ohci, ed->dummy);
 350                         ed_free (ohci, ed);
 351                         break;
 352                 }
 353                 /* else FALL THROUGH */
 354         default:
 355                 /* caller was supposed to have unlinked any requests;
 356                  * that's not our job.  can't recover; must leak ed.
 357                  */
 358                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
 359                         ed, ep->desc.bEndpointAddress, ed->state,
 360                         list_empty (&ed->td_list) ? "" : " (has tds)");
 361                 td_free (ohci, ed->dummy);
 362                 break;
 363         }
 364         ep->hcpriv = NULL;
 365         spin_unlock_irqrestore (&ohci->lock, flags);
 366 }
 367
 368 static int ohci_get_frame (struct usb_hcd *hcd)
 369 {
 370         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 371
 372         return ohci_frame_no(ohci);
 373 }
 374
 375 static void ohci_usb_reset (struct ohci_hcd *ohci)
 376 {
 377         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
 378         ohci->hc_control &= OHCI_CTRL_RWC;
 379         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 380 }
 381
 382 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
 383  * other cases where the next software may expect clean state from the
 384  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 385  */
 386 static void
 387 ohci_shutdown (struct usb_hcd *hcd)
 388 {
 389         struct ohci_hcd *ohci;
 390
 391         ohci = hcd_to_ohci (hcd);
 392         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 393         ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
 394
 395         /* If the SHUTDOWN quirk is set, don't put the controller in RESET */
 396         ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ?
 397                         OHCI_CTRL_RWC | OHCI_CTRL_HCFS :
 398                         OHCI_CTRL_RWC);
 399         ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
 400
 401         /* flush the writes */
 402         (void) ohci_readl (ohci, &ohci->regs->control);
 403 }
 404
 405 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
 406 {
 407         return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
 408                 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
 409                         == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
 410                 && !list_empty(&ed->td_list);
 411 }
 412
 413 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
 414  * an interrupt TD but neglects to add it to the donelist.  On systems with
 415  * this chipset, we need to periodically check the state of the queues to look
 416  * for such "lost" TDs.
 417  */
 418 static void unlink_watchdog_func(unsigned long _ohci)
 419 {
 420         unsigned long   flags;
 421         unsigned        max;
 422         unsigned        seen_count = 0;
 423         unsigned        i;
 424         struct ed       **seen = NULL;
 425         struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
 426
 427         spin_lock_irqsave(&ohci->lock, flags);
 428         max = ohci->eds_scheduled;
 429         if (!max)
 430                 goto done;
 431
 432         if (ohci->ed_to_check)
 433                 goto out;
 434
 435         seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
 436         if (!seen)
 437                 goto out;
 438
 439         for (i = 0; i < NUM_INTS; i++) {
 440                 struct ed       *ed = ohci->periodic[i];
 441
 442                 while (ed) {
 443                         unsigned        temp;
 444
 445                         /* scan this branch of the periodic schedule tree */
 446                         for (temp = 0; temp < seen_count; temp++) {
 447                                 if (seen[temp] == ed) {
 448                                         /* we've checked it and what's after */
 449                                         ed = NULL;
 450                                         break;
 451                                 }
 452                         }
 453                         if (!ed)
 454                                 break;
 455                         seen[seen_count++] = ed;
 456                         if (!check_ed(ohci, ed)) {
 457                                 ed = ed->ed_next;
 458                                 continue;
 459                         }
 460
 461                         /* HC's TD list is empty, but HCD sees at least one
 462                          * TD that's not been sent through the donelist.
 463                          */
 464                         ohci->ed_to_check = ed;
 465                         ohci->zf_delay = 2;
 466
 467                         /* The HC may wait until the next frame to report the
 468                          * TD as done through the donelist and INTR_WDH.  (We
 469                          * just *assume* it's not a multi-TD interrupt URB;
 470                          * those could defer the IRQ more than one frame, using
 471                          * DI...)  Check again after the next INTR_SF.
 472                          */
 473                         ohci_writel(ohci, OHCI_INTR_SF,
 474                                         &ohci->regs->intrstatus);
 475                         ohci_writel(ohci, OHCI_INTR_SF,
 476                                         &ohci->regs->intrenable);
 477
 478                         /* flush those writes */
 479                         (void) ohci_readl(ohci, &ohci->regs->control);
 480
 481                         goto out;
 482                 }
 483         }
 484 out:
 485         kfree(seen);
 486         if (ohci->eds_scheduled)
 487                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 488 done:
 489         spin_unlock_irqrestore(&ohci->lock, flags);
 490 }
 491
 492 /*-------------------------------------------------------------------------*
 493  * HC functions
 494  *-------------------------------------------------------------------------*/
 495
 496 /* init memory, and kick BIOS/SMM off */
 497
 498 static int ohci_init (struct ohci_hcd *ohci)
 499 {
 500         int ret;
 501         struct usb_hcd *hcd = ohci_to_hcd(ohci);
 502
 503         if (distrust_firmware)
 504                 ohci->flags |= OHCI_QUIRK_HUB_POWER;
 505
 506         disable (ohci);
 507         ohci->regs = hcd->regs;
 508
 509         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
 510          * was never needed for most non-PCI systems ... remove the code?
 511          */
 512
 513 #ifndef IR_DISABLE
 514         /* SMM owns the HC?  not for long! */
 515         if (!no_handshake && ohci_readl (ohci,
 516                                         &ohci->regs->control) & OHCI_CTRL_IR) {
 517                 u32 temp;
 518
 519                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
 520
 521                 /* this timeout is arbitrary.  we make it long, so systems
 522                  * depending on usb keyboards may be usable even if the
 523                  * BIOS/SMM code seems pretty broken.
 524                  */
 525                 temp = 500;     /* arbitrary: five seconds */
 526
 527                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
 528                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
 529                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
 530                         msleep (10);
 531                         if (--temp == 0) {
 532                                 ohci_err (ohci, "USB HC takeover failed!"
 533                                         "  (BIOS/SMM bug)\n");
 534                                 return -EBUSY;
 535                         }
 536                 }
 537                 ohci_usb_reset (ohci);
 538         }
 539 #endif
 540
 541         /* Disable HC interrupts */
 542         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 543
 544         /* flush the writes, and save key bits like RWC */
 545         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
 546                 ohci->hc_control |= OHCI_CTRL_RWC;
 547
 548         /* Read the number of ports unless overridden */
 549         if (ohci->num_ports == 0)
 550                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
 551
 552         if (ohci->hcca)
 553                 return 0;
 554
 555         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
 556                         sizeof *ohci->hcca, &ohci->hcca_dma, 0);
 557         if (!ohci->hcca)
 558                 return -ENOMEM;
 559
 560         if ((ret = ohci_mem_init (ohci)) < 0)
 561                 ohci_stop (hcd);
 562         else {
 563                 create_debug_files (ohci);
 564         }
 565
 566         return ret;
 567 }
 568
 569 /*-------------------------------------------------------------------------*/
 570
 571 /* Start an OHCI controller, set the BUS operational
 572  * resets USB and controller
 573  * enable interrupts
 574  */
 575 static int ohci_run (struct ohci_hcd *ohci)
 576 {
 577         u32                     mask, val;
 578         int                     first = ohci->fminterval == 0;
 579         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 580
 581         disable (ohci);
 582
 583         /* boot firmware should have set this up (5.1.1.3.1) */
 584         if (first) {
 585
 586                 val = ohci_readl (ohci, &ohci->regs->fminterval);
 587                 ohci->fminterval = val & 0x3fff;
 588                 if (ohci->fminterval != FI)
 589                         ohci_dbg (ohci, "fminterval delta %d\n",
 590                                 ohci->fminterval - FI);
 591                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
 592                 /* also: power/overcurrent flags in roothub.a */
 593         }
 594
 595         /* Reset USB nearly "by the book".  RemoteWakeupConnected has
 596          * to be checked in case boot firmware (BIOS/SMM/...) has set up
 597          * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
 598          * If the bus glue detected wakeup capability then it should
 599          * already be enabled; if so we'll just enable it again.
 600          */
 601         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
 602                 device_set_wakeup_capable(hcd->self.controller, 1);
 603
 604         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 605         case OHCI_USB_OPER:
 606                 val = 0;
 607                 break;
 608         case OHCI_USB_SUSPEND:
 609         case OHCI_USB_RESUME:
 610                 ohci->hc_control &= OHCI_CTRL_RWC;
 611                 ohci->hc_control |= OHCI_USB_RESUME;
 612                 val = 10 /* msec wait */;
 613                 break;
 614         // case OHCI_USB_RESET:
 615         default:
 616                 ohci->hc_control &= OHCI_CTRL_RWC;
 617                 ohci->hc_control |= OHCI_USB_RESET;
 618                 val = 50 /* msec wait */;
 619                 break;
 620         }
 621         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 622         // flush the writes
 623         (void) ohci_readl (ohci, &ohci->regs->control);
 624         msleep(val);
 625
 626         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 627
 628         /* 2msec timelimit here means no irqs/preempt */
 629         spin_lock_irq (&ohci->lock);
 630
 631 retry:
 632         /* HC Reset requires max 10 us delay */
 633         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
 634         val = 30;       /* ... allow extra time */
 635         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 636                 if (--val == 0) {
 637                         spin_unlock_irq (&ohci->lock);
 638                         ohci_err (ohci, "USB HC reset timed out!\n");
 639                         return -1;
 640                 }
 641                 udelay (1);
 642         }
 643
 644         /* now we're in the SUSPEND state ... must go OPERATIONAL
 645          * within 2msec else HC enters RESUME
 646          *
 647          * ... but some hardware won't init fmInterval "by the book"
 648          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
 649          * this if we write fmInterval after we're OPERATIONAL.
 650          * Unclear about ALi, ServerWorks, and others ... this could
 651          * easily be a longstanding bug in chip init on Linux.
 652          */
 653         if (ohci->flags & OHCI_QUIRK_INITRESET) {
 654                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 655                 // flush those writes
 656                 (void) ohci_readl (ohci, &ohci->regs->control);
 657         }
 658
 659         /* Tell the controller where the control and bulk lists are
 660          * The lists are empty now. */
 661         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
 662         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
 663
 664         /* a reset clears this */
 665         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
 666
 667         periodic_reinit (ohci);
 668
 669         /* some OHCI implementations are finicky about how they init.
 670          * bogus values here mean not even enumeration could work.
 671          */
 672         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
 673                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
 674                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
 675                         ohci->flags |= OHCI_QUIRK_INITRESET;
 676                         ohci_dbg (ohci, "enabling initreset quirk\n");
 677                         goto retry;
 678                 }
 679                 spin_unlock_irq (&ohci->lock);
 680                 ohci_err (ohci, "init err (%08x %04x)\n",
 681                         ohci_readl (ohci, &ohci->regs->fminterval),
 682                         ohci_readl (ohci, &ohci->regs->periodicstart));
 683                 return -EOVERFLOW;
 684         }
 685
 686         /* use rhsc irqs after khubd is fully initialized */
 687         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 688         hcd->uses_new_polling = 1;
 689
 690         /* start controller operations */
 691         ohci->hc_control &= OHCI_CTRL_RWC;
 692         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
 693         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 694         hcd->state = HC_STATE_RUNNING;
 695
 696         /* wake on ConnectStatusChange, matching external hubs */
 697         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
 698
 699         /* Choose the interrupts we care about now, others later on demand */
 700         mask = OHCI_INTR_INIT;
 701         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
 702         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 703
 704         /* handle root hub init quirks ... */
 705         val = roothub_a (ohci);
 706         val &= ~(RH_A_PSM | RH_A_OCPM);
 707         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
 708                 /* NSC 87560 and maybe others */
 709                 val |= RH_A_NOCP;
 710                 val &= ~(RH_A_POTPGT | RH_A_NPS);
 711                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 712         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
 713                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
 714                 /* hub power always on; required for AMD-756 and some
 715                  * Mac platforms.  ganged overcurrent reporting, if any.
 716                  */
 717                 val |= RH_A_NPS;
 718                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 719         }
 720         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
 721         ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
 722                                                 &ohci->regs->roothub.b);
 723         // flush those writes
 724         (void) ohci_readl (ohci, &ohci->regs->control);
 725
 726         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 727         spin_unlock_irq (&ohci->lock);
 728
 729         // POTPGT delay is bits 24-31, in 2 ms units.
 730         mdelay ((val >> 23) & 0x1fe);
 731         hcd->state = HC_STATE_RUNNING;
 732
 733         if (quirk_zfmicro(ohci)) {
 734                 /* Create timer to watch for bad queue state on ZF Micro */
 735                 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
 736                                 (unsigned long) ohci);
 737
 738                 ohci->eds_scheduled = 0;
 739                 ohci->ed_to_check = NULL;
 740         }
 741
 742         ohci_dump (ohci, 1);
 743
 744         return 0;
 745 }
 746
 747 /*-------------------------------------------------------------------------*/
 748
 749 /* an interrupt happens */
 750
 751 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
 752 {
 753         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 754         struct ohci_regs __iomem *regs = ohci->regs;
 755         int                     ints;
 756
 757         /* Read interrupt status (and flush pending writes).  We ignore the
 758          * optimization of checking the LSB of hcca->done_head; it doesn't
 759          * work on all systems (edge triggering for OHCI can be a factor).
 760          */
 761         ints = ohci_readl(ohci, &regs->intrstatus);
 762
 763         /* Check for an all 1's result which is a typical consequence
 764          * of dead, unclocked, or unplugged (CardBus...) devices
 765          */
 766         if (ints == ~(u32)0) {
 767                 disable (ohci);
 768                 ohci_dbg (ohci, "device removed!\n");
 769                 usb_hc_died(hcd);
 770                 return IRQ_HANDLED;
 771         }
 772
 773         /* We only care about interrupts that are enabled */
 774         ints &= ohci_readl(ohci, &regs->intrenable);
 775
 776         /* interrupt for some other device? */
 777         if (ints == 0 || unlikely(hcd->state == HC_STATE_HALT))
 778                 return IRQ_NOTMINE;
 779
 780         if (ints & OHCI_INTR_UE) {
 781                 // e.g. due to PCI Master/Target Abort
 782                 if (quirk_nec(ohci)) {
 783                         /* Workaround for a silicon bug in some NEC chips used
 784                          * in Apple's PowerBooks. Adapted from Darwin code.
 785                          */
 786                         ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
 787
 788                         ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
 789
 790                         schedule_work (&ohci->nec_work);
 791                 } else {
 792                         disable (ohci);
 793                         ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
 794                         usb_hc_died(hcd);
 795                 }
 796
 797                 ohci_dump (ohci, 1);
 798                 ohci_usb_reset (ohci);
 799         }
 800
 801         if (ints & OHCI_INTR_RHSC) {
 802                 ohci_vdbg(ohci, "rhsc\n");
 803                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 804                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
 805                                 &regs->intrstatus);
 806
 807                 /* NOTE: Vendors didn't always make the same implementation
 808                  * choices for RHSC.  Many followed the spec; RHSC triggers
 809                  * on an edge, like setting and maybe clearing a port status
 810                  * change bit.  With others it's level-triggered, active
 811                  * until khubd clears all the port status change bits.  We'll
 812                  * always disable it here and rely on polling until khubd
 813                  * re-enables it.
 814                  */
 815                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
 816                 usb_hcd_poll_rh_status(hcd);
 817         }
 818
 819         /* For connect and disconnect events, we expect the controller
 820          * to turn on RHSC along with RD.  But for remote wakeup events
 821          * this might not happen.
 822          */
 823         else if (ints & OHCI_INTR_RD) {
 824                 ohci_vdbg(ohci, "resume detect\n");
 825                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
 826                 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 827                 if (ohci->autostop) {
 828                         spin_lock (&ohci->lock);
 829                         ohci_rh_resume (ohci);
 830                         spin_unlock (&ohci->lock);
 831                 } else
 832                         usb_hcd_resume_root_hub(hcd);
 833         }
 834
 835         if (ints & OHCI_INTR_WDH) {
 836                 spin_lock (&ohci->lock);
 837                 dl_done_list (ohci);
 838                 spin_unlock (&ohci->lock);
 839         }
 840
 841         if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
 842                 spin_lock(&ohci->lock);
 843                 if (ohci->ed_to_check) {
 844                         struct ed *ed = ohci->ed_to_check;
 845
 846                         if (check_ed(ohci, ed)) {
 847                                 /* HC thinks the TD list is empty; HCD knows
 848                                  * at least one TD is outstanding
 849                                  */
 850                                 if (--ohci->zf_delay == 0) {
 851                                         struct td *td = list_entry(
 852                                                 ed->td_list.next,
 853                                                 struct td, td_list);
 854                                         ohci_warn(ohci,
 855                                                   "Reclaiming orphan TD %p\n",
 856                                                   td);
 857                                         takeback_td(ohci, td);
 858                                         ohci->ed_to_check = NULL;
 859                                 }
 860                         } else
 861                                 ohci->ed_to_check = NULL;
 862                 }
 863                 spin_unlock(&ohci->lock);
 864         }
 865
 866         /* could track INTR_SO to reduce available PCI/... bandwidth */
 867
 868         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
 869          * when there's still unlinking to be done (next frame).
 870          */
 871         spin_lock (&ohci->lock);
 872         if (ohci->ed_rm_list)
 873                 finish_unlinks (ohci, ohci_frame_no(ohci));
 874         if ((ints & OHCI_INTR_SF) != 0
 875                         && !ohci->ed_rm_list
 876                         && !ohci->ed_to_check
 877                         && HC_IS_RUNNING(hcd->state))
 878                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
 879         spin_unlock (&ohci->lock);
 880
 881         if (HC_IS_RUNNING(hcd->state)) {
 882                 ohci_writel (ohci, ints, &regs->intrstatus);
 883                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
 884                 // flush those writes
 885                 (void) ohci_readl (ohci, &ohci->regs->control);
 886         }
 887
 888         return IRQ_HANDLED;
 889 }
 890
 891 /*-------------------------------------------------------------------------*/
 892
 893 static void ohci_stop (struct usb_hcd *hcd)
 894 {
 895         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 896
 897         ohci_dump (ohci, 1);
 898
 899         if (quirk_nec(ohci))
 900                 flush_work_sync(&ohci->nec_work);
 901
 902         ohci_usb_reset (ohci);
 903         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 904         free_irq(hcd->irq, hcd);
 905         hcd->irq = -1;
 906
 907         if (quirk_zfmicro(ohci))
 908                 del_timer(&ohci->unlink_watchdog);
 909         if (quirk_amdiso(ohci))
 910                 usb_amd_dev_put();
 911
 912         remove_debug_files (ohci);
 913         ohci_mem_cleanup (ohci);
 914         if (ohci->hcca) {
 915                 dma_free_coherent (hcd->self.controller,
 916                                 sizeof *ohci->hcca,
 917                                 ohci->hcca, ohci->hcca_dma);
 918                 ohci->hcca = NULL;
 919                 ohci->hcca_dma = 0;
 920         }
 921 }
 922
 923 /*-------------------------------------------------------------------------*/
 924
 925 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 926
 927 /* must not be called from interrupt context */
 928 static int ohci_restart (struct ohci_hcd *ohci)
 929 {
 930         int temp;
 931         int i;
 932         struct urb_priv *priv;
 933
 934         spin_lock_irq(&ohci->lock);
 935         disable (ohci);
 936
 937         /* Recycle any "live" eds/tds (and urbs). */
 938         if (!list_empty (&ohci->pending))
 939                 ohci_dbg(ohci, "abort schedule...\n");
 940         list_for_each_entry (priv, &ohci->pending, pending) {
 941                 struct urb      *urb = priv->td[0]->urb;
 942                 struct ed       *ed = priv->ed;
 943
 944                 switch (ed->state) {
 945                 case ED_OPER:
 946                         ed->state = ED_UNLINK;
 947                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
 948                         ed_deschedule (ohci, ed);
 949
 950                         ed->ed_next = ohci->ed_rm_list;
 951                         ed->ed_prev = NULL;
 952                         ohci->ed_rm_list = ed;
 953                         /* FALLTHROUGH */
 954                 case ED_UNLINK:
 955                         break;
 956                 default:
 957                         ohci_dbg(ohci, "bogus ed %p state %d\n",
 958                                         ed, ed->state);
 959                 }
 960
 961                 if (!urb->unlinked)
 962                         urb->unlinked = -ESHUTDOWN;
 963         }
 964         finish_unlinks (ohci, 0);
 965         spin_unlock_irq(&ohci->lock);
 966
 967         /* paranoia, in case that didn't work: */
 968
 969         /* empty the interrupt branches */
 970         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
 971         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
 972
 973         /* no EDs to remove */
 974         ohci->ed_rm_list = NULL;
 975
 976         /* empty control and bulk lists */
 977         ohci->ed_controltail = NULL;
 978         ohci->ed_bulktail    = NULL;
 979
 980         if ((temp = ohci_run (ohci)) < 0) {
 981                 ohci_err (ohci, "can't restart, %d\n", temp);
 982                 return temp;
 983         }
 984         ohci_dbg(ohci, "restart complete\n");
 985         return 0;
 986 }
 987
 988 #endif
 989
 990 /*-------------------------------------------------------------------------*/
 991
 992 MODULE_AUTHOR (DRIVER_AUTHOR);
 993 MODULE_DESCRIPTION(DRIVER_DESC);
 994 MODULE_LICENSE ("GPL");
 995
 996 #ifdef CONFIG_PCI
 997 #include "ohci-pci.c"
 998 #define PCI_DRIVER              ohci_pci_driver
 999 #endif
1000
1001 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1002 #include "ohci-sa1111.c"
1003 #define SA1111_DRIVER           ohci_hcd_sa1111_driver
1004 #endif
1005
1006 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1007 #include "ohci-s3c2410.c"
1008 #define PLATFORM_DRIVER         ohci_hcd_s3c2410_driver
1009 #endif
1010
1011 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1012 #include "ohci-omap.c"
1013 #define OMAP1_PLATFORM_DRIVER   ohci_hcd_omap_driver
1014 #endif
1015
1016 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1017 #include "ohci-omap3.c"
1018 #define OMAP3_PLATFORM_DRIVER   ohci_hcd_omap3_driver
1019 #endif
1020
1021 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1022 #include "ohci-pxa27x.c"
1023 #define PLATFORM_DRIVER         ohci_hcd_pxa27x_driver
1024 #endif
1025
1026 #ifdef CONFIG_ARCH_EP93XX
1027 #include "ohci-ep93xx.c"
1028 #define PLATFORM_DRIVER         ohci_hcd_ep93xx_driver
1029 #endif
1030
1031 #ifdef CONFIG_MIPS_ALCHEMY
1032 #include "ohci-au1xxx.c"
1033 #define PLATFORM_DRIVER         ohci_hcd_au1xxx_driver
1034 #endif
1035
1036 #ifdef CONFIG_PNX8550
1037 #include "ohci-pnx8550.c"
1038 #define PLATFORM_DRIVER         ohci_hcd_pnx8550_driver
1039 #endif
1040
1041 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1042 #include "ohci-ppc-soc.c"
1043 #define PLATFORM_DRIVER         ohci_hcd_ppc_soc_driver
1044 #endif
1045
1046 #ifdef CONFIG_ARCH_AT91
1047 #include "ohci-at91.c"
1048 #define PLATFORM_DRIVER         ohci_hcd_at91_driver
1049 #endif
1050
1051 #ifdef CONFIG_ARCH_PNX4008
1052 #include "ohci-pnx4008.c"
1053 #define PLATFORM_DRIVER         usb_hcd_pnx4008_driver
1054 #endif
1055
1056 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1057 #include "ohci-da8xx.c"
1058 #define PLATFORM_DRIVER         ohci_hcd_da8xx_driver
1059 #endif
1060
1061 #ifdef CONFIG_USB_OHCI_SH
1062 #include "ohci-sh.c"
1063 #define PLATFORM_DRIVER         ohci_hcd_sh_driver
1064 #endif
1065
1066
1067 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1068 #include "ohci-ppc-of.c"
1069 #define OF_PLATFORM_DRIVER      ohci_hcd_ppc_of_driver
1070 #endif
1071
1072 #ifdef CONFIG_PLAT_SPEAR
1073 #include "ohci-spear.c"
1074 #define PLATFORM_DRIVER         spear_ohci_hcd_driver
1075 #endif
1076
1077 #ifdef CONFIG_PPC_PS3
1078 #include "ohci-ps3.c"
1079 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1080 #endif
1081
1082 #ifdef CONFIG_USB_OHCI_HCD_SSB
1083 #include "ohci-ssb.c"
1084 #define SSB_OHCI_DRIVER         ssb_ohci_driver
1085 #endif
1086
1087 #ifdef CONFIG_MFD_SM501
1088 #include "ohci-sm501.c"
1089 #define SM501_OHCI_DRIVER       ohci_hcd_sm501_driver
1090 #endif
1091
1092 #ifdef CONFIG_MFD_TC6393XB
1093 #include "ohci-tmio.c"
1094 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
1095 #endif
1096
1097 #ifdef CONFIG_MACH_JZ4740
1098 #include "ohci-jz4740.c"
1099 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1100 #endif
1101
1102 #ifdef CONFIG_USB_OCTEON_OHCI
1103 #include "ohci-octeon.c"
1104 #define PLATFORM_DRIVER         ohci_octeon_driver
1105 #endif
1106
1107 #ifdef CONFIG_USB_CNS3XXX_OHCI
1108 #include "ohci-cns3xxx.c"
1109 #define PLATFORM_DRIVER         ohci_hcd_cns3xxx_driver
1110 #endif
1111
1112 #ifdef CONFIG_USB_OHCI_ATH79
1113 #include "ohci-ath79.c"
1114 #define PLATFORM_DRIVER         ohci_hcd_ath79_driver
1115 #endif
1116
1117 #if     !defined(PCI_DRIVER) &&         \
1118         !defined(PLATFORM_DRIVER) &&    \
1119         !defined(OMAP1_PLATFORM_DRIVER) &&      \
1120         !defined(OMAP3_PLATFORM_DRIVER) &&      \
1121         !defined(OF_PLATFORM_DRIVER) && \
1122         !defined(SA1111_DRIVER) &&      \
1123         !defined(PS3_SYSTEM_BUS_DRIVER) && \
1124         !defined(SM501_OHCI_DRIVER) && \
1125         !defined(TMIO_OHCI_DRIVER) && \
1126         !defined(SSB_OHCI_DRIVER)
1127 #error "missing bus glue for ohci-hcd"
1128 #endif
1129
1130 static int __init ohci_hcd_mod_init(void)
1131 {
1132         int retval = 0;
1133
1134         if (usb_disabled())
1135                 return -ENODEV;
1136
1137         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1138         pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1139                 sizeof (struct ed), sizeof (struct td));
1140         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1141
1142 #ifdef DEBUG
1143         ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1144         if (!ohci_debug_root) {
1145                 retval = -ENOENT;
1146                 goto error_debug;
1147         }
1148 #endif
1149
1150 #ifdef PS3_SYSTEM_BUS_DRIVER
1151         retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1152         if (retval < 0)
1153                 goto error_ps3;
1154 #endif
1155
1156 #ifdef PLATFORM_DRIVER
1157         retval = platform_driver_register(&PLATFORM_DRIVER);
1158         if (retval < 0)
1159                 goto error_platform;
1160 #endif
1161
1162 #ifdef OMAP1_PLATFORM_DRIVER
1163         retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1164         if (retval < 0)
1165                 goto error_omap1_platform;
1166 #endif
1167
1168 #ifdef OMAP3_PLATFORM_DRIVER
1169         retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1170         if (retval < 0)
1171                 goto error_omap3_platform;
1172 #endif
1173
1174 #ifdef OF_PLATFORM_DRIVER
1175         retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1176         if (retval < 0)
1177                 goto error_of_platform;
1178 #endif
1179
1180 #ifdef SA1111_DRIVER
1181         retval = sa1111_driver_register(&SA1111_DRIVER);
1182         if (retval < 0)
1183                 goto error_sa1111;
1184 #endif
1185
1186 #ifdef PCI_DRIVER
1187         retval = pci_register_driver(&PCI_DRIVER);
1188         if (retval < 0)
1189                 goto error_pci;
1190 #endif
1191
1192 #ifdef SSB_OHCI_DRIVER
1193         retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1194         if (retval)
1195                 goto error_ssb;
1196 #endif
1197
1198 #ifdef SM501_OHCI_DRIVER
1199         retval = platform_driver_register(&SM501_OHCI_DRIVER);
1200         if (retval < 0)
1201                 goto error_sm501;
1202 #endif
1203
1204 #ifdef TMIO_OHCI_DRIVER
1205         retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1206         if (retval < 0)
1207                 goto error_tmio;
1208 #endif
1209
1210         return retval;
1211
1212         /* Error path */
1213 #ifdef TMIO_OHCI_DRIVER
1214         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1215  error_tmio:
1216 #endif
1217 #ifdef SM501_OHCI_DRIVER
1218         platform_driver_unregister(&SM501_OHCI_DRIVER);
1219  error_sm501:
1220 #endif
1221 #ifdef SSB_OHCI_DRIVER
1222         ssb_driver_unregister(&SSB_OHCI_DRIVER);
1223  error_ssb:
1224 #endif
1225 #ifdef PCI_DRIVER
1226         pci_unregister_driver(&PCI_DRIVER);
1227  error_pci:
1228 #endif
1229 #ifdef SA1111_DRIVER
1230         sa1111_driver_unregister(&SA1111_DRIVER);
1231  error_sa1111:
1232 #endif
1233 #ifdef OF_PLATFORM_DRIVER
1234         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1235  error_of_platform:
1236 #endif
1237 #ifdef PLATFORM_DRIVER
1238         platform_driver_unregister(&PLATFORM_DRIVER);
1239  error_platform:
1240 #endif
1241 #ifdef OMAP1_PLATFORM_DRIVER
1242         platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1243  error_omap1_platform:
1244 #endif
1245 #ifdef OMAP3_PLATFORM_DRIVER
1246         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1247  error_omap3_platform:
1248 #endif
1249 #ifdef PS3_SYSTEM_BUS_DRIVER
1250         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1251  error_ps3:
1252 #endif
1253 #ifdef DEBUG
1254         debugfs_remove(ohci_debug_root);
1255         ohci_debug_root = NULL;
1256  error_debug:
1257 #endif
1258
1259         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1260         return retval;
1261 }
1262 module_init(ohci_hcd_mod_init);
1263
1264 static void __exit ohci_hcd_mod_exit(void)
1265 {
1266 #ifdef TMIO_OHCI_DRIVER
1267         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1268 #endif
1269 #ifdef SM501_OHCI_DRIVER
1270         platform_driver_unregister(&SM501_OHCI_DRIVER);
1271 #endif
1272 #ifdef SSB_OHCI_DRIVER
1273         ssb_driver_unregister(&SSB_OHCI_DRIVER);
1274 #endif
1275 #ifdef PCI_DRIVER
1276         pci_unregister_driver(&PCI_DRIVER);
1277 #endif
1278 #ifdef SA1111_DRIVER
1279         sa1111_driver_unregister(&SA1111_DRIVER);
1280 #endif
1281 #ifdef OF_PLATFORM_DRIVER
1282         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1283 #endif
1284 #ifdef PLATFORM_DRIVER
1285         platform_driver_unregister(&PLATFORM_DRIVER);
1286 #endif
1287 #ifdef OMAP3_PLATFORM_DRIVER
1288         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1289 #endif
1290 #ifdef PS3_SYSTEM_BUS_DRIVER
1291         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1292 #endif
1293 #ifdef DEBUG
1294         debugfs_remove(ohci_debug_root);
1295 #endif
1296         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1297 }
1298 module_exit(ohci_hcd_mod_exit);
1299