drivers/net/sfc/tenxpress.c

   1 /****************************************************************************
   2  * Driver for Solarflare 802.3an compliant PHY
   3  * Copyright 2007 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/seq_file.h>
  12 #include "efx.h"
  13 #include "gmii.h"
  14 #include "mdio_10g.h"
  15 #include "falcon.h"
  16 #include "phy.h"
  17 #include "falcon_hwdefs.h"
  18 #include "boards.h"
  19 #include "mac.h"
  20
  21 /* We expect these MMDs to be in the package */
  22 /* AN not here as mdio_check_mmds() requires STAT2 support */
  23 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD | \
  24                                  MDIO_MMDREG_DEVS0_PCS    | \
  25                                  MDIO_MMDREG_DEVS0_PHYXS)
  26
  27 /* We complain if we fail to see the link partner as 10G capable this many
  28  * times in a row (must be > 1 as sampling the autoneg. registers is racy)
  29  */
  30 #define MAX_BAD_LP_TRIES        (5)
  31
  32 /* Extended control register */
  33 #define PMA_PMD_XCONTROL_REG 0xc000
  34 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8
  35 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
  36
  37 /* extended status register */
  38 #define PMA_PMD_XSTATUS_REG 0xc001
  39 #define PMA_PMD_XSTAT_FLP_LBN   (12)
  40
  41 /* LED control register */
  42 #define PMA_PMD_LED_CTRL_REG    (0xc007)
  43 #define PMA_PMA_LED_ACTIVITY_LBN        (3)
  44
  45 /* LED function override register */
  46 #define PMA_PMD_LED_OVERR_REG   (0xc009)
  47 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
  48 #define PMA_PMD_LED_LINK_LBN    (0)
  49 #define PMA_PMD_LED_SPEED_LBN   (2)
  50 #define PMA_PMD_LED_TX_LBN      (4)
  51 #define PMA_PMD_LED_RX_LBN      (6)
  52 /* Override settings */
  53 #define PMA_PMD_LED_AUTO        (0)     /* H/W control */
  54 #define PMA_PMD_LED_ON          (1)
  55 #define PMA_PMD_LED_OFF         (2)
  56 #define PMA_PMD_LED_FLASH       (3)
  57 /* All LEDs under hardware control */
  58 #define PMA_PMD_LED_FULL_AUTO   (0)
  59 /* Green and Amber under hardware control, Red off */
  60 #define PMA_PMD_LED_DEFAULT     (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
  61
  62
  63 /* Self test (BIST) control register */
  64 #define PMA_PMD_BIST_CTRL_REG   (0xc014)
  65 #define PMA_PMD_BIST_BER_LBN    (2)     /* Run BER test */
  66 #define PMA_PMD_BIST_CONT_LBN   (1)     /* Run continuous BIST until cleared */
  67 #define PMA_PMD_BIST_SINGLE_LBN (0)     /* Run 1 BIST iteration (self clears) */
  68 /* Self test status register */
  69 #define PMA_PMD_BIST_STAT_REG   (0xc015)
  70 #define PMA_PMD_BIST_ENX_LBN    (3)
  71 #define PMA_PMD_BIST_PMA_LBN    (2)
  72 #define PMA_PMD_BIST_RXD_LBN    (1)
  73 #define PMA_PMD_BIST_AFE_LBN    (0)
  74
  75 #define BIST_MAX_DELAY  (1000)
  76 #define BIST_POLL_DELAY (10)
  77
  78 /* Misc register defines */
  79 #define PCS_CLOCK_CTRL_REG 0xd801
  80 #define PLL312_RST_N_LBN 2
  81
  82 #define PCS_SOFT_RST2_REG 0xd806
  83 #define SERDES_RST_N_LBN 13
  84 #define XGXS_RST_N_LBN 12
  85
  86 #define PCS_TEST_SELECT_REG 0xd807      /* PRM 10.5.8 */
  87 #define CLK312_EN_LBN 3
  88
  89 /* Boot status register */
  90 #define PCS_BOOT_STATUS_REG     (0xd000)
  91 #define PCS_BOOT_FATAL_ERR_LBN  (0)
  92 #define PCS_BOOT_PROGRESS_LBN   (1)
  93 #define PCS_BOOT_PROGRESS_WIDTH (2)
  94 #define PCS_BOOT_COMPLETE_LBN   (3)
  95 #define PCS_BOOT_MAX_DELAY      (100)
  96 #define PCS_BOOT_POLL_DELAY     (10)
  97
  98 /* Time to wait between powering down the LNPGA and turning off the power
  99  * rails */
 100 #define LNPGA_PDOWN_WAIT        (HZ / 5)
 101
 102 static int crc_error_reset_threshold = 100;
 103 module_param(crc_error_reset_threshold, int, 0644);
 104 MODULE_PARM_DESC(crc_error_reset_threshold,
 105                  "Max number of CRC errors before XAUI reset");
 106
 107 struct tenxpress_phy_data {
 108         enum tenxpress_state state;
 109         atomic_t bad_crc_count;
 110         int bad_lp_tries;
 111 };
 112
 113 static int tenxpress_state_is(struct efx_nic *efx, int state)
 114 {
 115         struct tenxpress_phy_data *phy_data = efx->phy_data;
 116         return (phy_data != NULL) && (state == phy_data->state);
 117 }
 118
 119 void tenxpress_set_state(struct efx_nic *efx,
 120                                 enum tenxpress_state state)
 121 {
 122         struct tenxpress_phy_data *phy_data = efx->phy_data;
 123         if (phy_data != NULL)
 124                 phy_data->state = state;
 125 }
 126
 127 void tenxpress_crc_err(struct efx_nic *efx)
 128 {
 129         struct tenxpress_phy_data *phy_data = efx->phy_data;
 130         if (phy_data != NULL)
 131                 atomic_inc(&phy_data->bad_crc_count);
 132 }
 133
 134 /* Check that the C166 has booted successfully */
 135 static int tenxpress_phy_check(struct efx_nic *efx)
 136 {
 137         int phy_id = efx->mii.phy_id;
 138         int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
 139         int boot_stat;
 140
 141         /* Wait for the boot to complete (or not) */
 142         while (count) {
 143                 boot_stat = mdio_clause45_read(efx, phy_id,
 144                                                MDIO_MMD_PCS,
 145                                                PCS_BOOT_STATUS_REG);
 146                 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
 147                         break;
 148                 count--;
 149                 udelay(PCS_BOOT_POLL_DELAY);
 150         }
 151
 152         if (!count) {
 153                 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
 154                         "%x\n", __func__,
 155                         (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
 156                         ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
 157                 return -ETIMEDOUT;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static void tenxpress_reset_xaui(struct efx_nic *efx);
 164
 165 static int tenxpress_init(struct efx_nic *efx)
 166 {
 167         int rc, reg;
 168
 169         /* Turn on the clock  */
 170         reg = (1 << CLK312_EN_LBN);
 171         mdio_clause45_write(efx, efx->mii.phy_id,
 172                             MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);
 173
 174         rc = tenxpress_phy_check(efx);
 175         if (rc < 0)
 176                 return rc;
 177
 178         /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
 179         reg = mdio_clause45_read(efx, efx->mii.phy_id,
 180                                  MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG);
 181         reg |= (1 << PMA_PMA_LED_ACTIVITY_LBN);
 182         mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 183                             PMA_PMD_LED_CTRL_REG, reg);
 184
 185         reg = PMA_PMD_LED_DEFAULT;
 186         mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 187                             PMA_PMD_LED_OVERR_REG, reg);
 188
 189         return rc;
 190 }
 191
 192 static int tenxpress_phy_init(struct efx_nic *efx)
 193 {
 194         struct tenxpress_phy_data *phy_data;
 195         int rc = 0;
 196
 197         phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
 198         efx->phy_data = phy_data;
 199
 200         tenxpress_set_state(efx, TENXPRESS_STATUS_NORMAL);
 201
 202         if (!sfe4001_phy_flash_cfg) {
 203                 rc = mdio_clause45_wait_reset_mmds(efx,
 204                                                    TENXPRESS_REQUIRED_DEVS);
 205                 if (rc < 0)
 206                         goto fail;
 207         }
 208
 209         rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
 210         if (rc < 0)
 211                 goto fail;
 212
 213         rc = tenxpress_init(efx);
 214         if (rc < 0)
 215                 goto fail;
 216
 217         schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
 218
 219         /* Let XGXS and SerDes out of reset and resets 10XPress */
 220         falcon_reset_xaui(efx);
 221
 222         return 0;
 223
 224  fail:
 225         kfree(efx->phy_data);
 226         efx->phy_data = NULL;
 227         return rc;
 228 }
 229
 230 static void tenxpress_set_bad_lp(struct efx_nic *efx, int bad_lp)
 231 {
 232         struct tenxpress_phy_data *pd = efx->phy_data;
 233         int reg;
 234
 235         /* Nothing to do if all is well and was previously so. */
 236         if (!(bad_lp || pd->bad_lp_tries))
 237                 return;
 238
 239         reg = mdio_clause45_read(efx, efx->mii.phy_id,
 240                                  MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG);
 241
 242         if (bad_lp)
 243                 pd->bad_lp_tries++;
 244         else
 245                 pd->bad_lp_tries = 0;
 246
 247         if (pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
 248                 pd->bad_lp_tries = 0;   /* Restart count */
 249                 reg &= ~(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
 250                 reg |= (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
 251                 EFX_ERR(efx, "This NIC appears to be plugged into"
 252                         " a port that is not 10GBASE-T capable.\n"
 253                         " This PHY is 10GBASE-T ONLY, so no link can"
 254                         " be established.\n");
 255         } else {
 256                 reg |= (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN);
 257         }
 258         mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 259                             PMA_PMD_LED_OVERR_REG, reg);
 260 }
 261
 262 /* Check link status and return a boolean OK value. If the link is NOT
 263  * OK we have a quick rummage round to see if we appear to be plugged
 264  * into a non-10GBT port and if so warn the user that they won't get
 265  * link any time soon as we are 10GBT only, unless caller specified
 266  * not to do this check (it isn't useful in loopback) */
 267 static int tenxpress_link_ok(struct efx_nic *efx, int check_lp)
 268 {
 269         int ok = mdio_clause45_links_ok(efx, TENXPRESS_REQUIRED_DEVS);
 270
 271         if (ok) {
 272                 tenxpress_set_bad_lp(efx, 0);
 273         } else if (check_lp) {
 274                 /* Are we plugged into the wrong sort of link? */
 275                 int bad_lp = 0;
 276                 int phy_id = efx->mii.phy_id;
 277                 int an_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 278                                                  MDIO_AN_STATUS);
 279                 int xphy_stat = mdio_clause45_read(efx, phy_id,
 280                                                    MDIO_MMD_PMAPMD,
 281                                                    PMA_PMD_XSTATUS_REG);
 282                 /* Are we plugged into anything that sends FLPs? If
 283                  * not we can't distinguish between not being plugged
 284                  * in and being plugged into a non-AN antique. The FLP
 285                  * bit has the advantage of not clearing when autoneg
 286                  * restarts. */
 287                 if (!(xphy_stat & (1 << PMA_PMD_XSTAT_FLP_LBN))) {
 288                         tenxpress_set_bad_lp(efx, 0);
 289                         return ok;
 290                 }
 291
 292                 /* If it can do 10GBT it must be XNP capable */
 293                 bad_lp = !(an_stat & (1 << MDIO_AN_STATUS_XNP_LBN));
 294                 if (!bad_lp && (an_stat & (1 << MDIO_AN_STATUS_PAGE_LBN))) {
 295                         bad_lp = !(mdio_clause45_read(efx, phy_id,
 296                                         MDIO_MMD_AN, MDIO_AN_10GBT_STATUS) &
 297                                         (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN));
 298                 }
 299                 tenxpress_set_bad_lp(efx, bad_lp);
 300         }
 301         return ok;
 302 }
 303
 304 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
 305 {
 306         if (!tenxpress_state_is(efx, TENXPRESS_STATUS_NORMAL))
 307                 return;
 308
 309         efx->link_up = tenxpress_link_ok(efx, 0);
 310         efx->link_options = GM_LPA_10000FULL;
 311 }
 312
 313 static void tenxpress_phy_clear_interrupt(struct efx_nic *efx)
 314 {
 315         /* Nothing done here - LASI interrupts aren't reliable so poll  */
 316 }
 317
 318
 319 /* Poll PHY for interrupt */
 320 static int tenxpress_phy_check_hw(struct efx_nic *efx)
 321 {
 322         struct tenxpress_phy_data *phy_data = efx->phy_data;
 323         int phy_up = tenxpress_state_is(efx, TENXPRESS_STATUS_NORMAL);
 324         int link_ok;
 325
 326         link_ok = phy_up && tenxpress_link_ok(efx, 1);
 327
 328         if (link_ok != efx->link_up)
 329                 falcon_xmac_sim_phy_event(efx);
 330
 331         /* Nothing to check if we've already shut down the PHY */
 332         if (!phy_up)
 333                 return 0;
 334
 335         if (atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
 336                 EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
 337                 falcon_reset_xaui(efx);
 338                 atomic_set(&phy_data->bad_crc_count, 0);
 339         }
 340
 341         return 0;
 342 }
 343
 344 static void tenxpress_phy_fini(struct efx_nic *efx)
 345 {
 346         int reg;
 347
 348         /* Power down the LNPGA */
 349         reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
 350         mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 351                             PMA_PMD_XCONTROL_REG, reg);
 352
 353         /* Waiting here ensures that the board fini, which can turn off the
 354          * power to the PHY, won't get run until the LNPGA powerdown has been
 355          * given long enough to complete. */
 356         schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
 357
 358         kfree(efx->phy_data);
 359         efx->phy_data = NULL;
 360 }
 361
 362
 363 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
 364  * (which probably aren't wired anyway) are left in AUTO mode */
 365 void tenxpress_phy_blink(struct efx_nic *efx, int blink)
 366 {
 367         int reg;
 368
 369         if (blink)
 370                 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
 371                         (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
 372                         (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
 373         else
 374                 reg = PMA_PMD_LED_DEFAULT;
 375
 376         mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 377                             PMA_PMD_LED_OVERR_REG, reg);
 378 }
 379
 380 static void tenxpress_reset_xaui(struct efx_nic *efx)
 381 {
 382         int phy = efx->mii.phy_id;
 383         int clk_ctrl, test_select, soft_rst2;
 384
 385         /* Real work is done on clock_ctrl other resets are thought to be
 386          * optional but make the reset more reliable
 387          */
 388
 389         /* Read */
 390         clk_ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
 391                                       PCS_CLOCK_CTRL_REG);
 392         test_select = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
 393                                          PCS_TEST_SELECT_REG);
 394         soft_rst2 = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
 395                                        PCS_SOFT_RST2_REG);
 396
 397         /* Put in reset */
 398         test_select &= ~(1 << CLK312_EN_LBN);
 399         mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
 400                             PCS_TEST_SELECT_REG, test_select);
 401
 402         soft_rst2 &= ~((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
 403         mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
 404                             PCS_SOFT_RST2_REG, soft_rst2);
 405
 406         clk_ctrl &= ~(1 << PLL312_RST_N_LBN);
 407         mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
 408                             PCS_CLOCK_CTRL_REG, clk_ctrl);
 409         udelay(10);
 410
 411         /* Remove reset */
 412         clk_ctrl |= (1 << PLL312_RST_N_LBN);
 413         mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
 414                             PCS_CLOCK_CTRL_REG, clk_ctrl);
 415         udelay(10);
 416
 417         soft_rst2 |= ((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
 418         mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
 419                             PCS_SOFT_RST2_REG, soft_rst2);
 420         udelay(10);
 421
 422         test_select |= (1 << CLK312_EN_LBN);
 423         mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
 424                             PCS_TEST_SELECT_REG, test_select);
 425         udelay(10);
 426 }
 427
 428 struct efx_phy_operations falcon_tenxpress_phy_ops = {
 429         .init             = tenxpress_phy_init,
 430         .reconfigure      = tenxpress_phy_reconfigure,
 431         .check_hw         = tenxpress_phy_check_hw,
 432         .fini             = tenxpress_phy_fini,
 433         .clear_interrupt  = tenxpress_phy_clear_interrupt,
 434         .reset_xaui       = tenxpress_reset_xaui,
 435         .mmds             = TENXPRESS_REQUIRED_DEVS,
 436 };