2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
79 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
80 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
82 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
84 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
85 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
86 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* 5424 Condor (PCI-E)*/
99 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
102 static struct ath5k_srev_name srev_names
[] = {
103 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
104 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
105 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
106 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
107 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
108 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
109 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
110 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
111 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
112 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
113 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
114 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
115 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
116 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
117 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
118 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
119 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
120 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
121 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
122 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
123 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
124 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
125 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
126 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
127 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
128 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
129 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
130 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
131 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
132 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
133 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
134 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
135 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
136 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
137 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
138 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
141 static struct ieee80211_rate ath5k_rates
[] = {
143 .hw_value
= ATH5K_RATE_CODE_1M
, },
145 .hw_value
= ATH5K_RATE_CODE_2M
,
146 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
147 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
149 .hw_value
= ATH5K_RATE_CODE_5_5M
,
150 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
151 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
153 .hw_value
= ATH5K_RATE_CODE_11M
,
154 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
155 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
157 .hw_value
= ATH5K_RATE_CODE_6M
,
160 .hw_value
= ATH5K_RATE_CODE_9M
,
163 .hw_value
= ATH5K_RATE_CODE_12M
,
166 .hw_value
= ATH5K_RATE_CODE_18M
,
169 .hw_value
= ATH5K_RATE_CODE_24M
,
172 .hw_value
= ATH5K_RATE_CODE_36M
,
175 .hw_value
= ATH5K_RATE_CODE_48M
,
178 .hw_value
= ATH5K_RATE_CODE_54M
,
184 * Prototypes - PCI stack related functions
186 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
187 const struct pci_device_id
*id
);
188 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
190 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
192 static int ath5k_pci_resume(struct pci_dev
*pdev
);
194 #define ath5k_pci_suspend NULL
195 #define ath5k_pci_resume NULL
196 #endif /* CONFIG_PM */
198 static struct pci_driver ath5k_pci_driver
= {
200 .id_table
= ath5k_pci_id_table
,
201 .probe
= ath5k_pci_probe
,
202 .remove
= __devexit_p(ath5k_pci_remove
),
203 .suspend
= ath5k_pci_suspend
,
204 .resume
= ath5k_pci_resume
,
210 * Prototypes - MAC 802.11 stack related functions
212 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
213 static int ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
);
214 static int ath5k_reset_wake(struct ath5k_softc
*sc
);
215 static int ath5k_start(struct ieee80211_hw
*hw
);
216 static void ath5k_stop(struct ieee80211_hw
*hw
);
217 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
218 struct ieee80211_if_init_conf
*conf
);
219 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
220 struct ieee80211_if_init_conf
*conf
);
221 static int ath5k_config(struct ieee80211_hw
*hw
,
222 struct ieee80211_conf
*conf
);
223 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
224 struct ieee80211_vif
*vif
,
225 struct ieee80211_if_conf
*conf
);
226 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
227 unsigned int changed_flags
,
228 unsigned int *new_flags
,
229 int mc_count
, struct dev_mc_list
*mclist
);
230 static int ath5k_set_key(struct ieee80211_hw
*hw
,
231 enum set_key_cmd cmd
,
232 const u8
*local_addr
, const u8
*addr
,
233 struct ieee80211_key_conf
*key
);
234 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
235 struct ieee80211_low_level_stats
*stats
);
236 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
237 struct ieee80211_tx_queue_stats
*stats
);
238 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
239 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
240 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
241 struct sk_buff
*skb
);
243 static struct ieee80211_ops ath5k_hw_ops
= {
245 .start
= ath5k_start
,
247 .add_interface
= ath5k_add_interface
,
248 .remove_interface
= ath5k_remove_interface
,
249 .config
= ath5k_config
,
250 .config_interface
= ath5k_config_interface
,
251 .configure_filter
= ath5k_configure_filter
,
252 .set_key
= ath5k_set_key
,
253 .get_stats
= ath5k_get_stats
,
255 .get_tx_stats
= ath5k_get_tx_stats
,
256 .get_tsf
= ath5k_get_tsf
,
257 .reset_tsf
= ath5k_reset_tsf
,
261 * Prototypes - Internal functions
264 static int ath5k_attach(struct pci_dev
*pdev
,
265 struct ieee80211_hw
*hw
);
266 static void ath5k_detach(struct pci_dev
*pdev
,
267 struct ieee80211_hw
*hw
);
268 /* Channel/mode setup */
269 static inline short ath5k_ieee2mhz(short chan
);
270 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
271 struct ieee80211_channel
*channels
,
274 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
275 static int ath5k_chan_set(struct ath5k_softc
*sc
,
276 struct ieee80211_channel
*chan
);
277 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
279 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
281 /* Descriptor setup */
282 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
283 struct pci_dev
*pdev
);
284 static void ath5k_desc_free(struct ath5k_softc
*sc
,
285 struct pci_dev
*pdev
);
287 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
288 struct ath5k_buf
*bf
);
289 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
290 struct ath5k_buf
*bf
);
291 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
292 struct ath5k_buf
*bf
)
297 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
299 dev_kfree_skb_any(bf
->skb
);
304 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
305 int qtype
, int subtype
);
306 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
307 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
308 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
309 struct ath5k_txq
*txq
);
310 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
311 static void ath5k_txq_release(struct ath5k_softc
*sc
);
313 static int ath5k_rx_start(struct ath5k_softc
*sc
);
314 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
315 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
316 struct ath5k_desc
*ds
,
318 struct ath5k_rx_status
*rs
);
319 static void ath5k_tasklet_rx(unsigned long data
);
321 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
322 struct ath5k_txq
*txq
);
323 static void ath5k_tasklet_tx(unsigned long data
);
324 /* Beacon handling */
325 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
326 struct ath5k_buf
*bf
);
327 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
328 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
329 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
331 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
333 u64 tsf
= ath5k_hw_get_tsf64(ah
);
335 if ((tsf
& 0x7fff) < rstamp
)
338 return (tsf
& ~0x7fff) | rstamp
;
341 /* Interrupt handling */
342 static int ath5k_init(struct ath5k_softc
*sc
);
343 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
344 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
345 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
346 static void ath5k_tasklet_reset(unsigned long data
);
348 static void ath5k_calibrate(unsigned long data
);
350 static int ath5k_init_leds(struct ath5k_softc
*sc
);
351 static void ath5k_led_enable(struct ath5k_softc
*sc
);
352 static void ath5k_led_off(struct ath5k_softc
*sc
);
353 static void ath5k_unregister_leds(struct ath5k_softc
*sc
);
356 * Module init/exit functions
365 ret
= pci_register_driver(&ath5k_pci_driver
);
367 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
377 pci_unregister_driver(&ath5k_pci_driver
);
379 ath5k_debug_finish();
382 module_init(init_ath5k_pci
);
383 module_exit(exit_ath5k_pci
);
386 /********************\
387 * PCI Initialization *
388 \********************/
391 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
393 const char *name
= "xxxxx";
396 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
397 if (srev_names
[i
].sr_type
!= type
)
400 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
401 name
= srev_names
[i
].sr_name
;
403 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
404 name
= srev_names
[i
].sr_name
;
413 ath5k_pci_probe(struct pci_dev
*pdev
,
414 const struct pci_device_id
*id
)
417 struct ath5k_softc
*sc
;
418 struct ieee80211_hw
*hw
;
422 ret
= pci_enable_device(pdev
);
424 dev_err(&pdev
->dev
, "can't enable device\n");
428 /* XXX 32-bit addressing only */
429 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
431 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
436 * Cache line size is used to size and align various
437 * structures used to communicate with the hardware.
439 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
442 * Linux 2.4.18 (at least) writes the cache line size
443 * register as a 16-bit wide register which is wrong.
444 * We must have this setup properly for rx buffer
445 * DMA to work so force a reasonable value here if it
448 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
449 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
452 * The default setting of latency timer yields poor results,
453 * set it to the value used by other systems. It may be worth
454 * tweaking this setting more.
456 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
458 /* Enable bus mastering */
459 pci_set_master(pdev
);
462 * Disable the RETRY_TIMEOUT register (0x41) to keep
463 * PCI Tx retries from interfering with C3 CPU state.
465 pci_write_config_byte(pdev
, 0x41, 0);
467 ret
= pci_request_region(pdev
, 0, "ath5k");
469 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
473 mem
= pci_iomap(pdev
, 0, 0);
475 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
481 * Allocate hw (mac80211 main struct)
482 * and hw->priv (driver private data)
484 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
486 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
491 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
493 /* Initialize driver private data */
494 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
495 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
496 IEEE80211_HW_SIGNAL_DBM
|
497 IEEE80211_HW_NOISE_DBM
;
499 hw
->wiphy
->interface_modes
=
500 BIT(NL80211_IFTYPE_STATION
) |
501 BIT(NL80211_IFTYPE_ADHOC
) |
502 BIT(NL80211_IFTYPE_MESH_POINT
);
504 hw
->extra_tx_headroom
= 2;
505 hw
->channel_change_time
= 5000;
510 ath5k_debug_init_device(sc
);
513 * Mark the device as detached to avoid processing
514 * interrupts until setup is complete.
516 __set_bit(ATH_STAT_INVALID
, sc
->status
);
518 sc
->iobase
= mem
; /* So we can unmap it on detach */
519 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
520 sc
->opmode
= NL80211_IFTYPE_STATION
;
521 mutex_init(&sc
->lock
);
522 spin_lock_init(&sc
->rxbuflock
);
523 spin_lock_init(&sc
->txbuflock
);
524 spin_lock_init(&sc
->block
);
526 /* Set private data */
527 pci_set_drvdata(pdev
, hw
);
529 /* Setup interrupt handler */
530 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
532 ATH5K_ERR(sc
, "request_irq failed\n");
536 /* Initialize device */
537 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
538 if (IS_ERR(sc
->ah
)) {
539 ret
= PTR_ERR(sc
->ah
);
543 /* Finish private driver data initialization */
544 ret
= ath5k_attach(pdev
, hw
);
548 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
549 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
551 sc
->ah
->ah_phy_revision
);
553 if (!sc
->ah
->ah_single_chip
) {
554 /* Single chip radio (!RF5111) */
555 if (sc
->ah
->ah_radio_5ghz_revision
&&
556 !sc
->ah
->ah_radio_2ghz_revision
) {
557 /* No 5GHz support -> report 2GHz radio */
558 if (!test_bit(AR5K_MODE_11A
,
559 sc
->ah
->ah_capabilities
.cap_mode
)) {
560 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
561 ath5k_chip_name(AR5K_VERSION_RAD
,
562 sc
->ah
->ah_radio_5ghz_revision
),
563 sc
->ah
->ah_radio_5ghz_revision
);
564 /* No 2GHz support (5110 and some
565 * 5Ghz only cards) -> report 5Ghz radio */
566 } else if (!test_bit(AR5K_MODE_11B
,
567 sc
->ah
->ah_capabilities
.cap_mode
)) {
568 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
569 ath5k_chip_name(AR5K_VERSION_RAD
,
570 sc
->ah
->ah_radio_5ghz_revision
),
571 sc
->ah
->ah_radio_5ghz_revision
);
572 /* Multiband radio */
574 ATH5K_INFO(sc
, "RF%s multiband radio found"
576 ath5k_chip_name(AR5K_VERSION_RAD
,
577 sc
->ah
->ah_radio_5ghz_revision
),
578 sc
->ah
->ah_radio_5ghz_revision
);
581 /* Multi chip radio (RF5111 - RF2111) ->
582 * report both 2GHz/5GHz radios */
583 else if (sc
->ah
->ah_radio_5ghz_revision
&&
584 sc
->ah
->ah_radio_2ghz_revision
){
585 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
586 ath5k_chip_name(AR5K_VERSION_RAD
,
587 sc
->ah
->ah_radio_5ghz_revision
),
588 sc
->ah
->ah_radio_5ghz_revision
);
589 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
590 ath5k_chip_name(AR5K_VERSION_RAD
,
591 sc
->ah
->ah_radio_2ghz_revision
),
592 sc
->ah
->ah_radio_2ghz_revision
);
597 /* ready to process interrupts */
598 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
602 ath5k_hw_detach(sc
->ah
);
604 free_irq(pdev
->irq
, sc
);
606 ieee80211_free_hw(hw
);
608 pci_iounmap(pdev
, mem
);
610 pci_release_region(pdev
, 0);
612 pci_disable_device(pdev
);
617 static void __devexit
618 ath5k_pci_remove(struct pci_dev
*pdev
)
620 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
621 struct ath5k_softc
*sc
= hw
->priv
;
623 ath5k_debug_finish_device(sc
);
624 ath5k_detach(pdev
, hw
);
625 ath5k_hw_detach(sc
->ah
);
626 free_irq(pdev
->irq
, sc
);
627 pci_iounmap(pdev
, sc
->iobase
);
628 pci_release_region(pdev
, 0);
629 pci_disable_device(pdev
);
630 ieee80211_free_hw(hw
);
635 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
637 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
638 struct ath5k_softc
*sc
= hw
->priv
;
644 free_irq(pdev
->irq
, sc
);
645 pci_save_state(pdev
);
646 pci_disable_device(pdev
);
647 pci_set_power_state(pdev
, PCI_D3hot
);
653 ath5k_pci_resume(struct pci_dev
*pdev
)
655 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
656 struct ath5k_softc
*sc
= hw
->priv
;
657 struct ath5k_hw
*ah
= sc
->ah
;
660 pci_restore_state(pdev
);
662 err
= pci_enable_device(pdev
);
667 * Suspend/Resume resets the PCI configuration space, so we have to
668 * re-disable the RETRY_TIMEOUT register (0x41) to keep
669 * PCI Tx retries from interfering with C3 CPU state
671 pci_write_config_byte(pdev
, 0x41, 0);
673 err
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
675 ATH5K_ERR(sc
, "request_irq failed\n");
679 err
= ath5k_init(sc
);
682 ath5k_led_enable(sc
);
685 * Reset the key cache since some parts do not
686 * reset the contents on initial power up or resume.
688 * FIXME: This may need to be revisited when mac80211 becomes
689 * aware of suspend/resume.
691 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
692 ath5k_hw_reset_key(ah
, i
);
696 free_irq(pdev
->irq
, sc
);
698 pci_disable_device(pdev
);
701 #endif /* CONFIG_PM */
704 /***********************\
705 * Driver Initialization *
706 \***********************/
709 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
711 struct ath5k_softc
*sc
= hw
->priv
;
712 struct ath5k_hw
*ah
= sc
->ah
;
717 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
720 * Check if the MAC has multi-rate retry support.
721 * We do this by trying to setup a fake extended
722 * descriptor. MAC's that don't have support will
723 * return false w/o doing anything. MAC's that do
724 * support it will return true w/o doing anything.
726 ret
= ah
->ah_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
730 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
733 * Reset the key cache since some parts do not
734 * reset the contents on initial power up.
736 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
737 ath5k_hw_reset_key(ah
, i
);
740 * Collect the channel list. The 802.11 layer
741 * is resposible for filtering this list based
742 * on settings like the phy mode and regulatory
743 * domain restrictions.
745 ret
= ath5k_setup_bands(hw
);
747 ATH5K_ERR(sc
, "can't get channels\n");
751 /* NB: setup here so ath5k_rate_update is happy */
752 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
753 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
755 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
758 * Allocate tx+rx descriptors and populate the lists.
760 ret
= ath5k_desc_alloc(sc
, pdev
);
762 ATH5K_ERR(sc
, "can't allocate descriptors\n");
767 * Allocate hardware transmit queues: one queue for
768 * beacon frames and one data queue for each QoS
769 * priority. Note that hw functions handle reseting
770 * these queues at the needed time.
772 ret
= ath5k_beaconq_setup(ah
);
774 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
779 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
780 if (IS_ERR(sc
->txq
)) {
781 ATH5K_ERR(sc
, "can't setup xmit queue\n");
782 ret
= PTR_ERR(sc
->txq
);
786 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
787 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
788 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
789 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
791 ath5k_hw_get_lladdr(ah
, mac
);
792 SET_IEEE80211_PERM_ADDR(hw
, mac
);
793 /* All MAC address bits matter for ACKs */
794 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
795 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
797 ret
= ieee80211_register_hw(hw
);
799 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
807 ath5k_txq_release(sc
);
809 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
811 ath5k_desc_free(sc
, pdev
);
817 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
819 struct ath5k_softc
*sc
= hw
->priv
;
822 * NB: the order of these is important:
823 * o call the 802.11 layer before detaching ath5k_hw to
824 * insure callbacks into the driver to delete global
825 * key cache entries can be handled
826 * o reclaim the tx queue data structures after calling
827 * the 802.11 layer as we'll get called back to reclaim
828 * node state and potentially want to use them
829 * o to cleanup the tx queues the hal is called, so detach
831 * XXX: ??? detach ath5k_hw ???
832 * Other than that, it's straightforward...
834 ieee80211_unregister_hw(hw
);
835 ath5k_desc_free(sc
, pdev
);
836 ath5k_txq_release(sc
);
837 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
838 ath5k_unregister_leds(sc
);
841 * NB: can't reclaim these until after ieee80211_ifdetach
842 * returns because we'll get called back to reclaim node
843 * state and potentially want to use them.
850 /********************\
851 * Channel/mode setup *
852 \********************/
855 * Convert IEEE channel number to MHz frequency.
858 ath5k_ieee2mhz(short chan
)
860 if (chan
<= 14 || chan
>= 27)
861 return ieee80211chan2mhz(chan
);
863 return 2212 + chan
* 20;
867 ath5k_copy_channels(struct ath5k_hw
*ah
,
868 struct ieee80211_channel
*channels
,
872 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
874 if (!test_bit(mode
, ah
->ah_modes
))
879 case AR5K_MODE_11A_TURBO
:
880 /* 1..220, but 2GHz frequencies are filtered by check_channel */
882 chfreq
= CHANNEL_5GHZ
;
886 case AR5K_MODE_11G_TURBO
:
888 chfreq
= CHANNEL_2GHZ
;
891 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
895 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
897 freq
= ath5k_ieee2mhz(ch
);
899 /* Check if channel is supported by the chipset */
900 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
903 /* Write channel info and increment counter */
904 channels
[count
].center_freq
= freq
;
905 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
906 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
910 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
912 case AR5K_MODE_11A_TURBO
:
913 case AR5K_MODE_11G_TURBO
:
914 channels
[count
].hw_value
= chfreq
|
915 CHANNEL_OFDM
| CHANNEL_TURBO
;
918 channels
[count
].hw_value
= CHANNEL_B
;
929 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
933 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
934 sc
->rate_idx
[b
->band
][i
] = -1;
936 for (i
= 0; i
< b
->n_bitrates
; i
++) {
937 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
938 if (b
->bitrates
[i
].hw_value_short
)
939 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
944 ath5k_setup_bands(struct ieee80211_hw
*hw
)
946 struct ath5k_softc
*sc
= hw
->priv
;
947 struct ath5k_hw
*ah
= sc
->ah
;
948 struct ieee80211_supported_band
*sband
;
949 int max_c
, count_c
= 0;
952 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
953 max_c
= ARRAY_SIZE(sc
->channels
);
956 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
957 sband
->band
= IEEE80211_BAND_2GHZ
;
958 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
960 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
962 memcpy(sband
->bitrates
, &ath5k_rates
[0],
963 sizeof(struct ieee80211_rate
) * 12);
964 sband
->n_bitrates
= 12;
966 sband
->channels
= sc
->channels
;
967 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
968 AR5K_MODE_11G
, max_c
);
970 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
971 count_c
= sband
->n_channels
;
973 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
975 memcpy(sband
->bitrates
, &ath5k_rates
[0],
976 sizeof(struct ieee80211_rate
) * 4);
977 sband
->n_bitrates
= 4;
979 /* 5211 only supports B rates and uses 4bit rate codes
980 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
983 if (ah
->ah_version
== AR5K_AR5211
) {
984 for (i
= 0; i
< 4; i
++) {
985 sband
->bitrates
[i
].hw_value
=
986 sband
->bitrates
[i
].hw_value
& 0xF;
987 sband
->bitrates
[i
].hw_value_short
=
988 sband
->bitrates
[i
].hw_value_short
& 0xF;
992 sband
->channels
= sc
->channels
;
993 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
994 AR5K_MODE_11B
, max_c
);
996 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
997 count_c
= sband
->n_channels
;
1000 ath5k_setup_rate_idx(sc
, sband
);
1002 /* 5GHz band, A mode */
1003 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1004 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1005 sband
->band
= IEEE80211_BAND_5GHZ
;
1006 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
1008 memcpy(sband
->bitrates
, &ath5k_rates
[4],
1009 sizeof(struct ieee80211_rate
) * 8);
1010 sband
->n_bitrates
= 8;
1012 sband
->channels
= &sc
->channels
[count_c
];
1013 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1014 AR5K_MODE_11A
, max_c
);
1016 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1018 ath5k_setup_rate_idx(sc
, sband
);
1020 ath5k_debug_dump_bands(sc
);
1026 * Set/change channels. If the channel is really being changed,
1027 * it's done by reseting the chip. To accomplish this we must
1028 * first cleanup any pending DMA, then restart stuff after a la
1032 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1034 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1035 sc
->curchan
->center_freq
, chan
->center_freq
);
1037 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
1038 chan
->hw_value
!= sc
->curchan
->hw_value
) {
1041 sc
->curband
= &sc
->sbands
[chan
->band
];
1044 * To switch channels clear any pending DMA operations;
1045 * wait long enough for the RX fifo to drain, reset the
1046 * hardware at the new frequency, and then re-enable
1047 * the relevant bits of the h/w.
1049 return ath5k_reset(sc
, true, true);
1056 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1060 if (mode
== AR5K_MODE_11A
) {
1061 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1063 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1068 ath5k_mode_setup(struct ath5k_softc
*sc
)
1070 struct ath5k_hw
*ah
= sc
->ah
;
1073 /* configure rx filter */
1074 rfilt
= sc
->filter_flags
;
1075 ath5k_hw_set_rx_filter(ah
, rfilt
);
1077 if (ath5k_hw_hasbssidmask(ah
))
1078 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1080 /* configure operational mode */
1081 ath5k_hw_set_opmode(ah
);
1083 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1084 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1088 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1090 WARN_ON(hw_rix
< 0 || hw_rix
> AR5K_MAX_RATES
);
1091 return sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1099 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1101 struct ath5k_hw
*ah
= sc
->ah
;
1102 struct sk_buff
*skb
= bf
->skb
;
1103 struct ath5k_desc
*ds
;
1105 if (likely(skb
== NULL
)) {
1109 * Allocate buffer with headroom_needed space for the
1110 * fake physical layer header at the start.
1112 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1113 if (unlikely(skb
== NULL
)) {
1114 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1115 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1119 * Cache-line-align. This is important (for the
1120 * 5210 at least) as not doing so causes bogus data
1123 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1125 skb_reserve(skb
, sc
->cachelsz
- off
);
1128 bf
->skbaddr
= pci_map_single(sc
->pdev
,
1129 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1130 if (unlikely(pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
))) {
1131 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1139 * Setup descriptors. For receive we always terminate
1140 * the descriptor list with a self-linked entry so we'll
1141 * not get overrun under high load (as can happen with a
1142 * 5212 when ANI processing enables PHY error frames).
1144 * To insure the last descriptor is self-linked we create
1145 * each descriptor as self-linked and add it to the end. As
1146 * each additional descriptor is added the previous self-linked
1147 * entry is ``fixed'' naturally. This should be safe even
1148 * if DMA is happening. When processing RX interrupts we
1149 * never remove/process the last, self-linked, entry on the
1150 * descriptor list. This insures the hardware always has
1151 * someplace to write a new frame.
1154 ds
->ds_link
= bf
->daddr
; /* link to self */
1155 ds
->ds_data
= bf
->skbaddr
;
1156 ah
->ah_setup_rx_desc(ah
, ds
,
1157 skb_tailroom(skb
), /* buffer size */
1160 if (sc
->rxlink
!= NULL
)
1161 *sc
->rxlink
= bf
->daddr
;
1162 sc
->rxlink
= &ds
->ds_link
;
1167 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1169 struct ath5k_hw
*ah
= sc
->ah
;
1170 struct ath5k_txq
*txq
= sc
->txq
;
1171 struct ath5k_desc
*ds
= bf
->desc
;
1172 struct sk_buff
*skb
= bf
->skb
;
1173 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1174 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1177 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1179 /* XXX endianness */
1180 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1183 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1184 flags
|= AR5K_TXDESC_NOACK
;
1188 if (info
->control
.hw_key
) {
1189 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1190 pktlen
+= info
->control
.icv_len
;
1192 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1193 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1194 (sc
->power_level
* 2),
1195 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1196 info
->control
.retry_limit
, keyidx
, 0, flags
, 0, 0);
1201 ds
->ds_data
= bf
->skbaddr
;
1203 spin_lock_bh(&txq
->lock
);
1204 list_add_tail(&bf
->list
, &txq
->q
);
1205 sc
->tx_stats
[txq
->qnum
].len
++;
1206 if (txq
->link
== NULL
) /* is this first packet? */
1207 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1208 else /* no, so only link it */
1209 *txq
->link
= bf
->daddr
;
1211 txq
->link
= &ds
->ds_link
;
1212 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1214 spin_unlock_bh(&txq
->lock
);
1218 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1222 /*******************\
1223 * Descriptors setup *
1224 \*******************/
1227 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1229 struct ath5k_desc
*ds
;
1230 struct ath5k_buf
*bf
;
1235 /* allocate descriptors */
1236 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1237 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1238 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1239 if (sc
->desc
== NULL
) {
1240 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1245 da
= sc
->desc_daddr
;
1246 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1247 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1249 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1250 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1252 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1258 INIT_LIST_HEAD(&sc
->rxbuf
);
1259 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1262 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1265 INIT_LIST_HEAD(&sc
->txbuf
);
1266 sc
->txbuf_len
= ATH_TXBUF
;
1267 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1268 da
+= sizeof(*ds
)) {
1271 list_add_tail(&bf
->list
, &sc
->txbuf
);
1281 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1288 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1290 struct ath5k_buf
*bf
;
1292 ath5k_txbuf_free(sc
, sc
->bbuf
);
1293 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1294 ath5k_txbuf_free(sc
, bf
);
1295 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1296 ath5k_txbuf_free(sc
, bf
);
1298 /* Free memory associated with all descriptors */
1299 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1313 static struct ath5k_txq
*
1314 ath5k_txq_setup(struct ath5k_softc
*sc
,
1315 int qtype
, int subtype
)
1317 struct ath5k_hw
*ah
= sc
->ah
;
1318 struct ath5k_txq
*txq
;
1319 struct ath5k_txq_info qi
= {
1320 .tqi_subtype
= subtype
,
1321 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1322 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1323 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1328 * Enable interrupts only for EOL and DESC conditions.
1329 * We mark tx descriptors to receive a DESC interrupt
1330 * when a tx queue gets deep; otherwise waiting for the
1331 * EOL to reap descriptors. Note that this is done to
1332 * reduce interrupt load and this only defers reaping
1333 * descriptors, never transmitting frames. Aside from
1334 * reducing interrupts this also permits more concurrency.
1335 * The only potential downside is if the tx queue backs
1336 * up in which case the top half of the kernel may backup
1337 * due to a lack of tx descriptors.
1339 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1340 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1341 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1344 * NB: don't print a message, this happens
1345 * normally on parts with too few tx queues
1347 return ERR_PTR(qnum
);
1349 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1350 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1351 qnum
, ARRAY_SIZE(sc
->txqs
));
1352 ath5k_hw_release_tx_queue(ah
, qnum
);
1353 return ERR_PTR(-EINVAL
);
1355 txq
= &sc
->txqs
[qnum
];
1359 INIT_LIST_HEAD(&txq
->q
);
1360 spin_lock_init(&txq
->lock
);
1363 return &sc
->txqs
[qnum
];
1367 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1369 struct ath5k_txq_info qi
= {
1370 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1371 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1372 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1373 /* NB: for dynamic turbo, don't enable any other interrupts */
1374 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1377 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1381 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1383 struct ath5k_hw
*ah
= sc
->ah
;
1384 struct ath5k_txq_info qi
;
1387 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1390 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1391 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1393 * Always burst out beacon and CAB traffic
1394 * (aifs = cwmin = cwmax = 0)
1399 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1401 * Adhoc mode; backoff between 0 and (2 * cw_min).
1405 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1408 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1409 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1410 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1412 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1414 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1415 "hardware queue!\n", __func__
);
1419 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1423 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1425 struct ath5k_buf
*bf
, *bf0
;
1428 * NB: this assumes output has been stopped and
1429 * we do not need to block ath5k_tx_tasklet
1431 spin_lock_bh(&txq
->lock
);
1432 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1433 ath5k_debug_printtxbuf(sc
, bf
);
1435 ath5k_txbuf_free(sc
, bf
);
1437 spin_lock_bh(&sc
->txbuflock
);
1438 sc
->tx_stats
[txq
->qnum
].len
--;
1439 list_move_tail(&bf
->list
, &sc
->txbuf
);
1441 spin_unlock_bh(&sc
->txbuflock
);
1444 spin_unlock_bh(&txq
->lock
);
1448 * Drain the transmit queues and reclaim resources.
1451 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1453 struct ath5k_hw
*ah
= sc
->ah
;
1456 /* XXX return value */
1457 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1458 /* don't touch the hardware if marked invalid */
1459 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1460 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1461 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1462 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1463 if (sc
->txqs
[i
].setup
) {
1464 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1465 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1468 ath5k_hw_get_txdp(ah
,
1473 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1475 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1476 if (sc
->txqs
[i
].setup
)
1477 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1481 ath5k_txq_release(struct ath5k_softc
*sc
)
1483 struct ath5k_txq
*txq
= sc
->txqs
;
1486 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1488 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1501 * Enable the receive h/w following a reset.
1504 ath5k_rx_start(struct ath5k_softc
*sc
)
1506 struct ath5k_hw
*ah
= sc
->ah
;
1507 struct ath5k_buf
*bf
;
1510 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1512 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1513 sc
->cachelsz
, sc
->rxbufsize
);
1517 spin_lock_bh(&sc
->rxbuflock
);
1518 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1519 ret
= ath5k_rxbuf_setup(sc
, bf
);
1521 spin_unlock_bh(&sc
->rxbuflock
);
1525 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1526 spin_unlock_bh(&sc
->rxbuflock
);
1528 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1529 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1530 ath5k_mode_setup(sc
); /* set filters, etc. */
1531 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1539 * Disable the receive h/w in preparation for a reset.
1542 ath5k_rx_stop(struct ath5k_softc
*sc
)
1544 struct ath5k_hw
*ah
= sc
->ah
;
1546 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1547 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1548 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1550 ath5k_debug_printrxbuffs(sc
, ah
);
1552 sc
->rxlink
= NULL
; /* just in case */
1556 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1557 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1559 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1560 unsigned int keyix
, hlen
;
1562 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1563 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1564 return RX_FLAG_DECRYPTED
;
1566 /* Apparently when a default key is used to decrypt the packet
1567 the hw does not set the index used to decrypt. In such cases
1568 get the index from the packet. */
1569 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1570 if (ieee80211_has_protected(hdr
->frame_control
) &&
1571 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1572 skb
->len
>= hlen
+ 4) {
1573 keyix
= skb
->data
[hlen
+ 3] >> 6;
1575 if (test_bit(keyix
, sc
->keymap
))
1576 return RX_FLAG_DECRYPTED
;
1584 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1585 struct ieee80211_rx_status
*rxs
)
1589 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1591 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1592 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1593 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1595 * Received an IBSS beacon with the same BSSID. Hardware *must*
1596 * have updated the local TSF. We have to work around various
1597 * hardware bugs, though...
1599 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1600 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1601 hw_tu
= TSF_TO_TU(tsf
);
1603 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1604 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1605 (unsigned long long)bc_tstamp
,
1606 (unsigned long long)rxs
->mactime
,
1607 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1608 (unsigned long long)tsf
);
1611 * Sometimes the HW will give us a wrong tstamp in the rx
1612 * status, causing the timestamp extension to go wrong.
1613 * (This seems to happen especially with beacon frames bigger
1614 * than 78 byte (incl. FCS))
1615 * But we know that the receive timestamp must be later than the
1616 * timestamp of the beacon since HW must have synced to that.
1618 * NOTE: here we assume mactime to be after the frame was
1619 * received, not like mac80211 which defines it at the start.
1621 if (bc_tstamp
> rxs
->mactime
) {
1622 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1623 "fixing mactime from %llx to %llx\n",
1624 (unsigned long long)rxs
->mactime
,
1625 (unsigned long long)tsf
);
1630 * Local TSF might have moved higher than our beacon timers,
1631 * in that case we have to update them to continue sending
1632 * beacons. This also takes care of synchronizing beacon sending
1633 * times with other stations.
1635 if (hw_tu
>= sc
->nexttbtt
)
1636 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1642 ath5k_tasklet_rx(unsigned long data
)
1644 struct ieee80211_rx_status rxs
= {};
1645 struct ath5k_rx_status rs
= {};
1646 struct sk_buff
*skb
;
1647 struct ath5k_softc
*sc
= (void *)data
;
1648 struct ath5k_buf
*bf
, *bf_last
;
1649 struct ath5k_desc
*ds
;
1654 spin_lock(&sc
->rxbuflock
);
1655 if (list_empty(&sc
->rxbuf
)) {
1656 ATH5K_WARN(sc
, "empty rx buf pool\n");
1659 bf_last
= list_entry(sc
->rxbuf
.prev
, struct ath5k_buf
, list
);
1663 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1664 BUG_ON(bf
->skb
== NULL
);
1669 * last buffer must not be freed to ensure proper hardware
1670 * function. When the hardware finishes also a packet next to
1671 * it, we are sure, it doesn't use it anymore and we can go on.
1676 struct ath5k_buf
*bf_next
= list_entry(bf
->list
.next
,
1677 struct ath5k_buf
, list
);
1678 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, bf_next
->desc
,
1683 /* skip the overwritten one (even status is martian) */
1687 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1688 if (unlikely(ret
== -EINPROGRESS
))
1690 else if (unlikely(ret
)) {
1691 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1692 spin_unlock(&sc
->rxbuflock
);
1696 if (unlikely(rs
.rs_more
)) {
1697 ATH5K_WARN(sc
, "unsupported jumbo\n");
1701 if (unlikely(rs
.rs_status
)) {
1702 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1704 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1706 * Decrypt error. If the error occurred
1707 * because there was no hardware key, then
1708 * let the frame through so the upper layers
1709 * can process it. This is necessary for 5210
1710 * parts which have no way to setup a ``clear''
1713 * XXX do key cache faulting
1715 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1716 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1719 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1720 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1724 /* let crypto-error packets fall through in MNTR */
1726 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1727 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
1731 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1732 PCI_DMA_FROMDEVICE
);
1735 skb_put(skb
, rs
.rs_datalen
);
1738 * the hardware adds a padding to 4 byte boundaries between
1739 * the header and the payload data if the header length is
1740 * not multiples of 4 - remove it
1742 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1745 memmove(skb
->data
+ pad
, skb
->data
, hdrlen
);
1750 * always extend the mac timestamp, since this information is
1751 * also needed for proper IBSS merging.
1753 * XXX: it might be too late to do it here, since rs_tstamp is
1754 * 15bit only. that means TSF extension has to be done within
1755 * 32768usec (about 32ms). it might be necessary to move this to
1756 * the interrupt handler, like it is done in madwifi.
1758 * Unfortunately we don't know when the hardware takes the rx
1759 * timestamp (beginning of phy frame, data frame, end of rx?).
1760 * The only thing we know is that it is hardware specific...
1761 * On AR5213 it seems the rx timestamp is at the end of the
1762 * frame, but i'm not sure.
1764 * NOTE: mac80211 defines mactime at the beginning of the first
1765 * data symbol. Since we don't have any time references it's
1766 * impossible to comply to that. This affects IBSS merge only
1767 * right now, so it's not too bad...
1769 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1770 rxs
.flag
|= RX_FLAG_TSFT
;
1772 rxs
.freq
= sc
->curchan
->center_freq
;
1773 rxs
.band
= sc
->curband
->band
;
1775 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1776 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1777 rxs
.qual
= rs
.rs_rssi
* 100 / 64;
1779 rxs
.antenna
= rs
.rs_antenna
;
1780 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1781 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1783 if (rxs
.rate_idx
>= 0 && rs
.rs_rate
==
1784 sc
->curband
->bitrates
[rxs
.rate_idx
].hw_value_short
)
1785 rxs
.flag
|= RX_FLAG_SHORTPRE
;
1787 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1789 /* check beacons in IBSS mode */
1790 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1791 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1793 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1795 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1796 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1798 spin_unlock(&sc
->rxbuflock
);
1809 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1811 struct ath5k_tx_status ts
= {};
1812 struct ath5k_buf
*bf
, *bf0
;
1813 struct ath5k_desc
*ds
;
1814 struct sk_buff
*skb
;
1815 struct ieee80211_tx_info
*info
;
1818 spin_lock(&txq
->lock
);
1819 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1822 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1823 if (unlikely(ret
== -EINPROGRESS
))
1825 else if (unlikely(ret
)) {
1826 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1832 info
= IEEE80211_SKB_CB(skb
);
1835 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1838 info
->status
.retry_count
= ts
.ts_shortretry
+ ts
.ts_longretry
/ 6;
1839 if (unlikely(ts
.ts_status
)) {
1840 sc
->ll_stats
.dot11ACKFailureCount
++;
1841 if (ts
.ts_status
& AR5K_TXERR_XRETRY
)
1842 info
->status
.excessive_retries
= 1;
1843 else if (ts
.ts_status
& AR5K_TXERR_FILT
)
1844 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1846 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1847 info
->status
.ack_signal
= ts
.ts_rssi
;
1850 ieee80211_tx_status(sc
->hw
, skb
);
1851 sc
->tx_stats
[txq
->qnum
].count
++;
1853 spin_lock(&sc
->txbuflock
);
1854 sc
->tx_stats
[txq
->qnum
].len
--;
1855 list_move_tail(&bf
->list
, &sc
->txbuf
);
1857 spin_unlock(&sc
->txbuflock
);
1859 if (likely(list_empty(&txq
->q
)))
1861 spin_unlock(&txq
->lock
);
1862 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1863 ieee80211_wake_queues(sc
->hw
);
1867 ath5k_tasklet_tx(unsigned long data
)
1869 struct ath5k_softc
*sc
= (void *)data
;
1871 ath5k_tx_processq(sc
, sc
->txq
);
1880 * Setup the beacon frame for transmit.
1883 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1885 struct sk_buff
*skb
= bf
->skb
;
1886 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1887 struct ath5k_hw
*ah
= sc
->ah
;
1888 struct ath5k_desc
*ds
;
1889 int ret
, antenna
= 0;
1892 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1894 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1895 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1896 (unsigned long long)bf
->skbaddr
);
1897 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
1898 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1904 flags
= AR5K_TXDESC_NOACK
;
1905 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1906 ds
->ds_link
= bf
->daddr
; /* self-linked */
1907 flags
|= AR5K_TXDESC_VEOL
;
1909 * Let hardware handle antenna switching if txantenna is not set
1914 * Switch antenna every 4 beacons if txantenna is not set
1915 * XXX assumes two antennas
1918 antenna
= sc
->bsent
& 4 ? 2 : 1;
1921 ds
->ds_data
= bf
->skbaddr
;
1922 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1923 ieee80211_get_hdrlen_from_skb(skb
),
1924 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
1925 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1926 1, AR5K_TXKEYIX_INVALID
,
1927 antenna
, flags
, 0, 0);
1933 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1938 * Transmit a beacon frame at SWBA. Dynamic updates to the
1939 * frame contents are done as needed and the slot time is
1940 * also adjusted based on current state.
1942 * this is usually called from interrupt context (ath5k_intr())
1943 * but also from ath5k_beacon_config() in IBSS mode which in turn
1944 * can be called from a tasklet and user context
1947 ath5k_beacon_send(struct ath5k_softc
*sc
)
1949 struct ath5k_buf
*bf
= sc
->bbuf
;
1950 struct ath5k_hw
*ah
= sc
->ah
;
1952 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1954 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
1955 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1956 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1960 * Check if the previous beacon has gone out. If
1961 * not don't don't try to post another, skip this
1962 * period and wait for the next. Missed beacons
1963 * indicate a problem and should not occur. If we
1964 * miss too many consecutive beacons reset the device.
1966 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
1968 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1969 "missed %u consecutive beacons\n", sc
->bmisscount
);
1970 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
1971 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1972 "stuck beacon time (%u missed)\n",
1974 tasklet_schedule(&sc
->restq
);
1978 if (unlikely(sc
->bmisscount
!= 0)) {
1979 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1980 "resume beacon xmit after %u misses\n",
1986 * Stop any current dma and put the new frame on the queue.
1987 * This should never fail since we check above that no frames
1988 * are still pending on the queue.
1990 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
1991 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
1992 /* NB: hw still stops DMA, so proceed */
1995 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
1996 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
1997 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
1998 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2005 * ath5k_beacon_update_timers - update beacon timers
2007 * @sc: struct ath5k_softc pointer we are operating on
2008 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2009 * beacon timer update based on the current HW TSF.
2011 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2012 * of a received beacon or the current local hardware TSF and write it to the
2013 * beacon timer registers.
2015 * This is called in a variety of situations, e.g. when a beacon is received,
2016 * when a TSF update has been detected, but also when an new IBSS is created or
2017 * when we otherwise know we have to update the timers, but we keep it in this
2018 * function to have it all together in one place.
2021 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2023 struct ath5k_hw
*ah
= sc
->ah
;
2024 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2027 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2028 if (WARN_ON(!intval
))
2031 /* beacon TSF converted to TU */
2032 bc_tu
= TSF_TO_TU(bc_tsf
);
2034 /* current TSF converted to TU */
2035 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2036 hw_tu
= TSF_TO_TU(hw_tsf
);
2039 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2042 * no beacons received, called internally.
2043 * just need to refresh timers based on HW TSF.
2045 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2046 } else if (bc_tsf
== 0) {
2048 * no beacon received, probably called by ath5k_reset_tsf().
2049 * reset TSF to start with 0.
2052 intval
|= AR5K_BEACON_RESET_TSF
;
2053 } else if (bc_tsf
> hw_tsf
) {
2055 * beacon received, SW merge happend but HW TSF not yet updated.
2056 * not possible to reconfigure timers yet, but next time we
2057 * receive a beacon with the same BSSID, the hardware will
2058 * automatically update the TSF and then we need to reconfigure
2061 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2062 "need to wait for HW TSF sync\n");
2066 * most important case for beacon synchronization between STA.
2068 * beacon received and HW TSF has been already updated by HW.
2069 * update next TBTT based on the TSF of the beacon, but make
2070 * sure it is ahead of our local TSF timer.
2072 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2076 sc
->nexttbtt
= nexttbtt
;
2078 intval
|= AR5K_BEACON_ENA
;
2079 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2082 * debugging output last in order to preserve the time critical aspect
2086 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2087 "reconfigured timers based on HW TSF\n");
2088 else if (bc_tsf
== 0)
2089 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2090 "reset HW TSF and timers\n");
2092 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2093 "updated timers based on beacon TSF\n");
2095 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2096 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2097 (unsigned long long) bc_tsf
,
2098 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2099 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2100 intval
& AR5K_BEACON_PERIOD
,
2101 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2102 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2107 * ath5k_beacon_config - Configure the beacon queues and interrupts
2109 * @sc: struct ath5k_softc pointer we are operating on
2111 * When operating in station mode we want to receive a BMISS interrupt when we
2112 * stop seeing beacons from the AP we've associated with so we can look for
2113 * another AP to associate with.
2115 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2116 * interrupts to detect TSF updates only.
2118 * AP mode is missing.
2121 ath5k_beacon_config(struct ath5k_softc
*sc
)
2123 struct ath5k_hw
*ah
= sc
->ah
;
2125 ath5k_hw_set_imr(ah
, 0);
2127 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2129 if (sc
->opmode
== NL80211_IFTYPE_STATION
) {
2130 sc
->imask
|= AR5K_INT_BMISS
;
2131 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2133 * In IBSS mode we use a self-linked tx descriptor and let the
2134 * hardware send the beacons automatically. We have to load it
2136 * We use the SWBA interrupt only to keep track of the beacon
2137 * timers in order to detect automatic TSF updates.
2139 ath5k_beaconq_config(sc
);
2141 sc
->imask
|= AR5K_INT_SWBA
;
2143 if (ath5k_hw_hasveol(ah
)) {
2144 spin_lock(&sc
->block
);
2145 ath5k_beacon_send(sc
);
2146 spin_unlock(&sc
->block
);
2151 ath5k_hw_set_imr(ah
, sc
->imask
);
2155 /********************\
2156 * Interrupt handling *
2157 \********************/
2160 ath5k_init(struct ath5k_softc
*sc
)
2164 mutex_lock(&sc
->lock
);
2166 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2169 * Stop anything previously setup. This is safe
2170 * no matter this is the first time through or not.
2172 ath5k_stop_locked(sc
);
2175 * The basic interface to setting the hardware in a good
2176 * state is ``reset''. On return the hardware is known to
2177 * be powered up and with interrupts disabled. This must
2178 * be followed by initialization of the appropriate bits
2179 * and then setup of the interrupt mask.
2181 sc
->curchan
= sc
->hw
->conf
.channel
;
2182 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2183 sc
->imask
= AR5K_INT_RX
| AR5K_INT_TX
| AR5K_INT_RXEOL
|
2184 AR5K_INT_RXORN
| AR5K_INT_FATAL
| AR5K_INT_GLOBAL
|
2186 ret
= ath5k_reset(sc
, false, false);
2190 /* Set ack to be sent at low bit-rates */
2191 ath5k_hw_set_ack_bitrate_high(sc
->ah
, false);
2193 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2194 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2199 mutex_unlock(&sc
->lock
);
2204 ath5k_stop_locked(struct ath5k_softc
*sc
)
2206 struct ath5k_hw
*ah
= sc
->ah
;
2208 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2209 test_bit(ATH_STAT_INVALID
, sc
->status
));
2212 * Shutdown the hardware and driver:
2213 * stop output from above
2214 * disable interrupts
2216 * turn off the radio
2217 * clear transmit machinery
2218 * clear receive machinery
2219 * drain and release tx queues
2220 * reclaim beacon resources
2221 * power down hardware
2223 * Note that some of this work is not possible if the
2224 * hardware is gone (invalid).
2226 ieee80211_stop_queues(sc
->hw
);
2228 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2230 ath5k_hw_set_imr(ah
, 0);
2231 synchronize_irq(sc
->pdev
->irq
);
2233 ath5k_txq_cleanup(sc
);
2234 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2236 ath5k_hw_phy_disable(ah
);
2244 * Stop the device, grabbing the top-level lock to protect
2245 * against concurrent entry through ath5k_init (which can happen
2246 * if another thread does a system call and the thread doing the
2247 * stop is preempted).
2250 ath5k_stop_hw(struct ath5k_softc
*sc
)
2254 mutex_lock(&sc
->lock
);
2255 ret
= ath5k_stop_locked(sc
);
2256 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2258 * Set the chip in full sleep mode. Note that we are
2259 * careful to do this only when bringing the interface
2260 * completely to a stop. When the chip is in this state
2261 * it must be carefully woken up or references to
2262 * registers in the PCI clock domain may freeze the bus
2263 * (and system). This varies by chip and is mostly an
2264 * issue with newer parts that go to sleep more quickly.
2266 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2269 * don't put newer MAC revisions > 7.8 to sleep because
2270 * of the above mentioned problems
2272 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2273 "not putting device to sleep\n");
2275 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2276 "putting device to full sleep\n");
2277 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2280 ath5k_txbuf_free(sc
, sc
->bbuf
);
2282 mutex_unlock(&sc
->lock
);
2284 del_timer_sync(&sc
->calib_tim
);
2285 tasklet_kill(&sc
->rxtq
);
2286 tasklet_kill(&sc
->txtq
);
2287 tasklet_kill(&sc
->restq
);
2293 ath5k_intr(int irq
, void *dev_id
)
2295 struct ath5k_softc
*sc
= dev_id
;
2296 struct ath5k_hw
*ah
= sc
->ah
;
2297 enum ath5k_int status
;
2298 unsigned int counter
= 1000;
2300 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2301 !ath5k_hw_is_intr_pending(ah
)))
2306 * Figure out the reason(s) for the interrupt. Note
2307 * that get_isr returns a pseudo-ISR that may include
2308 * bits we haven't explicitly enabled so we mask the
2309 * value to insure we only process bits we requested.
2311 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2312 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2314 status
&= sc
->imask
; /* discard unasked for bits */
2315 if (unlikely(status
& AR5K_INT_FATAL
)) {
2317 * Fatal errors are unrecoverable.
2318 * Typically these are caused by DMA errors.
2320 tasklet_schedule(&sc
->restq
);
2321 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2322 tasklet_schedule(&sc
->restq
);
2324 if (status
& AR5K_INT_SWBA
) {
2326 * Software beacon alert--time to send a beacon.
2327 * Handle beacon transmission directly; deferring
2328 * this is too slow to meet timing constraints
2331 * In IBSS mode we use this interrupt just to
2332 * keep track of the next TBTT (target beacon
2333 * transmission time) in order to detect wether
2334 * automatic TSF updates happened.
2336 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2337 /* XXX: only if VEOL suppported */
2338 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2339 sc
->nexttbtt
+= sc
->bintval
;
2340 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2341 "SWBA nexttbtt: %x hw_tu: %x "
2345 (unsigned long long) tsf
);
2347 spin_lock(&sc
->block
);
2348 ath5k_beacon_send(sc
);
2349 spin_unlock(&sc
->block
);
2352 if (status
& AR5K_INT_RXEOL
) {
2354 * NB: the hardware should re-read the link when
2355 * RXE bit is written, but it doesn't work at
2356 * least on older hardware revs.
2360 if (status
& AR5K_INT_TXURN
) {
2361 /* bump tx trigger level */
2362 ath5k_hw_update_tx_triglevel(ah
, true);
2364 if (status
& AR5K_INT_RX
)
2365 tasklet_schedule(&sc
->rxtq
);
2366 if (status
& AR5K_INT_TX
)
2367 tasklet_schedule(&sc
->txtq
);
2368 if (status
& AR5K_INT_BMISS
) {
2370 if (status
& AR5K_INT_MIB
) {
2372 * These stats are also used for ANI i think
2373 * so how about updating them more often ?
2375 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2378 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2380 if (unlikely(!counter
))
2381 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2387 ath5k_tasklet_reset(unsigned long data
)
2389 struct ath5k_softc
*sc
= (void *)data
;
2391 ath5k_reset_wake(sc
);
2395 * Periodically recalibrate the PHY to account
2396 * for temperature/environment changes.
2399 ath5k_calibrate(unsigned long data
)
2401 struct ath5k_softc
*sc
= (void *)data
;
2402 struct ath5k_hw
*ah
= sc
->ah
;
2404 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2405 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2406 sc
->curchan
->hw_value
);
2408 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2410 * Rfgain is out of bounds, reset the chip
2411 * to load new gain values.
2413 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2414 ath5k_reset_wake(sc
);
2416 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2417 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2418 ieee80211_frequency_to_channel(
2419 sc
->curchan
->center_freq
));
2421 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2422 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2432 ath5k_led_enable(struct ath5k_softc
*sc
)
2434 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2435 ath5k_hw_set_gpio_output(sc
->ah
, sc
->led_pin
);
2441 ath5k_led_on(struct ath5k_softc
*sc
)
2443 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2445 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2449 ath5k_led_off(struct ath5k_softc
*sc
)
2451 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2453 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2457 ath5k_led_brightness_set(struct led_classdev
*led_dev
,
2458 enum led_brightness brightness
)
2460 struct ath5k_led
*led
= container_of(led_dev
, struct ath5k_led
,
2463 if (brightness
== LED_OFF
)
2464 ath5k_led_off(led
->sc
);
2466 ath5k_led_on(led
->sc
);
2470 ath5k_register_led(struct ath5k_softc
*sc
, struct ath5k_led
*led
,
2471 const char *name
, char *trigger
)
2476 strncpy(led
->name
, name
, sizeof(led
->name
));
2477 led
->led_dev
.name
= led
->name
;
2478 led
->led_dev
.default_trigger
= trigger
;
2479 led
->led_dev
.brightness_set
= ath5k_led_brightness_set
;
2481 err
= led_classdev_register(&sc
->pdev
->dev
, &led
->led_dev
);
2484 ATH5K_WARN(sc
, "could not register LED %s\n", name
);
2491 ath5k_unregister_led(struct ath5k_led
*led
)
2495 led_classdev_unregister(&led
->led_dev
);
2496 ath5k_led_off(led
->sc
);
2501 ath5k_unregister_leds(struct ath5k_softc
*sc
)
2503 ath5k_unregister_led(&sc
->rx_led
);
2504 ath5k_unregister_led(&sc
->tx_led
);
2509 ath5k_init_leds(struct ath5k_softc
*sc
)
2512 struct ieee80211_hw
*hw
= sc
->hw
;
2513 struct pci_dev
*pdev
= sc
->pdev
;
2514 char name
[ATH5K_LED_MAX_NAME_LEN
+ 1];
2517 * Auto-enable soft led processing for IBM cards and for
2518 * 5211 minipci cards.
2520 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
2521 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
2522 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2524 sc
->led_on
= 0; /* active low */
2526 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2527 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
2528 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2530 sc
->led_on
= 1; /* active high */
2532 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2535 ath5k_led_enable(sc
);
2537 snprintf(name
, sizeof(name
), "ath5k-%s::rx", wiphy_name(hw
->wiphy
));
2538 ret
= ath5k_register_led(sc
, &sc
->rx_led
, name
,
2539 ieee80211_get_rx_led_name(hw
));
2543 snprintf(name
, sizeof(name
), "ath5k-%s::tx", wiphy_name(hw
->wiphy
));
2544 ret
= ath5k_register_led(sc
, &sc
->tx_led
, name
,
2545 ieee80211_get_tx_led_name(hw
));
2551 /********************\
2552 * Mac80211 functions *
2553 \********************/
2556 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2558 struct ath5k_softc
*sc
= hw
->priv
;
2559 struct ath5k_buf
*bf
;
2560 unsigned long flags
;
2564 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2566 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2567 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2570 * the hardware expects the header padded to 4 byte boundaries
2571 * if this is not the case we add the padding after the header
2573 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2576 if (skb_headroom(skb
) < pad
) {
2577 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2578 " headroom to pad %d\n", hdrlen
, pad
);
2582 memmove(skb
->data
, skb
->data
+pad
, hdrlen
);
2585 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2586 if (list_empty(&sc
->txbuf
)) {
2587 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2588 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2589 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2592 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2593 list_del(&bf
->list
);
2595 if (list_empty(&sc
->txbuf
))
2596 ieee80211_stop_queues(hw
);
2597 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2601 if (ath5k_txbuf_setup(sc
, bf
)) {
2603 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2604 list_add_tail(&bf
->list
, &sc
->txbuf
);
2606 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2607 dev_kfree_skb_any(skb
);
2615 ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
)
2617 struct ath5k_hw
*ah
= sc
->ah
;
2620 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2623 ath5k_hw_set_imr(ah
, 0);
2624 ath5k_txq_cleanup(sc
);
2627 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2629 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2634 * This is needed only to setup initial state
2635 * but it's best done after a reset.
2637 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2639 ret
= ath5k_rx_start(sc
);
2641 ATH5K_ERR(sc
, "can't start recv logic\n");
2646 * Change channels and update the h/w rate map if we're switching;
2647 * e.g. 11a to 11b/g.
2649 * We may be doing a reset in response to an ioctl that changes the
2650 * channel so update any state that might change as a result.
2654 /* ath5k_chan_change(sc, c); */
2656 ath5k_beacon_config(sc
);
2657 /* intrs are enabled by ath5k_beacon_config */
2665 ath5k_reset_wake(struct ath5k_softc
*sc
)
2669 ret
= ath5k_reset(sc
, true, true);
2671 ieee80211_wake_queues(sc
->hw
);
2676 static int ath5k_start(struct ieee80211_hw
*hw
)
2678 return ath5k_init(hw
->priv
);
2681 static void ath5k_stop(struct ieee80211_hw
*hw
)
2683 ath5k_stop_hw(hw
->priv
);
2686 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2687 struct ieee80211_if_init_conf
*conf
)
2689 struct ath5k_softc
*sc
= hw
->priv
;
2692 mutex_lock(&sc
->lock
);
2698 sc
->vif
= conf
->vif
;
2700 switch (conf
->type
) {
2701 case NL80211_IFTYPE_STATION
:
2702 case NL80211_IFTYPE_ADHOC
:
2703 case NL80211_IFTYPE_MONITOR
:
2704 sc
->opmode
= conf
->type
;
2711 /* Set to a reasonable value. Note that this will
2712 * be set to mac80211's value at ath5k_config(). */
2717 mutex_unlock(&sc
->lock
);
2722 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2723 struct ieee80211_if_init_conf
*conf
)
2725 struct ath5k_softc
*sc
= hw
->priv
;
2727 mutex_lock(&sc
->lock
);
2728 if (sc
->vif
!= conf
->vif
)
2733 mutex_unlock(&sc
->lock
);
2737 * TODO: Phy disable/diversity etc
2740 ath5k_config(struct ieee80211_hw
*hw
,
2741 struct ieee80211_conf
*conf
)
2743 struct ath5k_softc
*sc
= hw
->priv
;
2745 sc
->bintval
= conf
->beacon_int
;
2746 sc
->power_level
= conf
->power_level
;
2748 return ath5k_chan_set(sc
, conf
->channel
);
2752 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2753 struct ieee80211_if_conf
*conf
)
2755 struct ath5k_softc
*sc
= hw
->priv
;
2756 struct ath5k_hw
*ah
= sc
->ah
;
2759 mutex_lock(&sc
->lock
);
2760 if (sc
->vif
!= vif
) {
2765 /* Cache for later use during resets */
2766 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2767 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2768 * a clean way of letting us retrieve this yet. */
2769 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2773 if (conf
->changed
& IEEE80211_IFCC_BEACON
&&
2774 vif
->type
== NL80211_IFTYPE_ADHOC
) {
2775 struct sk_buff
*beacon
= ieee80211_beacon_get(hw
, vif
);
2780 /* call old handler for now */
2781 ath5k_beacon_update(hw
, beacon
);
2784 mutex_unlock(&sc
->lock
);
2786 return ath5k_reset_wake(sc
);
2788 mutex_unlock(&sc
->lock
);
2792 #define SUPPORTED_FIF_FLAGS \
2793 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2794 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2795 FIF_BCN_PRBRESP_PROMISC
2797 * o always accept unicast, broadcast, and multicast traffic
2798 * o multicast traffic for all BSSIDs will be enabled if mac80211
2800 * o maintain current state of phy ofdm or phy cck error reception.
2801 * If the hardware detects any of these type of errors then
2802 * ath5k_hw_get_rx_filter() will pass to us the respective
2803 * hardware filters to be able to receive these type of frames.
2804 * o probe request frames are accepted only when operating in
2805 * hostap, adhoc, or monitor modes
2806 * o enable promiscuous mode according to the interface state
2808 * - when operating in adhoc mode so the 802.11 layer creates
2809 * node table entries for peers,
2810 * - when operating in station mode for collecting rssi data when
2811 * the station is otherwise quiet, or
2814 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2815 unsigned int changed_flags
,
2816 unsigned int *new_flags
,
2817 int mc_count
, struct dev_mc_list
*mclist
)
2819 struct ath5k_softc
*sc
= hw
->priv
;
2820 struct ath5k_hw
*ah
= sc
->ah
;
2821 u32 mfilt
[2], val
, rfilt
;
2828 /* Only deal with supported flags */
2829 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2830 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2832 /* If HW detects any phy or radar errors, leave those filters on.
2833 * Also, always enable Unicast, Broadcasts and Multicast
2834 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2835 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2836 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2837 AR5K_RX_FILTER_MCAST
);
2839 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2840 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2841 rfilt
|= AR5K_RX_FILTER_PROM
;
2842 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2845 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2848 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2849 if (*new_flags
& FIF_ALLMULTI
) {
2853 for (i
= 0; i
< mc_count
; i
++) {
2856 /* calculate XOR of eight 6-bit values */
2857 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2858 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2859 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2860 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2862 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2863 /* XXX: we might be able to just do this instead,
2864 * but not sure, needs testing, if we do use this we'd
2865 * neet to inform below to not reset the mcast */
2866 /* ath5k_hw_set_mcast_filterindex(ah,
2867 * mclist->dmi_addr[5]); */
2868 mclist
= mclist
->next
;
2872 /* This is the best we can do */
2873 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2874 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2876 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2877 * and probes for any BSSID, this needs testing */
2878 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2879 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2881 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2882 * set we should only pass on control frames for this
2883 * station. This needs testing. I believe right now this
2884 * enables *all* control frames, which is OK.. but
2885 * but we should see if we can improve on granularity */
2886 if (*new_flags
& FIF_CONTROL
)
2887 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2889 /* Additional settings per mode -- this is per ath5k */
2891 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2893 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2894 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2895 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2896 if (sc
->opmode
!= NL80211_IFTYPE_STATION
)
2897 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2898 if (sc
->opmode
!= NL80211_IFTYPE_AP
&&
2899 sc
->opmode
!= NL80211_IFTYPE_MESH_POINT
&&
2900 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2901 rfilt
|= AR5K_RX_FILTER_PROM
;
2902 if (sc
->opmode
== NL80211_IFTYPE_STATION
||
2903 sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2904 rfilt
|= AR5K_RX_FILTER_BEACON
;
2908 ath5k_hw_set_rx_filter(ah
,rfilt
);
2910 /* Set multicast bits */
2911 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2912 /* Set the cached hw filter flags, this will alter actually
2914 sc
->filter_flags
= rfilt
;
2918 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2919 const u8
*local_addr
, const u8
*addr
,
2920 struct ieee80211_key_conf
*key
)
2922 struct ath5k_softc
*sc
= hw
->priv
;
2927 /* XXX: fix hardware encryption, its not working. For now
2928 * allow software encryption */
2938 mutex_lock(&sc
->lock
);
2942 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
, addr
);
2944 ATH5K_ERR(sc
, "can't set the key\n");
2947 __set_bit(key
->keyidx
, sc
->keymap
);
2948 key
->hw_key_idx
= key
->keyidx
;
2951 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
2952 __clear_bit(key
->keyidx
, sc
->keymap
);
2961 mutex_unlock(&sc
->lock
);
2966 ath5k_get_stats(struct ieee80211_hw
*hw
,
2967 struct ieee80211_low_level_stats
*stats
)
2969 struct ath5k_softc
*sc
= hw
->priv
;
2970 struct ath5k_hw
*ah
= sc
->ah
;
2973 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2975 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
2981 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
2982 struct ieee80211_tx_queue_stats
*stats
)
2984 struct ath5k_softc
*sc
= hw
->priv
;
2986 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
2992 ath5k_get_tsf(struct ieee80211_hw
*hw
)
2994 struct ath5k_softc
*sc
= hw
->priv
;
2996 return ath5k_hw_get_tsf64(sc
->ah
);
3000 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3002 struct ath5k_softc
*sc
= hw
->priv
;
3005 * in IBSS mode we need to update the beacon timers too.
3006 * this will also reset the TSF if we call it with 0
3008 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3009 ath5k_beacon_update_timers(sc
, 0);
3011 ath5k_hw_reset_tsf(sc
->ah
);
3015 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
3017 struct ath5k_softc
*sc
= hw
->priv
;
3018 unsigned long flags
;
3021 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3023 if (sc
->opmode
!= NL80211_IFTYPE_ADHOC
) {
3028 spin_lock_irqsave(&sc
->block
, flags
);
3029 ath5k_txbuf_free(sc
, sc
->bbuf
);
3030 sc
->bbuf
->skb
= skb
;
3031 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3033 sc
->bbuf
->skb
= NULL
;
3034 spin_unlock_irqrestore(&sc
->block
, flags
);
3036 ath5k_beacon_config(sc
);