2 * An i2c driver for the Xicor/Intersil X1205 RTC
3 * Copyright 2004 Karen Spearel
4 * Copyright 2005 Alessandro Zummo
6 * please send all reports to:
7 * Karen Spearel <kas111 at gmail dot com>
8 * Alessandro Zummo <a.zummo@towertech.it>
10 * based on a lot of other RTC drivers.
12 * Information and datasheet:
13 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/i2c.h>
21 #include <linux/bcd.h>
22 #include <linux/rtc.h>
23 #include <linux/delay.h>
25 #define DRV_VERSION "1.0.8"
27 /* offsets into CCR area */
38 #define X1205_REG_SR 0x3F /* status register */
39 #define X1205_REG_Y2K 0x37
40 #define X1205_REG_DW 0x36
41 #define X1205_REG_YR 0x35
42 #define X1205_REG_MO 0x34
43 #define X1205_REG_DT 0x33
44 #define X1205_REG_HR 0x32
45 #define X1205_REG_MN 0x31
46 #define X1205_REG_SC 0x30
47 #define X1205_REG_DTR 0x13
48 #define X1205_REG_ATR 0x12
49 #define X1205_REG_INT 0x11
50 #define X1205_REG_0 0x10
51 #define X1205_REG_Y2K1 0x0F
52 #define X1205_REG_DWA1 0x0E
53 #define X1205_REG_YRA1 0x0D
54 #define X1205_REG_MOA1 0x0C
55 #define X1205_REG_DTA1 0x0B
56 #define X1205_REG_HRA1 0x0A
57 #define X1205_REG_MNA1 0x09
58 #define X1205_REG_SCA1 0x08
59 #define X1205_REG_Y2K0 0x07
60 #define X1205_REG_DWA0 0x06
61 #define X1205_REG_YRA0 0x05
62 #define X1205_REG_MOA0 0x04
63 #define X1205_REG_DTA0 0x03
64 #define X1205_REG_HRA0 0x02
65 #define X1205_REG_MNA0 0x01
66 #define X1205_REG_SCA0 0x00
68 #define X1205_CCR_BASE 0x30 /* Base address of CCR */
69 #define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
71 #define X1205_SR_RTCF 0x01 /* Clock failure */
72 #define X1205_SR_WEL 0x02 /* Write Enable Latch */
73 #define X1205_SR_RWEL 0x04 /* Register Write Enable */
74 #define X1205_SR_AL0 0x20 /* Alarm 0 match */
76 #define X1205_DTR_DTR0 0x01
77 #define X1205_DTR_DTR1 0x02
78 #define X1205_DTR_DTR2 0x04
80 #define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
82 #define X1205_INT_AL0E 0x20 /* Alarm 0 enable */
84 static struct i2c_driver x1205_driver
;
87 * In the routines that deal directly with the x1205 hardware, we use
88 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
89 * Epoch is initialized as 2000. Time is set to UTC.
91 static int x1205_get_datetime(struct i2c_client
*client
, struct rtc_time
*tm
,
92 unsigned char reg_base
)
94 unsigned char dt_addr
[2] = { 0, reg_base
};
98 struct i2c_msg msgs
[] = {
99 { client
->addr
, 0, 2, dt_addr
}, /* setup read ptr */
100 { client
->addr
, I2C_M_RD
, 8, buf
}, /* read date */
103 /* read date registers */
104 if (i2c_transfer(client
->adapter
, &msgs
[0], 2) != 2) {
105 dev_err(&client
->dev
, "%s: read error\n", __func__
);
109 dev_dbg(&client
->dev
,
110 "%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
111 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
113 buf
[0], buf
[1], buf
[2], buf
[3],
114 buf
[4], buf
[5], buf
[6], buf
[7]);
116 /* Mask out the enable bits if these are alarm registers */
117 if (reg_base
< X1205_CCR_BASE
)
118 for (i
= 0; i
<= 4; i
++)
121 tm
->tm_sec
= bcd2bin(buf
[CCR_SEC
]);
122 tm
->tm_min
= bcd2bin(buf
[CCR_MIN
]);
123 tm
->tm_hour
= bcd2bin(buf
[CCR_HOUR
] & 0x3F); /* hr is 0-23 */
124 tm
->tm_mday
= bcd2bin(buf
[CCR_MDAY
]);
125 tm
->tm_mon
= bcd2bin(buf
[CCR_MONTH
]) - 1; /* mon is 0-11 */
126 tm
->tm_year
= bcd2bin(buf
[CCR_YEAR
])
127 + (bcd2bin(buf
[CCR_Y2K
]) * 100) - 1900;
128 tm
->tm_wday
= buf
[CCR_WDAY
];
130 dev_dbg(&client
->dev
, "%s: tm is secs=%d, mins=%d, hours=%d, "
131 "mday=%d, mon=%d, year=%d, wday=%d\n",
133 tm
->tm_sec
, tm
->tm_min
, tm
->tm_hour
,
134 tm
->tm_mday
, tm
->tm_mon
, tm
->tm_year
, tm
->tm_wday
);
139 static int x1205_get_status(struct i2c_client
*client
, unsigned char *sr
)
141 static unsigned char sr_addr
[2] = { 0, X1205_REG_SR
};
143 struct i2c_msg msgs
[] = {
144 { client
->addr
, 0, 2, sr_addr
}, /* setup read ptr */
145 { client
->addr
, I2C_M_RD
, 1, sr
}, /* read status */
148 /* read status register */
149 if (i2c_transfer(client
->adapter
, &msgs
[0], 2) != 2) {
150 dev_err(&client
->dev
, "%s: read error\n", __func__
);
157 static int x1205_set_datetime(struct i2c_client
*client
, struct rtc_time
*tm
,
158 u8 reg_base
, unsigned char alm_enable
)
161 unsigned char rdata
[10] = { 0, reg_base
};
162 unsigned char *buf
= rdata
+ 2;
164 static const unsigned char wel
[3] = { 0, X1205_REG_SR
,
167 static const unsigned char rwel
[3] = { 0, X1205_REG_SR
,
168 X1205_SR_WEL
| X1205_SR_RWEL
};
170 static const unsigned char diswe
[3] = { 0, X1205_REG_SR
, 0 };
172 dev_dbg(&client
->dev
,
173 "%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
174 __func__
, tm
->tm_sec
, tm
->tm_min
, tm
->tm_hour
, tm
->tm_mday
,
175 tm
->tm_mon
, tm
->tm_year
, tm
->tm_wday
);
177 buf
[CCR_SEC
] = bin2bcd(tm
->tm_sec
);
178 buf
[CCR_MIN
] = bin2bcd(tm
->tm_min
);
180 /* set hour and 24hr bit */
181 buf
[CCR_HOUR
] = bin2bcd(tm
->tm_hour
) | X1205_HR_MIL
;
183 buf
[CCR_MDAY
] = bin2bcd(tm
->tm_mday
);
186 buf
[CCR_MONTH
] = bin2bcd(tm
->tm_mon
+ 1);
188 /* year, since the rtc epoch*/
189 buf
[CCR_YEAR
] = bin2bcd(tm
->tm_year
% 100);
190 buf
[CCR_WDAY
] = tm
->tm_wday
& 0x07;
191 buf
[CCR_Y2K
] = bin2bcd((tm
->tm_year
+ 1900) / 100);
193 /* If writing alarm registers, set compare bits on registers 0-4 */
194 if (reg_base
< X1205_CCR_BASE
)
195 for (i
= 0; i
<= 4; i
++)
198 /* this sequence is required to unlock the chip */
199 if ((xfer
= i2c_master_send(client
, wel
, 3)) != 3) {
200 dev_err(&client
->dev
, "%s: wel - %d\n", __func__
, xfer
);
204 if ((xfer
= i2c_master_send(client
, rwel
, 3)) != 3) {
205 dev_err(&client
->dev
, "%s: rwel - %d\n", __func__
, xfer
);
209 xfer
= i2c_master_send(client
, rdata
, sizeof(rdata
));
210 if (xfer
!= sizeof(rdata
)) {
211 dev_err(&client
->dev
,
212 "%s: result=%d addr=%02x, data=%02x\n",
214 xfer
, rdata
[1], rdata
[2]);
218 /* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
219 if (reg_base
< X1205_CCR_BASE
) {
220 unsigned char al0e
[3] = { 0, X1205_REG_INT
, 0 };
224 /* ...and set or clear the AL0E bit in the INT register */
226 /* Need to set RWEL again as the write has cleared it */
227 xfer
= i2c_master_send(client
, rwel
, 3);
229 dev_err(&client
->dev
,
230 "%s: aloe rwel - %d\n",
237 al0e
[2] = X1205_INT_AL0E
;
239 xfer
= i2c_master_send(client
, al0e
, 3);
241 dev_err(&client
->dev
,
248 /* and wait 10msec again for this write to complete */
252 /* disable further writes */
253 if ((xfer
= i2c_master_send(client
, diswe
, 3)) != 3) {
254 dev_err(&client
->dev
, "%s: diswe - %d\n", __func__
, xfer
);
261 static int x1205_fix_osc(struct i2c_client
*client
)
266 memset(&tm
, 0, sizeof(tm
));
268 err
= x1205_set_datetime(client
, &tm
, X1205_CCR_BASE
, 0);
270 dev_err(&client
->dev
, "unable to restart the oscillator\n");
275 static int x1205_get_dtrim(struct i2c_client
*client
, int *trim
)
278 static unsigned char dtr_addr
[2] = { 0, X1205_REG_DTR
};
280 struct i2c_msg msgs
[] = {
281 { client
->addr
, 0, 2, dtr_addr
}, /* setup read ptr */
282 { client
->addr
, I2C_M_RD
, 1, &dtr
}, /* read dtr */
285 /* read dtr register */
286 if (i2c_transfer(client
->adapter
, &msgs
[0], 2) != 2) {
287 dev_err(&client
->dev
, "%s: read error\n", __func__
);
291 dev_dbg(&client
->dev
, "%s: raw dtr=%x\n", __func__
, dtr
);
295 if (dtr
& X1205_DTR_DTR0
)
298 if (dtr
& X1205_DTR_DTR1
)
301 if (dtr
& X1205_DTR_DTR2
)
307 static int x1205_get_atrim(struct i2c_client
*client
, int *trim
)
310 static unsigned char atr_addr
[2] = { 0, X1205_REG_ATR
};
312 struct i2c_msg msgs
[] = {
313 { client
->addr
, 0, 2, atr_addr
}, /* setup read ptr */
314 { client
->addr
, I2C_M_RD
, 1, &atr
}, /* read atr */
317 /* read atr register */
318 if (i2c_transfer(client
->adapter
, &msgs
[0], 2) != 2) {
319 dev_err(&client
->dev
, "%s: read error\n", __func__
);
323 dev_dbg(&client
->dev
, "%s: raw atr=%x\n", __func__
, atr
);
325 /* atr is a two's complement value on 6 bits,
326 * perform sign extension. The formula is
327 * Catr = (atr * 0.25pF) + 11.00pF.
332 dev_dbg(&client
->dev
, "%s: raw atr=%x (%d)\n", __func__
, atr
, atr
);
334 *trim
= (atr
* 250) + 11000;
336 dev_dbg(&client
->dev
, "%s: real=%d\n", __func__
, *trim
);
343 unsigned char reg
, mask
, min
, max
;
346 static int x1205_validate_client(struct i2c_client
*client
)
350 /* Probe array. We will read the register at the specified
351 * address and check if the given bits are zero.
353 static const unsigned char probe_zero_pattern
[] = {
362 static const struct x1205_limit probe_limits_pattern
[] = {
363 /* register, mask, min, max */
364 { X1205_REG_Y2K
, 0xFF, 19, 20 },
365 { X1205_REG_DW
, 0xFF, 0, 6 },
366 { X1205_REG_YR
, 0xFF, 0, 99 },
367 { X1205_REG_MO
, 0xFF, 0, 12 },
368 { X1205_REG_DT
, 0xFF, 0, 31 },
369 { X1205_REG_HR
, 0x7F, 0, 23 },
370 { X1205_REG_MN
, 0xFF, 0, 59 },
371 { X1205_REG_SC
, 0xFF, 0, 59 },
372 { X1205_REG_Y2K1
, 0xFF, 19, 20 },
373 { X1205_REG_Y2K0
, 0xFF, 19, 20 },
376 /* check that registers have bits a 0 where expected */
377 for (i
= 0; i
< ARRAY_SIZE(probe_zero_pattern
); i
+= 2) {
380 unsigned char addr
[2] = { 0, probe_zero_pattern
[i
] };
382 struct i2c_msg msgs
[2] = {
383 { client
->addr
, 0, 2, addr
},
384 { client
->addr
, I2C_M_RD
, 1, &buf
},
387 if ((xfer
= i2c_transfer(client
->adapter
, msgs
, 2)) != 2) {
388 dev_err(&client
->dev
,
389 "%s: could not read register %x\n",
390 __func__
, probe_zero_pattern
[i
]);
395 if ((buf
& probe_zero_pattern
[i
+1]) != 0) {
396 dev_err(&client
->dev
,
397 "%s: register=%02x, zero pattern=%d, value=%x\n",
398 __func__
, probe_zero_pattern
[i
], i
, buf
);
404 /* check limits (only registers with bcd values) */
405 for (i
= 0; i
< ARRAY_SIZE(probe_limits_pattern
); i
++) {
406 unsigned char reg
, value
;
408 unsigned char addr
[2] = { 0, probe_limits_pattern
[i
].reg
};
410 struct i2c_msg msgs
[2] = {
411 { client
->addr
, 0, 2, addr
},
412 { client
->addr
, I2C_M_RD
, 1, ®
},
415 if ((xfer
= i2c_transfer(client
->adapter
, msgs
, 2)) != 2) {
416 dev_err(&client
->dev
,
417 "%s: could not read register %x\n",
418 __func__
, probe_limits_pattern
[i
].reg
);
423 value
= bcd2bin(reg
& probe_limits_pattern
[i
].mask
);
425 if (value
> probe_limits_pattern
[i
].max
||
426 value
< probe_limits_pattern
[i
].min
) {
427 dev_dbg(&client
->dev
,
428 "%s: register=%x, lim pattern=%d, value=%d\n",
429 __func__
, probe_limits_pattern
[i
].reg
,
439 static int x1205_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
442 unsigned char intreg
, status
;
443 static unsigned char int_addr
[2] = { 0, X1205_REG_INT
};
444 struct i2c_client
*client
= to_i2c_client(dev
);
445 struct i2c_msg msgs
[] = {
446 { client
->addr
, 0, 2, int_addr
}, /* setup read ptr */
447 { client
->addr
, I2C_M_RD
, 1, &intreg
}, /* read INT register */
450 /* read interrupt register and status register */
451 if (i2c_transfer(client
->adapter
, &msgs
[0], 2) != 2) {
452 dev_err(&client
->dev
, "%s: read error\n", __func__
);
455 err
= x1205_get_status(client
, &status
);
457 alrm
->pending
= (status
& X1205_SR_AL0
) ? 1 : 0;
458 alrm
->enabled
= (intreg
& X1205_INT_AL0E
) ? 1 : 0;
459 err
= x1205_get_datetime(client
, &alrm
->time
, X1205_ALM0_BASE
);
464 static int x1205_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
466 return x1205_set_datetime(to_i2c_client(dev
),
467 &alrm
->time
, X1205_ALM0_BASE
, alrm
->enabled
);
470 static int x1205_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
472 return x1205_get_datetime(to_i2c_client(dev
),
476 static int x1205_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
478 return x1205_set_datetime(to_i2c_client(dev
),
479 tm
, X1205_CCR_BASE
, 0);
482 static int x1205_rtc_proc(struct device
*dev
, struct seq_file
*seq
)
484 int err
, dtrim
, atrim
;
486 if ((err
= x1205_get_dtrim(to_i2c_client(dev
), &dtrim
)) == 0)
487 seq_printf(seq
, "digital_trim\t: %d ppm\n", dtrim
);
489 if ((err
= x1205_get_atrim(to_i2c_client(dev
), &atrim
)) == 0)
490 seq_printf(seq
, "analog_trim\t: %d.%02d pF\n",
491 atrim
/ 1000, atrim
% 1000);
495 static const struct rtc_class_ops x1205_rtc_ops
= {
496 .proc
= x1205_rtc_proc
,
497 .read_time
= x1205_rtc_read_time
,
498 .set_time
= x1205_rtc_set_time
,
499 .read_alarm
= x1205_rtc_read_alarm
,
500 .set_alarm
= x1205_rtc_set_alarm
,
503 static ssize_t
x1205_sysfs_show_atrim(struct device
*dev
,
504 struct device_attribute
*attr
, char *buf
)
508 err
= x1205_get_atrim(to_i2c_client(dev
), &atrim
);
512 return sprintf(buf
, "%d.%02d pF\n", atrim
/ 1000, atrim
% 1000);
514 static DEVICE_ATTR(atrim
, S_IRUGO
, x1205_sysfs_show_atrim
, NULL
);
516 static ssize_t
x1205_sysfs_show_dtrim(struct device
*dev
,
517 struct device_attribute
*attr
, char *buf
)
521 err
= x1205_get_dtrim(to_i2c_client(dev
), &dtrim
);
525 return sprintf(buf
, "%d ppm\n", dtrim
);
527 static DEVICE_ATTR(dtrim
, S_IRUGO
, x1205_sysfs_show_dtrim
, NULL
);
529 static int x1205_sysfs_register(struct device
*dev
)
533 err
= device_create_file(dev
, &dev_attr_atrim
);
537 err
= device_create_file(dev
, &dev_attr_dtrim
);
539 device_remove_file(dev
, &dev_attr_atrim
);
544 static void x1205_sysfs_unregister(struct device
*dev
)
546 device_remove_file(dev
, &dev_attr_atrim
);
547 device_remove_file(dev
, &dev_attr_dtrim
);
551 static int x1205_probe(struct i2c_client
*client
,
552 const struct i2c_device_id
*id
)
556 struct rtc_device
*rtc
;
558 dev_dbg(&client
->dev
, "%s\n", __func__
);
560 if (!i2c_check_functionality(client
->adapter
, I2C_FUNC_I2C
))
563 if (x1205_validate_client(client
) < 0)
566 dev_info(&client
->dev
, "chip found, driver version " DRV_VERSION
"\n");
568 rtc
= rtc_device_register(x1205_driver
.driver
.name
, &client
->dev
,
569 &x1205_rtc_ops
, THIS_MODULE
);
574 i2c_set_clientdata(client
, rtc
);
576 /* Check for power failures and eventually enable the osc */
577 if ((err
= x1205_get_status(client
, &sr
)) == 0) {
578 if (sr
& X1205_SR_RTCF
) {
579 dev_err(&client
->dev
,
580 "power failure detected, "
581 "please set the clock\n");
583 x1205_fix_osc(client
);
587 dev_err(&client
->dev
, "couldn't read status\n");
589 err
= x1205_sysfs_register(&client
->dev
);
596 rtc_device_unregister(rtc
);
601 static int x1205_remove(struct i2c_client
*client
)
603 struct rtc_device
*rtc
= i2c_get_clientdata(client
);
605 rtc_device_unregister(rtc
);
606 x1205_sysfs_unregister(&client
->dev
);
610 static const struct i2c_device_id x1205_id
[] = {
614 MODULE_DEVICE_TABLE(i2c
, x1205_id
);
616 static struct i2c_driver x1205_driver
= {
620 .probe
= x1205_probe
,
621 .remove
= x1205_remove
,
622 .id_table
= x1205_id
,
625 static int __init
x1205_init(void)
627 return i2c_add_driver(&x1205_driver
);
630 static void __exit
x1205_exit(void)
632 i2c_del_driver(&x1205_driver
);
636 "Karen Spearel <kas111 at gmail dot com>, "
637 "Alessandro Zummo <a.zummo@towertech.it>");
638 MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
639 MODULE_LICENSE("GPL");
640 MODULE_VERSION(DRV_VERSION
);
642 module_init(x1205_init
);
643 module_exit(x1205_exit
);