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dm: calculate queue limits during resume not load
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / pci / hotplug / pciehp_hpc.c
blob07bd321511463653ebe0005ebdf000efd083fe4c
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
45 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
46 {
47 struct pci_dev *dev = ctrl->pci_dev;
48 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
49 }
50
51 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
52 {
53 struct pci_dev *dev = ctrl->pci_dev;
54 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
55 }
56
57 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
58 {
59 struct pci_dev *dev = ctrl->pci_dev;
60 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
61 }
62
63 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
64 {
65 struct pci_dev *dev = ctrl->pci_dev;
66 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
67 }
68
69 /* Power Control Command */
70 #define POWER_ON 0
71 #define POWER_OFF PCI_EXP_SLTCTL_PCC
72
73 static irqreturn_t pcie_isr(int irq, void *dev_id);
74 static void start_int_poll_timer(struct controller *ctrl, int sec);
75
76 /* This is the interrupt polling timeout function. */
77 static void int_poll_timeout(unsigned long data)
78 {
79 struct controller *ctrl = (struct controller *)data;
80
81 /* Poll for interrupt events. regs == NULL => polling */
82 pcie_isr(0, ctrl);
83
84 init_timer(&ctrl->poll_timer);
85 if (!pciehp_poll_time)
86 pciehp_poll_time = 2; /* default polling interval is 2 sec */
87
88 start_int_poll_timer(ctrl, pciehp_poll_time);
89 }
90
91 /* This function starts the interrupt polling timer. */
92 static void start_int_poll_timer(struct controller *ctrl, int sec)
93 {
94 /* Clamp to sane value */
95 if ((sec <= 0) || (sec > 60))
96 sec = 2;
97
98 ctrl->poll_timer.function = &int_poll_timeout;
99 ctrl->poll_timer.data = (unsigned long)ctrl;
100 ctrl->poll_timer.expires = jiffies + sec * HZ;
101 add_timer(&ctrl->poll_timer);
102 }
103
104 static inline int pciehp_request_irq(struct controller *ctrl)
105 {
106 int retval, irq = ctrl->pcie->irq;
107
108 /* Install interrupt polling timer. Start with 10 sec delay */
109 if (pciehp_poll_mode) {
110 init_timer(&ctrl->poll_timer);
111 start_int_poll_timer(ctrl, 10);
112 return 0;
113 }
114
115 /* Installs the interrupt handler */
116 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
117 if (retval)
118 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
119 irq);
120 return retval;
121 }
122
123 static inline void pciehp_free_irq(struct controller *ctrl)
124 {
125 if (pciehp_poll_mode)
126 del_timer_sync(&ctrl->poll_timer);
127 else
128 free_irq(ctrl->pcie->irq, ctrl);
129 }
130
131 static int pcie_poll_cmd(struct controller *ctrl)
132 {
133 u16 slot_status;
134 int err, timeout = 1000;
135
136 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
137 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
138 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
139 return 1;
140 }
141 while (timeout > 0) {
142 msleep(10);
143 timeout -= 10;
144 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
145 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
146 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
147 return 1;
148 }
149 }
150 return 0; /* timeout */
151 }
152
153 static void pcie_wait_cmd(struct controller *ctrl, int poll)
154 {
155 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
156 unsigned long timeout = msecs_to_jiffies(msecs);
157 int rc;
158
159 if (poll)
160 rc = pcie_poll_cmd(ctrl);
161 else
162 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
163 if (!rc)
164 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
165 }
166
167 /**
168 * pcie_write_cmd - Issue controller command
169 * @ctrl: controller to which the command is issued
170 * @cmd: command value written to slot control register
171 * @mask: bitmask of slot control register to be modified
172 */
173 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
174 {
175 int retval = 0;
176 u16 slot_status;
177 u16 slot_ctrl;
178
179 mutex_lock(&ctrl->ctrl_lock);
180
181 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
182 if (retval) {
183 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
184 __func__);
185 goto out;
186 }
187
188 if (slot_status & PCI_EXP_SLTSTA_CC) {
189 if (!ctrl->no_cmd_complete) {
190 /*
191 * After 1 sec and CMD_COMPLETED still not set, just
192 * proceed forward to issue the next command according
193 * to spec. Just print out the error message.
194 */
195 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
196 } else if (!NO_CMD_CMPL(ctrl)) {
197 /*
198 * This controller semms to notify of command completed
199 * event even though it supports none of power
200 * controller, attention led, power led and EMI.
201 */
202 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
203 "wait for command completed event.\n");
204 ctrl->no_cmd_complete = 0;
205 } else {
206 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
207 "the controller is broken.\n");
208 }
209 }
210
211 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
212 if (retval) {
213 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
214 goto out;
215 }
216
217 slot_ctrl &= ~mask;
218 slot_ctrl |= (cmd & mask);
219 ctrl->cmd_busy = 1;
220 smp_mb();
221 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
222 if (retval)
223 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
224
225 /*
226 * Wait for command completion.
227 */
228 if (!retval && !ctrl->no_cmd_complete) {
229 int poll = 0;
230 /*
231 * if hotplug interrupt is not enabled or command
232 * completed interrupt is not enabled, we need to poll
233 * command completed event.
234 */
235 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
236 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
237 poll = 1;
238 pcie_wait_cmd(ctrl, poll);
239 }
240 out:
241 mutex_unlock(&ctrl->ctrl_lock);
242 return retval;
243 }
244
245 static inline int check_link_active(struct controller *ctrl)
246 {
247 u16 link_status;
248
249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
250 return 0;
251 return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
252 }
253
254 static void pcie_wait_link_active(struct controller *ctrl)
255 {
256 int timeout = 1000;
257
258 if (check_link_active(ctrl))
259 return;
260 while (timeout > 0) {
261 msleep(10);
262 timeout -= 10;
263 if (check_link_active(ctrl))
264 return;
265 }
266 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
267 }
268
269 static int hpc_check_lnk_status(struct controller *ctrl)
270 {
271 u16 lnk_status;
272 int retval = 0;
273
274 /*
275 * Data Link Layer Link Active Reporting must be capable for
276 * hot-plug capable downstream port. But old controller might
277 * not implement it. In this case, we wait for 1000 ms.
278 */
279 if (ctrl->link_active_reporting){
280 /* Wait for Data Link Layer Link Active bit to be set */
281 pcie_wait_link_active(ctrl);
282 /*
283 * We must wait for 100 ms after the Data Link Layer
284 * Link Active bit reads 1b before initiating a
285 * configuration access to the hot added device.
286 */
287 msleep(100);
288 } else
289 msleep(1000);
290
291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
292 if (retval) {
293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
294 return retval;
295 }
296
297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
298 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
300 ctrl_err(ctrl, "Link Training Error occurs \n");
301 retval = -1;
302 return retval;
303 }
304
305 return retval;
306 }
307
308 static int hpc_get_attention_status(struct slot *slot, u8 *status)
309 {
310 struct controller *ctrl = slot->ctrl;
311 u16 slot_ctrl;
312 u8 atten_led_state;
313 int retval = 0;
314
315 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
316 if (retval) {
317 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
318 return retval;
319 }
320
321 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
322 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
323
324 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
325
326 switch (atten_led_state) {
327 case 0:
328 *status = 0xFF; /* Reserved */
329 break;
330 case 1:
331 *status = 1; /* On */
332 break;
333 case 2:
334 *status = 2; /* Blink */
335 break;
336 case 3:
337 *status = 0; /* Off */
338 break;
339 default:
340 *status = 0xFF;
341 break;
342 }
343
344 return 0;
345 }
346
347 static int hpc_get_power_status(struct slot *slot, u8 *status)
348 {
349 struct controller *ctrl = slot->ctrl;
350 u16 slot_ctrl;
351 u8 pwr_state;
352 int retval = 0;
353
354 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
355 if (retval) {
356 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
357 return retval;
358 }
359 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
360 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
361
362 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
363
364 switch (pwr_state) {
365 case 0:
366 *status = 1;
367 break;
368 case 1:
369 *status = 0;
370 break;
371 default:
372 *status = 0xFF;
373 break;
374 }
375
376 return retval;
377 }
378
379 static int hpc_get_latch_status(struct slot *slot, u8 *status)
380 {
381 struct controller *ctrl = slot->ctrl;
382 u16 slot_status;
383 int retval;
384
385 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
386 if (retval) {
387 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
388 __func__);
389 return retval;
390 }
391 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
392 return 0;
393 }
394
395 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
396 {
397 struct controller *ctrl = slot->ctrl;
398 u16 slot_status;
399 int retval;
400
401 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
402 if (retval) {
403 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
404 __func__);
405 return retval;
406 }
407 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
408 return 0;
409 }
410
411 static int hpc_query_power_fault(struct slot *slot)
412 {
413 struct controller *ctrl = slot->ctrl;
414 u16 slot_status;
415 int retval;
416
417 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
418 if (retval) {
419 ctrl_err(ctrl, "Cannot check for power fault\n");
420 return retval;
421 }
422 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
423 }
424
425 static int hpc_get_emi_status(struct slot *slot, u8 *status)
426 {
427 struct controller *ctrl = slot->ctrl;
428 u16 slot_status;
429 int retval;
430
431 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
432 if (retval) {
433 ctrl_err(ctrl, "Cannot check EMI status\n");
434 return retval;
435 }
436 *status = !!(slot_status & PCI_EXP_SLTSTA_EIS);
437 return retval;
438 }
439
440 static int hpc_toggle_emi(struct slot *slot)
441 {
442 u16 slot_cmd;
443 u16 cmd_mask;
444 int rc;
445
446 slot_cmd = PCI_EXP_SLTCTL_EIC;
447 cmd_mask = PCI_EXP_SLTCTL_EIC;
448 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
449 slot->last_emi_toggle = get_seconds();
450
451 return rc;
452 }
453
454 static int hpc_set_attention_status(struct slot *slot, u8 value)
455 {
456 struct controller *ctrl = slot->ctrl;
457 u16 slot_cmd;
458 u16 cmd_mask;
459 int rc;
460
461 cmd_mask = PCI_EXP_SLTCTL_AIC;
462 switch (value) {
463 case 0 : /* turn off */
464 slot_cmd = 0x00C0;
465 break;
466 case 1: /* turn on */
467 slot_cmd = 0x0040;
468 break;
469 case 2: /* turn blink */
470 slot_cmd = 0x0080;
471 break;
472 default:
473 return -1;
474 }
475 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
476 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
477 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
478
479 return rc;
480 }
481
482 static void hpc_set_green_led_on(struct slot *slot)
483 {
484 struct controller *ctrl = slot->ctrl;
485 u16 slot_cmd;
486 u16 cmd_mask;
487
488 slot_cmd = 0x0100;
489 cmd_mask = PCI_EXP_SLTCTL_PIC;
490 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
491 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
492 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
493 }
494
495 static void hpc_set_green_led_off(struct slot *slot)
496 {
497 struct controller *ctrl = slot->ctrl;
498 u16 slot_cmd;
499 u16 cmd_mask;
500
501 slot_cmd = 0x0300;
502 cmd_mask = PCI_EXP_SLTCTL_PIC;
503 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
504 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
505 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
506 }
507
508 static void hpc_set_green_led_blink(struct slot *slot)
509 {
510 struct controller *ctrl = slot->ctrl;
511 u16 slot_cmd;
512 u16 cmd_mask;
513
514 slot_cmd = 0x0200;
515 cmd_mask = PCI_EXP_SLTCTL_PIC;
516 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
517 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
518 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
519 }
520
521 static int hpc_power_on_slot(struct slot * slot)
522 {
523 struct controller *ctrl = slot->ctrl;
524 u16 slot_cmd;
525 u16 cmd_mask;
526 u16 slot_status;
527 int retval = 0;
528
529 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
530
531 /* Clear sticky power-fault bit from previous power failures */
532 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
533 if (retval) {
534 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
535 __func__);
536 return retval;
537 }
538 slot_status &= PCI_EXP_SLTSTA_PFD;
539 if (slot_status) {
540 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
541 if (retval) {
542 ctrl_err(ctrl,
543 "%s: Cannot write to SLOTSTATUS register\n",
544 __func__);
545 return retval;
546 }
547 }
548
549 slot_cmd = POWER_ON;
550 cmd_mask = PCI_EXP_SLTCTL_PCC;
551 if (!pciehp_poll_mode) {
552 /* Enable power fault detection turned off at power off time */
553 slot_cmd |= PCI_EXP_SLTCTL_PFDE;
554 cmd_mask |= PCI_EXP_SLTCTL_PFDE;
555 }
556
557 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
558 if (retval) {
559 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
560 return retval;
561 }
562 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
563 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
564
565 ctrl->power_fault_detected = 0;
566 return retval;
567 }
568
569 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
570 {
571 struct pci_dev *dev = ctrl->pci_dev;
572 int pos;
573 u32 reg;
574
575 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
576 if (!pos)
577 return 0;
578 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
579 if (reg & PCI_ERR_COR_BAD_DLLP)
580 return 0;
581 reg |= PCI_ERR_COR_BAD_DLLP;
582 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
583 return 1;
584 }
585
586 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
587 {
588 struct pci_dev *dev = ctrl->pci_dev;
589 u32 reg;
590 int pos;
591
592 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
593 if (!pos)
594 return;
595 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
596 if (!(reg & PCI_ERR_COR_BAD_DLLP))
597 return;
598 reg &= ~PCI_ERR_COR_BAD_DLLP;
599 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
600 }
601
602 static int hpc_power_off_slot(struct slot * slot)
603 {
604 struct controller *ctrl = slot->ctrl;
605 u16 slot_cmd;
606 u16 cmd_mask;
607 int retval = 0;
608 int changed;
609
610 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
611
612 /*
613 * Set Bad DLLP Mask bit in Correctable Error Mask
614 * Register. This is the workaround against Bad DLLP error
615 * that sometimes happens during turning power off the slot
616 * which conforms to PCI Express 1.0a spec.
617 */
618 changed = pcie_mask_bad_dllp(ctrl);
619
620 slot_cmd = POWER_OFF;
621 cmd_mask = PCI_EXP_SLTCTL_PCC;
622 if (!pciehp_poll_mode) {
623 /* Disable power fault detection */
624 slot_cmd &= ~PCI_EXP_SLTCTL_PFDE;
625 cmd_mask |= PCI_EXP_SLTCTL_PFDE;
626 }
627
628 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
629 if (retval) {
630 ctrl_err(ctrl, "Write command failed!\n");
631 retval = -1;
632 goto out;
633 }
634 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
635 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
636 out:
637 if (changed)
638 pcie_unmask_bad_dllp(ctrl);
639
640 return retval;
641 }
642
643 static irqreturn_t pcie_isr(int irq, void *dev_id)
644 {
645 struct controller *ctrl = (struct controller *)dev_id;
646 u16 detected, intr_loc;
647 struct slot *p_slot;
648
649 /*
650 * In order to guarantee that all interrupt events are
651 * serviced, we need to re-inspect Slot Status register after
652 * clearing what is presumed to be the last pending interrupt.
653 */
654 intr_loc = 0;
655 do {
656 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
657 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
658 __func__);
659 return IRQ_NONE;
660 }
661
662 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
663 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
664 PCI_EXP_SLTSTA_CC);
665 detected &= ~intr_loc;
666 intr_loc |= detected;
667 if (!intr_loc)
668 return IRQ_NONE;
669 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
670 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
671 __func__);
672 return IRQ_NONE;
673 }
674 } while (detected);
675
676 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
677
678 /* Check Command Complete Interrupt Pending */
679 if (intr_loc & PCI_EXP_SLTSTA_CC) {
680 ctrl->cmd_busy = 0;
681 smp_mb();
682 wake_up(&ctrl->queue);
683 }
684
685 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
686 return IRQ_HANDLED;
687
688 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
689
690 /* Check MRL Sensor Changed */
691 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
692 pciehp_handle_switch_change(p_slot);
693
694 /* Check Attention Button Pressed */
695 if (intr_loc & PCI_EXP_SLTSTA_ABP)
696 pciehp_handle_attention_button(p_slot);
697
698 /* Check Presence Detect Changed */
699 if (intr_loc & PCI_EXP_SLTSTA_PDC)
700 pciehp_handle_presence_change(p_slot);
701
702 /* Check Power Fault Detected */
703 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
704 ctrl->power_fault_detected = 1;
705 pciehp_handle_power_fault(p_slot);
706 }
707 return IRQ_HANDLED;
708 }
709
710 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
711 {
712 struct controller *ctrl = slot->ctrl;
713 enum pcie_link_speed lnk_speed;
714 u32 lnk_cap;
715 int retval = 0;
716
717 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
718 if (retval) {
719 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
720 return retval;
721 }
722
723 switch (lnk_cap & 0x000F) {
724 case 1:
725 lnk_speed = PCIE_2PT5GB;
726 break;
727 default:
728 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
729 break;
730 }
731
732 *value = lnk_speed;
733 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
734
735 return retval;
736 }
737
738 static int hpc_get_max_lnk_width(struct slot *slot,
739 enum pcie_link_width *value)
740 {
741 struct controller *ctrl = slot->ctrl;
742 enum pcie_link_width lnk_wdth;
743 u32 lnk_cap;
744 int retval = 0;
745
746 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
747 if (retval) {
748 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
749 return retval;
750 }
751
752 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
753 case 0:
754 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
755 break;
756 case 1:
757 lnk_wdth = PCIE_LNK_X1;
758 break;
759 case 2:
760 lnk_wdth = PCIE_LNK_X2;
761 break;
762 case 4:
763 lnk_wdth = PCIE_LNK_X4;
764 break;
765 case 8:
766 lnk_wdth = PCIE_LNK_X8;
767 break;
768 case 12:
769 lnk_wdth = PCIE_LNK_X12;
770 break;
771 case 16:
772 lnk_wdth = PCIE_LNK_X16;
773 break;
774 case 32:
775 lnk_wdth = PCIE_LNK_X32;
776 break;
777 default:
778 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
779 break;
780 }
781
782 *value = lnk_wdth;
783 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
784
785 return retval;
786 }
787
788 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
789 {
790 struct controller *ctrl = slot->ctrl;
791 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
792 int retval = 0;
793 u16 lnk_status;
794
795 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
796 if (retval) {
797 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
798 __func__);
799 return retval;
800 }
801
802 switch (lnk_status & PCI_EXP_LNKSTA_CLS) {
803 case 1:
804 lnk_speed = PCIE_2PT5GB;
805 break;
806 default:
807 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
808 break;
809 }
810
811 *value = lnk_speed;
812 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
813
814 return retval;
815 }
816
817 static int hpc_get_cur_lnk_width(struct slot *slot,
818 enum pcie_link_width *value)
819 {
820 struct controller *ctrl = slot->ctrl;
821 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
822 int retval = 0;
823 u16 lnk_status;
824
825 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
826 if (retval) {
827 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
828 __func__);
829 return retval;
830 }
831
832 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
833 case 0:
834 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
835 break;
836 case 1:
837 lnk_wdth = PCIE_LNK_X1;
838 break;
839 case 2:
840 lnk_wdth = PCIE_LNK_X2;
841 break;
842 case 4:
843 lnk_wdth = PCIE_LNK_X4;
844 break;
845 case 8:
846 lnk_wdth = PCIE_LNK_X8;
847 break;
848 case 12:
849 lnk_wdth = PCIE_LNK_X12;
850 break;
851 case 16:
852 lnk_wdth = PCIE_LNK_X16;
853 break;
854 case 32:
855 lnk_wdth = PCIE_LNK_X32;
856 break;
857 default:
858 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
859 break;
860 }
861
862 *value = lnk_wdth;
863 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
864
865 return retval;
866 }
867
868 static void pcie_release_ctrl(struct controller *ctrl);
869 static struct hpc_ops pciehp_hpc_ops = {
870 .power_on_slot = hpc_power_on_slot,
871 .power_off_slot = hpc_power_off_slot,
872 .set_attention_status = hpc_set_attention_status,
873 .get_power_status = hpc_get_power_status,
874 .get_attention_status = hpc_get_attention_status,
875 .get_latch_status = hpc_get_latch_status,
876 .get_adapter_status = hpc_get_adapter_status,
877 .get_emi_status = hpc_get_emi_status,
878 .toggle_emi = hpc_toggle_emi,
879
880 .get_max_bus_speed = hpc_get_max_lnk_speed,
881 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
882 .get_max_lnk_width = hpc_get_max_lnk_width,
883 .get_cur_lnk_width = hpc_get_cur_lnk_width,
884
885 .query_power_fault = hpc_query_power_fault,
886 .green_led_on = hpc_set_green_led_on,
887 .green_led_off = hpc_set_green_led_off,
888 .green_led_blink = hpc_set_green_led_blink,
889
890 .release_ctlr = pcie_release_ctrl,
891 .check_lnk_status = hpc_check_lnk_status,
892 };
893
894 int pcie_enable_notification(struct controller *ctrl)
895 {
896 u16 cmd, mask;
897
898 cmd = PCI_EXP_SLTCTL_PDCE;
899 if (ATTN_BUTTN(ctrl))
900 cmd |= PCI_EXP_SLTCTL_ABPE;
901 if (POWER_CTRL(ctrl))
902 cmd |= PCI_EXP_SLTCTL_PFDE;
903 if (MRL_SENS(ctrl))
904 cmd |= PCI_EXP_SLTCTL_MRLSCE;
905 if (!pciehp_poll_mode)
906 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
907
908 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
909 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
910 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
911
912 if (pcie_write_cmd(ctrl, cmd, mask)) {
913 ctrl_err(ctrl, "Cannot enable software notification\n");
914 return -1;
915 }
916 return 0;
917 }
918
919 static void pcie_disable_notification(struct controller *ctrl)
920 {
921 u16 mask;
922 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
923 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
924 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
925 if (pcie_write_cmd(ctrl, 0, mask))
926 ctrl_warn(ctrl, "Cannot disable software notification\n");
927 }
928
929 int pcie_init_notification(struct controller *ctrl)
930 {
931 if (pciehp_request_irq(ctrl))
932 return -1;
933 if (pcie_enable_notification(ctrl)) {
934 pciehp_free_irq(ctrl);
935 return -1;
936 }
937 ctrl->notification_enabled = 1;
938 return 0;
939 }
940
941 static void pcie_shutdown_notification(struct controller *ctrl)
942 {
943 if (ctrl->notification_enabled) {
944 pcie_disable_notification(ctrl);
945 pciehp_free_irq(ctrl);
946 ctrl->notification_enabled = 0;
947 }
948 }
949
950 static int pcie_init_slot(struct controller *ctrl)
951 {
952 struct slot *slot;
953
954 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
955 if (!slot)
956 return -ENOMEM;
957
958 slot->hp_slot = 0;
959 slot->ctrl = ctrl;
960 slot->bus = ctrl->pci_dev->subordinate->number;
961 slot->device = ctrl->slot_device_offset + slot->hp_slot;
962 slot->hpc_ops = ctrl->hpc_ops;
963 slot->number = ctrl->first_slot;
964 mutex_init(&slot->lock);
965 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
966 list_add(&slot->slot_list, &ctrl->slot_list);
967 return 0;
968 }
969
970 static void pcie_cleanup_slot(struct controller *ctrl)
971 {
972 struct slot *slot;
973 slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list);
974 list_del(&slot->slot_list);
975 cancel_delayed_work(&slot->work);
976 flush_scheduled_work();
977 flush_workqueue(pciehp_wq);
978 kfree(slot);
979 }
980
981 static inline void dbg_ctrl(struct controller *ctrl)
982 {
983 int i;
984 u16 reg16;
985 struct pci_dev *pdev = ctrl->pci_dev;
986
987 if (!pciehp_debug)
988 return;
989
990 ctrl_info(ctrl, "Hotplug Controller:\n");
991 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
992 pci_name(pdev), pdev->irq);
993 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
994 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
995 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
996 pdev->subsystem_device);
997 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
998 pdev->subsystem_vendor);
999 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
1000 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1001 if (!pci_resource_len(pdev, i))
1002 continue;
1003 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n",
1004 i, (unsigned long long)pci_resource_len(pdev, i),
1005 (unsigned long long)pci_resource_start(pdev, i));
1006 }
1007 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
1008 ctrl_info(ctrl, " Physical Slot Number : %d\n", ctrl->first_slot);
1009 ctrl_info(ctrl, " Attention Button : %3s\n",
1010 ATTN_BUTTN(ctrl) ? "yes" : "no");
1011 ctrl_info(ctrl, " Power Controller : %3s\n",
1012 POWER_CTRL(ctrl) ? "yes" : "no");
1013 ctrl_info(ctrl, " MRL Sensor : %3s\n",
1014 MRL_SENS(ctrl) ? "yes" : "no");
1015 ctrl_info(ctrl, " Attention Indicator : %3s\n",
1016 ATTN_LED(ctrl) ? "yes" : "no");
1017 ctrl_info(ctrl, " Power Indicator : %3s\n",
1018 PWR_LED(ctrl) ? "yes" : "no");
1019 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
1020 HP_SUPR_RM(ctrl) ? "yes" : "no");
1021 ctrl_info(ctrl, " EMI Present : %3s\n",
1022 EMI(ctrl) ? "yes" : "no");
1023 ctrl_info(ctrl, " Command Completed : %3s\n",
1024 NO_CMD_CMPL(ctrl) ? "no" : "yes");
1025 pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
1026 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
1027 pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
1028 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
1029 }
1030
1031 struct controller *pcie_init(struct pcie_device *dev)
1032 {
1033 struct controller *ctrl;
1034 u32 slot_cap, link_cap;
1035 struct pci_dev *pdev = dev->port;
1036
1037 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1038 if (!ctrl) {
1039 dev_err(&dev->device, "%s: Out of memory\n", __func__);
1040 goto abort;
1041 }
1042 INIT_LIST_HEAD(&ctrl->slot_list);
1043
1044 ctrl->pcie = dev;
1045 ctrl->pci_dev = pdev;
1046 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1047 if (!ctrl->cap_base) {
1048 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
1049 goto abort_ctrl;
1050 }
1051 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
1052 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
1053 goto abort_ctrl;
1054 }
1055
1056 ctrl->slot_cap = slot_cap;
1057 ctrl->first_slot = slot_cap >> 19;
1058 ctrl->slot_device_offset = 0;
1059 ctrl->num_slots = 1;
1060 ctrl->hpc_ops = &pciehp_hpc_ops;
1061 mutex_init(&ctrl->crit_sect);
1062 mutex_init(&ctrl->ctrl_lock);
1063 init_waitqueue_head(&ctrl->queue);
1064 dbg_ctrl(ctrl);
1065 /*
1066 * Controller doesn't notify of command completion if the "No
1067 * Command Completed Support" bit is set in Slot Capability
1068 * register or the controller supports none of power
1069 * controller, attention led, power led and EMI.
1070 */
1071 if (NO_CMD_CMPL(ctrl) ||
1072 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1073 ctrl->no_cmd_complete = 1;
1074
1075 /* Check if Data Link Layer Link Active Reporting is implemented */
1076 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
1077 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1078 goto abort_ctrl;
1079 }
1080 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
1081 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
1082 ctrl->link_active_reporting = 1;
1083 }
1084
1085 /* Clear all remaining event bits in Slot Status register */
1086 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
1087 goto abort_ctrl;
1088
1089 /* Disable sotfware notification */
1090 pcie_disable_notification(ctrl);
1091
1092 /*
1093 * If this is the first controller to be initialized,
1094 * initialize the pciehp work queue
1095 */
1096 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1097 pciehp_wq = create_singlethread_workqueue("pciehpd");
1098 if (!pciehp_wq)
1099 goto abort_ctrl;
1100 }
1101
1102 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1103 pdev->vendor, pdev->device, pdev->subsystem_vendor,
1104 pdev->subsystem_device);
1105
1106 if (pcie_init_slot(ctrl))
1107 goto abort_ctrl;
1108
1109 return ctrl;
1110
1111 abort_ctrl:
1112 kfree(ctrl);
1113 abort:
1114 return NULL;
1115 }
1116
1117 void pcie_release_ctrl(struct controller *ctrl)
1118 {
1119 pcie_shutdown_notification(ctrl);
1120 pcie_cleanup_slot(ctrl);
1121 /*
1122 * If this is the last controller to be released, destroy the
1123 * pciehp work queue
1124 */
1125 if (atomic_dec_and_test(&pciehp_num_controllers))
1126 destroy_workqueue(pciehp_wq);
1127 kfree(ctrl);
1128 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree