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i2c-bfin-twi: Add missing pin mux operation
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / i2c / busses / i2c-bfin-twi.c
blob446b4f855b034826cdf3b4026a4f88af7748842d
1 /*
2 * drivers/i2c/busses/i2c-bfin-twi.c
3 *
4 * Description: Driver for Blackfin Two Wire Interface
5 *
6 * Author: sonicz <sonic.zhang@analog.com>
7 *
8 * Copyright (c) 2005-2007 Analog Devices, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/i2c.h>
29 #include <linux/mm.h>
30 #include <linux/timer.h>
31 #include <linux/spinlock.h>
32 #include <linux/completion.h>
33 #include <linux/interrupt.h>
34 #include <linux/platform_device.h>
35
36 #include <asm/blackfin.h>
37 #include <asm/portmux.h>
38 #include <asm/irq.h>
39
40 #define POLL_TIMEOUT (2 * HZ)
41
42 /* SMBus mode*/
43 #define TWI_I2C_MODE_STANDARD 1
44 #define TWI_I2C_MODE_STANDARDSUB 2
45 #define TWI_I2C_MODE_COMBINED 3
46 #define TWI_I2C_MODE_REPEAT 4
47
48 struct bfin_twi_iface {
49 int irq;
50 spinlock_t lock;
51 char read_write;
52 u8 command;
53 u8 *transPtr;
54 int readNum;
55 int writeNum;
56 int cur_mode;
57 int manual_stop;
58 int result;
59 int timeout_count;
60 struct timer_list timeout_timer;
61 struct i2c_adapter adap;
62 struct completion complete;
63 struct i2c_msg *pmsg;
64 int msg_num;
65 int cur_msg;
66 void __iomem *regs_base;
67 };
68
69
70 #define DEFINE_TWI_REG(reg, off) \
71 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
72 { return bfin_read16(iface->regs_base + (off)); } \
73 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
74 { bfin_write16(iface->regs_base + (off), v); }
75
76 DEFINE_TWI_REG(CLKDIV, 0x00)
77 DEFINE_TWI_REG(CONTROL, 0x04)
78 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
79 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
80 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
81 DEFINE_TWI_REG(MASTER_CTL, 0x14)
82 DEFINE_TWI_REG(MASTER_STAT, 0x18)
83 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
84 DEFINE_TWI_REG(INT_STAT, 0x20)
85 DEFINE_TWI_REG(INT_MASK, 0x24)
86 DEFINE_TWI_REG(FIFO_CTL, 0x28)
87 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
88 DEFINE_TWI_REG(XMT_DATA8, 0x80)
89 DEFINE_TWI_REG(XMT_DATA16, 0x84)
90 DEFINE_TWI_REG(RCV_DATA8, 0x88)
91 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
92
93 static const u16 pin_req[2][3] = {
94 {P_TWI0_SCL, P_TWI0_SDA, 0},
95 {P_TWI1_SCL, P_TWI1_SDA, 0},
96 };
97
98 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
99 {
100 unsigned short twi_int_status = read_INT_STAT(iface);
101 unsigned short mast_stat = read_MASTER_STAT(iface);
102
103 if (twi_int_status & XMTSERV) {
104 /* Transmit next data */
105 if (iface->writeNum > 0) {
106 write_XMT_DATA8(iface, *(iface->transPtr++));
107 iface->writeNum--;
108 }
109 /* start receive immediately after complete sending in
110 * combine mode.
111 */
112 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
113 write_MASTER_CTL(iface,
114 read_MASTER_CTL(iface) | MDIR | RSTART);
115 else if (iface->manual_stop)
116 write_MASTER_CTL(iface,
117 read_MASTER_CTL(iface) | STOP);
118 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
119 iface->cur_msg+1 < iface->msg_num)
120 write_MASTER_CTL(iface,
121 read_MASTER_CTL(iface) | RSTART);
122 SSYNC();
123 /* Clear status */
124 write_INT_STAT(iface, XMTSERV);
125 SSYNC();
126 }
127 if (twi_int_status & RCVSERV) {
128 if (iface->readNum > 0) {
129 /* Receive next data */
130 *(iface->transPtr) = read_RCV_DATA8(iface);
131 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
132 /* Change combine mode into sub mode after
133 * read first data.
134 */
135 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
136 /* Get read number from first byte in block
137 * combine mode.
138 */
139 if (iface->readNum == 1 && iface->manual_stop)
140 iface->readNum = *iface->transPtr + 1;
141 }
142 iface->transPtr++;
143 iface->readNum--;
144 } else if (iface->manual_stop) {
145 write_MASTER_CTL(iface,
146 read_MASTER_CTL(iface) | STOP);
147 SSYNC();
148 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
149 iface->cur_msg+1 < iface->msg_num) {
150 write_MASTER_CTL(iface,
151 read_MASTER_CTL(iface) | RSTART);
152 SSYNC();
153 }
154 /* Clear interrupt source */
155 write_INT_STAT(iface, RCVSERV);
156 SSYNC();
157 }
158 if (twi_int_status & MERR) {
159 write_INT_STAT(iface, MERR);
160 write_INT_MASK(iface, 0);
161 write_MASTER_STAT(iface, 0x3e);
162 write_MASTER_CTL(iface, 0);
163 SSYNC();
164 iface->result = -EIO;
165 /* if both err and complete int stats are set, return proper
166 * results.
167 */
168 if (twi_int_status & MCOMP) {
169 write_INT_STAT(iface, MCOMP);
170 write_INT_MASK(iface, 0);
171 write_MASTER_CTL(iface, 0);
172 SSYNC();
173 /* If it is a quick transfer, only address bug no data,
174 * not an err, return 1.
175 */
176 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
177 iface->result = 1;
178 /* If address not acknowledged return -1,
179 * else return 0.
180 */
181 else if (!(mast_stat & ANAK))
182 iface->result = 0;
183 }
184 complete(&iface->complete);
185 return;
186 }
187 if (twi_int_status & MCOMP) {
188 write_INT_STAT(iface, MCOMP);
189 SSYNC();
190 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
191 if (iface->readNum == 0) {
192 /* set the read number to 1 and ask for manual
193 * stop in block combine mode
194 */
195 iface->readNum = 1;
196 iface->manual_stop = 1;
197 write_MASTER_CTL(iface,
198 read_MASTER_CTL(iface) | (0xff << 6));
199 } else {
200 /* set the readd number in other
201 * combine mode.
202 */
203 write_MASTER_CTL(iface,
204 (read_MASTER_CTL(iface) &
205 (~(0xff << 6))) |
206 (iface->readNum << 6));
207 }
208 /* remove restart bit and enable master receive */
209 write_MASTER_CTL(iface,
210 read_MASTER_CTL(iface) & ~RSTART);
211 write_MASTER_CTL(iface,
212 read_MASTER_CTL(iface) | MEN | MDIR);
213 SSYNC();
214 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
215 iface->cur_msg+1 < iface->msg_num) {
216 iface->cur_msg++;
217 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
218 iface->writeNum = iface->readNum =
219 iface->pmsg[iface->cur_msg].len;
220 /* Set Transmit device address */
221 write_MASTER_ADDR(iface,
222 iface->pmsg[iface->cur_msg].addr);
223 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
224 iface->read_write = I2C_SMBUS_READ;
225 else {
226 iface->read_write = I2C_SMBUS_WRITE;
227 /* Transmit first data */
228 if (iface->writeNum > 0) {
229 write_XMT_DATA8(iface,
230 *(iface->transPtr++));
231 iface->writeNum--;
232 SSYNC();
233 }
234 }
235
236 if (iface->pmsg[iface->cur_msg].len <= 255)
237 write_MASTER_CTL(iface,
238 iface->pmsg[iface->cur_msg].len << 6);
239 else {
240 write_MASTER_CTL(iface, 0xff << 6);
241 iface->manual_stop = 1;
242 }
243 /* remove restart bit and enable master receive */
244 write_MASTER_CTL(iface,
245 read_MASTER_CTL(iface) & ~RSTART);
246 write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
247 MEN | ((iface->read_write == I2C_SMBUS_READ) ?
248 MDIR : 0));
249 SSYNC();
250 } else {
251 iface->result = 1;
252 write_INT_MASK(iface, 0);
253 write_MASTER_CTL(iface, 0);
254 SSYNC();
255 complete(&iface->complete);
256 }
257 }
258 }
259
260 /* Interrupt handler */
261 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
262 {
263 struct bfin_twi_iface *iface = dev_id;
264 unsigned long flags;
265
266 spin_lock_irqsave(&iface->lock, flags);
267 del_timer(&iface->timeout_timer);
268 bfin_twi_handle_interrupt(iface);
269 spin_unlock_irqrestore(&iface->lock, flags);
270 return IRQ_HANDLED;
271 }
272
273 static void bfin_twi_timeout(unsigned long data)
274 {
275 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
276 unsigned long flags;
277
278 spin_lock_irqsave(&iface->lock, flags);
279 bfin_twi_handle_interrupt(iface);
280 if (iface->result == 0) {
281 iface->timeout_count--;
282 if (iface->timeout_count > 0) {
283 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
284 add_timer(&iface->timeout_timer);
285 } else {
286 iface->result = -1;
287 complete(&iface->complete);
288 }
289 }
290 spin_unlock_irqrestore(&iface->lock, flags);
291 }
292
293 /*
294 * Generic i2c master transfer entrypoint
295 */
296 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
297 struct i2c_msg *msgs, int num)
298 {
299 struct bfin_twi_iface *iface = adap->algo_data;
300 struct i2c_msg *pmsg;
301 int rc = 0;
302
303 if (!(read_CONTROL(iface) & TWI_ENA))
304 return -ENXIO;
305
306 while (read_MASTER_STAT(iface) & BUSBUSY)
307 yield();
308
309 iface->pmsg = msgs;
310 iface->msg_num = num;
311 iface->cur_msg = 0;
312
313 pmsg = &msgs[0];
314 if (pmsg->flags & I2C_M_TEN) {
315 dev_err(&adap->dev, "10 bits addr not supported!\n");
316 return -EINVAL;
317 }
318
319 iface->cur_mode = TWI_I2C_MODE_REPEAT;
320 iface->manual_stop = 0;
321 iface->transPtr = pmsg->buf;
322 iface->writeNum = iface->readNum = pmsg->len;
323 iface->result = 0;
324 iface->timeout_count = 10;
325 /* Set Transmit device address */
326 write_MASTER_ADDR(iface, pmsg->addr);
327
328 /* FIFO Initiation. Data in FIFO should be
329 * discarded before start a new operation.
330 */
331 write_FIFO_CTL(iface, 0x3);
332 SSYNC();
333 write_FIFO_CTL(iface, 0);
334 SSYNC();
335
336 if (pmsg->flags & I2C_M_RD)
337 iface->read_write = I2C_SMBUS_READ;
338 else {
339 iface->read_write = I2C_SMBUS_WRITE;
340 /* Transmit first data */
341 if (iface->writeNum > 0) {
342 write_XMT_DATA8(iface, *(iface->transPtr++));
343 iface->writeNum--;
344 SSYNC();
345 }
346 }
347
348 /* clear int stat */
349 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
350
351 /* Interrupt mask . Enable XMT, RCV interrupt */
352 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
353 SSYNC();
354
355 if (pmsg->len <= 255)
356 write_MASTER_CTL(iface, pmsg->len << 6);
357 else {
358 write_MASTER_CTL(iface, 0xff << 6);
359 iface->manual_stop = 1;
360 }
361
362 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
363 add_timer(&iface->timeout_timer);
364
365 /* Master enable */
366 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
367 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
368 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
369 SSYNC();
370
371 wait_for_completion(&iface->complete);
372
373 rc = iface->result;
374
375 if (rc == 1)
376 return num;
377 else
378 return rc;
379 }
380
381 /*
382 * SMBus type transfer entrypoint
383 */
384
385 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
386 unsigned short flags, char read_write,
387 u8 command, int size, union i2c_smbus_data *data)
388 {
389 struct bfin_twi_iface *iface = adap->algo_data;
390 int rc = 0;
391
392 if (!(read_CONTROL(iface) & TWI_ENA))
393 return -ENXIO;
394
395 while (read_MASTER_STAT(iface) & BUSBUSY)
396 yield();
397
398 iface->writeNum = 0;
399 iface->readNum = 0;
400
401 /* Prepare datas & select mode */
402 switch (size) {
403 case I2C_SMBUS_QUICK:
404 iface->transPtr = NULL;
405 iface->cur_mode = TWI_I2C_MODE_STANDARD;
406 break;
407 case I2C_SMBUS_BYTE:
408 if (data == NULL)
409 iface->transPtr = NULL;
410 else {
411 if (read_write == I2C_SMBUS_READ)
412 iface->readNum = 1;
413 else
414 iface->writeNum = 1;
415 iface->transPtr = &data->byte;
416 }
417 iface->cur_mode = TWI_I2C_MODE_STANDARD;
418 break;
419 case I2C_SMBUS_BYTE_DATA:
420 if (read_write == I2C_SMBUS_READ) {
421 iface->readNum = 1;
422 iface->cur_mode = TWI_I2C_MODE_COMBINED;
423 } else {
424 iface->writeNum = 1;
425 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
426 }
427 iface->transPtr = &data->byte;
428 break;
429 case I2C_SMBUS_WORD_DATA:
430 if (read_write == I2C_SMBUS_READ) {
431 iface->readNum = 2;
432 iface->cur_mode = TWI_I2C_MODE_COMBINED;
433 } else {
434 iface->writeNum = 2;
435 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
436 }
437 iface->transPtr = (u8 *)&data->word;
438 break;
439 case I2C_SMBUS_PROC_CALL:
440 iface->writeNum = 2;
441 iface->readNum = 2;
442 iface->cur_mode = TWI_I2C_MODE_COMBINED;
443 iface->transPtr = (u8 *)&data->word;
444 break;
445 case I2C_SMBUS_BLOCK_DATA:
446 if (read_write == I2C_SMBUS_READ) {
447 iface->readNum = 0;
448 iface->cur_mode = TWI_I2C_MODE_COMBINED;
449 } else {
450 iface->writeNum = data->block[0] + 1;
451 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
452 }
453 iface->transPtr = data->block;
454 break;
455 default:
456 return -1;
457 }
458
459 iface->result = 0;
460 iface->manual_stop = 0;
461 iface->read_write = read_write;
462 iface->command = command;
463 iface->timeout_count = 10;
464
465 /* FIFO Initiation. Data in FIFO should be discarded before
466 * start a new operation.
467 */
468 write_FIFO_CTL(iface, 0x3);
469 SSYNC();
470 write_FIFO_CTL(iface, 0);
471
472 /* clear int stat */
473 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
474
475 /* Set Transmit device address */
476 write_MASTER_ADDR(iface, addr);
477 SSYNC();
478
479 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
480 add_timer(&iface->timeout_timer);
481
482 switch (iface->cur_mode) {
483 case TWI_I2C_MODE_STANDARDSUB:
484 write_XMT_DATA8(iface, iface->command);
485 write_INT_MASK(iface, MCOMP | MERR |
486 ((iface->read_write == I2C_SMBUS_READ) ?
487 RCVSERV : XMTSERV));
488 SSYNC();
489
490 if (iface->writeNum + 1 <= 255)
491 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
492 else {
493 write_MASTER_CTL(iface, 0xff << 6);
494 iface->manual_stop = 1;
495 }
496 /* Master enable */
497 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
498 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
499 break;
500 case TWI_I2C_MODE_COMBINED:
501 write_XMT_DATA8(iface, iface->command);
502 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
503 SSYNC();
504
505 if (iface->writeNum > 0)
506 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
507 else
508 write_MASTER_CTL(iface, 0x1 << 6);
509 /* Master enable */
510 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
511 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
512 break;
513 default:
514 write_MASTER_CTL(iface, 0);
515 if (size != I2C_SMBUS_QUICK) {
516 /* Don't access xmit data register when this is a
517 * read operation.
518 */
519 if (iface->read_write != I2C_SMBUS_READ) {
520 if (iface->writeNum > 0) {
521 write_XMT_DATA8(iface,
522 *(iface->transPtr++));
523 if (iface->writeNum <= 255)
524 write_MASTER_CTL(iface,
525 iface->writeNum << 6);
526 else {
527 write_MASTER_CTL(iface,
528 0xff << 6);
529 iface->manual_stop = 1;
530 }
531 iface->writeNum--;
532 } else {
533 write_XMT_DATA8(iface, iface->command);
534 write_MASTER_CTL(iface, 1 << 6);
535 }
536 } else {
537 if (iface->readNum > 0 && iface->readNum <= 255)
538 write_MASTER_CTL(iface,
539 iface->readNum << 6);
540 else if (iface->readNum > 255) {
541 write_MASTER_CTL(iface, 0xff << 6);
542 iface->manual_stop = 1;
543 } else {
544 del_timer(&iface->timeout_timer);
545 break;
546 }
547 }
548 }
549 write_INT_MASK(iface, MCOMP | MERR |
550 ((iface->read_write == I2C_SMBUS_READ) ?
551 RCVSERV : XMTSERV));
552 SSYNC();
553
554 /* Master enable */
555 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
556 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
557 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
558 break;
559 }
560 SSYNC();
561
562 wait_for_completion(&iface->complete);
563
564 rc = (iface->result >= 0) ? 0 : -1;
565
566 return rc;
567 }
568
569 /*
570 * Return what the adapter supports
571 */
572 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
573 {
574 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
575 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
576 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
577 I2C_FUNC_I2C;
578 }
579
580
581 static struct i2c_algorithm bfin_twi_algorithm = {
582 .master_xfer = bfin_twi_master_xfer,
583 .smbus_xfer = bfin_twi_smbus_xfer,
584 .functionality = bfin_twi_functionality,
585 };
586
587
588 static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
589 {
590 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
591
592 /* Disable TWI */
593 write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
594 SSYNC();
595
596 return 0;
597 }
598
599 static int i2c_bfin_twi_resume(struct platform_device *dev)
600 {
601 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
602
603 /* Enable TWI */
604 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
605 SSYNC();
606
607 return 0;
608 }
609
610 static int i2c_bfin_twi_probe(struct platform_device *pdev)
611 {
612 struct bfin_twi_iface *iface;
613 struct i2c_adapter *p_adap;
614 struct resource *res;
615 int rc;
616
617 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
618 if (!iface) {
619 dev_err(&pdev->dev, "Cannot allocate memory\n");
620 rc = -ENOMEM;
621 goto out_error_nomem;
622 }
623
624 spin_lock_init(&(iface->lock));
625 init_completion(&(iface->complete));
626
627 /* Find and map our resources */
628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
629 if (res == NULL) {
630 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
631 rc = -ENOENT;
632 goto out_error_get_res;
633 }
634
635 iface->regs_base = ioremap(res->start, res->end - res->start + 1);
636 if (iface->regs_base == NULL) {
637 dev_err(&pdev->dev, "Cannot map IO\n");
638 rc = -ENXIO;
639 goto out_error_ioremap;
640 }
641
642 iface->irq = platform_get_irq(pdev, 0);
643 if (iface->irq < 0) {
644 dev_err(&pdev->dev, "No IRQ specified\n");
645 rc = -ENOENT;
646 goto out_error_no_irq;
647 }
648
649 init_timer(&(iface->timeout_timer));
650 iface->timeout_timer.function = bfin_twi_timeout;
651 iface->timeout_timer.data = (unsigned long)iface;
652
653 p_adap = &iface->adap;
654 p_adap->id = I2C_HW_BLACKFIN;
655 p_adap->nr = pdev->id;
656 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
657 p_adap->algo = &bfin_twi_algorithm;
658 p_adap->algo_data = iface;
659 p_adap->class = I2C_CLASS_ALL;
660 p_adap->dev.parent = &pdev->dev;
661
662 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
663 if (rc) {
664 dev_err(&pdev->dev, "Can't setup pin mux!\n");
665 goto out_error_pin_mux;
666 }
667
668 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
669 IRQF_DISABLED, pdev->name, iface);
670 if (rc) {
671 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
672 rc = -ENODEV;
673 goto out_error_req_irq;
674 }
675
676 /* Set TWI internal clock as 10MHz */
677 write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
678
679 /* Set Twi interface clock as specified */
680 write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
681 << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
682 & 0xFF));
683
684 /* Enable TWI */
685 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
686 SSYNC();
687
688 rc = i2c_add_numbered_adapter(p_adap);
689 if (rc < 0) {
690 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
691 goto out_error_add_adapter;
692 }
693
694 platform_set_drvdata(pdev, iface);
695
696 dev_info(&pdev->dev, "Blackfin I2C TWI controller, regs_base@%p\n",
697 iface->regs_base);
698
699 return 0;
700
701 out_error_add_adapter:
702 free_irq(iface->irq, iface);
703 out_error_req_irq:
704 out_error_no_irq:
705 peripheral_free_list(pin_req[pdev->id]);
706 out_error_pin_mux:
707 iounmap(iface->regs_base);
708 out_error_ioremap:
709 out_error_get_res:
710 kfree(iface);
711 out_error_nomem:
712 return rc;
713 }
714
715 static int i2c_bfin_twi_remove(struct platform_device *pdev)
716 {
717 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
718
719 platform_set_drvdata(pdev, NULL);
720
721 i2c_del_adapter(&(iface->adap));
722 free_irq(iface->irq, iface);
723 peripheral_free_list(pin_req[pdev->id]);
724 iounmap(iface->regs_base);
725 kfree(iface);
726
727 return 0;
728 }
729
730 static struct platform_driver i2c_bfin_twi_driver = {
731 .probe = i2c_bfin_twi_probe,
732 .remove = i2c_bfin_twi_remove,
733 .suspend = i2c_bfin_twi_suspend,
734 .resume = i2c_bfin_twi_resume,
735 .driver = {
736 .name = "i2c-bfin-twi",
737 .owner = THIS_MODULE,
738 },
739 };
740
741 static int __init i2c_bfin_twi_init(void)
742 {
743 return platform_driver_register(&i2c_bfin_twi_driver);
744 }
745
746 static void __exit i2c_bfin_twi_exit(void)
747 {
748 platform_driver_unregister(&i2c_bfin_twi_driver);
749 }
750
751 MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
752 MODULE_DESCRIPTION("I2C-Bus adapter routines for Blackfin TWI");
753 MODULE_LICENSE("GPL");
754
755 module_init(i2c_bfin_twi_init);
756 module_exit(i2c_bfin_twi_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree