2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson AB.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/highmem.h>
20 #include <linux/log2.h>
21 #include <linux/mmc/host.h>
22 #include <linux/amba/bus.h>
23 #include <linux/clk.h>
24 #include <linux/scatterlist.h>
25 #include <linux/gpio.h>
26 #include <linux/amba/mmci.h>
27 #include <linux/regulator/consumer.h>
29 #include <asm/cacheflush.h>
30 #include <asm/div64.h>
32 #include <asm/sizes.h>
36 #define DRIVER_NAME "mmci-pl18x"
38 static unsigned int fmax
= 515633;
41 * This must be called with host->lock held
43 static void mmci_set_clkreg(struct mmci_host
*host
, unsigned int desired
)
48 if (desired
>= host
->mclk
) {
50 host
->cclk
= host
->mclk
;
52 clk
= host
->mclk
/ (2 * desired
) - 1;
55 host
->cclk
= host
->mclk
/ (2 * (clk
+ 1));
57 if (host
->hw_designer
== AMBA_VENDOR_ST
)
58 clk
|= MCI_ST_FCEN
; /* Bug fix in ST IP block */
59 clk
|= MCI_CLK_ENABLE
;
60 /* This hasn't proven to be worthwhile */
61 /* clk |= MCI_CLK_PWRSAVE; */
64 if (host
->mmc
->ios
.bus_width
== MMC_BUS_WIDTH_4
)
66 if (host
->mmc
->ios
.bus_width
== MMC_BUS_WIDTH_8
)
67 clk
|= MCI_ST_8BIT_BUS
;
69 writel(clk
, host
->base
+ MMCICLOCK
);
73 mmci_request_end(struct mmci_host
*host
, struct mmc_request
*mrq
)
75 writel(0, host
->base
+ MMCICOMMAND
);
83 mrq
->data
->bytes_xfered
= host
->data_xfered
;
86 * Need to drop the host lock here; mmc_request_done may call
87 * back into the driver...
89 spin_unlock(&host
->lock
);
90 mmc_request_done(host
->mmc
, mrq
);
91 spin_lock(&host
->lock
);
94 static void mmci_stop_data(struct mmci_host
*host
)
96 writel(0, host
->base
+ MMCIDATACTRL
);
97 writel(0, host
->base
+ MMCIMASK1
);
101 static void mmci_start_data(struct mmci_host
*host
, struct mmc_data
*data
)
103 unsigned int datactrl
, timeout
, irqmask
;
104 unsigned long long clks
;
108 dev_dbg(mmc_dev(host
->mmc
), "blksz %04x blks %04x flags %08x\n",
109 data
->blksz
, data
->blocks
, data
->flags
);
112 host
->size
= data
->blksz
;
113 host
->data_xfered
= 0;
115 mmci_init_sg(host
, data
);
117 clks
= (unsigned long long)data
->timeout_ns
* host
->cclk
;
118 do_div(clks
, 1000000000UL);
120 timeout
= data
->timeout_clks
+ (unsigned int)clks
;
123 writel(timeout
, base
+ MMCIDATATIMER
);
124 writel(host
->size
, base
+ MMCIDATALENGTH
);
126 blksz_bits
= ffs(data
->blksz
) - 1;
127 BUG_ON(1 << blksz_bits
!= data
->blksz
);
129 datactrl
= MCI_DPSM_ENABLE
| blksz_bits
<< 4;
130 if (data
->flags
& MMC_DATA_READ
) {
131 datactrl
|= MCI_DPSM_DIRECTION
;
132 irqmask
= MCI_RXFIFOHALFFULLMASK
;
135 * If we have less than a FIFOSIZE of bytes to transfer,
136 * trigger a PIO interrupt as soon as any data is available.
138 if (host
->size
< MCI_FIFOSIZE
)
139 irqmask
|= MCI_RXDATAAVLBLMASK
;
142 * We don't actually need to include "FIFO empty" here
143 * since its implicit in "FIFO half empty".
145 irqmask
= MCI_TXFIFOHALFEMPTYMASK
;
148 writel(datactrl
, base
+ MMCIDATACTRL
);
149 writel(readl(base
+ MMCIMASK0
) & ~MCI_DATAENDMASK
, base
+ MMCIMASK0
);
150 writel(irqmask
, base
+ MMCIMASK1
);
154 mmci_start_command(struct mmci_host
*host
, struct mmc_command
*cmd
, u32 c
)
156 void __iomem
*base
= host
->base
;
158 dev_dbg(mmc_dev(host
->mmc
), "op %02x arg %08x flags %08x\n",
159 cmd
->opcode
, cmd
->arg
, cmd
->flags
);
161 if (readl(base
+ MMCICOMMAND
) & MCI_CPSM_ENABLE
) {
162 writel(0, base
+ MMCICOMMAND
);
166 c
|= cmd
->opcode
| MCI_CPSM_ENABLE
;
167 if (cmd
->flags
& MMC_RSP_PRESENT
) {
168 if (cmd
->flags
& MMC_RSP_136
)
169 c
|= MCI_CPSM_LONGRSP
;
170 c
|= MCI_CPSM_RESPONSE
;
173 c
|= MCI_CPSM_INTERRUPT
;
177 writel(cmd
->arg
, base
+ MMCIARGUMENT
);
178 writel(c
, base
+ MMCICOMMAND
);
182 mmci_data_irq(struct mmci_host
*host
, struct mmc_data
*data
,
185 if (status
& MCI_DATABLOCKEND
) {
186 host
->data_xfered
+= data
->blksz
;
187 #ifdef CONFIG_ARCH_U300
189 * On the U300 some signal or other is
190 * badly routed so that a data write does
191 * not properly terminate with a MCI_DATAEND
192 * status flag. This quirk will make writes
195 if (data
->flags
& MMC_DATA_WRITE
)
196 status
|= MCI_DATAEND
;
199 if (status
& (MCI_DATACRCFAIL
|MCI_DATATIMEOUT
|MCI_TXUNDERRUN
|MCI_RXOVERRUN
)) {
200 dev_dbg(mmc_dev(host
->mmc
), "MCI ERROR IRQ (status %08x)\n", status
);
201 if (status
& MCI_DATACRCFAIL
)
202 data
->error
= -EILSEQ
;
203 else if (status
& MCI_DATATIMEOUT
)
204 data
->error
= -ETIMEDOUT
;
205 else if (status
& (MCI_TXUNDERRUN
|MCI_RXOVERRUN
))
207 status
|= MCI_DATAEND
;
210 * We hit an error condition. Ensure that any data
211 * partially written to a page is properly coherent.
213 if (host
->sg_len
&& data
->flags
& MMC_DATA_READ
)
214 flush_dcache_page(sg_page(host
->sg_ptr
));
216 if (status
& MCI_DATAEND
) {
217 mmci_stop_data(host
);
220 mmci_request_end(host
, data
->mrq
);
222 mmci_start_command(host
, data
->stop
, 0);
228 mmci_cmd_irq(struct mmci_host
*host
, struct mmc_command
*cmd
,
231 void __iomem
*base
= host
->base
;
235 cmd
->resp
[0] = readl(base
+ MMCIRESPONSE0
);
236 cmd
->resp
[1] = readl(base
+ MMCIRESPONSE1
);
237 cmd
->resp
[2] = readl(base
+ MMCIRESPONSE2
);
238 cmd
->resp
[3] = readl(base
+ MMCIRESPONSE3
);
240 if (status
& MCI_CMDTIMEOUT
) {
241 cmd
->error
= -ETIMEDOUT
;
242 } else if (status
& MCI_CMDCRCFAIL
&& cmd
->flags
& MMC_RSP_CRC
) {
243 cmd
->error
= -EILSEQ
;
246 if (!cmd
->data
|| cmd
->error
) {
248 mmci_stop_data(host
);
249 mmci_request_end(host
, cmd
->mrq
);
250 } else if (!(cmd
->data
->flags
& MMC_DATA_READ
)) {
251 mmci_start_data(host
, cmd
->data
);
255 static int mmci_pio_read(struct mmci_host
*host
, char *buffer
, unsigned int remain
)
257 void __iomem
*base
= host
->base
;
260 int host_remain
= host
->size
;
263 int count
= host_remain
- (readl(base
+ MMCIFIFOCNT
) << 2);
271 readsl(base
+ MMCIFIFO
, ptr
, count
>> 2);
275 host_remain
-= count
;
280 status
= readl(base
+ MMCISTATUS
);
281 } while (status
& MCI_RXDATAAVLBL
);
286 static int mmci_pio_write(struct mmci_host
*host
, char *buffer
, unsigned int remain
, u32 status
)
288 void __iomem
*base
= host
->base
;
292 unsigned int count
, maxcnt
;
294 maxcnt
= status
& MCI_TXFIFOEMPTY
? MCI_FIFOSIZE
: MCI_FIFOHALFSIZE
;
295 count
= min(remain
, maxcnt
);
297 writesl(base
+ MMCIFIFO
, ptr
, count
>> 2);
305 status
= readl(base
+ MMCISTATUS
);
306 } while (status
& MCI_TXFIFOHALFEMPTY
);
312 * PIO data transfer IRQ handler.
314 static irqreturn_t
mmci_pio_irq(int irq
, void *dev_id
)
316 struct mmci_host
*host
= dev_id
;
317 void __iomem
*base
= host
->base
;
320 status
= readl(base
+ MMCISTATUS
);
322 dev_dbg(mmc_dev(host
->mmc
), "irq1 (pio) %08x\n", status
);
326 unsigned int remain
, len
;
330 * For write, we only need to test the half-empty flag
331 * here - if the FIFO is completely empty, then by
332 * definition it is more than half empty.
334 * For read, check for data available.
336 if (!(status
& (MCI_TXFIFOHALFEMPTY
|MCI_RXDATAAVLBL
)))
340 * Map the current scatter buffer.
342 buffer
= mmci_kmap_atomic(host
, &flags
) + host
->sg_off
;
343 remain
= host
->sg_ptr
->length
- host
->sg_off
;
346 if (status
& MCI_RXACTIVE
)
347 len
= mmci_pio_read(host
, buffer
, remain
);
348 if (status
& MCI_TXACTIVE
)
349 len
= mmci_pio_write(host
, buffer
, remain
, status
);
354 mmci_kunmap_atomic(host
, buffer
, &flags
);
364 * If we were reading, and we have completed this
365 * page, ensure that the data cache is coherent.
367 if (status
& MCI_RXACTIVE
)
368 flush_dcache_page(sg_page(host
->sg_ptr
));
370 if (!mmci_next_sg(host
))
373 status
= readl(base
+ MMCISTATUS
);
377 * If we're nearing the end of the read, switch to
378 * "any data available" mode.
380 if (status
& MCI_RXACTIVE
&& host
->size
< MCI_FIFOSIZE
)
381 writel(MCI_RXDATAAVLBLMASK
, base
+ MMCIMASK1
);
384 * If we run out of data, disable the data IRQs; this
385 * prevents a race where the FIFO becomes empty before
386 * the chip itself has disabled the data path, and
387 * stops us racing with our data end IRQ.
389 if (host
->size
== 0) {
390 writel(0, base
+ MMCIMASK1
);
391 writel(readl(base
+ MMCIMASK0
) | MCI_DATAENDMASK
, base
+ MMCIMASK0
);
398 * Handle completion of command and data transfers.
400 static irqreturn_t
mmci_irq(int irq
, void *dev_id
)
402 struct mmci_host
*host
= dev_id
;
406 spin_lock(&host
->lock
);
409 struct mmc_command
*cmd
;
410 struct mmc_data
*data
;
412 status
= readl(host
->base
+ MMCISTATUS
);
413 status
&= readl(host
->base
+ MMCIMASK0
);
414 writel(status
, host
->base
+ MMCICLEAR
);
416 dev_dbg(mmc_dev(host
->mmc
), "irq0 (data+cmd) %08x\n", status
);
419 if (status
& (MCI_DATACRCFAIL
|MCI_DATATIMEOUT
|MCI_TXUNDERRUN
|
420 MCI_RXOVERRUN
|MCI_DATAEND
|MCI_DATABLOCKEND
) && data
)
421 mmci_data_irq(host
, data
, status
);
424 if (status
& (MCI_CMDCRCFAIL
|MCI_CMDTIMEOUT
|MCI_CMDSENT
|MCI_CMDRESPEND
) && cmd
)
425 mmci_cmd_irq(host
, cmd
, status
);
430 spin_unlock(&host
->lock
);
432 return IRQ_RETVAL(ret
);
435 static void mmci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
437 struct mmci_host
*host
= mmc_priv(mmc
);
440 WARN_ON(host
->mrq
!= NULL
);
442 if (mrq
->data
&& !is_power_of_2(mrq
->data
->blksz
)) {
443 dev_err(mmc_dev(mmc
), "unsupported block size (%d bytes)\n",
445 mrq
->cmd
->error
= -EINVAL
;
446 mmc_request_done(mmc
, mrq
);
450 spin_lock_irqsave(&host
->lock
, flags
);
454 if (mrq
->data
&& mrq
->data
->flags
& MMC_DATA_READ
)
455 mmci_start_data(host
, mrq
->data
);
457 mmci_start_command(host
, mrq
->cmd
, 0);
459 spin_unlock_irqrestore(&host
->lock
, flags
);
462 static void mmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
464 struct mmci_host
*host
= mmc_priv(mmc
);
468 switch (ios
->power_mode
) {
471 regulator_is_enabled(host
->vcc
))
472 regulator_disable(host
->vcc
);
475 #ifdef CONFIG_REGULATOR
477 /* This implicitly enables the regulator */
478 mmc_regulator_set_ocr(host
->vcc
, ios
->vdd
);
481 * The translate_vdd function is not used if you have
482 * an external regulator, or your design is really weird.
483 * Using it would mean sending in power control BOTH using
484 * a regulator AND the 4 MMCIPWR bits. If we don't have
485 * a regulator, we might have some other platform specific
486 * power control behind this translate function.
488 if (!host
->vcc
&& host
->plat
->translate_vdd
)
489 pwr
|= host
->plat
->translate_vdd(mmc_dev(mmc
), ios
->vdd
);
490 /* The ST version does not have this, fall through to POWER_ON */
491 if (host
->hw_designer
!= AMBA_VENDOR_ST
) {
500 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
) {
501 if (host
->hw_designer
!= AMBA_VENDOR_ST
)
505 * The ST Micro variant use the ROD bit for something
506 * else and only has OD (Open Drain).
512 spin_lock_irqsave(&host
->lock
, flags
);
514 mmci_set_clkreg(host
, ios
->clock
);
516 if (host
->pwr
!= pwr
) {
518 writel(pwr
, host
->base
+ MMCIPOWER
);
521 spin_unlock_irqrestore(&host
->lock
, flags
);
524 static int mmci_get_ro(struct mmc_host
*mmc
)
526 struct mmci_host
*host
= mmc_priv(mmc
);
528 if (host
->gpio_wp
== -ENOSYS
)
531 return gpio_get_value(host
->gpio_wp
);
534 static int mmci_get_cd(struct mmc_host
*mmc
)
536 struct mmci_host
*host
= mmc_priv(mmc
);
539 if (host
->gpio_cd
== -ENOSYS
)
540 status
= host
->plat
->status(mmc_dev(host
->mmc
));
542 status
= !gpio_get_value(host
->gpio_cd
);
545 * Use positive logic throughout - status is zero for no card,
546 * non-zero for card inserted.
551 static const struct mmc_host_ops mmci_ops
= {
552 .request
= mmci_request
,
553 .set_ios
= mmci_set_ios
,
554 .get_ro
= mmci_get_ro
,
555 .get_cd
= mmci_get_cd
,
558 static void mmci_check_status(unsigned long data
)
560 struct mmci_host
*host
= (struct mmci_host
*)data
;
561 unsigned int status
= mmci_get_cd(host
->mmc
);
563 if (status
^ host
->oldstat
)
564 mmc_detect_change(host
->mmc
, 0);
566 host
->oldstat
= status
;
567 mod_timer(&host
->timer
, jiffies
+ HZ
);
570 static int __devinit
mmci_probe(struct amba_device
*dev
, struct amba_id
*id
)
572 struct mmci_platform_data
*plat
= dev
->dev
.platform_data
;
573 struct mmci_host
*host
;
574 struct mmc_host
*mmc
;
577 /* must have platform data */
583 ret
= amba_request_regions(dev
, DRIVER_NAME
);
587 mmc
= mmc_alloc_host(sizeof(struct mmci_host
), &dev
->dev
);
593 host
= mmc_priv(mmc
);
596 host
->gpio_wp
= -ENOSYS
;
597 host
->gpio_cd
= -ENOSYS
;
599 host
->hw_designer
= amba_manf(dev
);
600 host
->hw_revision
= amba_rev(dev
);
601 dev_dbg(mmc_dev(mmc
), "designer ID = 0x%02x\n", host
->hw_designer
);
602 dev_dbg(mmc_dev(mmc
), "revision = 0x%01x\n", host
->hw_revision
);
604 host
->clk
= clk_get(&dev
->dev
, NULL
);
605 if (IS_ERR(host
->clk
)) {
606 ret
= PTR_ERR(host
->clk
);
611 ret
= clk_enable(host
->clk
);
616 host
->mclk
= clk_get_rate(host
->clk
);
618 * According to the spec, mclk is max 100 MHz,
619 * so we try to adjust the clock down to this,
622 if (host
->mclk
> 100000000) {
623 ret
= clk_set_rate(host
->clk
, 100000000);
626 host
->mclk
= clk_get_rate(host
->clk
);
627 dev_dbg(mmc_dev(mmc
), "eventual mclk rate: %u Hz\n",
630 host
->base
= ioremap(dev
->res
.start
, resource_size(&dev
->res
));
636 mmc
->ops
= &mmci_ops
;
637 mmc
->f_min
= (host
->mclk
+ 511) / 512;
639 * If the platform data supplies a maximum operating
640 * frequency, this takes precedence. Else, we fall back
641 * to using the module parameter, which has a (low)
642 * default value in case it is not specified. Either
643 * value must not exceed the clock rate into the block,
647 mmc
->f_max
= min(host
->mclk
, plat
->f_max
);
649 mmc
->f_max
= min(host
->mclk
, fmax
);
650 dev_dbg(mmc_dev(mmc
), "clocking block at %u Hz\n", mmc
->f_max
);
652 #ifdef CONFIG_REGULATOR
653 /* If we're using the regulator framework, try to fetch a regulator */
654 host
->vcc
= regulator_get(&dev
->dev
, "vmmc");
655 if (IS_ERR(host
->vcc
))
658 int mask
= mmc_regulator_get_ocrmask(host
->vcc
);
661 dev_err(&dev
->dev
, "error getting OCR mask (%d)\n",
664 host
->mmc
->ocr_avail
= (u32
) mask
;
667 "Provided ocr_mask/setpower will not be used "
668 "(using regulator instead)\n");
672 /* Fall back to platform data if no regulator is found */
673 if (host
->vcc
== NULL
)
674 mmc
->ocr_avail
= plat
->ocr_mask
;
675 mmc
->caps
= plat
->capabilities
;
680 mmc
->max_hw_segs
= 16;
681 mmc
->max_phys_segs
= NR_SG
;
684 * Since we only have a 16-bit data length register, we must
685 * ensure that we don't exceed 2^16-1 bytes in a single request.
687 mmc
->max_req_size
= 65535;
690 * Set the maximum segment size. Since we aren't doing DMA
691 * (yet) we are only limited by the data length register.
693 mmc
->max_seg_size
= mmc
->max_req_size
;
696 * Block size can be up to 2048 bytes, but must be a power of two.
698 mmc
->max_blk_size
= 2048;
701 * No limit on the number of blocks transferred.
703 mmc
->max_blk_count
= mmc
->max_req_size
;
705 spin_lock_init(&host
->lock
);
707 writel(0, host
->base
+ MMCIMASK0
);
708 writel(0, host
->base
+ MMCIMASK1
);
709 writel(0xfff, host
->base
+ MMCICLEAR
);
711 if (gpio_is_valid(plat
->gpio_cd
)) {
712 ret
= gpio_request(plat
->gpio_cd
, DRIVER_NAME
" (cd)");
714 ret
= gpio_direction_input(plat
->gpio_cd
);
716 host
->gpio_cd
= plat
->gpio_cd
;
717 else if (ret
!= -ENOSYS
)
720 if (gpio_is_valid(plat
->gpio_wp
)) {
721 ret
= gpio_request(plat
->gpio_wp
, DRIVER_NAME
" (wp)");
723 ret
= gpio_direction_input(plat
->gpio_wp
);
725 host
->gpio_wp
= plat
->gpio_wp
;
726 else if (ret
!= -ENOSYS
)
730 ret
= request_irq(dev
->irq
[0], mmci_irq
, IRQF_SHARED
, DRIVER_NAME
" (cmd)", host
);
734 ret
= request_irq(dev
->irq
[1], mmci_pio_irq
, IRQF_SHARED
, DRIVER_NAME
" (pio)", host
);
738 writel(MCI_IRQENABLE
, host
->base
+ MMCIMASK0
);
740 amba_set_drvdata(dev
, mmc
);
741 host
->oldstat
= mmci_get_cd(host
->mmc
);
745 dev_info(&dev
->dev
, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
746 mmc_hostname(mmc
), amba_rev(dev
), amba_config(dev
),
747 (unsigned long long)dev
->res
.start
, dev
->irq
[0], dev
->irq
[1]);
749 init_timer(&host
->timer
);
750 host
->timer
.data
= (unsigned long)host
;
751 host
->timer
.function
= mmci_check_status
;
752 host
->timer
.expires
= jiffies
+ HZ
;
753 add_timer(&host
->timer
);
758 free_irq(dev
->irq
[0], host
);
760 if (host
->gpio_wp
!= -ENOSYS
)
761 gpio_free(host
->gpio_wp
);
763 if (host
->gpio_cd
!= -ENOSYS
)
764 gpio_free(host
->gpio_cd
);
768 clk_disable(host
->clk
);
774 amba_release_regions(dev
);
779 static int __devexit
mmci_remove(struct amba_device
*dev
)
781 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
783 amba_set_drvdata(dev
, NULL
);
786 struct mmci_host
*host
= mmc_priv(mmc
);
788 del_timer_sync(&host
->timer
);
790 mmc_remove_host(mmc
);
792 writel(0, host
->base
+ MMCIMASK0
);
793 writel(0, host
->base
+ MMCIMASK1
);
795 writel(0, host
->base
+ MMCICOMMAND
);
796 writel(0, host
->base
+ MMCIDATACTRL
);
798 free_irq(dev
->irq
[0], host
);
799 free_irq(dev
->irq
[1], host
);
801 if (host
->gpio_wp
!= -ENOSYS
)
802 gpio_free(host
->gpio_wp
);
803 if (host
->gpio_cd
!= -ENOSYS
)
804 gpio_free(host
->gpio_cd
);
807 clk_disable(host
->clk
);
810 if (regulator_is_enabled(host
->vcc
))
811 regulator_disable(host
->vcc
);
812 regulator_put(host
->vcc
);
816 amba_release_regions(dev
);
823 static int mmci_suspend(struct amba_device
*dev
, pm_message_t state
)
825 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
829 struct mmci_host
*host
= mmc_priv(mmc
);
831 ret
= mmc_suspend_host(mmc
);
833 writel(0, host
->base
+ MMCIMASK0
);
839 static int mmci_resume(struct amba_device
*dev
)
841 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
845 struct mmci_host
*host
= mmc_priv(mmc
);
847 writel(MCI_IRQENABLE
, host
->base
+ MMCIMASK0
);
849 ret
= mmc_resume_host(mmc
);
855 #define mmci_suspend NULL
856 #define mmci_resume NULL
859 static struct amba_id mmci_ids
[] = {
868 /* ST Micro variants */
880 static struct amba_driver mmci_driver
= {
885 .remove
= __devexit_p(mmci_remove
),
886 .suspend
= mmci_suspend
,
887 .resume
= mmci_resume
,
888 .id_table
= mmci_ids
,
891 static int __init
mmci_init(void)
893 return amba_driver_register(&mmci_driver
);
896 static void __exit
mmci_exit(void)
898 amba_driver_unregister(&mmci_driver
);
901 module_init(mmci_init
);
902 module_exit(mmci_exit
);
903 module_param(fmax
, uint
, 0444);
905 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
906 MODULE_LICENSE("GPL");