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mwl8k: get rid of the AMSDU check in the transmit path
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / mwl8k.c
blob18542fba1f43c87bb75fed560e707f9b036d8e3d
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
51
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
68
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
82
83 struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
89 };
90
91 struct mwl8k_device_info {
92 char *part_name;
93 char *helper_image;
94 char *fw_image;
95 struct rxd_ops *rxd_ops;
96 u16 modes;
97 };
98
99 struct mwl8k_rx_queue {
100 int rxd_count;
101
102 /* hw receives here */
103 int head;
104
105 /* refill descs here */
106 int tail;
107
108 void *rxd;
109 dma_addr_t rxd_dma;
110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
114 };
115
116 struct mwl8k_tx_queue {
117 /* hw transmits here */
118 int head;
119
120 /* sw appends here */
121 int tail;
122
123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
127 };
128
129 /* Pointers to the firmware data and meta information about it. */
130 struct mwl8k_firmware {
131 /* Boot helper code */
132 struct firmware *helper;
133
134 /* Microcode */
135 struct firmware *ucode;
136 };
137
138 struct mwl8k_priv {
139 void __iomem *sram;
140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
144
145 struct mwl8k_device_info *device_info;
146 bool ap_fw;
147 struct rxd_ops *rxd_ops;
148
149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
151
152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
156 struct completion *hostcmd_wait;
157
158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
160
161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
164 struct ieee80211_vif *vif;
165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
173 u8 hw_rev;
174 u32 fw_rev;
175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
188 struct ieee80211_rate rates[14];
189
190 bool radio_on;
191 bool radio_short_preamble;
192 bool sniffer_enabled;
193 bool wmm_enabled;
194
195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
197 u8 capture_bssid[ETH_ALEN];
198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
210 };
211
212 /* Per interface specific private data */
213 struct mwl8k_vif {
214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
223
224 /* Index into station database. Returned by UPDATE_STADB. */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
229 };
230
231 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
232
233 static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245 };
246
247 static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
261 { .bitrate = 720, .hw_value = 144, },
262 };
263
264 static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
266 };
267
268 /* Set or get info from Firmware */
269 #define MWL8K_CMD_SET 0x0001
270 #define MWL8K_CMD_GET 0x0000
271
272 /* Firmware command codes */
273 #define MWL8K_CMD_CODE_DNLD 0x0001
274 #define MWL8K_CMD_GET_HW_SPEC 0x0003
275 #define MWL8K_CMD_SET_HW_SPEC 0x0004
276 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277 #define MWL8K_CMD_GET_STAT 0x0014
278 #define MWL8K_CMD_RADIO_CONTROL 0x001c
279 #define MWL8K_CMD_RF_TX_POWER 0x001e
280 #define MWL8K_CMD_RF_ANTENNA 0x0020
281 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
282 #define MWL8K_CMD_SET_POST_SCAN 0x0108
283 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284 #define MWL8K_CMD_SET_AID 0x010d
285 #define MWL8K_CMD_SET_RATE 0x0110
286 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
288 #define MWL8K_CMD_SET_SLOT 0x0114
289 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290 #define MWL8K_CMD_SET_WMM_MODE 0x0123
291 #define MWL8K_CMD_MIMO_CONFIG 0x0125
292 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
293 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
294 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
295 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
296 #define MWL8K_CMD_UPDATE_STADB 0x1123
297
298 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299 {
300 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
304 switch (cmd & ~0x8000) {
305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
307 MWL8K_CMDNAME(SET_HW_SPEC);
308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
312 MWL8K_CMDNAME(RF_ANTENNA);
313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
320 MWL8K_CMDNAME(SET_SLOT);
321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
323 MWL8K_CMDNAME(MIMO_CONFIG);
324 MWL8K_CMDNAME(USE_FIXED_RATE);
325 MWL8K_CMDNAME(ENABLE_SNIFFER);
326 MWL8K_CMDNAME(SET_MAC_ADDR);
327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
328 MWL8K_CMDNAME(UPDATE_STADB);
329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332 #undef MWL8K_CMDNAME
333
334 return buf;
335 }
336
337 /* Hardware and firmware reset */
338 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339 {
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345 }
346
347 /* Release fw image */
348 static void mwl8k_release_fw(struct firmware **fw)
349 {
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354 }
355
356 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357 {
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360 }
361
362 /* Request fw image */
363 static int mwl8k_request_fw(struct mwl8k_priv *priv,
364 const char *fname, struct firmware **fw)
365 {
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
371 fname, &priv->pdev->dev);
372 }
373
374 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
375 {
376 struct mwl8k_device_info *di = priv->device_info;
377 int rc;
378
379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
387 }
388
389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
390 if (rc) {
391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
392 pci_name(priv->pdev), di->fw_image);
393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398 }
399
400 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
403 struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409 } __attribute__((packed));
410
411 /*
412 * Firmware loading.
413 */
414 static int
415 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416 {
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
439 break;
440 }
441
442 cond_resched();
443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
448 return loops ? 0 : -ETIMEDOUT;
449 }
450
451 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453 {
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490 }
491
492 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494 {
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549 }
550
551 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
552 {
553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
555 struct mwl8k_device_info *di = priv->device_info;
556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
561
562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
567
568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
571 "helper image\n", pci_name(priv->pdev));
572 return rc;
573 }
574 msleep(5);
575
576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
577 } else {
578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
579 }
580
581 if (rc) {
582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
584 return rc;
585 }
586
587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
591
592 loops = 500000;
593 do {
594 u32 ready_code;
595
596 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
597 if (ready_code == MWL8K_FWAP_READY) {
598 priv->ap_fw = 1;
599 break;
600 } else if (ready_code == MWL8K_FWSTA_READY) {
601 priv->ap_fw = 0;
602 break;
603 }
604
605 cond_resched();
606 udelay(1);
607 } while (--loops);
608
609 return loops ? 0 : -ETIMEDOUT;
610 }
611
612
613 /*
614 * Defines shared between transmission and reception.
615 */
616 /* HT control fields for firmware */
617 struct ewc_ht_info {
618 __le16 control1;
619 __le16 control2;
620 __le16 control3;
621 } __attribute__((packed));
622
623 /* Firmware Station database operations */
624 #define MWL8K_STA_DB_ADD_ENTRY 0
625 #define MWL8K_STA_DB_MODIFY_ENTRY 1
626 #define MWL8K_STA_DB_DEL_ENTRY 2
627 #define MWL8K_STA_DB_FLUSH 3
628
629 /* Peer Entry flags - used to define the type of the peer node */
630 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
631
632 struct peer_capability_info {
633 /* Peer type - AP vs. STA. */
634 __u8 peer_type;
635
636 /* Basic 802.11 capabilities from assoc resp. */
637 __le16 basic_caps;
638
639 /* Set if peer supports 802.11n high throughput (HT). */
640 __u8 ht_support;
641
642 /* Valid if HT is supported. */
643 __le16 ht_caps;
644 __u8 extended_ht_caps;
645 struct ewc_ht_info ewc_info;
646
647 /* Legacy rate table. Intersection of our rates and peer rates. */
648 __u8 legacy_rates[12];
649
650 /* HT rate table. Intersection of our rates and peer rates. */
651 __u8 ht_rates[16];
652 __u8 pad[16];
653
654 /* If set, interoperability mode, no proprietary extensions. */
655 __u8 interop;
656 __u8 pad2;
657 __u8 station_id;
658 __le16 amsdu_enabled;
659 } __attribute__((packed));
660
661 /* Inline functions to manipulate QoS field in data descriptor. */
662 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
663 {
664 u16 val_mask = 1 << 4;
665
666 /* End of Service Period Bit 4 */
667 return qos | val_mask;
668 }
669
670 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
671 {
672 u16 val_mask = 0x3;
673 u8 shift = 5;
674 u16 qos_mask = ~(val_mask << shift);
675
676 /* Ack Policy Bit 5-6 */
677 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
678 }
679
680 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
681 {
682 u16 val_mask = 0xff;
683 u8 shift = 8;
684 u16 qos_mask = ~(val_mask << shift);
685
686 /* Queue Length Bits 8-15 */
687 return (qos & qos_mask) | ((len & val_mask) << shift);
688 }
689
690 /* DMA header used by firmware and hardware. */
691 struct mwl8k_dma_data {
692 __le16 fwlen;
693 struct ieee80211_hdr wh;
694 char data[0];
695 } __attribute__((packed));
696
697 /* Routines to add/remove DMA header from skb. */
698 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
699 {
700 struct mwl8k_dma_data *tr;
701 int hdrlen;
702
703 tr = (struct mwl8k_dma_data *)skb->data;
704 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
705
706 if (hdrlen != sizeof(tr->wh)) {
707 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
708 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
709 *((__le16 *)(tr->data - 2)) = qos;
710 } else {
711 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
712 }
713 }
714
715 if (hdrlen != sizeof(*tr))
716 skb_pull(skb, sizeof(*tr) - hdrlen);
717 }
718
719 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
720 {
721 struct ieee80211_hdr *wh;
722 int hdrlen;
723 struct mwl8k_dma_data *tr;
724
725 /*
726 * Add a firmware DMA header; the firmware requires that we
727 * present a 2-byte payload length followed by a 4-address
728 * header (without QoS field), followed (optionally) by any
729 * WEP/ExtIV header (but only filled in for CCMP).
730 */
731 wh = (struct ieee80211_hdr *)skb->data;
732
733 hdrlen = ieee80211_hdrlen(wh->frame_control);
734 if (hdrlen != sizeof(*tr))
735 skb_push(skb, sizeof(*tr) - hdrlen);
736
737 if (ieee80211_is_data_qos(wh->frame_control))
738 hdrlen -= 2;
739
740 tr = (struct mwl8k_dma_data *)skb->data;
741 if (wh != &tr->wh)
742 memmove(&tr->wh, wh, hdrlen);
743 if (hdrlen != sizeof(tr->wh))
744 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
745
746 /*
747 * Firmware length is the length of the fully formed "802.11
748 * payload". That is, everything except for the 802.11 header.
749 * This includes all crypto material including the MIC.
750 */
751 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
752 }
753
754
755 /*
756 * Packet reception for 88w8366.
757 */
758 struct mwl8k_rxd_8366 {
759 __le16 pkt_len;
760 __u8 sq2;
761 __u8 rate;
762 __le32 pkt_phys_addr;
763 __le32 next_rxd_phys_addr;
764 __le16 qos_control;
765 __le16 htsig2;
766 __le32 hw_rssi_info;
767 __le32 hw_noise_floor_info;
768 __u8 noise_floor;
769 __u8 pad0[3];
770 __u8 rssi;
771 __u8 rx_status;
772 __u8 channel;
773 __u8 rx_ctrl;
774 } __attribute__((packed));
775
776 #define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
777 #define MWL8K_8366_RATE_INFO_40MHZ 0x40
778 #define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
779
780 #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
781
782 static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
783 {
784 struct mwl8k_rxd_8366 *rxd = _rxd;
785
786 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
787 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
788 }
789
790 static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
791 {
792 struct mwl8k_rxd_8366 *rxd = _rxd;
793
794 rxd->pkt_len = cpu_to_le16(len);
795 rxd->pkt_phys_addr = cpu_to_le32(addr);
796 wmb();
797 rxd->rx_ctrl = 0;
798 }
799
800 static int
801 mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
802 __le16 *qos)
803 {
804 struct mwl8k_rxd_8366 *rxd = _rxd;
805
806 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
807 return -1;
808 rmb();
809
810 memset(status, 0, sizeof(*status));
811
812 status->signal = -rxd->rssi;
813 status->noise = -rxd->noise_floor;
814
815 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
816 status->flag |= RX_FLAG_HT;
817 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
818 status->flag |= RX_FLAG_40MHZ;
819 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
820 } else {
821 int i;
822
823 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
824 if (mwl8k_rates[i].hw_value == rxd->rate) {
825 status->rate_idx = i;
826 break;
827 }
828 }
829 }
830
831 status->band = IEEE80211_BAND_2GHZ;
832 status->freq = ieee80211_channel_to_frequency(rxd->channel);
833
834 *qos = rxd->qos_control;
835
836 return le16_to_cpu(rxd->pkt_len);
837 }
838
839 static struct rxd_ops rxd_8366_ops = {
840 .rxd_size = sizeof(struct mwl8k_rxd_8366),
841 .rxd_init = mwl8k_rxd_8366_init,
842 .rxd_refill = mwl8k_rxd_8366_refill,
843 .rxd_process = mwl8k_rxd_8366_process,
844 };
845
846 /*
847 * Packet reception for 88w8687.
848 */
849 struct mwl8k_rxd_8687 {
850 __le16 pkt_len;
851 __u8 link_quality;
852 __u8 noise_level;
853 __le32 pkt_phys_addr;
854 __le32 next_rxd_phys_addr;
855 __le16 qos_control;
856 __le16 rate_info;
857 __le32 pad0[4];
858 __u8 rssi;
859 __u8 channel;
860 __le16 pad1;
861 __u8 rx_ctrl;
862 __u8 rx_status;
863 __u8 pad2[2];
864 } __attribute__((packed));
865
866 #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
867 #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
868 #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
869 #define MWL8K_8687_RATE_INFO_40MHZ 0x0004
870 #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
871 #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
872
873 #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
874
875 static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
876 {
877 struct mwl8k_rxd_8687 *rxd = _rxd;
878
879 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
880 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
881 }
882
883 static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
884 {
885 struct mwl8k_rxd_8687 *rxd = _rxd;
886
887 rxd->pkt_len = cpu_to_le16(len);
888 rxd->pkt_phys_addr = cpu_to_le32(addr);
889 wmb();
890 rxd->rx_ctrl = 0;
891 }
892
893 static int
894 mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
895 __le16 *qos)
896 {
897 struct mwl8k_rxd_8687 *rxd = _rxd;
898 u16 rate_info;
899
900 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
901 return -1;
902 rmb();
903
904 rate_info = le16_to_cpu(rxd->rate_info);
905
906 memset(status, 0, sizeof(*status));
907
908 status->signal = -rxd->rssi;
909 status->noise = -rxd->noise_level;
910 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
911 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
912
913 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
914 status->flag |= RX_FLAG_SHORTPRE;
915 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
916 status->flag |= RX_FLAG_40MHZ;
917 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
918 status->flag |= RX_FLAG_SHORT_GI;
919 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
920 status->flag |= RX_FLAG_HT;
921
922 status->band = IEEE80211_BAND_2GHZ;
923 status->freq = ieee80211_channel_to_frequency(rxd->channel);
924
925 *qos = rxd->qos_control;
926
927 return le16_to_cpu(rxd->pkt_len);
928 }
929
930 static struct rxd_ops rxd_8687_ops = {
931 .rxd_size = sizeof(struct mwl8k_rxd_8687),
932 .rxd_init = mwl8k_rxd_8687_init,
933 .rxd_refill = mwl8k_rxd_8687_refill,
934 .rxd_process = mwl8k_rxd_8687_process,
935 };
936
937
938 #define MWL8K_RX_DESCS 256
939 #define MWL8K_RX_MAXSZ 3800
940
941 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
942 {
943 struct mwl8k_priv *priv = hw->priv;
944 struct mwl8k_rx_queue *rxq = priv->rxq + index;
945 int size;
946 int i;
947
948 rxq->rxd_count = 0;
949 rxq->head = 0;
950 rxq->tail = 0;
951
952 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
953
954 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
955 if (rxq->rxd == NULL) {
956 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
957 wiphy_name(hw->wiphy));
958 return -ENOMEM;
959 }
960 memset(rxq->rxd, 0, size);
961
962 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
963 if (rxq->buf == NULL) {
964 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
965 wiphy_name(hw->wiphy));
966 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
967 return -ENOMEM;
968 }
969 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
970
971 for (i = 0; i < MWL8K_RX_DESCS; i++) {
972 int desc_size;
973 void *rxd;
974 int nexti;
975 dma_addr_t next_dma_addr;
976
977 desc_size = priv->rxd_ops->rxd_size;
978 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
979
980 nexti = i + 1;
981 if (nexti == MWL8K_RX_DESCS)
982 nexti = 0;
983 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
984
985 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
986 }
987
988 return 0;
989 }
990
991 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
992 {
993 struct mwl8k_priv *priv = hw->priv;
994 struct mwl8k_rx_queue *rxq = priv->rxq + index;
995 int refilled;
996
997 refilled = 0;
998 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
999 struct sk_buff *skb;
1000 dma_addr_t addr;
1001 int rx;
1002 void *rxd;
1003
1004 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1005 if (skb == NULL)
1006 break;
1007
1008 addr = pci_map_single(priv->pdev, skb->data,
1009 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
1010
1011 rxq->rxd_count++;
1012 rx = rxq->tail++;
1013 if (rxq->tail == MWL8K_RX_DESCS)
1014 rxq->tail = 0;
1015 rxq->buf[rx].skb = skb;
1016 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
1017
1018 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1019 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
1020
1021 refilled++;
1022 }
1023
1024 return refilled;
1025 }
1026
1027 /* Must be called only when the card's reception is completely halted */
1028 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1029 {
1030 struct mwl8k_priv *priv = hw->priv;
1031 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1032 int i;
1033
1034 for (i = 0; i < MWL8K_RX_DESCS; i++) {
1035 if (rxq->buf[i].skb != NULL) {
1036 pci_unmap_single(priv->pdev,
1037 pci_unmap_addr(&rxq->buf[i], dma),
1038 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1039 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1040
1041 kfree_skb(rxq->buf[i].skb);
1042 rxq->buf[i].skb = NULL;
1043 }
1044 }
1045
1046 kfree(rxq->buf);
1047 rxq->buf = NULL;
1048
1049 pci_free_consistent(priv->pdev,
1050 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1051 rxq->rxd, rxq->rxd_dma);
1052 rxq->rxd = NULL;
1053 }
1054
1055
1056 /*
1057 * Scan a list of BSSIDs to process for finalize join.
1058 * Allows for extension to process multiple BSSIDs.
1059 */
1060 static inline int
1061 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1062 {
1063 return priv->capture_beacon &&
1064 ieee80211_is_beacon(wh->frame_control) &&
1065 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1066 }
1067
1068 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1069 struct sk_buff *skb)
1070 {
1071 struct mwl8k_priv *priv = hw->priv;
1072
1073 priv->capture_beacon = false;
1074 memset(priv->capture_bssid, 0, ETH_ALEN);
1075
1076 /*
1077 * Use GFP_ATOMIC as rxq_process is called from
1078 * the primary interrupt handler, memory allocation call
1079 * must not sleep.
1080 */
1081 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1082 if (priv->beacon_skb != NULL)
1083 ieee80211_queue_work(hw, &priv->finalize_join_worker);
1084 }
1085
1086 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1087 {
1088 struct mwl8k_priv *priv = hw->priv;
1089 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1090 int processed;
1091
1092 processed = 0;
1093 while (rxq->rxd_count && limit--) {
1094 struct sk_buff *skb;
1095 void *rxd;
1096 int pkt_len;
1097 struct ieee80211_rx_status status;
1098 __le16 qos;
1099
1100 skb = rxq->buf[rxq->head].skb;
1101 if (skb == NULL)
1102 break;
1103
1104 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1105
1106 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1107 if (pkt_len < 0)
1108 break;
1109
1110 rxq->buf[rxq->head].skb = NULL;
1111
1112 pci_unmap_single(priv->pdev,
1113 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1114 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1115 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1116
1117 rxq->head++;
1118 if (rxq->head == MWL8K_RX_DESCS)
1119 rxq->head = 0;
1120
1121 rxq->rxd_count--;
1122
1123 skb_put(skb, pkt_len);
1124 mwl8k_remove_dma_header(skb, qos);
1125
1126 /*
1127 * Check for a pending join operation. Save a
1128 * copy of the beacon and schedule a tasklet to
1129 * send a FINALIZE_JOIN command to the firmware.
1130 */
1131 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1132 mwl8k_save_beacon(hw, skb);
1133
1134 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1135 ieee80211_rx_irqsafe(hw, skb);
1136
1137 processed++;
1138 }
1139
1140 return processed;
1141 }
1142
1143
1144 /*
1145 * Packet transmission.
1146 */
1147
1148 /* Transmit packet ACK policy */
1149 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
1150 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1151
1152 #define MWL8K_TXD_STATUS_OK 0x00000001
1153 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1154 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1155 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1156 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1157
1158 struct mwl8k_tx_desc {
1159 __le32 status;
1160 __u8 data_rate;
1161 __u8 tx_priority;
1162 __le16 qos_control;
1163 __le32 pkt_phys_addr;
1164 __le16 pkt_len;
1165 __u8 dest_MAC_addr[ETH_ALEN];
1166 __le32 next_txd_phys_addr;
1167 __le32 reserved;
1168 __le16 rate_info;
1169 __u8 peer_id;
1170 __u8 tx_frag_cnt;
1171 } __attribute__((packed));
1172
1173 #define MWL8K_TX_DESCS 128
1174
1175 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1176 {
1177 struct mwl8k_priv *priv = hw->priv;
1178 struct mwl8k_tx_queue *txq = priv->txq + index;
1179 int size;
1180 int i;
1181
1182 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1183 txq->stats.limit = MWL8K_TX_DESCS;
1184 txq->head = 0;
1185 txq->tail = 0;
1186
1187 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1188
1189 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1190 if (txq->txd == NULL) {
1191 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1192 wiphy_name(hw->wiphy));
1193 return -ENOMEM;
1194 }
1195 memset(txq->txd, 0, size);
1196
1197 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1198 if (txq->skb == NULL) {
1199 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1200 wiphy_name(hw->wiphy));
1201 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1202 return -ENOMEM;
1203 }
1204 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1205
1206 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1207 struct mwl8k_tx_desc *tx_desc;
1208 int nexti;
1209
1210 tx_desc = txq->txd + i;
1211 nexti = (i + 1) % MWL8K_TX_DESCS;
1212
1213 tx_desc->status = 0;
1214 tx_desc->next_txd_phys_addr =
1215 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1216 }
1217
1218 return 0;
1219 }
1220
1221 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1222 {
1223 iowrite32(MWL8K_H2A_INT_PPA_READY,
1224 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1225 iowrite32(MWL8K_H2A_INT_DUMMY,
1226 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1227 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1228 }
1229
1230 static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
1231 {
1232 struct mwl8k_priv *priv = hw->priv;
1233 int i;
1234
1235 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1236 struct mwl8k_tx_queue *txq = priv->txq + i;
1237 int fw_owned = 0;
1238 int drv_owned = 0;
1239 int unused = 0;
1240 int desc;
1241
1242 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1243 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1244 u32 status;
1245
1246 status = le32_to_cpu(tx_desc->status);
1247 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1248 fw_owned++;
1249 else
1250 drv_owned++;
1251
1252 if (tx_desc->pkt_len == 0)
1253 unused++;
1254 }
1255
1256 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1257 "fw_owned=%d drv_owned=%d unused=%d\n",
1258 wiphy_name(hw->wiphy), i,
1259 txq->stats.len, txq->head, txq->tail,
1260 fw_owned, drv_owned, unused);
1261 }
1262 }
1263
1264 /*
1265 * Must be called with priv->fw_mutex held and tx queues stopped.
1266 */
1267 #define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1268
1269 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1270 {
1271 struct mwl8k_priv *priv = hw->priv;
1272 DECLARE_COMPLETION_ONSTACK(tx_wait);
1273 int retry;
1274 int rc;
1275
1276 might_sleep();
1277
1278 /*
1279 * The TX queues are stopped at this point, so this test
1280 * doesn't need to take ->tx_lock.
1281 */
1282 if (!priv->pending_tx_pkts)
1283 return 0;
1284
1285 retry = 0;
1286 rc = 0;
1287
1288 spin_lock_bh(&priv->tx_lock);
1289 priv->tx_wait = &tx_wait;
1290 while (!rc) {
1291 int oldcount;
1292 unsigned long timeout;
1293
1294 oldcount = priv->pending_tx_pkts;
1295
1296 spin_unlock_bh(&priv->tx_lock);
1297 timeout = wait_for_completion_timeout(&tx_wait,
1298 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
1299 spin_lock_bh(&priv->tx_lock);
1300
1301 if (timeout) {
1302 WARN_ON(priv->pending_tx_pkts);
1303 if (retry) {
1304 printk(KERN_NOTICE "%s: tx rings drained\n",
1305 wiphy_name(hw->wiphy));
1306 }
1307 break;
1308 }
1309
1310 if (priv->pending_tx_pkts < oldcount) {
1311 printk(KERN_NOTICE "%s: timeout waiting for tx "
1312 "rings to drain (%d -> %d pkts), retrying\n",
1313 wiphy_name(hw->wiphy), oldcount,
1314 priv->pending_tx_pkts);
1315 retry = 1;
1316 continue;
1317 }
1318
1319 priv->tx_wait = NULL;
1320
1321 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1322 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1323 mwl8k_dump_tx_rings(hw);
1324
1325 rc = -ETIMEDOUT;
1326 }
1327 spin_unlock_bh(&priv->tx_lock);
1328
1329 return rc;
1330 }
1331
1332 #define MWL8K_TXD_SUCCESS(status) \
1333 ((status) & (MWL8K_TXD_STATUS_OK | \
1334 MWL8K_TXD_STATUS_OK_RETRY | \
1335 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1336
1337 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1338 {
1339 struct mwl8k_priv *priv = hw->priv;
1340 struct mwl8k_tx_queue *txq = priv->txq + index;
1341 int wake = 0;
1342
1343 while (txq->stats.len > 0) {
1344 int tx;
1345 struct mwl8k_tx_desc *tx_desc;
1346 unsigned long addr;
1347 int size;
1348 struct sk_buff *skb;
1349 struct ieee80211_tx_info *info;
1350 u32 status;
1351
1352 tx = txq->head;
1353 tx_desc = txq->txd + tx;
1354
1355 status = le32_to_cpu(tx_desc->status);
1356
1357 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1358 if (!force)
1359 break;
1360 tx_desc->status &=
1361 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1362 }
1363
1364 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1365 BUG_ON(txq->stats.len == 0);
1366 txq->stats.len--;
1367 priv->pending_tx_pkts--;
1368
1369 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1370 size = le16_to_cpu(tx_desc->pkt_len);
1371 skb = txq->skb[tx];
1372 txq->skb[tx] = NULL;
1373
1374 BUG_ON(skb == NULL);
1375 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1376
1377 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1378
1379 /* Mark descriptor as unused */
1380 tx_desc->pkt_phys_addr = 0;
1381 tx_desc->pkt_len = 0;
1382
1383 info = IEEE80211_SKB_CB(skb);
1384 ieee80211_tx_info_clear_status(info);
1385 if (MWL8K_TXD_SUCCESS(status))
1386 info->flags |= IEEE80211_TX_STAT_ACK;
1387
1388 ieee80211_tx_status_irqsafe(hw, skb);
1389
1390 wake = 1;
1391 }
1392
1393 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1394 ieee80211_wake_queue(hw, index);
1395 }
1396
1397 /* must be called only when the card's transmit is completely halted */
1398 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1399 {
1400 struct mwl8k_priv *priv = hw->priv;
1401 struct mwl8k_tx_queue *txq = priv->txq + index;
1402
1403 mwl8k_txq_reclaim(hw, index, 1);
1404
1405 kfree(txq->skb);
1406 txq->skb = NULL;
1407
1408 pci_free_consistent(priv->pdev,
1409 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1410 txq->txd, txq->txd_dma);
1411 txq->txd = NULL;
1412 }
1413
1414 static int
1415 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1416 {
1417 struct mwl8k_priv *priv = hw->priv;
1418 struct ieee80211_tx_info *tx_info;
1419 struct mwl8k_vif *mwl8k_vif;
1420 struct ieee80211_hdr *wh;
1421 struct mwl8k_tx_queue *txq;
1422 struct mwl8k_tx_desc *tx;
1423 dma_addr_t dma;
1424 u32 txstatus;
1425 u8 txdatarate;
1426 u16 qos;
1427
1428 wh = (struct ieee80211_hdr *)skb->data;
1429 if (ieee80211_is_data_qos(wh->frame_control))
1430 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1431 else
1432 qos = 0;
1433
1434 mwl8k_add_dma_header(skb);
1435 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1436
1437 tx_info = IEEE80211_SKB_CB(skb);
1438 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1439
1440 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1441 u16 seqno = mwl8k_vif->seqno;
1442
1443 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1444 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1445 mwl8k_vif->seqno = seqno++ % 4096;
1446 }
1447
1448 /* Setup firmware control bit fields for each frame type. */
1449 txstatus = 0;
1450 txdatarate = 0;
1451 if (ieee80211_is_mgmt(wh->frame_control) ||
1452 ieee80211_is_ctl(wh->frame_control)) {
1453 txdatarate = 0;
1454 qos = mwl8k_qos_setbit_eosp(qos);
1455 /* Set Queue size to unspecified */
1456 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1457 } else if (ieee80211_is_data(wh->frame_control)) {
1458 txdatarate = 1;
1459 if (is_multicast_ether_addr(wh->addr1))
1460 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1461
1462 /* Send pkt in an aggregate if AMPDU frame. */
1463 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1464 qos = mwl8k_qos_setbit_ack(qos,
1465 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1466 else
1467 qos = mwl8k_qos_setbit_ack(qos,
1468 MWL8K_TXD_ACK_POLICY_NORMAL);
1469 }
1470
1471 dma = pci_map_single(priv->pdev, skb->data,
1472 skb->len, PCI_DMA_TODEVICE);
1473
1474 if (pci_dma_mapping_error(priv->pdev, dma)) {
1475 printk(KERN_DEBUG "%s: failed to dma map skb, "
1476 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1477 dev_kfree_skb(skb);
1478 return NETDEV_TX_OK;
1479 }
1480
1481 spin_lock_bh(&priv->tx_lock);
1482
1483 txq = priv->txq + index;
1484
1485 BUG_ON(txq->skb[txq->tail] != NULL);
1486 txq->skb[txq->tail] = skb;
1487
1488 tx = txq->txd + txq->tail;
1489 tx->data_rate = txdatarate;
1490 tx->tx_priority = index;
1491 tx->qos_control = cpu_to_le16(qos);
1492 tx->pkt_phys_addr = cpu_to_le32(dma);
1493 tx->pkt_len = cpu_to_le16(skb->len);
1494 tx->rate_info = 0;
1495 tx->peer_id = mwl8k_vif->peer_id;
1496 wmb();
1497 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1498
1499 txq->stats.count++;
1500 txq->stats.len++;
1501 priv->pending_tx_pkts++;
1502
1503 txq->tail++;
1504 if (txq->tail == MWL8K_TX_DESCS)
1505 txq->tail = 0;
1506
1507 if (txq->head == txq->tail)
1508 ieee80211_stop_queue(hw, index);
1509
1510 mwl8k_tx_start(priv);
1511
1512 spin_unlock_bh(&priv->tx_lock);
1513
1514 return NETDEV_TX_OK;
1515 }
1516
1517
1518 /*
1519 * Firmware access.
1520 *
1521 * We have the following requirements for issuing firmware commands:
1522 * - Some commands require that the packet transmit path is idle when
1523 * the command is issued. (For simplicity, we'll just quiesce the
1524 * transmit path for every command.)
1525 * - There are certain sequences of commands that need to be issued to
1526 * the hardware sequentially, with no other intervening commands.
1527 *
1528 * This leads to an implementation of a "firmware lock" as a mutex that
1529 * can be taken recursively, and which is taken by both the low-level
1530 * command submission function (mwl8k_post_cmd) as well as any users of
1531 * that function that require issuing of an atomic sequence of commands,
1532 * and quiesces the transmit path whenever it's taken.
1533 */
1534 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1535 {
1536 struct mwl8k_priv *priv = hw->priv;
1537
1538 if (priv->fw_mutex_owner != current) {
1539 int rc;
1540
1541 mutex_lock(&priv->fw_mutex);
1542 ieee80211_stop_queues(hw);
1543
1544 rc = mwl8k_tx_wait_empty(hw);
1545 if (rc) {
1546 ieee80211_wake_queues(hw);
1547 mutex_unlock(&priv->fw_mutex);
1548
1549 return rc;
1550 }
1551
1552 priv->fw_mutex_owner = current;
1553 }
1554
1555 priv->fw_mutex_depth++;
1556
1557 return 0;
1558 }
1559
1560 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1561 {
1562 struct mwl8k_priv *priv = hw->priv;
1563
1564 if (!--priv->fw_mutex_depth) {
1565 ieee80211_wake_queues(hw);
1566 priv->fw_mutex_owner = NULL;
1567 mutex_unlock(&priv->fw_mutex);
1568 }
1569 }
1570
1571
1572 /*
1573 * Command processing.
1574 */
1575
1576 /* Timeout firmware commands after 10s */
1577 #define MWL8K_CMD_TIMEOUT_MS 10000
1578
1579 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1580 {
1581 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1582 struct mwl8k_priv *priv = hw->priv;
1583 void __iomem *regs = priv->regs;
1584 dma_addr_t dma_addr;
1585 unsigned int dma_size;
1586 int rc;
1587 unsigned long timeout = 0;
1588 u8 buf[32];
1589
1590 cmd->result = 0xffff;
1591 dma_size = le16_to_cpu(cmd->length);
1592 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1593 PCI_DMA_BIDIRECTIONAL);
1594 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1595 return -ENOMEM;
1596
1597 rc = mwl8k_fw_lock(hw);
1598 if (rc) {
1599 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1600 PCI_DMA_BIDIRECTIONAL);
1601 return rc;
1602 }
1603
1604 priv->hostcmd_wait = &cmd_wait;
1605 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1606 iowrite32(MWL8K_H2A_INT_DOORBELL,
1607 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1608 iowrite32(MWL8K_H2A_INT_DUMMY,
1609 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1610
1611 timeout = wait_for_completion_timeout(&cmd_wait,
1612 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1613
1614 priv->hostcmd_wait = NULL;
1615
1616 mwl8k_fw_unlock(hw);
1617
1618 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1619 PCI_DMA_BIDIRECTIONAL);
1620
1621 if (!timeout) {
1622 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1623 wiphy_name(hw->wiphy),
1624 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1625 MWL8K_CMD_TIMEOUT_MS);
1626 rc = -ETIMEDOUT;
1627 } else {
1628 int ms;
1629
1630 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1631
1632 rc = cmd->result ? -EINVAL : 0;
1633 if (rc)
1634 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1635 wiphy_name(hw->wiphy),
1636 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1637 le16_to_cpu(cmd->result));
1638 else if (ms > 2000)
1639 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1640 wiphy_name(hw->wiphy),
1641 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1642 ms);
1643 }
1644
1645 return rc;
1646 }
1647
1648 /*
1649 * CMD_GET_HW_SPEC (STA version).
1650 */
1651 struct mwl8k_cmd_get_hw_spec_sta {
1652 struct mwl8k_cmd_pkt header;
1653 __u8 hw_rev;
1654 __u8 host_interface;
1655 __le16 num_mcaddrs;
1656 __u8 perm_addr[ETH_ALEN];
1657 __le16 region_code;
1658 __le32 fw_rev;
1659 __le32 ps_cookie;
1660 __le32 caps;
1661 __u8 mcs_bitmap[16];
1662 __le32 rx_queue_ptr;
1663 __le32 num_tx_queues;
1664 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1665 __le32 caps2;
1666 __le32 num_tx_desc_per_queue;
1667 __le32 total_rxd;
1668 } __attribute__((packed));
1669
1670 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1671 {
1672 struct mwl8k_priv *priv = hw->priv;
1673 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1674 int rc;
1675 int i;
1676
1677 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1678 if (cmd == NULL)
1679 return -ENOMEM;
1680
1681 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1682 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1683
1684 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1685 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1686 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1687 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1688 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1689 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1690 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1691 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1692
1693 rc = mwl8k_post_cmd(hw, &cmd->header);
1694
1695 if (!rc) {
1696 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1697 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1698 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1699 priv->hw_rev = cmd->hw_rev;
1700 }
1701
1702 kfree(cmd);
1703 return rc;
1704 }
1705
1706 /*
1707 * CMD_GET_HW_SPEC (AP version).
1708 */
1709 struct mwl8k_cmd_get_hw_spec_ap {
1710 struct mwl8k_cmd_pkt header;
1711 __u8 hw_rev;
1712 __u8 host_interface;
1713 __le16 num_wcb;
1714 __le16 num_mcaddrs;
1715 __u8 perm_addr[ETH_ALEN];
1716 __le16 region_code;
1717 __le16 num_antenna;
1718 __le32 fw_rev;
1719 __le32 wcbbase0;
1720 __le32 rxwrptr;
1721 __le32 rxrdptr;
1722 __le32 ps_cookie;
1723 __le32 wcbbase1;
1724 __le32 wcbbase2;
1725 __le32 wcbbase3;
1726 } __attribute__((packed));
1727
1728 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1729 {
1730 struct mwl8k_priv *priv = hw->priv;
1731 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1732 int rc;
1733
1734 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1735 if (cmd == NULL)
1736 return -ENOMEM;
1737
1738 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1739 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1740
1741 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1742 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1743
1744 rc = mwl8k_post_cmd(hw, &cmd->header);
1745
1746 if (!rc) {
1747 int off;
1748
1749 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1750 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1751 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1752 priv->hw_rev = cmd->hw_rev;
1753
1754 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1755 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1756
1757 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1758 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1759
1760 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1761 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1762
1763 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1764 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1765
1766 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1767 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1768
1769 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1770 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1771 }
1772
1773 kfree(cmd);
1774 return rc;
1775 }
1776
1777 /*
1778 * CMD_SET_HW_SPEC.
1779 */
1780 struct mwl8k_cmd_set_hw_spec {
1781 struct mwl8k_cmd_pkt header;
1782 __u8 hw_rev;
1783 __u8 host_interface;
1784 __le16 num_mcaddrs;
1785 __u8 perm_addr[ETH_ALEN];
1786 __le16 region_code;
1787 __le32 fw_rev;
1788 __le32 ps_cookie;
1789 __le32 caps;
1790 __le32 rx_queue_ptr;
1791 __le32 num_tx_queues;
1792 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1793 __le32 flags;
1794 __le32 num_tx_desc_per_queue;
1795 __le32 total_rxd;
1796 } __attribute__((packed));
1797
1798 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1799
1800 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1801 {
1802 struct mwl8k_priv *priv = hw->priv;
1803 struct mwl8k_cmd_set_hw_spec *cmd;
1804 int rc;
1805 int i;
1806
1807 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1808 if (cmd == NULL)
1809 return -ENOMEM;
1810
1811 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1812 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1813
1814 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1815 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1816 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1817 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1818 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1819 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1820 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1821 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1822
1823 rc = mwl8k_post_cmd(hw, &cmd->header);
1824 kfree(cmd);
1825
1826 return rc;
1827 }
1828
1829 /*
1830 * CMD_MAC_MULTICAST_ADR.
1831 */
1832 struct mwl8k_cmd_mac_multicast_adr {
1833 struct mwl8k_cmd_pkt header;
1834 __le16 action;
1835 __le16 numaddr;
1836 __u8 addr[0][ETH_ALEN];
1837 };
1838
1839 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1840 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1841 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1842 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1843
1844 static struct mwl8k_cmd_pkt *
1845 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1846 int mc_count, struct dev_addr_list *mclist)
1847 {
1848 struct mwl8k_priv *priv = hw->priv;
1849 struct mwl8k_cmd_mac_multicast_adr *cmd;
1850 int size;
1851
1852 if (allmulti || mc_count > priv->num_mcaddrs) {
1853 allmulti = 1;
1854 mc_count = 0;
1855 }
1856
1857 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1858
1859 cmd = kzalloc(size, GFP_ATOMIC);
1860 if (cmd == NULL)
1861 return NULL;
1862
1863 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1864 cmd->header.length = cpu_to_le16(size);
1865 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1866 MWL8K_ENABLE_RX_BROADCAST);
1867
1868 if (allmulti) {
1869 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1870 } else if (mc_count) {
1871 int i;
1872
1873 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1874 cmd->numaddr = cpu_to_le16(mc_count);
1875 for (i = 0; i < mc_count && mclist; i++) {
1876 if (mclist->da_addrlen != ETH_ALEN) {
1877 kfree(cmd);
1878 return NULL;
1879 }
1880 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1881 mclist = mclist->next;
1882 }
1883 }
1884
1885 return &cmd->header;
1886 }
1887
1888 /*
1889 * CMD_GET_STAT.
1890 */
1891 struct mwl8k_cmd_get_stat {
1892 struct mwl8k_cmd_pkt header;
1893 __le32 stats[64];
1894 } __attribute__((packed));
1895
1896 #define MWL8K_STAT_ACK_FAILURE 9
1897 #define MWL8K_STAT_RTS_FAILURE 12
1898 #define MWL8K_STAT_FCS_ERROR 24
1899 #define MWL8K_STAT_RTS_SUCCESS 11
1900
1901 static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1902 struct ieee80211_low_level_stats *stats)
1903 {
1904 struct mwl8k_cmd_get_stat *cmd;
1905 int rc;
1906
1907 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1908 if (cmd == NULL)
1909 return -ENOMEM;
1910
1911 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1912 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1913
1914 rc = mwl8k_post_cmd(hw, &cmd->header);
1915 if (!rc) {
1916 stats->dot11ACKFailureCount =
1917 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1918 stats->dot11RTSFailureCount =
1919 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1920 stats->dot11FCSErrorCount =
1921 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1922 stats->dot11RTSSuccessCount =
1923 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1924 }
1925 kfree(cmd);
1926
1927 return rc;
1928 }
1929
1930 /*
1931 * CMD_RADIO_CONTROL.
1932 */
1933 struct mwl8k_cmd_radio_control {
1934 struct mwl8k_cmd_pkt header;
1935 __le16 action;
1936 __le16 control;
1937 __le16 radio_on;
1938 } __attribute__((packed));
1939
1940 static int
1941 mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1942 {
1943 struct mwl8k_priv *priv = hw->priv;
1944 struct mwl8k_cmd_radio_control *cmd;
1945 int rc;
1946
1947 if (enable == priv->radio_on && !force)
1948 return 0;
1949
1950 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1951 if (cmd == NULL)
1952 return -ENOMEM;
1953
1954 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1955 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1956 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1957 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1958 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1959
1960 rc = mwl8k_post_cmd(hw, &cmd->header);
1961 kfree(cmd);
1962
1963 if (!rc)
1964 priv->radio_on = enable;
1965
1966 return rc;
1967 }
1968
1969 static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
1970 {
1971 return mwl8k_cmd_radio_control(hw, 0, 0);
1972 }
1973
1974 static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
1975 {
1976 return mwl8k_cmd_radio_control(hw, 1, 0);
1977 }
1978
1979 static int
1980 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1981 {
1982 struct mwl8k_priv *priv = hw->priv;
1983
1984 priv->radio_short_preamble = short_preamble;
1985
1986 return mwl8k_cmd_radio_control(hw, 1, 1);
1987 }
1988
1989 /*
1990 * CMD_RF_TX_POWER.
1991 */
1992 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1993
1994 struct mwl8k_cmd_rf_tx_power {
1995 struct mwl8k_cmd_pkt header;
1996 __le16 action;
1997 __le16 support_level;
1998 __le16 current_level;
1999 __le16 reserved;
2000 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2001 } __attribute__((packed));
2002
2003 static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2004 {
2005 struct mwl8k_cmd_rf_tx_power *cmd;
2006 int rc;
2007
2008 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2009 if (cmd == NULL)
2010 return -ENOMEM;
2011
2012 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2013 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2014 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2015 cmd->support_level = cpu_to_le16(dBm);
2016
2017 rc = mwl8k_post_cmd(hw, &cmd->header);
2018 kfree(cmd);
2019
2020 return rc;
2021 }
2022
2023 /*
2024 * CMD_RF_ANTENNA.
2025 */
2026 struct mwl8k_cmd_rf_antenna {
2027 struct mwl8k_cmd_pkt header;
2028 __le16 antenna;
2029 __le16 mode;
2030 } __attribute__((packed));
2031
2032 #define MWL8K_RF_ANTENNA_RX 1
2033 #define MWL8K_RF_ANTENNA_TX 2
2034
2035 static int
2036 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2037 {
2038 struct mwl8k_cmd_rf_antenna *cmd;
2039 int rc;
2040
2041 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2042 if (cmd == NULL)
2043 return -ENOMEM;
2044
2045 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2046 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2047 cmd->antenna = cpu_to_le16(antenna);
2048 cmd->mode = cpu_to_le16(mask);
2049
2050 rc = mwl8k_post_cmd(hw, &cmd->header);
2051 kfree(cmd);
2052
2053 return rc;
2054 }
2055
2056 /*
2057 * CMD_SET_PRE_SCAN.
2058 */
2059 struct mwl8k_cmd_set_pre_scan {
2060 struct mwl8k_cmd_pkt header;
2061 } __attribute__((packed));
2062
2063 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2064 {
2065 struct mwl8k_cmd_set_pre_scan *cmd;
2066 int rc;
2067
2068 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2069 if (cmd == NULL)
2070 return -ENOMEM;
2071
2072 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2073 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2074
2075 rc = mwl8k_post_cmd(hw, &cmd->header);
2076 kfree(cmd);
2077
2078 return rc;
2079 }
2080
2081 /*
2082 * CMD_SET_POST_SCAN.
2083 */
2084 struct mwl8k_cmd_set_post_scan {
2085 struct mwl8k_cmd_pkt header;
2086 __le32 isibss;
2087 __u8 bssid[ETH_ALEN];
2088 } __attribute__((packed));
2089
2090 static int
2091 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
2092 {
2093 struct mwl8k_cmd_set_post_scan *cmd;
2094 int rc;
2095
2096 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2097 if (cmd == NULL)
2098 return -ENOMEM;
2099
2100 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2101 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2102 cmd->isibss = 0;
2103 memcpy(cmd->bssid, mac, ETH_ALEN);
2104
2105 rc = mwl8k_post_cmd(hw, &cmd->header);
2106 kfree(cmd);
2107
2108 return rc;
2109 }
2110
2111 /*
2112 * CMD_SET_RF_CHANNEL.
2113 */
2114 struct mwl8k_cmd_set_rf_channel {
2115 struct mwl8k_cmd_pkt header;
2116 __le16 action;
2117 __u8 current_channel;
2118 __le32 channel_flags;
2119 } __attribute__((packed));
2120
2121 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2122 struct ieee80211_channel *channel)
2123 {
2124 struct mwl8k_cmd_set_rf_channel *cmd;
2125 int rc;
2126
2127 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2128 if (cmd == NULL)
2129 return -ENOMEM;
2130
2131 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2132 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2133 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2134 cmd->current_channel = channel->hw_value;
2135 if (channel->band == IEEE80211_BAND_2GHZ)
2136 cmd->channel_flags = cpu_to_le32(0x00000081);
2137 else
2138 cmd->channel_flags = cpu_to_le32(0x00000000);
2139
2140 rc = mwl8k_post_cmd(hw, &cmd->header);
2141 kfree(cmd);
2142
2143 return rc;
2144 }
2145
2146 /*
2147 * CMD_SET_AID.
2148 */
2149 #define MWL8K_FRAME_PROT_DISABLED 0x00
2150 #define MWL8K_FRAME_PROT_11G 0x07
2151 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2152 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2153
2154 struct mwl8k_cmd_update_set_aid {
2155 struct mwl8k_cmd_pkt header;
2156 __le16 aid;
2157
2158 /* AP's MAC address (BSSID) */
2159 __u8 bssid[ETH_ALEN];
2160 __le16 protection_mode;
2161 __u8 supp_rates[14];
2162 } __attribute__((packed));
2163
2164 static int
2165 mwl8k_cmd_set_aid(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2166 {
2167 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2168 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2169 struct mwl8k_cmd_update_set_aid *cmd;
2170 u16 prot_mode;
2171 int rc;
2172
2173 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2174 if (cmd == NULL)
2175 return -ENOMEM;
2176
2177 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2178 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2179 cmd->aid = cpu_to_le16(info->aid);
2180
2181 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2182
2183 if (info->use_cts_prot) {
2184 prot_mode = MWL8K_FRAME_PROT_11G;
2185 } else {
2186 switch (info->ht_operation_mode &
2187 IEEE80211_HT_OP_MODE_PROTECTION) {
2188 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2189 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2190 break;
2191 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2192 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2193 break;
2194 default:
2195 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2196 break;
2197 }
2198 }
2199 cmd->protection_mode = cpu_to_le16(prot_mode);
2200
2201 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2202
2203 rc = mwl8k_post_cmd(hw, &cmd->header);
2204 kfree(cmd);
2205
2206 return rc;
2207 }
2208
2209 /*
2210 * CMD_SET_RATE.
2211 */
2212 struct mwl8k_cmd_set_rate {
2213 struct mwl8k_cmd_pkt header;
2214 __u8 legacy_rates[14];
2215
2216 /* Bitmap for supported MCS codes. */
2217 __u8 mcs_set[16];
2218 __u8 reserved[16];
2219 } __attribute__((packed));
2220
2221 static int
2222 mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2223 {
2224 struct mwl8k_cmd_set_rate *cmd;
2225 int rc;
2226
2227 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2228 if (cmd == NULL)
2229 return -ENOMEM;
2230
2231 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2232 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2233 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2234
2235 rc = mwl8k_post_cmd(hw, &cmd->header);
2236 kfree(cmd);
2237
2238 return rc;
2239 }
2240
2241 /*
2242 * CMD_FINALIZE_JOIN.
2243 */
2244 #define MWL8K_FJ_BEACON_MAXLEN 128
2245
2246 struct mwl8k_cmd_finalize_join {
2247 struct mwl8k_cmd_pkt header;
2248 __le32 sleep_interval; /* Number of beacon periods to sleep */
2249 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2250 } __attribute__((packed));
2251
2252 static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2253 int framelen, int dtim)
2254 {
2255 struct mwl8k_cmd_finalize_join *cmd;
2256 struct ieee80211_mgmt *payload = frame;
2257 int payload_len;
2258 int rc;
2259
2260 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2261 if (cmd == NULL)
2262 return -ENOMEM;
2263
2264 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2265 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2266 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2267
2268 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2269 if (payload_len < 0)
2270 payload_len = 0;
2271 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2272 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2273
2274 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2275
2276 rc = mwl8k_post_cmd(hw, &cmd->header);
2277 kfree(cmd);
2278
2279 return rc;
2280 }
2281
2282 /*
2283 * CMD_SET_RTS_THRESHOLD.
2284 */
2285 struct mwl8k_cmd_set_rts_threshold {
2286 struct mwl8k_cmd_pkt header;
2287 __le16 action;
2288 __le16 threshold;
2289 } __attribute__((packed));
2290
2291 static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw,
2292 u16 action, u16 threshold)
2293 {
2294 struct mwl8k_cmd_set_rts_threshold *cmd;
2295 int rc;
2296
2297 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2298 if (cmd == NULL)
2299 return -ENOMEM;
2300
2301 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2302 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2303 cmd->action = cpu_to_le16(action);
2304 cmd->threshold = cpu_to_le16(threshold);
2305
2306 rc = mwl8k_post_cmd(hw, &cmd->header);
2307 kfree(cmd);
2308
2309 return rc;
2310 }
2311
2312 /*
2313 * CMD_SET_SLOT.
2314 */
2315 struct mwl8k_cmd_set_slot {
2316 struct mwl8k_cmd_pkt header;
2317 __le16 action;
2318 __u8 short_slot;
2319 } __attribute__((packed));
2320
2321 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2322 {
2323 struct mwl8k_cmd_set_slot *cmd;
2324 int rc;
2325
2326 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2327 if (cmd == NULL)
2328 return -ENOMEM;
2329
2330 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2331 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2332 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2333 cmd->short_slot = short_slot_time;
2334
2335 rc = mwl8k_post_cmd(hw, &cmd->header);
2336 kfree(cmd);
2337
2338 return rc;
2339 }
2340
2341 /*
2342 * CMD_SET_EDCA_PARAMS.
2343 */
2344 struct mwl8k_cmd_set_edca_params {
2345 struct mwl8k_cmd_pkt header;
2346
2347 /* See MWL8K_SET_EDCA_XXX below */
2348 __le16 action;
2349
2350 /* TX opportunity in units of 32 us */
2351 __le16 txop;
2352
2353 union {
2354 struct {
2355 /* Log exponent of max contention period: 0...15 */
2356 __le32 log_cw_max;
2357
2358 /* Log exponent of min contention period: 0...15 */
2359 __le32 log_cw_min;
2360
2361 /* Adaptive interframe spacing in units of 32us */
2362 __u8 aifs;
2363
2364 /* TX queue to configure */
2365 __u8 txq;
2366 } ap;
2367 struct {
2368 /* Log exponent of max contention period: 0...15 */
2369 __u8 log_cw_max;
2370
2371 /* Log exponent of min contention period: 0...15 */
2372 __u8 log_cw_min;
2373
2374 /* Adaptive interframe spacing in units of 32us */
2375 __u8 aifs;
2376
2377 /* TX queue to configure */
2378 __u8 txq;
2379 } sta;
2380 };
2381 } __attribute__((packed));
2382
2383 #define MWL8K_SET_EDCA_CW 0x01
2384 #define MWL8K_SET_EDCA_TXOP 0x02
2385 #define MWL8K_SET_EDCA_AIFS 0x04
2386
2387 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2388 MWL8K_SET_EDCA_TXOP | \
2389 MWL8K_SET_EDCA_AIFS)
2390
2391 static int
2392 mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2393 __u16 cw_min, __u16 cw_max,
2394 __u8 aifs, __u16 txop)
2395 {
2396 struct mwl8k_priv *priv = hw->priv;
2397 struct mwl8k_cmd_set_edca_params *cmd;
2398 int rc;
2399
2400 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2401 if (cmd == NULL)
2402 return -ENOMEM;
2403
2404 /*
2405 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2406 * this call.
2407 */
2408 qnum ^= !(qnum >> 1);
2409
2410 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2411 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2412 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2413 cmd->txop = cpu_to_le16(txop);
2414 if (priv->ap_fw) {
2415 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2416 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2417 cmd->ap.aifs = aifs;
2418 cmd->ap.txq = qnum;
2419 } else {
2420 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2421 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2422 cmd->sta.aifs = aifs;
2423 cmd->sta.txq = qnum;
2424 }
2425
2426 rc = mwl8k_post_cmd(hw, &cmd->header);
2427 kfree(cmd);
2428
2429 return rc;
2430 }
2431
2432 /*
2433 * CMD_SET_WMM_MODE.
2434 */
2435 struct mwl8k_cmd_set_wmm_mode {
2436 struct mwl8k_cmd_pkt header;
2437 __le16 action;
2438 } __attribute__((packed));
2439
2440 static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
2441 {
2442 struct mwl8k_priv *priv = hw->priv;
2443 struct mwl8k_cmd_set_wmm_mode *cmd;
2444 int rc;
2445
2446 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2447 if (cmd == NULL)
2448 return -ENOMEM;
2449
2450 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2451 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2452 cmd->action = cpu_to_le16(!!enable);
2453
2454 rc = mwl8k_post_cmd(hw, &cmd->header);
2455 kfree(cmd);
2456
2457 if (!rc)
2458 priv->wmm_enabled = enable;
2459
2460 return rc;
2461 }
2462
2463 /*
2464 * CMD_MIMO_CONFIG.
2465 */
2466 struct mwl8k_cmd_mimo_config {
2467 struct mwl8k_cmd_pkt header;
2468 __le32 action;
2469 __u8 rx_antenna_map;
2470 __u8 tx_antenna_map;
2471 } __attribute__((packed));
2472
2473 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2474 {
2475 struct mwl8k_cmd_mimo_config *cmd;
2476 int rc;
2477
2478 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2479 if (cmd == NULL)
2480 return -ENOMEM;
2481
2482 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2483 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2484 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2485 cmd->rx_antenna_map = rx;
2486 cmd->tx_antenna_map = tx;
2487
2488 rc = mwl8k_post_cmd(hw, &cmd->header);
2489 kfree(cmd);
2490
2491 return rc;
2492 }
2493
2494 /*
2495 * CMD_USE_FIXED_RATE.
2496 */
2497 #define MWL8K_RATE_TABLE_SIZE 8
2498 #define MWL8K_UCAST_RATE 0
2499 #define MWL8K_USE_AUTO_RATE 0x0002
2500
2501 struct mwl8k_rate_entry {
2502 /* Set to 1 if HT rate, 0 if legacy. */
2503 __le32 is_ht_rate;
2504
2505 /* Set to 1 to use retry_count field. */
2506 __le32 enable_retry;
2507
2508 /* Specified legacy rate or MCS. */
2509 __le32 rate;
2510
2511 /* Number of allowed retries. */
2512 __le32 retry_count;
2513 } __attribute__((packed));
2514
2515 struct mwl8k_rate_table {
2516 /* 1 to allow specified rate and below */
2517 __le32 allow_rate_drop;
2518 __le32 num_rates;
2519 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2520 } __attribute__((packed));
2521
2522 struct mwl8k_cmd_use_fixed_rate {
2523 struct mwl8k_cmd_pkt header;
2524 __le32 action;
2525 struct mwl8k_rate_table rate_table;
2526
2527 /* Unicast, Broadcast or Multicast */
2528 __le32 rate_type;
2529 __le32 reserved1;
2530 __le32 reserved2;
2531 } __attribute__((packed));
2532
2533 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2534 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2535 {
2536 struct mwl8k_cmd_use_fixed_rate *cmd;
2537 int count;
2538 int rc;
2539
2540 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2541 if (cmd == NULL)
2542 return -ENOMEM;
2543
2544 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2545 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2546
2547 cmd->action = cpu_to_le32(action);
2548 cmd->rate_type = cpu_to_le32(rate_type);
2549
2550 if (rate_table != NULL) {
2551 /*
2552 * Copy over each field manually so that endian
2553 * conversion can be done.
2554 */
2555 cmd->rate_table.allow_rate_drop =
2556 cpu_to_le32(rate_table->allow_rate_drop);
2557 cmd->rate_table.num_rates =
2558 cpu_to_le32(rate_table->num_rates);
2559
2560 for (count = 0; count < rate_table->num_rates; count++) {
2561 struct mwl8k_rate_entry *dst =
2562 &cmd->rate_table.rate_entry[count];
2563 struct mwl8k_rate_entry *src =
2564 &rate_table->rate_entry[count];
2565
2566 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2567 dst->enable_retry = cpu_to_le32(src->enable_retry);
2568 dst->rate = cpu_to_le32(src->rate);
2569 dst->retry_count = cpu_to_le32(src->retry_count);
2570 }
2571 }
2572
2573 rc = mwl8k_post_cmd(hw, &cmd->header);
2574 kfree(cmd);
2575
2576 return rc;
2577 }
2578
2579 /*
2580 * CMD_ENABLE_SNIFFER.
2581 */
2582 struct mwl8k_cmd_enable_sniffer {
2583 struct mwl8k_cmd_pkt header;
2584 __le32 action;
2585 } __attribute__((packed));
2586
2587 static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2588 {
2589 struct mwl8k_cmd_enable_sniffer *cmd;
2590 int rc;
2591
2592 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2593 if (cmd == NULL)
2594 return -ENOMEM;
2595
2596 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2597 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2598 cmd->action = cpu_to_le32(!!enable);
2599
2600 rc = mwl8k_post_cmd(hw, &cmd->header);
2601 kfree(cmd);
2602
2603 return rc;
2604 }
2605
2606 /*
2607 * CMD_SET_MAC_ADDR.
2608 */
2609 struct mwl8k_cmd_set_mac_addr {
2610 struct mwl8k_cmd_pkt header;
2611 union {
2612 struct {
2613 __le16 mac_type;
2614 __u8 mac_addr[ETH_ALEN];
2615 } mbss;
2616 __u8 mac_addr[ETH_ALEN];
2617 };
2618 } __attribute__((packed));
2619
2620 static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2621 {
2622 struct mwl8k_priv *priv = hw->priv;
2623 struct mwl8k_cmd_set_mac_addr *cmd;
2624 int rc;
2625
2626 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2627 if (cmd == NULL)
2628 return -ENOMEM;
2629
2630 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2631 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2632 if (priv->ap_fw) {
2633 cmd->mbss.mac_type = 0;
2634 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2635 } else {
2636 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2637 }
2638
2639 rc = mwl8k_post_cmd(hw, &cmd->header);
2640 kfree(cmd);
2641
2642 return rc;
2643 }
2644
2645 /*
2646 * CMD_SET_RATEADAPT_MODE.
2647 */
2648 struct mwl8k_cmd_set_rate_adapt_mode {
2649 struct mwl8k_cmd_pkt header;
2650 __le16 action;
2651 __le16 mode;
2652 } __attribute__((packed));
2653
2654 static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2655 {
2656 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2657 int rc;
2658
2659 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2660 if (cmd == NULL)
2661 return -ENOMEM;
2662
2663 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2664 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2665 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2666 cmd->mode = cpu_to_le16(mode);
2667
2668 rc = mwl8k_post_cmd(hw, &cmd->header);
2669 kfree(cmd);
2670
2671 return rc;
2672 }
2673
2674 /*
2675 * CMD_UPDATE_STADB.
2676 */
2677 struct mwl8k_cmd_update_stadb {
2678 struct mwl8k_cmd_pkt header;
2679
2680 /* See STADB_ACTION_TYPE */
2681 __le32 action;
2682
2683 /* Peer MAC address */
2684 __u8 peer_addr[ETH_ALEN];
2685
2686 __le32 reserved;
2687
2688 /* Peer info - valid during add/update. */
2689 struct peer_capability_info peer_info;
2690 } __attribute__((packed));
2691
2692 static int mwl8k_cmd_update_stadb(struct ieee80211_hw *hw,
2693 struct ieee80211_vif *vif, __u32 action)
2694 {
2695 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2696 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2697 struct mwl8k_cmd_update_stadb *cmd;
2698 struct peer_capability_info *peer_info;
2699 int rc;
2700
2701 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2702 if (cmd == NULL)
2703 return -ENOMEM;
2704
2705 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2706 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2707
2708 cmd->action = cpu_to_le32(action);
2709 peer_info = &cmd->peer_info;
2710 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2711
2712 switch (action) {
2713 case MWL8K_STA_DB_ADD_ENTRY:
2714 case MWL8K_STA_DB_MODIFY_ENTRY:
2715 /* Build peer_info block */
2716 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2717 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2718 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2719 sizeof(mwl8k_rateids));
2720 peer_info->interop = 1;
2721 peer_info->amsdu_enabled = 0;
2722
2723 rc = mwl8k_post_cmd(hw, &cmd->header);
2724 if (rc == 0)
2725 mv_vif->peer_id = peer_info->station_id;
2726
2727 break;
2728
2729 case MWL8K_STA_DB_DEL_ENTRY:
2730 case MWL8K_STA_DB_FLUSH:
2731 default:
2732 rc = mwl8k_post_cmd(hw, &cmd->header);
2733 if (rc == 0)
2734 mv_vif->peer_id = 0;
2735 break;
2736 }
2737 kfree(cmd);
2738
2739 return rc;
2740 }
2741
2742
2743 /*
2744 * Interrupt handling.
2745 */
2746 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2747 {
2748 struct ieee80211_hw *hw = dev_id;
2749 struct mwl8k_priv *priv = hw->priv;
2750 u32 status;
2751
2752 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2753 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2754
2755 if (!status)
2756 return IRQ_NONE;
2757
2758 if (status & MWL8K_A2H_INT_TX_DONE)
2759 tasklet_schedule(&priv->tx_reclaim_task);
2760
2761 if (status & MWL8K_A2H_INT_RX_READY) {
2762 while (rxq_process(hw, 0, 1))
2763 rxq_refill(hw, 0, 1);
2764 }
2765
2766 if (status & MWL8K_A2H_INT_OPC_DONE) {
2767 if (priv->hostcmd_wait != NULL)
2768 complete(priv->hostcmd_wait);
2769 }
2770
2771 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2772 if (!mutex_is_locked(&priv->fw_mutex) &&
2773 priv->radio_on && priv->pending_tx_pkts)
2774 mwl8k_tx_start(priv);
2775 }
2776
2777 return IRQ_HANDLED;
2778 }
2779
2780
2781 /*
2782 * Core driver operations.
2783 */
2784 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2785 {
2786 struct mwl8k_priv *priv = hw->priv;
2787 int index = skb_get_queue_mapping(skb);
2788 int rc;
2789
2790 if (priv->current_channel == NULL) {
2791 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2792 "disabled\n", wiphy_name(hw->wiphy));
2793 dev_kfree_skb(skb);
2794 return NETDEV_TX_OK;
2795 }
2796
2797 rc = mwl8k_txq_xmit(hw, index, skb);
2798
2799 return rc;
2800 }
2801
2802 static int mwl8k_start(struct ieee80211_hw *hw)
2803 {
2804 struct mwl8k_priv *priv = hw->priv;
2805 int rc;
2806
2807 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2808 IRQF_SHARED, MWL8K_NAME, hw);
2809 if (rc) {
2810 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2811 wiphy_name(hw->wiphy));
2812 return -EIO;
2813 }
2814
2815 /* Enable tx reclaim tasklet */
2816 tasklet_enable(&priv->tx_reclaim_task);
2817
2818 /* Enable interrupts */
2819 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2820
2821 rc = mwl8k_fw_lock(hw);
2822 if (!rc) {
2823 rc = mwl8k_cmd_radio_enable(hw);
2824
2825 if (!priv->ap_fw) {
2826 if (!rc)
2827 rc = mwl8k_cmd_enable_sniffer(hw, 0);
2828
2829 if (!rc)
2830 rc = mwl8k_cmd_set_pre_scan(hw);
2831
2832 if (!rc)
2833 rc = mwl8k_cmd_set_post_scan(hw,
2834 "\x00\x00\x00\x00\x00\x00");
2835 }
2836
2837 if (!rc)
2838 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
2839
2840 if (!rc)
2841 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
2842
2843 mwl8k_fw_unlock(hw);
2844 }
2845
2846 if (rc) {
2847 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2848 free_irq(priv->pdev->irq, hw);
2849 tasklet_disable(&priv->tx_reclaim_task);
2850 }
2851
2852 return rc;
2853 }
2854
2855 static void mwl8k_stop(struct ieee80211_hw *hw)
2856 {
2857 struct mwl8k_priv *priv = hw->priv;
2858 int i;
2859
2860 mwl8k_cmd_radio_disable(hw);
2861
2862 ieee80211_stop_queues(hw);
2863
2864 /* Disable interrupts */
2865 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2866 free_irq(priv->pdev->irq, hw);
2867
2868 /* Stop finalize join worker */
2869 cancel_work_sync(&priv->finalize_join_worker);
2870 if (priv->beacon_skb != NULL)
2871 dev_kfree_skb(priv->beacon_skb);
2872
2873 /* Stop tx reclaim tasklet */
2874 tasklet_disable(&priv->tx_reclaim_task);
2875
2876 /* Return all skbs to mac80211 */
2877 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2878 mwl8k_txq_reclaim(hw, i, 1);
2879 }
2880
2881 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2882 struct ieee80211_if_init_conf *conf)
2883 {
2884 struct mwl8k_priv *priv = hw->priv;
2885 struct mwl8k_vif *mwl8k_vif;
2886
2887 /*
2888 * We only support one active interface at a time.
2889 */
2890 if (priv->vif != NULL)
2891 return -EBUSY;
2892
2893 /*
2894 * We only support managed interfaces for now.
2895 */
2896 if (conf->type != NL80211_IFTYPE_STATION)
2897 return -EINVAL;
2898
2899 /*
2900 * Reject interface creation if sniffer mode is active, as
2901 * STA operation is mutually exclusive with hardware sniffer
2902 * mode.
2903 */
2904 if (priv->sniffer_enabled) {
2905 printk(KERN_INFO "%s: unable to create STA "
2906 "interface due to sniffer mode being enabled\n",
2907 wiphy_name(hw->wiphy));
2908 return -EINVAL;
2909 }
2910
2911 /* Clean out driver private area */
2912 mwl8k_vif = MWL8K_VIF(conf->vif);
2913 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2914
2915 /* Set and save the mac address */
2916 mwl8k_cmd_set_mac_addr(hw, conf->mac_addr);
2917 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2918
2919 /* Back pointer to parent config block */
2920 mwl8k_vif->priv = priv;
2921
2922 /* Set Initial sequence number to zero */
2923 mwl8k_vif->seqno = 0;
2924
2925 priv->vif = conf->vif;
2926 priv->current_channel = NULL;
2927
2928 return 0;
2929 }
2930
2931 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2932 struct ieee80211_if_init_conf *conf)
2933 {
2934 struct mwl8k_priv *priv = hw->priv;
2935
2936 if (priv->vif == NULL)
2937 return;
2938
2939 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2940
2941 priv->vif = NULL;
2942 }
2943
2944 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2945 {
2946 struct ieee80211_conf *conf = &hw->conf;
2947 struct mwl8k_priv *priv = hw->priv;
2948 int rc;
2949
2950 if (conf->flags & IEEE80211_CONF_IDLE) {
2951 mwl8k_cmd_radio_disable(hw);
2952 priv->current_channel = NULL;
2953 return 0;
2954 }
2955
2956 rc = mwl8k_fw_lock(hw);
2957 if (rc)
2958 return rc;
2959
2960 rc = mwl8k_cmd_radio_enable(hw);
2961 if (rc)
2962 goto out;
2963
2964 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2965 if (rc)
2966 goto out;
2967
2968 priv->current_channel = conf->channel;
2969
2970 if (conf->power_level > 18)
2971 conf->power_level = 18;
2972 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
2973 if (rc)
2974 goto out;
2975
2976 if (priv->ap_fw) {
2977 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2978 if (!rc)
2979 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2980 } else {
2981 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2982 }
2983
2984 out:
2985 mwl8k_fw_unlock(hw);
2986
2987 return rc;
2988 }
2989
2990 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2991 struct ieee80211_vif *vif,
2992 struct ieee80211_bss_conf *info,
2993 u32 changed)
2994 {
2995 struct mwl8k_priv *priv = hw->priv;
2996 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2997 int rc;
2998
2999 if ((changed & BSS_CHANGED_ASSOC) == 0)
3000 return;
3001
3002 priv->capture_beacon = false;
3003
3004 rc = mwl8k_fw_lock(hw);
3005 if (rc)
3006 return;
3007
3008 if (info->assoc) {
3009 memcpy(&mwl8k_vif->bss_info, info,
3010 sizeof(struct ieee80211_bss_conf));
3011
3012 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3013
3014 /* Install rates */
3015 rc = mwl8k_cmd_set_rate(hw, vif);
3016 if (rc)
3017 goto out;
3018
3019 /* Turn on rate adaptation */
3020 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3021 MWL8K_UCAST_RATE, NULL);
3022 if (rc)
3023 goto out;
3024
3025 /* Set radio preamble */
3026 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3027 if (rc)
3028 goto out;
3029
3030 /* Set slot time */
3031 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3032 if (rc)
3033 goto out;
3034
3035 /* Update peer rate info */
3036 rc = mwl8k_cmd_update_stadb(hw, vif,
3037 MWL8K_STA_DB_MODIFY_ENTRY);
3038 if (rc)
3039 goto out;
3040
3041 /* Set AID */
3042 rc = mwl8k_cmd_set_aid(hw, vif);
3043 if (rc)
3044 goto out;
3045
3046 /*
3047 * Finalize the join. Tell rx handler to process
3048 * next beacon from our BSSID.
3049 */
3050 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
3051 priv->capture_beacon = true;
3052 } else {
3053 rc = mwl8k_cmd_update_stadb(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3054 memset(&mwl8k_vif->bss_info, 0,
3055 sizeof(struct ieee80211_bss_conf));
3056 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
3057 }
3058
3059 out:
3060 mwl8k_fw_unlock(hw);
3061 }
3062
3063 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3064 int mc_count, struct dev_addr_list *mclist)
3065 {
3066 struct mwl8k_cmd_pkt *cmd;
3067
3068 /*
3069 * Synthesize and return a command packet that programs the
3070 * hardware multicast address filter. At this point we don't
3071 * know whether FIF_ALLMULTI is being requested, but if it is,
3072 * we'll end up throwing this packet away and creating a new
3073 * one in mwl8k_configure_filter().
3074 */
3075 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3076
3077 return (unsigned long)cmd;
3078 }
3079
3080 static int
3081 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3082 unsigned int changed_flags,
3083 unsigned int *total_flags)
3084 {
3085 struct mwl8k_priv *priv = hw->priv;
3086
3087 /*
3088 * Hardware sniffer mode is mutually exclusive with STA
3089 * operation, so refuse to enable sniffer mode if a STA
3090 * interface is active.
3091 */
3092 if (priv->vif != NULL) {
3093 if (net_ratelimit())
3094 printk(KERN_INFO "%s: not enabling sniffer "
3095 "mode because STA interface is active\n",
3096 wiphy_name(hw->wiphy));
3097 return 0;
3098 }
3099
3100 if (!priv->sniffer_enabled) {
3101 if (mwl8k_cmd_enable_sniffer(hw, 1))
3102 return 0;
3103 priv->sniffer_enabled = true;
3104 }
3105
3106 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3107 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3108 FIF_OTHER_BSS;
3109
3110 return 1;
3111 }
3112
3113 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3114 unsigned int changed_flags,
3115 unsigned int *total_flags,
3116 u64 multicast)
3117 {
3118 struct mwl8k_priv *priv = hw->priv;
3119 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3120
3121 /*
3122 * AP firmware doesn't allow fine-grained control over
3123 * the receive filter.
3124 */
3125 if (priv->ap_fw) {
3126 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3127 kfree(cmd);
3128 return;
3129 }
3130
3131 /*
3132 * Enable hardware sniffer mode if FIF_CONTROL or
3133 * FIF_OTHER_BSS is requested.
3134 */
3135 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3136 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3137 kfree(cmd);
3138 return;
3139 }
3140
3141 /* Clear unsupported feature flags */
3142 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3143
3144 if (mwl8k_fw_lock(hw))
3145 return;
3146
3147 if (priv->sniffer_enabled) {
3148 mwl8k_cmd_enable_sniffer(hw, 0);
3149 priv->sniffer_enabled = false;
3150 }
3151
3152 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3153 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3154 /*
3155 * Disable the BSS filter.
3156 */
3157 mwl8k_cmd_set_pre_scan(hw);
3158 } else {
3159 u8 *bssid;
3160
3161 /*
3162 * Enable the BSS filter.
3163 *
3164 * If there is an active STA interface, use that
3165 * interface's BSSID, otherwise use a dummy one
3166 * (where the OUI part needs to be nonzero for
3167 * the BSSID to be accepted by POST_SCAN).
3168 */
3169 bssid = "\x01\x00\x00\x00\x00\x00";
3170 if (priv->vif != NULL)
3171 bssid = MWL8K_VIF(priv->vif)->bssid;
3172
3173 mwl8k_cmd_set_post_scan(hw, bssid);
3174 }
3175 }
3176
3177 /*
3178 * If FIF_ALLMULTI is being requested, throw away the command
3179 * packet that ->prepare_multicast() built and replace it with
3180 * a command packet that enables reception of all multicast
3181 * packets.
3182 */
3183 if (*total_flags & FIF_ALLMULTI) {
3184 kfree(cmd);
3185 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3186 }
3187
3188 if (cmd != NULL) {
3189 mwl8k_post_cmd(hw, cmd);
3190 kfree(cmd);
3191 }
3192
3193 mwl8k_fw_unlock(hw);
3194 }
3195
3196 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3197 {
3198 return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value);
3199 }
3200
3201 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3202 const struct ieee80211_tx_queue_params *params)
3203 {
3204 struct mwl8k_priv *priv = hw->priv;
3205 int rc;
3206
3207 rc = mwl8k_fw_lock(hw);
3208 if (!rc) {
3209 if (!priv->wmm_enabled)
3210 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
3211
3212 if (!rc)
3213 rc = mwl8k_cmd_set_edca_params(hw, queue,
3214 params->cw_min,
3215 params->cw_max,
3216 params->aifs,
3217 params->txop);
3218
3219 mwl8k_fw_unlock(hw);
3220 }
3221
3222 return rc;
3223 }
3224
3225 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3226 struct ieee80211_tx_queue_stats *stats)
3227 {
3228 struct mwl8k_priv *priv = hw->priv;
3229 struct mwl8k_tx_queue *txq;
3230 int index;
3231
3232 spin_lock_bh(&priv->tx_lock);
3233 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3234 txq = priv->txq + index;
3235 memcpy(&stats[index], &txq->stats,
3236 sizeof(struct ieee80211_tx_queue_stats));
3237 }
3238 spin_unlock_bh(&priv->tx_lock);
3239
3240 return 0;
3241 }
3242
3243 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3244 struct ieee80211_low_level_stats *stats)
3245 {
3246 return mwl8k_cmd_get_stat(hw, stats);
3247 }
3248
3249 static const struct ieee80211_ops mwl8k_ops = {
3250 .tx = mwl8k_tx,
3251 .start = mwl8k_start,
3252 .stop = mwl8k_stop,
3253 .add_interface = mwl8k_add_interface,
3254 .remove_interface = mwl8k_remove_interface,
3255 .config = mwl8k_config,
3256 .bss_info_changed = mwl8k_bss_info_changed,
3257 .prepare_multicast = mwl8k_prepare_multicast,
3258 .configure_filter = mwl8k_configure_filter,
3259 .set_rts_threshold = mwl8k_set_rts_threshold,
3260 .conf_tx = mwl8k_conf_tx,
3261 .get_tx_stats = mwl8k_get_tx_stats,
3262 .get_stats = mwl8k_get_stats,
3263 };
3264
3265 static void mwl8k_tx_reclaim_handler(unsigned long data)
3266 {
3267 int i;
3268 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3269 struct mwl8k_priv *priv = hw->priv;
3270
3271 spin_lock_bh(&priv->tx_lock);
3272 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3273 mwl8k_txq_reclaim(hw, i, 0);
3274
3275 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3276 complete(priv->tx_wait);
3277 priv->tx_wait = NULL;
3278 }
3279 spin_unlock_bh(&priv->tx_lock);
3280 }
3281
3282 static void mwl8k_finalize_join_worker(struct work_struct *work)
3283 {
3284 struct mwl8k_priv *priv =
3285 container_of(work, struct mwl8k_priv, finalize_join_worker);
3286 struct sk_buff *skb = priv->beacon_skb;
3287 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
3288
3289 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim);
3290 dev_kfree_skb(skb);
3291
3292 priv->beacon_skb = NULL;
3293 }
3294
3295 enum {
3296 MWL8687 = 0,
3297 MWL8366,
3298 };
3299
3300 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3301 {
3302 .part_name = "88w8687",
3303 .helper_image = "mwl8k/helper_8687.fw",
3304 .fw_image = "mwl8k/fmimage_8687.fw",
3305 .rxd_ops = &rxd_8687_ops,
3306 .modes = BIT(NL80211_IFTYPE_STATION),
3307 },
3308 {
3309 .part_name = "88w8366",
3310 .helper_image = "mwl8k/helper_8366.fw",
3311 .fw_image = "mwl8k/fmimage_8366.fw",
3312 .rxd_ops = &rxd_8366_ops,
3313 .modes = 0,
3314 },
3315 };
3316
3317 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3318 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3319 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3320 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3321 { },
3322 };
3323 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3324
3325 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3326 const struct pci_device_id *id)
3327 {
3328 static int printed_version = 0;
3329 struct ieee80211_hw *hw;
3330 struct mwl8k_priv *priv;
3331 int rc;
3332 int i;
3333
3334 if (!printed_version) {
3335 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3336 printed_version = 1;
3337 }
3338
3339 rc = pci_enable_device(pdev);
3340 if (rc) {
3341 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3342 MWL8K_NAME);
3343 return rc;
3344 }
3345
3346 rc = pci_request_regions(pdev, MWL8K_NAME);
3347 if (rc) {
3348 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3349 MWL8K_NAME);
3350 goto err_disable_device;
3351 }
3352
3353 pci_set_master(pdev);
3354
3355 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3356 if (hw == NULL) {
3357 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3358 rc = -ENOMEM;
3359 goto err_free_reg;
3360 }
3361
3362 priv = hw->priv;
3363 priv->hw = hw;
3364 priv->pdev = pdev;
3365 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3366 priv->rxd_ops = priv->device_info->rxd_ops;
3367 priv->sniffer_enabled = false;
3368 priv->wmm_enabled = false;
3369 priv->pending_tx_pkts = 0;
3370
3371 SET_IEEE80211_DEV(hw, &pdev->dev);
3372 pci_set_drvdata(pdev, hw);
3373
3374 priv->sram = pci_iomap(pdev, 0, 0x10000);
3375 if (priv->sram == NULL) {
3376 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3377 wiphy_name(hw->wiphy));
3378 goto err_iounmap;
3379 }
3380
3381 /*
3382 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3383 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3384 */
3385 priv->regs = pci_iomap(pdev, 1, 0x10000);
3386 if (priv->regs == NULL) {
3387 priv->regs = pci_iomap(pdev, 2, 0x10000);
3388 if (priv->regs == NULL) {
3389 printk(KERN_ERR "%s: Cannot map device registers\n",
3390 wiphy_name(hw->wiphy));
3391 goto err_iounmap;
3392 }
3393 }
3394
3395 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3396 priv->band.band = IEEE80211_BAND_2GHZ;
3397 priv->band.channels = priv->channels;
3398 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3399 priv->band.bitrates = priv->rates;
3400 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3401 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3402
3403 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3404 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3405
3406 /*
3407 * Extra headroom is the size of the required DMA header
3408 * minus the size of the smallest 802.11 frame (CTS frame).
3409 */
3410 hw->extra_tx_headroom =
3411 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3412
3413 hw->channel_change_time = 10;
3414
3415 hw->queues = MWL8K_TX_QUEUES;
3416
3417 hw->wiphy->interface_modes = priv->device_info->modes;
3418
3419 /* Set rssi and noise values to dBm */
3420 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3421 hw->vif_data_size = sizeof(struct mwl8k_vif);
3422 priv->vif = NULL;
3423
3424 /* Set default radio state and preamble */
3425 priv->radio_on = 0;
3426 priv->radio_short_preamble = 0;
3427
3428 /* Finalize join worker */
3429 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3430
3431 /* TX reclaim tasklet */
3432 tasklet_init(&priv->tx_reclaim_task,
3433 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3434 tasklet_disable(&priv->tx_reclaim_task);
3435
3436 /* Power management cookie */
3437 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3438 if (priv->cookie == NULL)
3439 goto err_iounmap;
3440
3441 rc = mwl8k_rxq_init(hw, 0);
3442 if (rc)
3443 goto err_iounmap;
3444 rxq_refill(hw, 0, INT_MAX);
3445
3446 mutex_init(&priv->fw_mutex);
3447 priv->fw_mutex_owner = NULL;
3448 priv->fw_mutex_depth = 0;
3449 priv->hostcmd_wait = NULL;
3450
3451 spin_lock_init(&priv->tx_lock);
3452
3453 priv->tx_wait = NULL;
3454
3455 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3456 rc = mwl8k_txq_init(hw, i);
3457 if (rc)
3458 goto err_free_queues;
3459 }
3460
3461 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3462 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3463 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3464 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3465
3466 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3467 IRQF_SHARED, MWL8K_NAME, hw);
3468 if (rc) {
3469 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3470 wiphy_name(hw->wiphy));
3471 goto err_free_queues;
3472 }
3473
3474 /* Reset firmware and hardware */
3475 mwl8k_hw_reset(priv);
3476
3477 /* Ask userland hotplug daemon for the device firmware */
3478 rc = mwl8k_request_firmware(priv);
3479 if (rc) {
3480 printk(KERN_ERR "%s: Firmware files not found\n",
3481 wiphy_name(hw->wiphy));
3482 goto err_free_irq;
3483 }
3484
3485 /* Load firmware into hardware */
3486 rc = mwl8k_load_firmware(hw);
3487 if (rc) {
3488 printk(KERN_ERR "%s: Cannot start firmware\n",
3489 wiphy_name(hw->wiphy));
3490 goto err_stop_firmware;
3491 }
3492
3493 /* Reclaim memory once firmware is successfully loaded */
3494 mwl8k_release_firmware(priv);
3495
3496 /*
3497 * Temporarily enable interrupts. Initial firmware host
3498 * commands use interrupts and avoids polling. Disable
3499 * interrupts when done.
3500 */
3501 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3502
3503 /* Get config data, mac addrs etc */
3504 if (priv->ap_fw) {
3505 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3506 if (!rc)
3507 rc = mwl8k_cmd_set_hw_spec(hw);
3508 } else {
3509 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3510 }
3511 if (rc) {
3512 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3513 wiphy_name(hw->wiphy));
3514 goto err_stop_firmware;
3515 }
3516
3517 /* Turn radio off */
3518 rc = mwl8k_cmd_radio_disable(hw);
3519 if (rc) {
3520 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3521 goto err_stop_firmware;
3522 }
3523
3524 /* Clear MAC address */
3525 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3526 if (rc) {
3527 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3528 wiphy_name(hw->wiphy));
3529 goto err_stop_firmware;
3530 }
3531
3532 /* Disable interrupts */
3533 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3534 free_irq(priv->pdev->irq, hw);
3535
3536 rc = ieee80211_register_hw(hw);
3537 if (rc) {
3538 printk(KERN_ERR "%s: Cannot register device\n",
3539 wiphy_name(hw->wiphy));
3540 goto err_stop_firmware;
3541 }
3542
3543 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3544 wiphy_name(hw->wiphy), priv->device_info->part_name,
3545 priv->hw_rev, hw->wiphy->perm_addr,
3546 priv->ap_fw ? "AP" : "STA",
3547 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3548 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3549
3550 return 0;
3551
3552 err_stop_firmware:
3553 mwl8k_hw_reset(priv);
3554 mwl8k_release_firmware(priv);
3555
3556 err_free_irq:
3557 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3558 free_irq(priv->pdev->irq, hw);
3559
3560 err_free_queues:
3561 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3562 mwl8k_txq_deinit(hw, i);
3563 mwl8k_rxq_deinit(hw, 0);
3564
3565 err_iounmap:
3566 if (priv->cookie != NULL)
3567 pci_free_consistent(priv->pdev, 4,
3568 priv->cookie, priv->cookie_dma);
3569
3570 if (priv->regs != NULL)
3571 pci_iounmap(pdev, priv->regs);
3572
3573 if (priv->sram != NULL)
3574 pci_iounmap(pdev, priv->sram);
3575
3576 pci_set_drvdata(pdev, NULL);
3577 ieee80211_free_hw(hw);
3578
3579 err_free_reg:
3580 pci_release_regions(pdev);
3581
3582 err_disable_device:
3583 pci_disable_device(pdev);
3584
3585 return rc;
3586 }
3587
3588 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3589 {
3590 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3591 }
3592
3593 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3594 {
3595 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3596 struct mwl8k_priv *priv;
3597 int i;
3598
3599 if (hw == NULL)
3600 return;
3601 priv = hw->priv;
3602
3603 ieee80211_stop_queues(hw);
3604
3605 ieee80211_unregister_hw(hw);
3606
3607 /* Remove tx reclaim tasklet */
3608 tasklet_kill(&priv->tx_reclaim_task);
3609
3610 /* Stop hardware */
3611 mwl8k_hw_reset(priv);
3612
3613 /* Return all skbs to mac80211 */
3614 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3615 mwl8k_txq_reclaim(hw, i, 1);
3616
3617 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3618 mwl8k_txq_deinit(hw, i);
3619
3620 mwl8k_rxq_deinit(hw, 0);
3621
3622 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3623
3624 pci_iounmap(pdev, priv->regs);
3625 pci_iounmap(pdev, priv->sram);
3626 pci_set_drvdata(pdev, NULL);
3627 ieee80211_free_hw(hw);
3628 pci_release_regions(pdev);
3629 pci_disable_device(pdev);
3630 }
3631
3632 static struct pci_driver mwl8k_driver = {
3633 .name = MWL8K_NAME,
3634 .id_table = mwl8k_pci_id_table,
3635 .probe = mwl8k_probe,
3636 .remove = __devexit_p(mwl8k_remove),
3637 .shutdown = __devexit_p(mwl8k_shutdown),
3638 };
3639
3640 static int __init mwl8k_init(void)
3641 {
3642 return pci_register_driver(&mwl8k_driver);
3643 }
3644
3645 static void __exit mwl8k_exit(void)
3646 {
3647 pci_unregister_driver(&mwl8k_driver);
3648 }
3649
3650 module_init(mwl8k_init);
3651 module_exit(mwl8k_exit);
3652
3653 MODULE_DESCRIPTION(MWL8K_DESC);
3654 MODULE_VERSION(MWL8K_VERSION);
3655 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3656 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree