?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mac80211: don't stop a single aggregation session twice
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / dvb / frontends / drxd_hard.c
blob2238bf0be95936320feccbfc65f30c1503167e08
1 /*
2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
3 *
4 * Copyright (C) 2003-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <asm/div64.h>
32
33 #include "dvb_frontend.h"
34 #include "drxd.h"
35 #include "drxd_firm.h"
36
37 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
38 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
39
40 #define CHUNK_SIZE 48
41
42 #define DRX_I2C_RMW 0x10
43 #define DRX_I2C_BROADCAST 0x20
44 #define DRX_I2C_CLEARCRC 0x80
45 #define DRX_I2C_SINGLE_MASTER 0xC0
46 #define DRX_I2C_MODEFLAGS 0xC0
47 #define DRX_I2C_FLAGS 0xF0
48
49 #ifndef SIZEOF_ARRAY
50 #define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
51 #endif
52
53 #define DEFAULT_LOCK_TIMEOUT 1100
54
55 #define DRX_CHANNEL_AUTO 0
56 #define DRX_CHANNEL_HIGH 1
57 #define DRX_CHANNEL_LOW 2
58
59 #define DRX_LOCK_MPEG 1
60 #define DRX_LOCK_FEC 2
61 #define DRX_LOCK_DEMOD 4
62
63 /****************************************************************************/
64
65 enum CSCDState {
66 CSCD_INIT = 0,
67 CSCD_SET,
68 CSCD_SAVED
69 };
70
71 enum CDrxdState {
72 DRXD_UNINITIALIZED = 0,
73 DRXD_STOPPED,
74 DRXD_STARTED
75 };
76
77 enum AGC_CTRL_MODE {
78 AGC_CTRL_AUTO = 0,
79 AGC_CTRL_USER,
80 AGC_CTRL_OFF
81 };
82
83 enum OperationMode {
84 OM_Default,
85 OM_DVBT_Diversity_Front,
86 OM_DVBT_Diversity_End
87 };
88
89 struct SCfgAgc {
90 enum AGC_CTRL_MODE ctrlMode;
91 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
92 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
93 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
94 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
95 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
96
97 u16 R1;
98 u16 R2;
99 u16 R3;
100 };
101
102 struct SNoiseCal {
103 int cpOpt;
104 u16 cpNexpOfs;
105 u16 tdCal2k;
106 u16 tdCal8k;
107 };
108
109 enum app_env {
110 APPENV_STATIC = 0,
111 APPENV_PORTABLE = 1,
112 APPENV_MOBILE = 2
113 };
114
115 enum EIFFilter {
116 IFFILTER_SAW = 0,
117 IFFILTER_DISCRETE = 1
118 };
119
120 struct drxd_state {
121 struct dvb_frontend frontend;
122 struct dvb_frontend_ops ops;
123 struct dvb_frontend_parameters param;
124
125 const struct firmware *fw;
126 struct device *dev;
127
128 struct i2c_adapter *i2c;
129 void *priv;
130 struct drxd_config config;
131
132 int i2c_access;
133 int init_done;
134 struct mutex mutex;
135
136 u8 chip_adr;
137 u16 hi_cfg_timing_div;
138 u16 hi_cfg_bridge_delay;
139 u16 hi_cfg_wakeup_key;
140 u16 hi_cfg_ctrl;
141
142 u16 intermediate_freq;
143 u16 osc_clock_freq;
144
145 enum CSCDState cscd_state;
146 enum CDrxdState drxd_state;
147
148 u16 sys_clock_freq;
149 s16 osc_clock_deviation;
150 u16 expected_sys_clock_freq;
151
152 u16 insert_rs_byte;
153 u16 enable_parallel;
154
155 int operation_mode;
156
157 struct SCfgAgc if_agc_cfg;
158 struct SCfgAgc rf_agc_cfg;
159
160 struct SNoiseCal noise_cal;
161
162 u32 fe_fs_add_incr;
163 u32 org_fe_fs_add_incr;
164 u16 current_fe_if_incr;
165
166 u16 m_FeAgRegAgPwd;
167 u16 m_FeAgRegAgAgcSio;
168
169 u16 m_EcOcRegOcModeLop;
170 u16 m_EcOcRegSncSncLvl;
171 u8 *m_InitAtomicRead;
172 u8 *m_HiI2cPatch;
173
174 u8 *m_ResetCEFR;
175 u8 *m_InitFE_1;
176 u8 *m_InitFE_2;
177 u8 *m_InitCP;
178 u8 *m_InitCE;
179 u8 *m_InitEQ;
180 u8 *m_InitSC;
181 u8 *m_InitEC;
182 u8 *m_ResetECRAM;
183 u8 *m_InitDiversityFront;
184 u8 *m_InitDiversityEnd;
185 u8 *m_DisableDiversity;
186 u8 *m_StartDiversityFront;
187 u8 *m_StartDiversityEnd;
188
189 u8 *m_DiversityDelay8MHZ;
190 u8 *m_DiversityDelay6MHZ;
191
192 u8 *microcode;
193 u32 microcode_length;
194
195 int type_A;
196 int PGA;
197 int diversity;
198 int tuner_mirrors;
199
200 enum app_env app_env_default;
201 enum app_env app_env_diversity;
202
203 };
204
205 /****************************************************************************/
206 /* I2C **********************************************************************/
207 /****************************************************************************/
208
209 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
210 {
211 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
212
213 if (i2c_transfer(adap, &msg, 1) != 1)
214 return -1;
215 return 0;
216 }
217
218 static int i2c_read(struct i2c_adapter *adap,
219 u8 adr, u8 *msg, int len, u8 *answ, int alen)
220 {
221 struct i2c_msg msgs[2] = {
222 {
223 .addr = adr, .flags = 0,
224 .buf = msg, .len = len
225 }, {
226 .addr = adr, .flags = I2C_M_RD,
227 .buf = answ, .len = alen
228 }
229 };
230 if (i2c_transfer(adap, msgs, 2) != 2)
231 return -1;
232 return 0;
233 }
234
235 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
236 {
237 u64 tmp64;
238
239 tmp64 = (u64)a * (u64)b;
240 do_div(tmp64, c);
241
242 return (u32) tmp64;
243 }
244
245 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
246 {
247 u8 adr = state->config.demod_address;
248 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
249 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
250 };
251 u8 mm2[2];
252 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
253 return -1;
254 if (data)
255 *data = mm2[0] | (mm2[1] << 8);
256 return mm2[0] | (mm2[1] << 8);
257 }
258
259 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
260 {
261 u8 adr = state->config.demod_address;
262 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
263 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
264 };
265 u8 mm2[4];
266
267 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
268 return -1;
269 if (data)
270 *data =
271 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
272 return 0;
273 }
274
275 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
276 {
277 u8 adr = state->config.demod_address;
278 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
279 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
280 data & 0xff, (data >> 8) & 0xff
281 };
282
283 if (i2c_write(state->i2c, adr, mm, 6) < 0)
284 return -1;
285 return 0;
286 }
287
288 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
289 {
290 u8 adr = state->config.demod_address;
291 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
292 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
293 data & 0xff, (data >> 8) & 0xff,
294 (data >> 16) & 0xff, (data >> 24) & 0xff
295 };
296
297 if (i2c_write(state->i2c, adr, mm, 8) < 0)
298 return -1;
299 return 0;
300 }
301
302 static int write_chunk(struct drxd_state *state,
303 u32 reg, u8 *data, u32 len, u8 flags)
304 {
305 u8 adr = state->config.demod_address;
306 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
307 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
308 };
309 int i;
310
311 for (i = 0; i < len; i++)
312 mm[4 + i] = data[i];
313 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
314 printk(KERN_ERR "error in write_chunk\n");
315 return -1;
316 }
317 return 0;
318 }
319
320 static int WriteBlock(struct drxd_state *state,
321 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
322 {
323 while (BlockSize > 0) {
324 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
325
326 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
327 return -1;
328 pBlock += Chunk;
329 Address += (Chunk >> 1);
330 BlockSize -= Chunk;
331 }
332 return 0;
333 }
334
335 static int WriteTable(struct drxd_state *state, u8 * pTable)
336 {
337 int status = 0;
338
339 if (pTable == NULL)
340 return 0;
341
342 while (!status) {
343 u16 Length;
344 u32 Address = pTable[0] | (pTable[1] << 8) |
345 (pTable[2] << 16) | (pTable[3] << 24);
346
347 if (Address == 0xFFFFFFFF)
348 break;
349 pTable += sizeof(u32);
350
351 Length = pTable[0] | (pTable[1] << 8);
352 pTable += sizeof(u16);
353 if (!Length)
354 break;
355 status = WriteBlock(state, Address, Length * 2, pTable, 0);
356 pTable += (Length * 2);
357 }
358 return status;
359 }
360
361 /****************************************************************************/
362 /****************************************************************************/
363 /****************************************************************************/
364
365 static int ResetCEFR(struct drxd_state *state)
366 {
367 return WriteTable(state, state->m_ResetCEFR);
368 }
369
370 static int InitCP(struct drxd_state *state)
371 {
372 return WriteTable(state, state->m_InitCP);
373 }
374
375 static int InitCE(struct drxd_state *state)
376 {
377 int status;
378 enum app_env AppEnv = state->app_env_default;
379
380 do {
381 status = WriteTable(state, state->m_InitCE);
382 if (status < 0)
383 break;
384
385 if (state->operation_mode == OM_DVBT_Diversity_Front ||
386 state->operation_mode == OM_DVBT_Diversity_End) {
387 AppEnv = state->app_env_diversity;
388 }
389 if (AppEnv == APPENV_STATIC) {
390 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
391 if (status < 0)
392 break;
393 } else if (AppEnv == APPENV_PORTABLE) {
394 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
395 if (status < 0)
396 break;
397 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
398 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
399 if (status < 0)
400 break;
401 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
402 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
403 if (status < 0)
404 break;
405 }
406
407 /* start ce */
408 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
409 if (status < 0)
410 break;
411 } while (0);
412 return status;
413 }
414
415 static int StopOC(struct drxd_state *state)
416 {
417 int status = 0;
418 u16 ocSyncLvl = 0;
419 u16 ocModeLop = state->m_EcOcRegOcModeLop;
420 u16 dtoIncLop = 0;
421 u16 dtoIncHip = 0;
422
423 do {
424 /* Store output configuration */
425 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
426 if (status < 0)
427 break;
428 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
429 state->m_EcOcRegSncSncLvl = ocSyncLvl;
430 /* m_EcOcRegOcModeLop = ocModeLop; */
431
432 /* Flush FIFO (byte-boundary) at fixed rate */
433 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
434 if (status < 0)
435 break;
436 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
437 if (status < 0)
438 break;
439 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
440 if (status < 0)
441 break;
442 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
443 if (status < 0)
444 break;
445 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
446 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
447 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
448 if (status < 0)
449 break;
450 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
451 if (status < 0)
452 break;
453
454 msleep(1);
455 /* Output pins to '0' */
456 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
457 if (status < 0)
458 break;
459
460 /* Force the OC out of sync */
461 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
462 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
463 if (status < 0)
464 break;
465 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
466 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
467 ocModeLop |= 0x2; /* Magically-out-of-sync */
468 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
469 if (status < 0)
470 break;
471 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
472 if (status < 0)
473 break;
474 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
475 if (status < 0)
476 break;
477 } while (0);
478
479 return status;
480 }
481
482 static int StartOC(struct drxd_state *state)
483 {
484 int status = 0;
485
486 do {
487 /* Stop OC */
488 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
489 if (status < 0)
490 break;
491
492 /* Restore output configuration */
493 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
494 if (status < 0)
495 break;
496 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
497 if (status < 0)
498 break;
499
500 /* Output pins active again */
501 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
502 if (status < 0)
503 break;
504
505 /* Start OC */
506 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
507 if (status < 0)
508 break;
509 } while (0);
510 return status;
511 }
512
513 static int InitEQ(struct drxd_state *state)
514 {
515 return WriteTable(state, state->m_InitEQ);
516 }
517
518 static int InitEC(struct drxd_state *state)
519 {
520 return WriteTable(state, state->m_InitEC);
521 }
522
523 static int InitSC(struct drxd_state *state)
524 {
525 return WriteTable(state, state->m_InitSC);
526 }
527
528 static int InitAtomicRead(struct drxd_state *state)
529 {
530 return WriteTable(state, state->m_InitAtomicRead);
531 }
532
533 static int CorrectSysClockDeviation(struct drxd_state *state);
534
535 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
536 {
537 u16 ScRaRamLock = 0;
538 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
539 SC_RA_RAM_LOCK_FEC__M |
540 SC_RA_RAM_LOCK_DEMOD__M);
541 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
542 SC_RA_RAM_LOCK_DEMOD__M);
543 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
544
545 int status;
546
547 *pLockStatus = 0;
548
549 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
550 if (status < 0) {
551 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
552 return status;
553 }
554
555 if (state->drxd_state != DRXD_STARTED)
556 return 0;
557
558 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
559 *pLockStatus |= DRX_LOCK_MPEG;
560 CorrectSysClockDeviation(state);
561 }
562
563 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
564 *pLockStatus |= DRX_LOCK_FEC;
565
566 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
567 *pLockStatus |= DRX_LOCK_DEMOD;
568 return 0;
569 }
570
571 /****************************************************************************/
572
573 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
574 {
575 int status;
576
577 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
578 return -1;
579
580 if (cfg->ctrlMode == AGC_CTRL_USER) {
581 do {
582 u16 FeAgRegPm1AgcWri;
583 u16 FeAgRegAgModeLop;
584
585 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
586 if (status < 0)
587 break;
588 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
589 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
590 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
591 if (status < 0)
592 break;
593
594 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
595 FE_AG_REG_PM1_AGC_WRI__M);
596 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
597 if (status < 0)
598 break;
599 } while (0);
600 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
601 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
602 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
603 ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
604 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
605 )
606 return -1;
607 do {
608 u16 FeAgRegAgModeLop;
609 u16 FeAgRegEgcSetLvl;
610 u16 slope, offset;
611
612 /* == Mode == */
613
614 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
615 if (status < 0)
616 break;
617 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
618 FeAgRegAgModeLop |=
619 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
620 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
621 if (status < 0)
622 break;
623
624 /* == Settle level == */
625
626 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
627 FE_AG_REG_EGC_SET_LVL__M);
628 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
629 if (status < 0)
630 break;
631
632 /* == Min/Max == */
633
634 slope = (u16) ((cfg->maxOutputLevel -
635 cfg->minOutputLevel) / 2);
636 offset = (u16) ((cfg->maxOutputLevel +
637 cfg->minOutputLevel) / 2 - 511);
638
639 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
640 if (status < 0)
641 break;
642 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
643 if (status < 0)
644 break;
645
646 /* == Speed == */
647 {
648 const u16 maxRur = 8;
649 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
650 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
651 17, 18, 18, 19,
652 20, 21, 22, 23,
653 24, 26, 27, 28,
654 29, 31
655 };
656
657 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
658 (maxRur + 1);
659 u16 fineSpeed = (u16) (cfg->speed -
660 ((cfg->speed /
661 fineSteps) *
662 fineSteps));
663 u16 invRurCount = (u16) (cfg->speed /
664 fineSteps);
665 u16 rurCount;
666 if (invRurCount > maxRur) {
667 rurCount = 0;
668 fineSpeed += fineSteps;
669 } else {
670 rurCount = maxRur - invRurCount;
671 }
672
673 /*
674 fastInc = default *
675 (2^(fineSpeed/fineSteps))
676 => range[default...2*default>
677 slowInc = default *
678 (2^(fineSpeed/fineSteps))
679 */
680 {
681 u16 fastIncrDec =
682 fastIncrDecLUT[fineSpeed /
683 ((fineSteps /
684 (14 + 1)) + 1)];
685 u16 slowIncrDec =
686 slowIncrDecLUT[fineSpeed /
687 (fineSteps /
688 (3 + 1))];
689
690 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
691 if (status < 0)
692 break;
693 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
694 if (status < 0)
695 break;
696 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
697 if (status < 0)
698 break;
699 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
700 if (status < 0)
701 break;
702 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
703 if (status < 0)
704 break;
705 }
706 }
707 } while (0);
708
709 } else {
710 /* No OFF mode for IF control */
711 return -1;
712 }
713 return status;
714 }
715
716 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
717 {
718 int status = 0;
719
720 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
721 return -1;
722
723 if (cfg->ctrlMode == AGC_CTRL_USER) {
724 do {
725 u16 AgModeLop = 0;
726 u16 level = (cfg->outputLevel);
727
728 if (level == DRXD_FE_CTRL_MAX)
729 level++;
730
731 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
732 if (status < 0)
733 break;
734
735 /*==== Mode ====*/
736
737 /* Powerdown PD2, WRI source */
738 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
739 state->m_FeAgRegAgPwd |=
740 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
741 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
742 if (status < 0)
743 break;
744
745 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
746 if (status < 0)
747 break;
748 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
749 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
750 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
751 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
752 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
753 if (status < 0)
754 break;
755
756 /* enable AGC2 pin */
757 {
758 u16 FeAgRegAgAgcSio = 0;
759 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
760 if (status < 0)
761 break;
762 FeAgRegAgAgcSio &=
763 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
764 FeAgRegAgAgcSio |=
765 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
766 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
767 if (status < 0)
768 break;
769 }
770
771 } while (0);
772 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
773 u16 AgModeLop = 0;
774
775 do {
776 u16 level;
777 /* Automatic control */
778 /* Powerup PD2, AGC2 as output, TGC source */
779 (state->m_FeAgRegAgPwd) &=
780 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
781 (state->m_FeAgRegAgPwd) |=
782 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
783 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
784 if (status < 0)
785 break;
786
787 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
788 if (status < 0)
789 break;
790 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
791 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
792 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
793 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
794 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
795 if (status < 0)
796 break;
797 /* Settle level */
798 level = (((cfg->settleLevel) >> 4) &
799 FE_AG_REG_TGC_SET_LVL__M);
800 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
801 if (status < 0)
802 break;
803
804 /* Min/max: don't care */
805
806 /* Speed: TODO */
807
808 /* enable AGC2 pin */
809 {
810 u16 FeAgRegAgAgcSio = 0;
811 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
812 if (status < 0)
813 break;
814 FeAgRegAgAgcSio &=
815 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
816 FeAgRegAgAgcSio |=
817 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
818 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
819 if (status < 0)
820 break;
821 }
822
823 } while (0);
824 } else {
825 u16 AgModeLop = 0;
826
827 do {
828 /* No RF AGC control */
829 /* Powerdown PD2, AGC2 as output, WRI source */
830 (state->m_FeAgRegAgPwd) &=
831 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
832 (state->m_FeAgRegAgPwd) |=
833 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
834 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
835 if (status < 0)
836 break;
837
838 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
839 if (status < 0)
840 break;
841 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
842 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
843 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
844 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
845 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
846 if (status < 0)
847 break;
848
849 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
850 {
851 u16 FeAgRegAgAgcSio = 0;
852 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
853 if (status < 0)
854 break;
855 FeAgRegAgAgcSio &=
856 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
857 FeAgRegAgAgcSio |=
858 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
859 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
860 if (status < 0)
861 break;
862 }
863 } while (0);
864 }
865 return status;
866 }
867
868 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
869 {
870 int status = 0;
871
872 *pValue = 0;
873 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
874 u16 Value;
875 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
876 Value &= FE_AG_REG_GC1_AGC_DAT__M;
877 if (status >= 0) {
878 /* 3.3V
879 |
880 R1
881 |
882 Vin - R3 - * -- Vout
883 |
884 R2
885 |
886 GND
887 */
888 u32 R1 = state->if_agc_cfg.R1;
889 u32 R2 = state->if_agc_cfg.R2;
890 u32 R3 = state->if_agc_cfg.R3;
891
892 u32 Vmax = (3300 * R2) / (R1 + R2);
893 u32 Rpar = (R2 * R3) / (R3 + R2);
894 u32 Vmin = (3300 * Rpar) / (R1 + Rpar);
895 u32 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
896
897 *pValue = Vout;
898 }
899 }
900 return status;
901 }
902
903 static int load_firmware(struct drxd_state *state, const char *fw_name)
904 {
905 const struct firmware *fw;
906
907 if (request_firmware(&fw, fw_name, state->dev) < 0) {
908 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
909 return -EIO;
910 }
911
912 state->microcode = kmalloc(fw->size, GFP_KERNEL);
913 if (state->microcode == NULL) {
914 release_firmware(fw);
915 printk(KERN_ERR "drxd: firmware load failure: no memory\n");
916 return -ENOMEM;
917 }
918
919 memcpy(state->microcode, fw->data, fw->size);
920 state->microcode_length = fw->size;
921 release_firmware(fw);
922 return 0;
923 }
924
925 static int DownloadMicrocode(struct drxd_state *state,
926 const u8 *pMCImage, u32 Length)
927 {
928 u8 *pSrc;
929 u16 Flags;
930 u32 Address;
931 u16 nBlocks;
932 u16 BlockSize;
933 u16 BlockCRC;
934 u32 offset = 0;
935 int i, status = 0;
936
937 pSrc = (u8 *) pMCImage;
938 Flags = (pSrc[0] << 8) | pSrc[1];
939 pSrc += sizeof(u16);
940 offset += sizeof(u16);
941 nBlocks = (pSrc[0] << 8) | pSrc[1];
942 pSrc += sizeof(u16);
943 offset += sizeof(u16);
944
945 for (i = 0; i < nBlocks; i++) {
946 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
947 (pSrc[2] << 8) | pSrc[3];
948 pSrc += sizeof(u32);
949 offset += sizeof(u32);
950
951 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
952 pSrc += sizeof(u16);
953 offset += sizeof(u16);
954
955 Flags = (pSrc[0] << 8) | pSrc[1];
956 pSrc += sizeof(u16);
957 offset += sizeof(u16);
958
959 BlockCRC = (pSrc[0] << 8) | pSrc[1];
960 pSrc += sizeof(u16);
961 offset += sizeof(u16);
962
963 status = WriteBlock(state, Address, BlockSize,
964 pSrc, DRX_I2C_CLEARCRC);
965 if (status < 0)
966 break;
967 pSrc += BlockSize;
968 offset += BlockSize;
969 }
970
971 return status;
972 }
973
974 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
975 {
976 u32 nrRetries = 0;
977 u16 waitCmd;
978 int status;
979
980 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
981 if (status < 0)
982 return status;
983
984 do {
985 nrRetries += 1;
986 if (nrRetries > DRXD_MAX_RETRIES) {
987 status = -1;
988 break;
989 };
990 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
991 } while (waitCmd != 0);
992
993 if (status >= 0)
994 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
995 return status;
996 }
997
998 static int HI_CfgCommand(struct drxd_state *state)
999 {
1000 int status = 0;
1001
1002 mutex_lock(&state->mutex);
1003 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1004 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1005 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1006 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1007 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1008
1009 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1010
1011 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1012 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1013 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1014 HI_RA_RAM_SRV_CMD_CONFIG, 0);
1015 else
1016 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
1017 mutex_unlock(&state->mutex);
1018 return status;
1019 }
1020
1021 static int InitHI(struct drxd_state *state)
1022 {
1023 state->hi_cfg_wakeup_key = (state->chip_adr);
1024 /* port/bridge/power down ctrl */
1025 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1026 return HI_CfgCommand(state);
1027 }
1028
1029 static int HI_ResetCommand(struct drxd_state *state)
1030 {
1031 int status;
1032
1033 mutex_lock(&state->mutex);
1034 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1035 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1036 if (status == 0)
1037 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
1038 mutex_unlock(&state->mutex);
1039 msleep(1);
1040 return status;
1041 }
1042
1043 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1044 {
1045 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1046 if (bEnableBridge)
1047 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1048 else
1049 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1050
1051 return HI_CfgCommand(state);
1052 }
1053
1054 #define HI_TR_WRITE 0x9
1055 #define HI_TR_READ 0xA
1056 #define HI_TR_READ_WRITE 0xB
1057 #define HI_TR_BROADCAST 0x4
1058
1059 #if 0
1060 static int AtomicReadBlock(struct drxd_state *state,
1061 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1062 {
1063 int status;
1064 int i = 0;
1065
1066 /* Parameter check */
1067 if ((!pData) || ((DataSize & 1) != 0))
1068 return -1;
1069
1070 mutex_lock(&state->mutex);
1071
1072 do {
1073 /* Instruct HI to read n bytes */
1074 /* TODO use proper names forthese egisters */
1075 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1076 if (status < 0)
1077 break;
1078 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1079 if (status < 0)
1080 break;
1081 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1082 if (status < 0)
1083 break;
1084 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1085 if (status < 0)
1086 break;
1087 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1088 if (status < 0)
1089 break;
1090
1091 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1092 if (status < 0)
1093 break;
1094
1095 } while (0);
1096
1097 if (status >= 0) {
1098 for (i = 0; i < (DataSize / 2); i += 1) {
1099 u16 word;
1100
1101 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1102 &word, 0);
1103 if (status < 0)
1104 break;
1105 pData[2 * i] = (u8) (word & 0xFF);
1106 pData[(2 * i) + 1] = (u8) (word >> 8);
1107 }
1108 }
1109 mutex_unlock(&state->mutex);
1110 return status;
1111 }
1112
1113 static int AtomicReadReg32(struct drxd_state *state,
1114 u32 Addr, u32 *pData, u8 Flags)
1115 {
1116 u8 buf[sizeof(u32)];
1117 int status;
1118
1119 if (!pData)
1120 return -1;
1121 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1122 *pData = (((u32) buf[0]) << 0) +
1123 (((u32) buf[1]) << 8) +
1124 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1125 return status;
1126 }
1127 #endif
1128
1129 static int StopAllProcessors(struct drxd_state *state)
1130 {
1131 return Write16(state, HI_COMM_EXEC__A,
1132 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1133 }
1134
1135 static int EnableAndResetMB(struct drxd_state *state)
1136 {
1137 if (state->type_A) {
1138 /* disable? monitor bus observe @ EC_OC */
1139 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1140 }
1141
1142 /* do inverse broadcast, followed by explicit write to HI */
1143 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1144 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1145 return 0;
1146 }
1147
1148 static int InitCC(struct drxd_state *state)
1149 {
1150 if (state->osc_clock_freq == 0 ||
1151 state->osc_clock_freq > 20000 ||
1152 (state->osc_clock_freq % 4000) != 0) {
1153 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1154 return -1;
1155 }
1156
1157 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1158 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1159 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1160 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1161 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1162 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1163
1164 return 0;
1165 }
1166
1167 static int ResetECOD(struct drxd_state *state)
1168 {
1169 int status = 0;
1170
1171 if (state->type_A)
1172 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1173 else
1174 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1175
1176 if (!(status < 0))
1177 status = WriteTable(state, state->m_ResetECRAM);
1178 if (!(status < 0))
1179 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1180 return status;
1181 }
1182
1183 /* Configure PGA switch */
1184
1185 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1186 {
1187 int status;
1188 u16 AgModeLop = 0;
1189 u16 AgModeHip = 0;
1190 do {
1191 if (pgaSwitch) {
1192 /* PGA on */
1193 /* fine gain */
1194 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1195 if (status < 0)
1196 break;
1197 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1198 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1199 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1200 if (status < 0)
1201 break;
1202
1203 /* coarse gain */
1204 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1205 if (status < 0)
1206 break;
1207 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1208 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1209 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1210 if (status < 0)
1211 break;
1212
1213 /* enable fine and coarse gain, enable AAF,
1214 no ext resistor */
1215 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1216 if (status < 0)
1217 break;
1218 } else {
1219 /* PGA off, bypass */
1220
1221 /* fine gain */
1222 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1223 if (status < 0)
1224 break;
1225 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1226 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1227 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1228 if (status < 0)
1229 break;
1230
1231 /* coarse gain */
1232 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1233 if (status < 0)
1234 break;
1235 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1236 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1237 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1238 if (status < 0)
1239 break;
1240
1241 /* disable fine and coarse gain, enable AAF,
1242 no ext resistor */
1243 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1244 if (status < 0)
1245 break;
1246 }
1247 } while (0);
1248 return status;
1249 }
1250
1251 static int InitFE(struct drxd_state *state)
1252 {
1253 int status;
1254
1255 do {
1256 status = WriteTable(state, state->m_InitFE_1);
1257 if (status < 0)
1258 break;
1259
1260 if (state->type_A) {
1261 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1262 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1263 0);
1264 } else {
1265 if (state->PGA)
1266 status = SetCfgPga(state, 0);
1267 else
1268 status =
1269 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1270 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1271 0);
1272 }
1273
1274 if (status < 0)
1275 break;
1276 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1277 if (status < 0)
1278 break;
1279 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1280 if (status < 0)
1281 break;
1282
1283 status = WriteTable(state, state->m_InitFE_2);
1284 if (status < 0)
1285 break;
1286
1287 } while (0);
1288
1289 return status;
1290 }
1291
1292 static int InitFT(struct drxd_state *state)
1293 {
1294 /*
1295 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1296 SC stuff
1297 */
1298 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1299 }
1300
1301 static int SC_WaitForReady(struct drxd_state *state)
1302 {
1303 u16 curCmd;
1304 int i;
1305
1306 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1307 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1308 if (status == 0 || curCmd == 0)
1309 return status;
1310 }
1311 return -1;
1312 }
1313
1314 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1315 {
1316 int status = 0;
1317 u16 errCode;
1318
1319 Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1320 SC_WaitForReady(state);
1321
1322 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1323
1324 if (errCode == 0xFFFF) {
1325 printk(KERN_ERR "Command Error\n");
1326 status = -1;
1327 }
1328
1329 return status;
1330 }
1331
1332 static int SC_ProcStartCommand(struct drxd_state *state,
1333 u16 subCmd, u16 param0, u16 param1)
1334 {
1335 int status = 0;
1336 u16 scExec;
1337
1338 mutex_lock(&state->mutex);
1339 do {
1340 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1341 if (scExec != 1) {
1342 status = -1;
1343 break;
1344 }
1345 SC_WaitForReady(state);
1346 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1347 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1348 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1349
1350 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1351 } while (0);
1352 mutex_unlock(&state->mutex);
1353 return status;
1354 }
1355
1356 static int SC_SetPrefParamCommand(struct drxd_state *state,
1357 u16 subCmd, u16 param0, u16 param1)
1358 {
1359 int status;
1360
1361 mutex_lock(&state->mutex);
1362 do {
1363 status = SC_WaitForReady(state);
1364 if (status < 0)
1365 break;
1366 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1367 if (status < 0)
1368 break;
1369 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1370 if (status < 0)
1371 break;
1372 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1373 if (status < 0)
1374 break;
1375
1376 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1377 if (status < 0)
1378 break;
1379 } while (0);
1380 mutex_unlock(&state->mutex);
1381 return status;
1382 }
1383
1384 #if 0
1385 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1386 {
1387 int status = 0;
1388
1389 mutex_lock(&state->mutex);
1390 do {
1391 status = SC_WaitForReady(state);
1392 if (status < 0)
1393 break;
1394 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1395 if (status < 0)
1396 break;
1397 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1398 if (status < 0)
1399 break;
1400 } while (0);
1401 mutex_unlock(&state->mutex);
1402 return status;
1403 }
1404 #endif
1405
1406 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1407 {
1408 int status;
1409
1410 do {
1411 u16 EcOcRegIprInvMpg = 0;
1412 u16 EcOcRegOcModeLop = 0;
1413 u16 EcOcRegOcModeHip = 0;
1414 u16 EcOcRegOcMpgSio = 0;
1415
1416 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1417
1418 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1419 if (bEnableOutput) {
1420 EcOcRegOcModeHip |=
1421 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1422 } else
1423 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1424 EcOcRegOcModeLop |=
1425 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1426 } else {
1427 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1428
1429 if (bEnableOutput)
1430 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1431 else
1432 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1433
1434 /* Don't Insert RS Byte */
1435 if (state->insert_rs_byte) {
1436 EcOcRegOcModeLop &=
1437 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1438 EcOcRegOcModeHip &=
1439 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1440 EcOcRegOcModeHip |=
1441 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1442 } else {
1443 EcOcRegOcModeLop |=
1444 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1445 EcOcRegOcModeHip &=
1446 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1447 EcOcRegOcModeHip |=
1448 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1449 }
1450
1451 /* Mode = Parallel */
1452 if (state->enable_parallel)
1453 EcOcRegOcModeLop &=
1454 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1455 else
1456 EcOcRegOcModeLop |=
1457 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1458 }
1459 /* Invert Data */
1460 /* EcOcRegIprInvMpg |= 0x00FF; */
1461 EcOcRegIprInvMpg &= (~(0x00FF));
1462
1463 /* Invert Error ( we don't use the pin ) */
1464 /* EcOcRegIprInvMpg |= 0x0100; */
1465 EcOcRegIprInvMpg &= (~(0x0100));
1466
1467 /* Invert Start ( we don't use the pin ) */
1468 /* EcOcRegIprInvMpg |= 0x0200; */
1469 EcOcRegIprInvMpg &= (~(0x0200));
1470
1471 /* Invert Valid ( we don't use the pin ) */
1472 /* EcOcRegIprInvMpg |= 0x0400; */
1473 EcOcRegIprInvMpg &= (~(0x0400));
1474
1475 /* Invert Clock */
1476 /* EcOcRegIprInvMpg |= 0x0800; */
1477 EcOcRegIprInvMpg &= (~(0x0800));
1478
1479 /* EcOcRegOcModeLop =0x05; */
1480 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1481 if (status < 0)
1482 break;
1483 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1484 if (status < 0)
1485 break;
1486 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1487 if (status < 0)
1488 break;
1489 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1490 if (status < 0)
1491 break;
1492 } while (0);
1493 return status;
1494 }
1495
1496 static int SetDeviceTypeId(struct drxd_state *state)
1497 {
1498 int status = 0;
1499 u16 deviceId = 0;
1500
1501 do {
1502 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1503 if (status < 0)
1504 break;
1505 /* TODO: why twice? */
1506 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1507 if (status < 0)
1508 break;
1509 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1510
1511 state->type_A = 0;
1512 state->PGA = 0;
1513 state->diversity = 0;
1514 if (deviceId == 0) { /* on A2 only 3975 available */
1515 state->type_A = 1;
1516 printk(KERN_INFO "DRX3975D-A2\n");
1517 } else {
1518 deviceId >>= 12;
1519 printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1520 switch (deviceId) {
1521 case 4:
1522 state->diversity = 1;
1523 case 3:
1524 case 7:
1525 state->PGA = 1;
1526 break;
1527 case 6:
1528 state->diversity = 1;
1529 case 5:
1530 case 8:
1531 break;
1532 default:
1533 status = -1;
1534 break;
1535 }
1536 }
1537 } while (0);
1538
1539 if (status < 0)
1540 return status;
1541
1542 /* Init Table selection */
1543 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1544 state->m_InitSC = DRXD_InitSC;
1545 state->m_ResetECRAM = DRXD_ResetECRAM;
1546 if (state->type_A) {
1547 state->m_ResetCEFR = DRXD_ResetCEFR;
1548 state->m_InitFE_1 = DRXD_InitFEA2_1;
1549 state->m_InitFE_2 = DRXD_InitFEA2_2;
1550 state->m_InitCP = DRXD_InitCPA2;
1551 state->m_InitCE = DRXD_InitCEA2;
1552 state->m_InitEQ = DRXD_InitEQA2;
1553 state->m_InitEC = DRXD_InitECA2;
1554 if (load_firmware(state, DRX_FW_FILENAME_A2))
1555 return -EIO;
1556 } else {
1557 state->m_ResetCEFR = NULL;
1558 state->m_InitFE_1 = DRXD_InitFEB1_1;
1559 state->m_InitFE_2 = DRXD_InitFEB1_2;
1560 state->m_InitCP = DRXD_InitCPB1;
1561 state->m_InitCE = DRXD_InitCEB1;
1562 state->m_InitEQ = DRXD_InitEQB1;
1563 state->m_InitEC = DRXD_InitECB1;
1564 if (load_firmware(state, DRX_FW_FILENAME_B1))
1565 return -EIO;
1566 }
1567 if (state->diversity) {
1568 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1569 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1570 state->m_DisableDiversity = DRXD_DisableDiversity;
1571 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1572 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1573 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1574 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1575 } else {
1576 state->m_InitDiversityFront = NULL;
1577 state->m_InitDiversityEnd = NULL;
1578 state->m_DisableDiversity = NULL;
1579 state->m_StartDiversityFront = NULL;
1580 state->m_StartDiversityEnd = NULL;
1581 state->m_DiversityDelay8MHZ = NULL;
1582 state->m_DiversityDelay6MHZ = NULL;
1583 }
1584
1585 return status;
1586 }
1587
1588 static int CorrectSysClockDeviation(struct drxd_state *state)
1589 {
1590 int status;
1591 s32 incr = 0;
1592 s32 nomincr = 0;
1593 u32 bandwidth = 0;
1594 u32 sysClockInHz = 0;
1595 u32 sysClockFreq = 0; /* in kHz */
1596 s16 oscClockDeviation;
1597 s16 Diff;
1598
1599 do {
1600 /* Retrieve bandwidth and incr, sanity check */
1601
1602 /* These accesses should be AtomicReadReg32, but that
1603 causes trouble (at least for diversity */
1604 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1605 if (status < 0)
1606 break;
1607 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1608 if (status < 0)
1609 break;
1610
1611 if (state->type_A) {
1612 if ((nomincr - incr < -500) || (nomincr - incr > 500))
1613 break;
1614 } else {
1615 if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1616 break;
1617 }
1618
1619 switch (state->param.u.ofdm.bandwidth) {
1620 case BANDWIDTH_8_MHZ:
1621 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1622 break;
1623 case BANDWIDTH_7_MHZ:
1624 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1625 break;
1626 case BANDWIDTH_6_MHZ:
1627 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1628 break;
1629 default:
1630 return -1;
1631 break;
1632 }
1633
1634 /* Compute new sysclock value
1635 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1636 incr += (1 << 23);
1637 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1638 sysClockFreq = (u32) (sysClockInHz / 1000);
1639 /* rounding */
1640 if ((sysClockInHz % 1000) > 500)
1641 sysClockFreq++;
1642
1643 /* Compute clock deviation in ppm */
1644 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1645 (s32)
1646 (state->expected_sys_clock_freq)) *
1647 1000000L) /
1648 (s32)
1649 (state->expected_sys_clock_freq));
1650
1651 Diff = oscClockDeviation - state->osc_clock_deviation;
1652 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1653 if (Diff >= -200 && Diff <= 200) {
1654 state->sys_clock_freq = (u16) sysClockFreq;
1655 if (oscClockDeviation != state->osc_clock_deviation) {
1656 if (state->config.osc_deviation) {
1657 state->config.osc_deviation(state->priv,
1658 oscClockDeviation,
1659 1);
1660 state->osc_clock_deviation =
1661 oscClockDeviation;
1662 }
1663 }
1664 /* switch OFF SRMM scan in SC */
1665 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1666 if (status < 0)
1667 break;
1668 /* overrule FE_IF internal value for
1669 proper re-locking */
1670 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1671 if (status < 0)
1672 break;
1673 state->cscd_state = CSCD_SAVED;
1674 }
1675 } while (0);
1676
1677 return status;
1678 }
1679
1680 static int DRX_Stop(struct drxd_state *state)
1681 {
1682 int status;
1683
1684 if (state->drxd_state != DRXD_STARTED)
1685 return 0;
1686
1687 do {
1688 if (state->cscd_state != CSCD_SAVED) {
1689 u32 lock;
1690 status = DRX_GetLockStatus(state, &lock);
1691 if (status < 0)
1692 break;
1693 }
1694
1695 status = StopOC(state);
1696 if (status < 0)
1697 break;
1698
1699 state->drxd_state = DRXD_STOPPED;
1700
1701 status = ConfigureMPEGOutput(state, 0);
1702 if (status < 0)
1703 break;
1704
1705 if (state->type_A) {
1706 /* Stop relevant processors off the device */
1707 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1708 if (status < 0)
1709 break;
1710
1711 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1712 if (status < 0)
1713 break;
1714 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1715 if (status < 0)
1716 break;
1717 } else {
1718 /* Stop all processors except HI & CC & FE */
1719 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1720 if (status < 0)
1721 break;
1722 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1723 if (status < 0)
1724 break;
1725 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1726 if (status < 0)
1727 break;
1728 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1729 if (status < 0)
1730 break;
1731 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1732 if (status < 0)
1733 break;
1734 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1735 if (status < 0)
1736 break;
1737 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1738 if (status < 0)
1739 break;
1740 }
1741
1742 } while (0);
1743 return status;
1744 }
1745
1746 int SetOperationMode(struct drxd_state *state, int oMode)
1747 {
1748 int status;
1749
1750 do {
1751 if (state->drxd_state != DRXD_STOPPED) {
1752 status = -1;
1753 break;
1754 }
1755
1756 if (oMode == state->operation_mode) {
1757 status = 0;
1758 break;
1759 }
1760
1761 if (oMode != OM_Default && !state->diversity) {
1762 status = -1;
1763 break;
1764 }
1765
1766 switch (oMode) {
1767 case OM_DVBT_Diversity_Front:
1768 status = WriteTable(state, state->m_InitDiversityFront);
1769 break;
1770 case OM_DVBT_Diversity_End:
1771 status = WriteTable(state, state->m_InitDiversityEnd);
1772 break;
1773 case OM_Default:
1774 /* We need to check how to
1775 get DRXD out of diversity */
1776 default:
1777 status = WriteTable(state, state->m_DisableDiversity);
1778 break;
1779 }
1780 } while (0);
1781
1782 if (!status)
1783 state->operation_mode = oMode;
1784 return status;
1785 }
1786
1787 static int StartDiversity(struct drxd_state *state)
1788 {
1789 int status = 0;
1790 u16 rcControl;
1791
1792 do {
1793 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1794 status = WriteTable(state, state->m_StartDiversityFront);
1795 if (status < 0)
1796 break;
1797 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1798 status = WriteTable(state, state->m_StartDiversityEnd);
1799 if (status < 0)
1800 break;
1801 if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
1802 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1803 if (status < 0)
1804 break;
1805 } else {
1806 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1807 if (status < 0)
1808 break;
1809 }
1810
1811 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1812 if (status < 0)
1813 break;
1814 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1815 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1816 /* combining enabled */
1817 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1818 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1819 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1820 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1821 if (status < 0)
1822 break;
1823 }
1824 } while (0);
1825 return status;
1826 }
1827
1828 static int SetFrequencyShift(struct drxd_state *state,
1829 u32 offsetFreq, int channelMirrored)
1830 {
1831 int negativeShift = (state->tuner_mirrors == channelMirrored);
1832
1833 /* Handle all mirroring
1834 *
1835 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1836 * feFsRegAddInc to 28 bits below
1837 * (if the result before masking is more than 28 bits, this means
1838 * that the ADC is mirroring.
1839 * The masking is in fact the aliasing of the ADC)
1840 *
1841 */
1842
1843 /* Compute register value, unsigned computation */
1844 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1845 offsetFreq,
1846 1 << 28, state->sys_clock_freq);
1847 /* Remove integer part */
1848 state->fe_fs_add_incr &= 0x0FFFFFFFL;
1849 if (negativeShift)
1850 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1851
1852 /* Save the frequency shift without tunerOffset compensation
1853 for CtrlGetChannel. */
1854 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1855 1 << 28, state->sys_clock_freq);
1856 /* Remove integer part */
1857 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1858 if (negativeShift)
1859 state->org_fe_fs_add_incr = ((1L << 28) -
1860 state->org_fe_fs_add_incr);
1861
1862 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1863 state->fe_fs_add_incr, 0);
1864 }
1865
1866 static int SetCfgNoiseCalibration(struct drxd_state *state,
1867 struct SNoiseCal *noiseCal)
1868 {
1869 u16 beOptEna;
1870 int status = 0;
1871
1872 do {
1873 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1874 if (status < 0)
1875 break;
1876 if (noiseCal->cpOpt) {
1877 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1878 } else {
1879 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1880 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1881 if (status < 0)
1882 break;
1883 }
1884 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1885 if (status < 0)
1886 break;
1887
1888 if (!state->type_A) {
1889 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1890 if (status < 0)
1891 break;
1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1893 if (status < 0)
1894 break;
1895 }
1896 } while (0);
1897
1898 return status;
1899 }
1900
1901 static int DRX_Start(struct drxd_state *state, s32 off)
1902 {
1903 struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
1904 int status;
1905
1906 u16 transmissionParams = 0;
1907 u16 operationMode = 0;
1908 u16 qpskTdTpsPwr = 0;
1909 u16 qam16TdTpsPwr = 0;
1910 u16 qam64TdTpsPwr = 0;
1911 u32 feIfIncr = 0;
1912 u32 bandwidth = 0;
1913 int mirrorFreqSpect;
1914
1915 u16 qpskSnCeGain = 0;
1916 u16 qam16SnCeGain = 0;
1917 u16 qam64SnCeGain = 0;
1918 u16 qpskIsGainMan = 0;
1919 u16 qam16IsGainMan = 0;
1920 u16 qam64IsGainMan = 0;
1921 u16 qpskIsGainExp = 0;
1922 u16 qam16IsGainExp = 0;
1923 u16 qam64IsGainExp = 0;
1924 u16 bandwidthParam = 0;
1925
1926 if (off < 0)
1927 off = (off - 500) / 1000;
1928 else
1929 off = (off + 500) / 1000;
1930
1931 do {
1932 if (state->drxd_state != DRXD_STOPPED)
1933 return -1;
1934 status = ResetECOD(state);
1935 if (status < 0)
1936 break;
1937 if (state->type_A) {
1938 status = InitSC(state);
1939 if (status < 0)
1940 break;
1941 } else {
1942 status = InitFT(state);
1943 if (status < 0)
1944 break;
1945 status = InitCP(state);
1946 if (status < 0)
1947 break;
1948 status = InitCE(state);
1949 if (status < 0)
1950 break;
1951 status = InitEQ(state);
1952 if (status < 0)
1953 break;
1954 status = InitSC(state);
1955 if (status < 0)
1956 break;
1957 }
1958
1959 /* Restore current IF & RF AGC settings */
1960
1961 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1962 if (status < 0)
1963 break;
1964 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1965 if (status < 0)
1966 break;
1967
1968 mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1969
1970 switch (p->transmission_mode) {
1971 default: /* Not set, detect it automatically */
1972 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1973 /* fall through , try first guess DRX_FFTMODE_8K */
1974 case TRANSMISSION_MODE_8K:
1975 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1976 if (state->type_A) {
1977 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1978 if (status < 0)
1979 break;
1980 qpskSnCeGain = 99;
1981 qam16SnCeGain = 83;
1982 qam64SnCeGain = 67;
1983 }
1984 break;
1985 case TRANSMISSION_MODE_2K:
1986 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1987 if (state->type_A) {
1988 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1989 if (status < 0)
1990 break;
1991 qpskSnCeGain = 97;
1992 qam16SnCeGain = 71;
1993 qam64SnCeGain = 65;
1994 }
1995 break;
1996 }
1997
1998 switch (p->guard_interval) {
1999 case GUARD_INTERVAL_1_4:
2000 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2001 break;
2002 case GUARD_INTERVAL_1_8:
2003 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2004 break;
2005 case GUARD_INTERVAL_1_16:
2006 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2007 break;
2008 case GUARD_INTERVAL_1_32:
2009 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2010 break;
2011 default: /* Not set, detect it automatically */
2012 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2013 /* try first guess 1/4 */
2014 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2015 break;
2016 }
2017
2018 switch (p->hierarchy_information) {
2019 case HIERARCHY_1:
2020 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2021 if (state->type_A) {
2022 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2023 if (status < 0)
2024 break;
2025 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2026 if (status < 0)
2027 break;
2028
2029 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2030 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2031 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2032
2033 qpskIsGainMan =
2034 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2035 qam16IsGainMan =
2036 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2037 qam64IsGainMan =
2038 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2039
2040 qpskIsGainExp =
2041 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2042 qam16IsGainExp =
2043 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2044 qam64IsGainExp =
2045 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2046 }
2047 break;
2048
2049 case HIERARCHY_2:
2050 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2051 if (state->type_A) {
2052 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2053 if (status < 0)
2054 break;
2055 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2056 if (status < 0)
2057 break;
2058
2059 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2060 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2061 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2062
2063 qpskIsGainMan =
2064 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2065 qam16IsGainMan =
2066 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2067 qam64IsGainMan =
2068 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2069
2070 qpskIsGainExp =
2071 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2072 qam16IsGainExp =
2073 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2074 qam64IsGainExp =
2075 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2076 }
2077 break;
2078 case HIERARCHY_4:
2079 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2080 if (state->type_A) {
2081 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2082 if (status < 0)
2083 break;
2084 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2085 if (status < 0)
2086 break;
2087
2088 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2089 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2090 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2091
2092 qpskIsGainMan =
2093 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2094 qam16IsGainMan =
2095 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2096 qam64IsGainMan =
2097 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2098
2099 qpskIsGainExp =
2100 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2101 qam16IsGainExp =
2102 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2103 qam64IsGainExp =
2104 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2105 }
2106 break;
2107 case HIERARCHY_AUTO:
2108 default:
2109 /* Not set, detect it automatically, start with none */
2110 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2111 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2112 if (state->type_A) {
2113 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2114 if (status < 0)
2115 break;
2116 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2117 if (status < 0)
2118 break;
2119
2120 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2121 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2122 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2123
2124 qpskIsGainMan =
2125 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2126 qam16IsGainMan =
2127 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2128 qam64IsGainMan =
2129 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2130
2131 qpskIsGainExp =
2132 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2133 qam16IsGainExp =
2134 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2135 qam64IsGainExp =
2136 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2137 }
2138 break;
2139 }
2140 status = status;
2141 if (status < 0)
2142 break;
2143
2144 switch (p->constellation) {
2145 default:
2146 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2147 /* fall through , try first guess
2148 DRX_CONSTELLATION_QAM64 */
2149 case QAM_64:
2150 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2151 if (state->type_A) {
2152 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2153 if (status < 0)
2154 break;
2155 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2156 if (status < 0)
2157 break;
2158 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2159 if (status < 0)
2160 break;
2161 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2162 if (status < 0)
2163 break;
2164 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2165 if (status < 0)
2166 break;
2167
2168 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2169 if (status < 0)
2170 break;
2171 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2172 if (status < 0)
2173 break;
2174 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2175 if (status < 0)
2176 break;
2177 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2178 if (status < 0)
2179 break;
2180 }
2181 break;
2182 case QPSK:
2183 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2184 if (state->type_A) {
2185 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2186 if (status < 0)
2187 break;
2188 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2189 if (status < 0)
2190 break;
2191 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2192 if (status < 0)
2193 break;
2194 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2195 if (status < 0)
2196 break;
2197 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2198 if (status < 0)
2199 break;
2200
2201 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2202 if (status < 0)
2203 break;
2204 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2205 if (status < 0)
2206 break;
2207 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2208 if (status < 0)
2209 break;
2210 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2211 if (status < 0)
2212 break;
2213 }
2214 break;
2215
2216 case QAM_16:
2217 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2218 if (state->type_A) {
2219 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2220 if (status < 0)
2221 break;
2222 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2223 if (status < 0)
2224 break;
2225 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2226 if (status < 0)
2227 break;
2228 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2229 if (status < 0)
2230 break;
2231 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2232 if (status < 0)
2233 break;
2234
2235 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2236 if (status < 0)
2237 break;
2238 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2239 if (status < 0)
2240 break;
2241 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2242 if (status < 0)
2243 break;
2244 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2245 if (status < 0)
2246 break;
2247 }
2248 break;
2249
2250 }
2251 status = status;
2252 if (status < 0)
2253 break;
2254
2255 switch (DRX_CHANNEL_HIGH) {
2256 default:
2257 case DRX_CHANNEL_AUTO:
2258 case DRX_CHANNEL_LOW:
2259 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2260 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2261 if (status < 0)
2262 break;
2263 break;
2264 case DRX_CHANNEL_HIGH:
2265 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2266 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2267 if (status < 0)
2268 break;
2269 break;
2270
2271 }
2272
2273 switch (p->code_rate_HP) {
2274 case FEC_1_2:
2275 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2276 if (state->type_A) {
2277 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2278 if (status < 0)
2279 break;
2280 }
2281 break;
2282 default:
2283 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2284 case FEC_2_3:
2285 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2286 if (state->type_A) {
2287 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2288 if (status < 0)
2289 break;
2290 }
2291 break;
2292 case FEC_3_4:
2293 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2294 if (state->type_A) {
2295 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2296 if (status < 0)
2297 break;
2298 }
2299 break;
2300 case FEC_5_6:
2301 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2302 if (state->type_A) {
2303 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2304 if (status < 0)
2305 break;
2306 }
2307 break;
2308 case FEC_7_8:
2309 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2310 if (state->type_A) {
2311 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2312 if (status < 0)
2313 break;
2314 }
2315 break;
2316 }
2317 status = status;
2318 if (status < 0)
2319 break;
2320
2321 /* First determine real bandwidth (Hz) */
2322 /* Also set delay for impulse noise cruncher (only A2) */
2323 /* Also set parameters for EC_OC fix, note
2324 EC_OC_REG_TMD_HIL_MAR is changed
2325 by SC for fix for some 8K,1/8 guard but is restored by
2326 InitEC and ResetEC
2327 functions */
2328 switch (p->bandwidth) {
2329 case BANDWIDTH_AUTO:
2330 case BANDWIDTH_8_MHZ:
2331 /* (64/7)*(8/8)*1000000 */
2332 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2333
2334 bandwidthParam = 0;
2335 status = Write16(state,
2336 FE_AG_REG_IND_DEL__A, 50, 0x0000);
2337 break;
2338 case BANDWIDTH_7_MHZ:
2339 /* (64/7)*(7/8)*1000000 */
2340 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2341 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
2342 status = Write16(state,
2343 FE_AG_REG_IND_DEL__A, 59, 0x0000);
2344 break;
2345 case BANDWIDTH_6_MHZ:
2346 /* (64/7)*(6/8)*1000000 */
2347 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2348 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
2349 status = Write16(state,
2350 FE_AG_REG_IND_DEL__A, 71, 0x0000);
2351 break;
2352 default:
2353 status = -EINVAL;
2354 }
2355 if (status < 0)
2356 break;
2357
2358 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2359 if (status < 0)
2360 break;
2361
2362 {
2363 u16 sc_config;
2364 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2365 if (status < 0)
2366 break;
2367
2368 /* enable SLAVE mode in 2k 1/32 to
2369 prevent timing change glitches */
2370 if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2371 (p->guard_interval == GUARD_INTERVAL_1_32)) {
2372 /* enable slave */
2373 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2374 } else {
2375 /* disable slave */
2376 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2377 }
2378 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2379 if (status < 0)
2380 break;
2381 }
2382
2383 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2384 if (status < 0)
2385 break;
2386
2387 if (state->cscd_state == CSCD_INIT) {
2388 /* switch on SRMM scan in SC */
2389 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2390 if (status < 0)
2391 break;
2392 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2393 state->cscd_state = CSCD_SET;
2394 }
2395
2396 /* Now compute FE_IF_REG_INCR */
2397 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2398 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2399 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2400 (1ULL << 21), bandwidth) - (1 << 23);
2401 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2402 if (status < 0)
2403 break;
2404 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2405 if (status < 0)
2406 break;
2407 /* Bandwidth setting done */
2408
2409 /* Mirror & frequency offset */
2410 SetFrequencyShift(state, off, mirrorFreqSpect);
2411
2412 /* Start SC, write channel settings to SC */
2413
2414 /* Enable SC after setting all other parameters */
2415 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2416 if (status < 0)
2417 break;
2418 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2419 if (status < 0)
2420 break;
2421
2422 /* Write SC parameter registers, operation mode */
2423 #if 1
2424 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2425 SC_RA_RAM_OP_AUTO_GUARD__M |
2426 SC_RA_RAM_OP_AUTO_CONST__M |
2427 SC_RA_RAM_OP_AUTO_HIER__M |
2428 SC_RA_RAM_OP_AUTO_RATE__M);
2429 #endif
2430 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2431 if (status < 0)
2432 break;
2433
2434 /* Start correct processes to get in lock */
2435 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2436 if (status < 0)
2437 break;
2438
2439 status = StartOC(state);
2440 if (status < 0)
2441 break;
2442
2443 if (state->operation_mode != OM_Default) {
2444 status = StartDiversity(state);
2445 if (status < 0)
2446 break;
2447 }
2448
2449 state->drxd_state = DRXD_STARTED;
2450 } while (0);
2451
2452 return status;
2453 }
2454
2455 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2456 {
2457 u32 ulRfAgcOutputLevel = 0xffffffff;
2458 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2459 u32 ulRfAgcMinLevel = 0; /* Currently unused */
2460 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2461 u32 ulRfAgcSpeed = 0; /* Currently unused */
2462 u32 ulRfAgcMode = 0; /*2; Off */
2463 u32 ulRfAgcR1 = 820;
2464 u32 ulRfAgcR2 = 2200;
2465 u32 ulRfAgcR3 = 150;
2466 u32 ulIfAgcMode = 0; /* Auto */
2467 u32 ulIfAgcOutputLevel = 0xffffffff;
2468 u32 ulIfAgcSettleLevel = 0xffffffff;
2469 u32 ulIfAgcMinLevel = 0xffffffff;
2470 u32 ulIfAgcMaxLevel = 0xffffffff;
2471 u32 ulIfAgcSpeed = 0xffffffff;
2472 u32 ulIfAgcR1 = 820;
2473 u32 ulIfAgcR2 = 2200;
2474 u32 ulIfAgcR3 = 150;
2475 u32 ulClock = state->config.clock;
2476 u32 ulSerialMode = 0;
2477 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
2478 u32 ulHiI2cDelay = HI_I2C_DELAY;
2479 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2480 u32 ulHiI2cPatch = 0;
2481 u32 ulEnvironment = APPENV_PORTABLE;
2482 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2483 u32 ulIFFilter = IFFILTER_SAW;
2484
2485 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2486 state->if_agc_cfg.outputLevel = 0;
2487 state->if_agc_cfg.settleLevel = 140;
2488 state->if_agc_cfg.minOutputLevel = 0;
2489 state->if_agc_cfg.maxOutputLevel = 1023;
2490 state->if_agc_cfg.speed = 904;
2491
2492 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2493 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2494 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2495 }
2496
2497 if (ulIfAgcMode == 0 &&
2498 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2499 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2500 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2501 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2502 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2503 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2504 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2505 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2506 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2507 }
2508
2509 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2510 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2511 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2512
2513 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2514 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2515 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2516
2517 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2518 /* rest of the RFAgcCfg structure currently unused */
2519 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2520 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2521 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2522 }
2523
2524 if (ulRfAgcMode == 0 &&
2525 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2526 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2527 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2528 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2529 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2530 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2531 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2532 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2533 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2534 }
2535
2536 if (ulRfAgcMode == 2)
2537 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2538
2539 if (ulEnvironment <= 2)
2540 state->app_env_default = (enum app_env)
2541 (ulEnvironment);
2542 if (ulEnvironmentDiversity <= 2)
2543 state->app_env_diversity = (enum app_env)
2544 (ulEnvironmentDiversity);
2545
2546 if (ulIFFilter == IFFILTER_DISCRETE) {
2547 /* discrete filter */
2548 state->noise_cal.cpOpt = 0;
2549 state->noise_cal.cpNexpOfs = 40;
2550 state->noise_cal.tdCal2k = -40;
2551 state->noise_cal.tdCal8k = -24;
2552 } else {
2553 /* SAW filter */
2554 state->noise_cal.cpOpt = 1;
2555 state->noise_cal.cpNexpOfs = 0;
2556 state->noise_cal.tdCal2k = -21;
2557 state->noise_cal.tdCal8k = -24;
2558 }
2559 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2560
2561 state->chip_adr = (state->config.demod_address << 1) | 1;
2562 switch (ulHiI2cPatch) {
2563 case 1:
2564 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2565 break;
2566 case 3:
2567 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2568 break;
2569 default:
2570 state->m_HiI2cPatch = NULL;
2571 }
2572
2573 /* modify tuner and clock attributes */
2574 state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2575 /* expected system clock frequency in kHz */
2576 state->expected_sys_clock_freq = 48000;
2577 /* real system clock frequency in kHz */
2578 state->sys_clock_freq = 48000;
2579 state->osc_clock_freq = (u16) ulClock;
2580 state->osc_clock_deviation = 0;
2581 state->cscd_state = CSCD_INIT;
2582 state->drxd_state = DRXD_UNINITIALIZED;
2583
2584 state->PGA = 0;
2585 state->type_A = 0;
2586 state->tuner_mirrors = 0;
2587
2588 /* modify MPEG output attributes */
2589 state->insert_rs_byte = state->config.insert_rs_byte;
2590 state->enable_parallel = (ulSerialMode != 1);
2591
2592 /* Timing div, 250ns/Psys */
2593 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2594
2595 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2596 ulHiI2cDelay) / 1000;
2597 /* Bridge delay, uses oscilator clock */
2598 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2599 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2600 ulHiI2cBridgeDelay) / 1000;
2601
2602 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2603 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2604 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2605 return 0;
2606 }
2607
2608 int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2609 {
2610 int status = 0;
2611 u32 driverVersion;
2612
2613 if (state->init_done)
2614 return 0;
2615
2616 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2617
2618 do {
2619 state->operation_mode = OM_Default;
2620
2621 status = SetDeviceTypeId(state);
2622 if (status < 0)
2623 break;
2624
2625 /* Apply I2c address patch to B1 */
2626 if (!state->type_A && state->m_HiI2cPatch != NULL)
2627 status = WriteTable(state, state->m_HiI2cPatch);
2628 if (status < 0)
2629 break;
2630
2631 if (state->type_A) {
2632 /* HI firmware patch for UIO readout,
2633 avoid clearing of result register */
2634 status = Write16(state, 0x43012D, 0x047f, 0);
2635 if (status < 0)
2636 break;
2637 }
2638
2639 status = HI_ResetCommand(state);
2640 if (status < 0)
2641 break;
2642
2643 status = StopAllProcessors(state);
2644 if (status < 0)
2645 break;
2646 status = InitCC(state);
2647 if (status < 0)
2648 break;
2649
2650 state->osc_clock_deviation = 0;
2651
2652 if (state->config.osc_deviation)
2653 state->osc_clock_deviation =
2654 state->config.osc_deviation(state->priv, 0, 0);
2655 {
2656 /* Handle clock deviation */
2657 s32 devB;
2658 s32 devA = (s32) (state->osc_clock_deviation) *
2659 (s32) (state->expected_sys_clock_freq);
2660 /* deviation in kHz */
2661 s32 deviation = (devA / (1000000L));
2662 /* rounding, signed */
2663 if (devA > 0)
2664 devB = (2);
2665 else
2666 devB = (-2);
2667 if ((devB * (devA % 1000000L) > 1000000L)) {
2668 /* add +1 or -1 */
2669 deviation += (devB / 2);
2670 }
2671
2672 state->sys_clock_freq =
2673 (u16) ((state->expected_sys_clock_freq) +
2674 deviation);
2675 }
2676 status = InitHI(state);
2677 if (status < 0)
2678 break;
2679 status = InitAtomicRead(state);
2680 if (status < 0)
2681 break;
2682
2683 status = EnableAndResetMB(state);
2684 if (status < 0)
2685 break;
2686 if (state->type_A)
2687 status = ResetCEFR(state);
2688 if (status < 0)
2689 break;
2690
2691 if (fw) {
2692 status = DownloadMicrocode(state, fw, fw_size);
2693 if (status < 0)
2694 break;
2695 } else {
2696 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2697 if (status < 0)
2698 break;
2699 }
2700
2701 if (state->PGA) {
2702 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2703 SetCfgPga(state, 0); /* PGA = 0 dB */
2704 } else {
2705 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2706 }
2707
2708 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2709
2710 status = InitFE(state);
2711 if (status < 0)
2712 break;
2713 status = InitFT(state);
2714 if (status < 0)
2715 break;
2716 status = InitCP(state);
2717 if (status < 0)
2718 break;
2719 status = InitCE(state);
2720 if (status < 0)
2721 break;
2722 status = InitEQ(state);
2723 if (status < 0)
2724 break;
2725 status = InitEC(state);
2726 if (status < 0)
2727 break;
2728 status = InitSC(state);
2729 if (status < 0)
2730 break;
2731
2732 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2733 if (status < 0)
2734 break;
2735 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2736 if (status < 0)
2737 break;
2738
2739 state->cscd_state = CSCD_INIT;
2740 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2741 if (status < 0)
2742 break;
2743 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2744 if (status < 0)
2745 break;
2746
2747 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2748 (VERSION_MAJOR % 10)) << 24;
2749 driverVersion += (((VERSION_MINOR / 10) << 4) +
2750 (VERSION_MINOR % 10)) << 16;
2751 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2752 ((VERSION_PATCH / 100) << 8) +
2753 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2754
2755 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2756 if (status < 0)
2757 break;
2758
2759 status = StopOC(state);
2760 if (status < 0)
2761 break;
2762
2763 state->drxd_state = DRXD_STOPPED;
2764 state->init_done = 1;
2765 status = 0;
2766 } while (0);
2767 return status;
2768 }
2769
2770 int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
2771 {
2772 DRX_GetLockStatus(state, pLockStatus);
2773
2774 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2775 if (*pLockStatus & DRX_LOCK_FEC) {
2776 ConfigureMPEGOutput(state, 1);
2777 /* Get status again, in case we have MPEG lock now */
2778 /*DRX_GetLockStatus(state, pLockStatus); */
2779 }
2780
2781 return 0;
2782 }
2783
2784 /****************************************************************************/
2785 /****************************************************************************/
2786 /****************************************************************************/
2787
2788 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2789 {
2790 struct drxd_state *state = fe->demodulator_priv;
2791 u32 value;
2792 int res;
2793
2794 res = ReadIFAgc(state, &value);
2795 if (res < 0)
2796 *strength = 0;
2797 else
2798 *strength = 0xffff - (value << 4);
2799 return 0;
2800 }
2801
2802 static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2803 {
2804 struct drxd_state *state = fe->demodulator_priv;
2805 u32 lock;
2806
2807 DRXD_status(state, &lock);
2808 *status = 0;
2809 /* No MPEG lock in V255 firmware, bug ? */
2810 #if 1
2811 if (lock & DRX_LOCK_MPEG)
2812 *status |= FE_HAS_LOCK;
2813 #else
2814 if (lock & DRX_LOCK_FEC)
2815 *status |= FE_HAS_LOCK;
2816 #endif
2817 if (lock & DRX_LOCK_FEC)
2818 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2819 if (lock & DRX_LOCK_DEMOD)
2820 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2821
2822 return 0;
2823 }
2824
2825 static int drxd_init(struct dvb_frontend *fe)
2826 {
2827 struct drxd_state *state = fe->demodulator_priv;
2828 int err = 0;
2829
2830 /* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2831 return DRXD_init(state, 0, 0);
2832
2833 err = DRXD_init(state, state->fw->data, state->fw->size);
2834 release_firmware(state->fw);
2835 return err;
2836 }
2837
2838 int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2839 {
2840 struct drxd_state *state = fe->demodulator_priv;
2841
2842 if (state->config.disable_i2c_gate_ctrl == 1)
2843 return 0;
2844
2845 return DRX_ConfigureI2CBridge(state, onoff);
2846 }
2847 EXPORT_SYMBOL(drxd_config_i2c);
2848
2849 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2850 struct dvb_frontend_tune_settings *sets)
2851 {
2852 sets->min_delay_ms = 10000;
2853 sets->max_drift = 0;
2854 sets->step_size = 0;
2855 return 0;
2856 }
2857
2858 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2859 {
2860 *ber = 0;
2861 return 0;
2862 }
2863
2864 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2865 {
2866 *snr = 0;
2867 return 0;
2868 }
2869
2870 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2871 {
2872 *ucblocks = 0;
2873 return 0;
2874 }
2875
2876 static int drxd_sleep(struct dvb_frontend *fe)
2877 {
2878 struct drxd_state *state = fe->demodulator_priv;
2879
2880 ConfigureMPEGOutput(state, 0);
2881 return 0;
2882 }
2883
2884 static int drxd_get_frontend(struct dvb_frontend *fe,
2885 struct dvb_frontend_parameters *param)
2886 {
2887 return 0;
2888 }
2889
2890 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2891 {
2892 return drxd_config_i2c(fe, enable);
2893 }
2894
2895 static int drxd_set_frontend(struct dvb_frontend *fe,
2896 struct dvb_frontend_parameters *param)
2897 {
2898 struct drxd_state *state = fe->demodulator_priv;
2899 s32 off = 0;
2900
2901 state->param = *param;
2902 DRX_Stop(state);
2903
2904 if (fe->ops.tuner_ops.set_params) {
2905 fe->ops.tuner_ops.set_params(fe, param);
2906 if (fe->ops.i2c_gate_ctrl)
2907 fe->ops.i2c_gate_ctrl(fe, 0);
2908 }
2909
2910 /* FIXME: move PLL drivers */
2911 if (state->config.pll_set &&
2912 state->config.pll_set(state->priv, param,
2913 state->config.pll_address,
2914 state->config.demoda_address, &off) < 0) {
2915 printk(KERN_ERR "Error in pll_set\n");
2916 return -1;
2917 }
2918
2919 msleep(200);
2920
2921 return DRX_Start(state, off);
2922 }
2923
2924 static void drxd_release(struct dvb_frontend *fe)
2925 {
2926 struct drxd_state *state = fe->demodulator_priv;
2927
2928 kfree(state);
2929 }
2930
2931 static struct dvb_frontend_ops drxd_ops = {
2932
2933 .info = {
2934 .name = "Micronas DRXD DVB-T",
2935 .type = FE_OFDM,
2936 .frequency_min = 47125000,
2937 .frequency_max = 855250000,
2938 .frequency_stepsize = 166667,
2939 .frequency_tolerance = 0,
2940 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2941 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2942 FE_CAN_FEC_AUTO |
2943 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2944 FE_CAN_QAM_AUTO |
2945 FE_CAN_TRANSMISSION_MODE_AUTO |
2946 FE_CAN_GUARD_INTERVAL_AUTO |
2947 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2948
2949 .release = drxd_release,
2950 .init = drxd_init,
2951 .sleep = drxd_sleep,
2952 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2953
2954 .set_frontend = drxd_set_frontend,
2955 .get_frontend = drxd_get_frontend,
2956 .get_tune_settings = drxd_get_tune_settings,
2957
2958 .read_status = drxd_read_status,
2959 .read_ber = drxd_read_ber,
2960 .read_signal_strength = drxd_read_signal_strength,
2961 .read_snr = drxd_read_snr,
2962 .read_ucblocks = drxd_read_ucblocks,
2963 };
2964
2965 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2966 void *priv, struct i2c_adapter *i2c,
2967 struct device *dev)
2968 {
2969 struct drxd_state *state = NULL;
2970
2971 state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2972 if (!state)
2973 return NULL;
2974 memset(state, 0, sizeof(*state));
2975
2976 memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
2977 state->dev = dev;
2978 state->config = *config;
2979 state->i2c = i2c;
2980 state->priv = priv;
2981
2982 mutex_init(&state->mutex);
2983
2984 if (Read16(state, 0, 0, 0) < 0)
2985 goto error;
2986
2987 memcpy(&state->frontend.ops, &drxd_ops,
2988 sizeof(struct dvb_frontend_ops));
2989 state->frontend.demodulator_priv = state;
2990 ConfigureMPEGOutput(state, 0);
2991 return &state->frontend;
2992
2993 error:
2994 printk(KERN_ERR "drxd: not found\n");
2995 kfree(state);
2996 return NULL;
2997 }
2998 EXPORT_SYMBOL(drxd_attach);
2999
3000 MODULE_DESCRIPTION("DRXD driver");
3001 MODULE_AUTHOR("Micronas");
3002 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree