drivers/usb/musb/omap2430.c

   1 /*
   2  * Copyright (C) 2005-2007 by Texas Instruments
   3  * Some code has been taken from tusb6010.c
   4  * Copyrights for that are attributable to:
   5  * Copyright (C) 2006 Nokia Corporation
   6  * Tony Lindgren <tony@atomide.com>
   7  *
   8  * This file is part of the Inventra Controller Driver for Linux.
   9  *
  10  * The Inventra Controller Driver for Linux is free software; you
  11  * can redistribute it and/or modify it under the terms of the GNU
  12  * General Public License version 2 as published by the Free Software
  13  * Foundation.
  14  *
  15  * The Inventra Controller Driver for Linux is distributed in
  16  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17  * without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  19  * License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with The Inventra Controller Driver for Linux ; if not,
  23  * write to the Free Software Foundation, Inc., 59 Temple Place,
  24  * Suite 330, Boston, MA  02111-1307  USA
  25  *
  26  */
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/sched.h>
  30 #include <linux/init.h>
  31 #include <linux/list.h>
  32 #include <linux/clk.h>
  33 #include <linux/io.h>
  34
  35 #include "musb_core.h"
  36 #include "omap2430.h"
  37
  38 static struct timer_list musb_idle_timer;
  39
  40 static void musb_do_idle(unsigned long _musb)
  41 {
  42         struct musb     *musb = (void *)_musb;
  43         unsigned long   flags;
  44 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  45         u8      power;
  46 #endif
  47         u8      devctl;
  48
  49         spin_lock_irqsave(&musb->lock, flags);
  50
  51         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  52
  53         switch (musb->xceiv->state) {
  54         case OTG_STATE_A_WAIT_BCON:
  55                 devctl &= ~MUSB_DEVCTL_SESSION;
  56                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  57
  58                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  59                 if (devctl & MUSB_DEVCTL_BDEVICE) {
  60                         musb->xceiv->state = OTG_STATE_B_IDLE;
  61                         MUSB_DEV_MODE(musb);
  62                 } else {
  63                         musb->xceiv->state = OTG_STATE_A_IDLE;
  64                         MUSB_HST_MODE(musb);
  65                 }
  66                 break;
  67 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  68         case OTG_STATE_A_SUSPEND:
  69                 /* finish RESUME signaling? */
  70                 if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
  71                         power = musb_readb(musb->mregs, MUSB_POWER);
  72                         power &= ~MUSB_POWER_RESUME;
  73                         DBG(1, "root port resume stopped, power %02x\n", power);
  74                         musb_writeb(musb->mregs, MUSB_POWER, power);
  75                         musb->is_active = 1;
  76                         musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
  77                                                 | MUSB_PORT_STAT_RESUME);
  78                         musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
  79                         usb_hcd_poll_rh_status(musb_to_hcd(musb));
  80                         /* NOTE: it might really be A_WAIT_BCON ... */
  81                         musb->xceiv->state = OTG_STATE_A_HOST;
  82                 }
  83                 break;
  84 #endif
  85 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  86         case OTG_STATE_A_HOST:
  87                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  88                 if (devctl &  MUSB_DEVCTL_BDEVICE)
  89                         musb->xceiv->state = OTG_STATE_B_IDLE;
  90                 else
  91                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  92 #endif
  93         default:
  94                 break;
  95         }
  96         spin_unlock_irqrestore(&musb->lock, flags);
  97 }
  98
  99
 100 static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
 101 {
 102         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
 103         static unsigned long    last_timer;
 104
 105         if (timeout == 0)
 106                 timeout = default_timeout;
 107
 108         /* Never idle if active, or when VBUS timeout is not set as host */
 109         if (musb->is_active || ((musb->a_wait_bcon == 0)
 110                         && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
 111                 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
 112                 del_timer(&musb_idle_timer);
 113                 last_timer = jiffies;
 114                 return;
 115         }
 116
 117         if (time_after(last_timer, timeout)) {
 118                 if (!timer_pending(&musb_idle_timer))
 119                         last_timer = timeout;
 120                 else {
 121                         DBG(4, "Longer idle timer already pending, ignoring\n");
 122                         return;
 123                 }
 124         }
 125         last_timer = timeout;
 126
 127         DBG(4, "%s inactive, for idle timer for %lu ms\n",
 128                 otg_state_string(musb),
 129                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
 130         mod_timer(&musb_idle_timer, timeout);
 131 }
 132
 133 static void omap2430_musb_enable(struct musb *musb)
 134 {
 135 }
 136
 137 static void omap2430_musb_disable(struct musb *musb)
 138 {
 139 }
 140
 141 static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
 142 {
 143         u8              devctl;
 144         /* HDRC controls CPEN, but beware current surges during device
 145          * connect.  They can trigger transient overcurrent conditions
 146          * that must be ignored.
 147          */
 148
 149         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 150
 151         if (is_on) {
 152                 musb->is_active = 1;
 153                 musb->xceiv->default_a = 1;
 154                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 155                 devctl |= MUSB_DEVCTL_SESSION;
 156
 157                 MUSB_HST_MODE(musb);
 158         } else {
 159                 musb->is_active = 0;
 160
 161                 /* NOTE:  we're skipping A_WAIT_VFALL -> A_IDLE and
 162                  * jumping right to B_IDLE...
 163                  */
 164
 165                 musb->xceiv->default_a = 0;
 166                 musb->xceiv->state = OTG_STATE_B_IDLE;
 167                 devctl &= ~MUSB_DEVCTL_SESSION;
 168
 169                 MUSB_DEV_MODE(musb);
 170         }
 171         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 172
 173         DBG(1, "VBUS %s, devctl %02x "
 174                 /* otg %3x conf %08x prcm %08x */ "\n",
 175                 otg_state_string(musb),
 176                 musb_readb(musb->mregs, MUSB_DEVCTL));
 177 }
 178
 179 static int omap2430_musb_resume(struct musb *musb);
 180
 181 static int omap2430_musb_set_mode(struct musb *musb, u8 musb_mode)
 182 {
 183         u8      devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 184
 185         devctl |= MUSB_DEVCTL_SESSION;
 186         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 187
 188         return 0;
 189 }
 190
 191 static int omap2430_musb_init(struct musb *musb)
 192 {
 193         u32 l;
 194         struct device *dev = musb->controller;
 195         struct musb_hdrc_platform_data *plat = dev->platform_data;
 196         struct omap_musb_board_data *data = plat->board_data;
 197
 198         /* We require some kind of external transceiver, hooked
 199          * up through ULPI.  TWL4030-family PMICs include one,
 200          * which needs a driver, drivers aren't always needed.
 201          */
 202         musb->xceiv = otg_get_transceiver();
 203         if (!musb->xceiv) {
 204                 pr_err("HS USB OTG: no transceiver configured\n");
 205                 return -ENODEV;
 206         }
 207
 208         omap2430_musb_resume(musb);
 209
 210         l = musb_readl(musb->mregs, OTG_SYSCONFIG);
 211         l &= ~ENABLEWAKEUP;     /* disable wakeup */
 212         l &= ~NOSTDBY;          /* remove possible nostdby */
 213         l |= SMARTSTDBY;        /* enable smart standby */
 214         l &= ~AUTOIDLE;         /* disable auto idle */
 215         l &= ~NOIDLE;           /* remove possible noidle */
 216         l |= SMARTIDLE;         /* enable smart idle */
 217         /*
 218          * MUSB AUTOIDLE don't work in 3430.
 219          * Workaround by Richard Woodruff/TI
 220          */
 221         if (!cpu_is_omap3430())
 222                 l |= AUTOIDLE;          /* enable auto idle */
 223         musb_writel(musb->mregs, OTG_SYSCONFIG, l);
 224
 225         l = musb_readl(musb->mregs, OTG_INTERFSEL);
 226
 227         if (data->interface_type == MUSB_INTERFACE_UTMI) {
 228                 /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
 229                 l &= ~ULPI_12PIN;       /* Disable ULPI */
 230                 l |= UTMI_8BIT;         /* Enable UTMI  */
 231         } else {
 232                 l |= ULPI_12PIN;
 233         }
 234
 235         musb_writel(musb->mregs, OTG_INTERFSEL, l);
 236
 237         pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
 238                         "sysstatus 0x%x, intrfsel 0x%x, simenable  0x%x\n",
 239                         musb_readl(musb->mregs, OTG_REVISION),
 240                         musb_readl(musb->mregs, OTG_SYSCONFIG),
 241                         musb_readl(musb->mregs, OTG_SYSSTATUS),
 242                         musb_readl(musb->mregs, OTG_INTERFSEL),
 243                         musb_readl(musb->mregs, OTG_SIMENABLE));
 244
 245         if (is_host_enabled(musb))
 246                 musb->board_set_vbus = omap2430_musb_set_vbus;
 247
 248         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
 249
 250         return 0;
 251 }
 252
 253 #ifdef CONFIG_PM
 254 void musb_platform_save_context(struct musb *musb,
 255                 struct musb_context_registers *musb_context)
 256 {
 257         musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG);
 258         musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY);
 259 }
 260
 261 void musb_platform_restore_context(struct musb *musb,
 262                 struct musb_context_registers *musb_context)
 263 {
 264         musb_writel(musb->mregs, OTG_SYSCONFIG, musb_context->otg_sysconfig);
 265         musb_writel(musb->mregs, OTG_FORCESTDBY, musb_context->otg_forcestandby);
 266 }
 267 #endif
 268
 269 static int omap2430_musb_suspend(struct musb *musb)
 270 {
 271         u32 l;
 272
 273         if (!musb->clock)
 274                 return 0;
 275
 276         /* in any role */
 277         l = musb_readl(musb->mregs, OTG_FORCESTDBY);
 278         l |= ENABLEFORCE;       /* enable MSTANDBY */
 279         musb_writel(musb->mregs, OTG_FORCESTDBY, l);
 280
 281         l = musb_readl(musb->mregs, OTG_SYSCONFIG);
 282         l |= ENABLEWAKEUP;      /* enable wakeup */
 283         musb_writel(musb->mregs, OTG_SYSCONFIG, l);
 284
 285         otg_set_suspend(musb->xceiv, 1);
 286
 287         if (musb->set_clock)
 288                 musb->set_clock(musb->clock, 0);
 289         else
 290                 clk_disable(musb->clock);
 291
 292         return 0;
 293 }
 294
 295 static int omap2430_musb_resume(struct musb *musb)
 296 {
 297         u32 l;
 298
 299         if (!musb->clock)
 300                 return 0;
 301
 302         otg_set_suspend(musb->xceiv, 0);
 303
 304         if (musb->set_clock)
 305                 musb->set_clock(musb->clock, 1);
 306         else
 307                 clk_enable(musb->clock);
 308
 309         l = musb_readl(musb->mregs, OTG_SYSCONFIG);
 310         l &= ~ENABLEWAKEUP;     /* disable wakeup */
 311         musb_writel(musb->mregs, OTG_SYSCONFIG, l);
 312
 313         l = musb_readl(musb->mregs, OTG_FORCESTDBY);
 314         l &= ~ENABLEFORCE;      /* disable MSTANDBY */
 315         musb_writel(musb->mregs, OTG_FORCESTDBY, l);
 316
 317         return 0;
 318 }
 319
 320 static int omap2430_musb_exit(struct musb *musb)
 321 {
 322
 323         omap2430_musb_suspend(musb);
 324
 325         otg_put_transceiver(musb->xceiv);
 326         return 0;
 327 }
 328
 329 const struct musb_platform_ops musb_ops = {
 330         .init           = omap2430_musb_init,
 331         .exit           = omap2430_musb_exit,
 332
 333         .suspend        = omap2430_musb_suspend,
 334         .resume         = omap2430_musb_resume,
 335
 336         .enable         = omap2430_musb_enable,
 337         .disable        = omap2430_musb_disable,
 338
 339         .set_mode       = omap2430_musb_set_mode,
 340         .try_idle       = omap2430_musb_try_idle,
 341
 342         .set_vbus       = omap2430_musb_set_vbus,
 343 };