drivers/net/wireless/rtlwifi/rtl8192se/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/vmalloc.h>
  33
  34 #include "../wifi.h"
  35 #include "../core.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "hw.h"
  43 #include "sw.h"
  44 #include "trx.h"
  45 #include "led.h"
  46
  47 static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
  48 {
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50
  51         /*close ASPM for AMD defaultly */
  52         rtlpci->const_amdpci_aspm = 0;
  53
  54         /*
  55          * ASPM PS mode.
  56          * 0 - Disable ASPM,
  57          * 1 - Enable ASPM without Clock Req,
  58          * 2 - Enable ASPM with Clock Req,
  59          * 3 - Alwyas Enable ASPM with Clock Req,
  60          * 4 - Always Enable ASPM without Clock Req.
  61          * set defult to RTL8192CE:3 RTL8192E:2
  62          * */
  63         rtlpci->const_pci_aspm = 2;
  64
  65         /*Setting for PCI-E device */
  66         rtlpci->const_devicepci_aspm_setting = 0x03;
  67
  68         /*Setting for PCI-E bridge */
  69         rtlpci->const_hostpci_aspm_setting = 0x02;
  70
  71         /*
  72          * In Hw/Sw Radio Off situation.
  73          * 0 - Default,
  74          * 1 - From ASPM setting without low Mac Pwr,
  75          * 2 - From ASPM setting with low Mac Pwr,
  76          * 3 - Bus D3
  77          * set default to RTL8192CE:0 RTL8192SE:2
  78          */
  79         rtlpci->const_hwsw_rfoff_d3 = 2;
  80
  81         /*
  82          * This setting works for those device with
  83          * backdoor ASPM setting such as EPHY setting.
  84          * 0 - Not support ASPM,
  85          * 1 - Support ASPM,
  86          * 2 - According to chipset.
  87          */
  88         rtlpci->const_support_pciaspm = 2;
  89 }
  90
  91 static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
  92 {
  93         struct rtl_priv *rtlpriv = rtl_priv(hw);
  94         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  95         const struct firmware *firmware;
  96         struct rt_firmware *pfirmware = NULL;
  97         int err = 0;
  98         u16 earlyrxthreshold = 7;
  99
 100         rtlpriv->dm.dm_initialgain_enable = 1;
 101         rtlpriv->dm.dm_flag = 0;
 102         rtlpriv->dm.disable_framebursting = 0;
 103         rtlpriv->dm.thermalvalue = 0;
 104         rtlpriv->dm.useramask = true;
 105
 106         /* compatible 5G band 91se just 2.4G band & smsp */
 107         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 108         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 109         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 110
 111         rtlpci->transmit_config = 0;
 112
 113         rtlpci->receive_config =
 114                         RCR_APPFCS |
 115                         RCR_APWRMGT |
 116                         /*RCR_ADD3 |*/
 117                         RCR_AMF |
 118                         RCR_ADF |
 119                         RCR_APP_MIC |
 120                         RCR_APP_ICV |
 121                         RCR_AICV |
 122                         /* Accept ICV error, CRC32 Error */
 123                         RCR_ACRC32 |
 124                         RCR_AB |
 125                         /* Accept Broadcast, Multicast */
 126                         RCR_AM  |
 127                         /* Accept Physical match */
 128                         RCR_APM |
 129                         /* Accept Destination Address packets */
 130                         /*RCR_AAP |*/
 131                         RCR_APP_PHYST_STAFF |
 132                         /* Accept PHY status */
 133                         RCR_APP_PHYST_RXFF |
 134                         (earlyrxthreshold << RCR_FIFO_OFFSET);
 135
 136         rtlpci->irq_mask[0] = (u32)
 137                         (IMR_ROK |
 138                         IMR_VODOK |
 139                         IMR_VIDOK |
 140                         IMR_BEDOK |
 141                         IMR_BKDOK |
 142                         IMR_HCCADOK |
 143                         IMR_MGNTDOK |
 144                         IMR_COMDOK |
 145                         IMR_HIGHDOK |
 146                         IMR_BDOK |
 147                         IMR_RXCMDOK |
 148                         /*IMR_TIMEOUT0 |*/
 149                         IMR_RDU |
 150                         IMR_RXFOVW      |
 151                         IMR_BCNINT
 152                         /*| IMR_TXFOVW*/
 153                         /*| IMR_TBDOK |
 154                         IMR_TBDER*/);
 155
 156         rtlpci->irq_mask[1] = (u32) 0;
 157
 158         rtlpci->shortretry_limit = 0x30;
 159         rtlpci->longretry_limit = 0x30;
 160
 161         rtlpci->first_init = true;
 162
 163         /* for debug level */
 164         rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
 165         /* for LPS & IPS */
 166         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 167         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 168         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 169         if (!rtlpriv->psc.inactiveps)
 170                 pr_info("rtl8192ce: Power Save off (module option)\n");
 171         if (!rtlpriv->psc.fwctrl_lps)
 172                 pr_info("rtl8192ce: FW Power Save off (module option)\n");
 173         rtlpriv->psc.reg_fwctrl_lps = 3;
 174         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 175         /* for ASPM, you can close aspm through
 176          * set const_support_pciaspm = 0 */
 177         rtl92s_init_aspm_vars(hw);
 178
 179         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 180                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 181         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 182                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 183         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 184                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 185
 186         /* for firmware buf */
 187         rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
 188         if (!rtlpriv->rtlhal.pfirmware) {
 189                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 190                          ("Can't alloc buffer for fw.\n"));
 191                 return 1;
 192         }
 193
 194         pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
 195                 "Loading firmware %s\n", rtlpriv->cfg->fw_name);
 196         /* request fw */
 197         err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
 198                         rtlpriv->io.dev);
 199         if (err) {
 200                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 201                          ("Failed to request firmware!\n"));
 202                 return 1;
 203         }
 204         if (firmware->size > sizeof(struct rt_firmware)) {
 205                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 206                          ("Firmware is too big!\n"));
 207                 release_firmware(firmware);
 208                 return 1;
 209         }
 210
 211         pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
 212         memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
 213         pfirmware->sz_fw_tmpbufferlen = firmware->size;
 214         release_firmware(firmware);
 215
 216         return err;
 217 }
 218
 219 static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
 220 {
 221         struct rtl_priv *rtlpriv = rtl_priv(hw);
 222
 223         if (rtlpriv->rtlhal.pfirmware) {
 224                 vfree(rtlpriv->rtlhal.pfirmware);
 225                 rtlpriv->rtlhal.pfirmware = NULL;
 226         }
 227 }
 228
 229 static struct rtl_hal_ops rtl8192se_hal_ops = {
 230         .init_sw_vars = rtl92s_init_sw_vars,
 231         .deinit_sw_vars = rtl92s_deinit_sw_vars,
 232         .read_eeprom_info = rtl92se_read_eeprom_info,
 233         .interrupt_recognized = rtl92se_interrupt_recognized,
 234         .hw_init = rtl92se_hw_init,
 235         .hw_disable = rtl92se_card_disable,
 236         .hw_suspend = rtl92se_suspend,
 237         .hw_resume = rtl92se_resume,
 238         .enable_interrupt = rtl92se_enable_interrupt,
 239         .disable_interrupt = rtl92se_disable_interrupt,
 240         .set_network_type = rtl92se_set_network_type,
 241         .set_chk_bssid = rtl92se_set_check_bssid,
 242         .set_qos = rtl92se_set_qos,
 243         .set_bcn_reg = rtl92se_set_beacon_related_registers,
 244         .set_bcn_intv = rtl92se_set_beacon_interval,
 245         .update_interrupt_mask = rtl92se_update_interrupt_mask,
 246         .get_hw_reg = rtl92se_get_hw_reg,
 247         .set_hw_reg = rtl92se_set_hw_reg,
 248         .update_rate_tbl = rtl92se_update_hal_rate_tbl,
 249         .fill_tx_desc = rtl92se_tx_fill_desc,
 250         .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
 251         .query_rx_desc = rtl92se_rx_query_desc,
 252         .set_channel_access = rtl92se_update_channel_access_setting,
 253         .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
 254         .set_bw_mode = rtl92s_phy_set_bw_mode,
 255         .switch_channel = rtl92s_phy_sw_chnl,
 256         .dm_watchdog = rtl92s_dm_watchdog,
 257         .scan_operation_backup = rtl92s_phy_scan_operation_backup,
 258         .set_rf_power_state = rtl92s_phy_set_rf_power_state,
 259         .led_control = rtl92se_led_control,
 260         .set_desc = rtl92se_set_desc,
 261         .get_desc = rtl92se_get_desc,
 262         .tx_polling = rtl92se_tx_polling,
 263         .enable_hw_sec = rtl92se_enable_hw_security_config,
 264         .set_key = rtl92se_set_key,
 265         .init_sw_leds = rtl92se_init_sw_leds,
 266         .get_bbreg = rtl92s_phy_query_bb_reg,
 267         .set_bbreg = rtl92s_phy_set_bb_reg,
 268         .get_rfreg = rtl92s_phy_query_rf_reg,
 269         .set_rfreg = rtl92s_phy_set_rf_reg,
 270 };
 271
 272 static struct rtl_mod_params rtl92se_mod_params = {
 273         .sw_crypto = false,
 274         .inactiveps = true,
 275         .swctrl_lps = true,
 276         .fwctrl_lps = false,
 277         .debug = DBG_EMERG,
 278 };
 279
 280 /* Because memory R/W bursting will cause system hang/crash
 281  * for 92se, so we don't read back after every write action */
 282 static struct rtl_hal_cfg rtl92se_hal_cfg = {
 283         .bar_id = 1,
 284         .write_readback = false,
 285         .name = "rtl92s_pci",
 286         .fw_name = "rtlwifi/rtl8192sefw.bin",
 287         .ops = &rtl8192se_hal_ops,
 288         .mod_params = &rtl92se_mod_params,
 289
 290         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 291         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 292         .maps[SYS_CLK] = SYS_CLKR,
 293         .maps[MAC_RCR_AM] = RCR_AM,
 294         .maps[MAC_RCR_AB] = RCR_AB,
 295         .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
 296         .maps[MAC_RCR_ACF] = RCR_ACF,
 297         .maps[MAC_RCR_AAP] = RCR_AAP,
 298
 299         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 300         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 301         .maps[EFUSE_CLK] = REG_EFUSE_CLK,
 302         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 303         .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
 304         .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
 305         .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
 306         .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
 307         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
 308         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 309         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 310
 311         .maps[RWCAM] = REG_RWCAM,
 312         .maps[WCAMI] = REG_WCAMI,
 313         .maps[RCAMO] = REG_RCAMO,
 314         .maps[CAMDBG] = REG_CAMDBG,
 315         .maps[SECR] = REG_SECR,
 316         .maps[SEC_CAM_NONE] = CAM_NONE,
 317         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 318         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 319         .maps[SEC_CAM_AES] = CAM_AES,
 320         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 321
 322         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 323         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 324         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 325         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 326         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 327         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 328         .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
 329         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 330         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 331         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 332         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 333         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 334         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 335         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 336         .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
 337         .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
 338
 339         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 340         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 341         .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
 342         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 343         .maps[RTL_IMR_RDU] = IMR_RDU,
 344         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 345         .maps[RTL_IMR_BDOK] = IMR_BDOK,
 346         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 347         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 348         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 349         .maps[RTL_IMR_COMDOK] = IMR_COMDOK,
 350         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 351         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 352         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 353         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 354         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 355         .maps[RTL_IMR_ROK] = IMR_ROK,
 356         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
 357
 358         .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
 359         .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
 360         .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
 361         .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
 362         .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
 363         .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
 364         .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
 365         .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
 366         .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
 367         .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
 368         .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
 369         .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
 370
 371         .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
 372         .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
 373 };
 374
 375 static struct pci_device_id rtl92se_pci_ids[] __devinitdata = {
 376         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
 377         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
 378         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
 379         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
 380         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
 381         {},
 382 };
 383
 384 MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
 385
 386 MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
 387 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 388 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 389 MODULE_LICENSE("GPL");
 390 MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
 391 MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
 392
 393 module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
 394 module_param_named(debug, rtl92se_mod_params.debug, int, 0444);
 395 module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
 396 module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
 397 module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
 398 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 399 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 400 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 401 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 402 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
 403
 404 static struct pci_driver rtl92se_driver = {
 405         .name = KBUILD_MODNAME,
 406         .id_table = rtl92se_pci_ids,
 407         .probe = rtl_pci_probe,
 408         .remove = rtl_pci_disconnect,
 409
 410 #ifdef CONFIG_PM
 411         .suspend = rtl_pci_suspend,
 412         .resume = rtl_pci_resume,
 413 #endif
 414
 415 };
 416
 417 static int __init rtl92se_module_init(void)
 418 {
 419         int ret = 0;
 420
 421         ret = pci_register_driver(&rtl92se_driver);
 422         if (ret)
 423                 RT_ASSERT(false, (": No device found\n"));
 424
 425         return ret;
 426 }
 427
 428 static void __exit rtl92se_module_exit(void)
 429 {
 430         pci_unregister_driver(&rtl92se_driver);
 431 }
 432
 433 module_init(rtl92se_module_init);
 434 module_exit(rtl92se_module_exit);