2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
138 unsigned long long addr
;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
145 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
146 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
148 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring
->cycle_state
);
152 ring
->deq_seg
= ring
->deq_seg
->next
;
153 ring
->dequeue
= ring
->deq_seg
->trbs
;
154 next
= ring
->dequeue
;
156 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
157 if (ring
== xhci
->event_ring
)
158 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
159 else if (ring
== xhci
->cmd_ring
)
160 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
162 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
179 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
182 union xhci_trb
*next
;
183 unsigned long long addr
;
185 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
186 next
= ++(ring
->enqueue
);
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
192 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
194 if (ring
!= xhci
->event_ring
) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
199 if (!xhci_link_trb_quirk(xhci
)) {
200 next
->link
.control
&= ~TRB_CHAIN
;
201 next
->link
.control
|= chain
;
203 /* Give this link TRB to the hardware */
205 if (next
->link
.control
& TRB_CYCLE
)
206 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
208 next
->link
.control
|= (u32
) TRB_CYCLE
;
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
212 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
214 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
216 (unsigned int) ring
->cycle_state
);
219 ring
->enq_seg
= ring
->enq_seg
->next
;
220 ring
->enqueue
= ring
->enq_seg
->trbs
;
221 next
= ring
->enqueue
;
223 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
224 if (ring
== xhci
->event_ring
)
225 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
226 else if (ring
== xhci
->cmd_ring
)
227 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
229 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
238 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
239 unsigned int num_trbs
)
242 union xhci_trb
*enq
= ring
->enqueue
;
243 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
244 struct xhci_segment
*cur_seg
;
245 unsigned int left_on_ring
;
247 /* Check if ring is empty */
248 if (enq
== ring
->dequeue
) {
249 /* Can't use link trbs */
250 left_on_ring
= TRBS_PER_SEGMENT
- 1;
251 for (cur_seg
= enq_seg
->next
; cur_seg
!= enq_seg
;
252 cur_seg
= cur_seg
->next
)
253 left_on_ring
+= TRBS_PER_SEGMENT
- 1;
255 /* Always need one TRB free in the ring. */
257 if (num_trbs
> left_on_ring
) {
258 xhci_warn(xhci
, "Not enough room on ring; "
259 "need %u TRBs, %u TRBs left\n",
260 num_trbs
, left_on_ring
);
265 /* Make sure there's an extra empty TRB available */
266 for (i
= 0; i
<= num_trbs
; ++i
) {
267 if (enq
== ring
->dequeue
)
270 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
271 enq_seg
= enq_seg
->next
;
278 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
283 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
284 xhci
->event_ring
->dequeue
);
285 if (deq
== 0 && !in_interrupt())
286 xhci_warn(xhci
, "WARN something wrong with SW event ring "
288 /* Update HC event ring dequeue pointer */
289 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
290 temp
&= ERST_PTR_MASK
;
291 /* Don't clear the EHB bit (which is RW1C) because
292 * there might be more events to service.
295 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
296 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
297 &xhci
->ir_set
->erst_dequeue
);
300 /* Ring the host controller doorbell after placing a command on the ring */
301 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
305 xhci_dbg(xhci
, "// Ding dong!\n");
306 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
307 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
308 /* Flush PCI posted writes */
309 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
312 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
313 unsigned int slot_id
,
314 unsigned int ep_index
)
316 struct xhci_virt_ep
*ep
;
317 unsigned int ep_state
;
319 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
321 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
322 ep_state
= ep
->ep_state
;
323 /* Don't ring the doorbell for this endpoint if there are pending
324 * cancellations because the we don't want to interrupt processing.
326 if (!(ep_state
& EP_HALT_PENDING
) && !(ep_state
& SET_DEQ_PENDING
)
327 && !(ep_state
& EP_HALTED
)) {
328 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
329 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
330 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
331 * isn't time-critical and we shouldn't make the CPU wait for
334 xhci_readl(xhci
, db_addr
);
339 * Find the segment that trb is in. Start searching in start_seg.
340 * If we must move past a segment that has a link TRB with a toggle cycle state
341 * bit set, then we will toggle the value pointed at by cycle_state.
343 static struct xhci_segment
*find_trb_seg(
344 struct xhci_segment
*start_seg
,
345 union xhci_trb
*trb
, int *cycle_state
)
347 struct xhci_segment
*cur_seg
= start_seg
;
348 struct xhci_generic_trb
*generic_trb
;
350 while (cur_seg
->trbs
> trb
||
351 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
352 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
353 if ((generic_trb
->field
[3] & TRB_TYPE_BITMASK
) ==
354 TRB_TYPE(TRB_LINK
) &&
355 (generic_trb
->field
[3] & LINK_TOGGLE
))
356 *cycle_state
= ~(*cycle_state
) & 0x1;
357 cur_seg
= cur_seg
->next
;
358 if (cur_seg
== start_seg
)
359 /* Looped over the entire list. Oops! */
366 * Move the xHC's endpoint ring dequeue pointer past cur_td.
367 * Record the new state of the xHC's endpoint ring dequeue segment,
368 * dequeue pointer, and new consumer cycle state in state.
369 * Update our internal representation of the ring's dequeue pointer.
371 * We do this in three jumps:
372 * - First we update our new ring state to be the same as when the xHC stopped.
373 * - Then we traverse the ring to find the segment that contains
374 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
375 * any link TRBs with the toggle cycle bit set.
376 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
377 * if we've moved it past a link TRB with the toggle cycle bit set.
379 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
380 unsigned int slot_id
, unsigned int ep_index
,
381 struct xhci_td
*cur_td
, struct xhci_dequeue_state
*state
)
383 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
384 struct xhci_ring
*ep_ring
= dev
->eps
[ep_index
].ring
;
385 struct xhci_generic_trb
*trb
;
386 struct xhci_ep_ctx
*ep_ctx
;
389 state
->new_cycle_state
= 0;
390 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
391 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
392 dev
->eps
[ep_index
].stopped_trb
,
393 &state
->new_cycle_state
);
394 if (!state
->new_deq_seg
) {
399 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
400 xhci_dbg(xhci
, "Finding endpoint context\n");
401 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
402 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
404 state
->new_deq_ptr
= cur_td
->last_trb
;
405 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
406 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
408 &state
->new_cycle_state
);
409 if (!state
->new_deq_seg
) {
414 trb
= &state
->new_deq_ptr
->generic
;
415 if ((trb
->field
[3] & TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
) &&
416 (trb
->field
[3] & LINK_TOGGLE
))
417 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
418 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
421 * If there is only one segment in a ring, find_trb_seg()'s while loop
422 * will not run, and it will return before it has a chance to see if it
423 * needs to toggle the cycle bit. It can't tell if the stalled transfer
424 * ended just before the link TRB on a one-segment ring, or if the TD
425 * wrapped around the top of the ring, because it doesn't have the TD in
426 * question. Look for the one-segment case where stalled TRB's address
427 * is greater than the new dequeue pointer address.
429 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
430 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
431 state
->new_cycle_state
^= 0x1;
432 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
434 /* Don't update the ring cycle state for the producer (us). */
435 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
437 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
438 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
439 (unsigned long long) addr
);
440 xhci_dbg(xhci
, "Setting dequeue pointer in internal ring state.\n");
441 ep_ring
->dequeue
= state
->new_deq_ptr
;
442 ep_ring
->deq_seg
= state
->new_deq_seg
;
445 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
446 struct xhci_td
*cur_td
)
448 struct xhci_segment
*cur_seg
;
449 union xhci_trb
*cur_trb
;
451 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
453 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
454 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
455 TRB_TYPE(TRB_LINK
)) {
456 /* Unchain any chained Link TRBs, but
457 * leave the pointers intact.
459 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
460 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
461 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
462 "in seg %p (0x%llx dma)\n",
464 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
466 (unsigned long long)cur_seg
->dma
);
468 cur_trb
->generic
.field
[0] = 0;
469 cur_trb
->generic
.field
[1] = 0;
470 cur_trb
->generic
.field
[2] = 0;
471 /* Preserve only the cycle bit of this TRB */
472 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
473 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
474 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
475 "in seg %p (0x%llx dma)\n",
477 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
479 (unsigned long long)cur_seg
->dma
);
481 if (cur_trb
== cur_td
->last_trb
)
486 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
487 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
488 union xhci_trb
*deq_ptr
, u32 cycle_state
);
490 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
491 unsigned int slot_id
, unsigned int ep_index
,
492 struct xhci_dequeue_state
*deq_state
)
494 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
496 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
497 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
498 deq_state
->new_deq_seg
,
499 (unsigned long long)deq_state
->new_deq_seg
->dma
,
500 deq_state
->new_deq_ptr
,
501 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
502 deq_state
->new_cycle_state
);
503 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
504 deq_state
->new_deq_seg
,
505 deq_state
->new_deq_ptr
,
506 (u32
) deq_state
->new_cycle_state
);
507 /* Stop the TD queueing code from ringing the doorbell until
508 * this command completes. The HC won't set the dequeue pointer
509 * if the ring is running, and ringing the doorbell starts the
512 ep
->ep_state
|= SET_DEQ_PENDING
;
515 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
516 struct xhci_virt_ep
*ep
)
518 ep
->ep_state
&= ~EP_HALT_PENDING
;
519 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
520 * timer is running on another CPU, we don't decrement stop_cmds_pending
521 * (since we didn't successfully stop the watchdog timer).
523 if (del_timer(&ep
->stop_cmd_timer
))
524 ep
->stop_cmds_pending
--;
527 /* Must be called with xhci->lock held in interrupt context */
528 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
529 struct xhci_td
*cur_td
, int status
, char *adjective
)
531 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
533 cur_td
->urb
->hcpriv
= NULL
;
534 usb_hcd_unlink_urb_from_ep(hcd
, cur_td
->urb
);
535 xhci_dbg(xhci
, "Giveback %s URB %p\n", adjective
, cur_td
->urb
);
537 spin_unlock(&xhci
->lock
);
538 usb_hcd_giveback_urb(hcd
, cur_td
->urb
, status
);
540 spin_lock(&xhci
->lock
);
541 xhci_dbg(xhci
, "%s URB given back\n", adjective
);
545 * When we get a command completion for a Stop Endpoint Command, we need to
546 * unlink any cancelled TDs from the ring. There are two ways to do that:
548 * 1. If the HW was in the middle of processing the TD that needs to be
549 * cancelled, then we must move the ring's dequeue pointer past the last TRB
550 * in the TD with a Set Dequeue Pointer Command.
551 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
552 * bit cleared) so that the HW will skip over them.
554 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
557 unsigned int slot_id
;
558 unsigned int ep_index
;
559 struct xhci_ring
*ep_ring
;
560 struct xhci_virt_ep
*ep
;
561 struct list_head
*entry
;
562 struct xhci_td
*cur_td
= 0;
563 struct xhci_td
*last_unlinked_td
;
565 struct xhci_dequeue_state deq_state
;
567 memset(&deq_state
, 0, sizeof(deq_state
));
568 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
569 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
570 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
573 if (list_empty(&ep
->cancelled_td_list
)) {
574 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
575 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
579 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
580 * We have the xHCI lock, so nothing can modify this list until we drop
581 * it. We're also in the event handler, so we can't get re-interrupted
582 * if another Stop Endpoint command completes
584 list_for_each(entry
, &ep
->cancelled_td_list
) {
585 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
586 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
588 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
590 * If we stopped on the TD we need to cancel, then we have to
591 * move the xHC endpoint ring dequeue pointer past this TD.
593 if (cur_td
== ep
->stopped_td
)
594 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
597 td_to_noop(xhci
, ep_ring
, cur_td
);
599 * The event handler won't see a completion for this TD anymore,
600 * so remove it from the endpoint ring's TD list. Keep it in
601 * the cancelled TD list for URB completion later.
603 list_del(&cur_td
->td_list
);
605 last_unlinked_td
= cur_td
;
606 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
608 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
609 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
610 xhci_queue_new_dequeue_state(xhci
,
611 slot_id
, ep_index
, &deq_state
);
612 xhci_ring_cmd_db(xhci
);
614 /* Otherwise just ring the doorbell to restart the ring */
615 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
617 ep
->stopped_td
= NULL
;
618 ep
->stopped_trb
= NULL
;
621 * Drop the lock and complete the URBs in the cancelled TD list.
622 * New TDs to be cancelled might be added to the end of the list before
623 * we can complete all the URBs for the TDs we already unlinked.
624 * So stop when we've completed the URB for the last TD we unlinked.
627 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
628 struct xhci_td
, cancelled_td_list
);
629 list_del(&cur_td
->cancelled_td_list
);
631 /* Clean up the cancelled URB */
632 /* Doesn't matter what we pass for status, since the core will
633 * just overwrite it (because the URB has been unlinked).
635 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
637 /* Stop processing the cancelled list if the watchdog timer is
640 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
642 } while (cur_td
!= last_unlinked_td
);
644 /* Return to the event handler with xhci->lock re-acquired */
647 /* Watchdog timer function for when a stop endpoint command fails to complete.
648 * In this case, we assume the host controller is broken or dying or dead. The
649 * host may still be completing some other events, so we have to be careful to
650 * let the event ring handler and the URB dequeueing/enqueueing functions know
651 * through xhci->state.
653 * The timer may also fire if the host takes a very long time to respond to the
654 * command, and the stop endpoint command completion handler cannot delete the
655 * timer before the timer function is called. Another endpoint cancellation may
656 * sneak in before the timer function can grab the lock, and that may queue
657 * another stop endpoint command and add the timer back. So we cannot use a
658 * simple flag to say whether there is a pending stop endpoint command for a
659 * particular endpoint.
661 * Instead we use a combination of that flag and a counter for the number of
662 * pending stop endpoint commands. If the timer is the tail end of the last
663 * stop endpoint command, and the endpoint's command is still pending, we assume
666 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
668 struct xhci_hcd
*xhci
;
669 struct xhci_virt_ep
*ep
;
670 struct xhci_virt_ep
*temp_ep
;
671 struct xhci_ring
*ring
;
672 struct xhci_td
*cur_td
;
675 ep
= (struct xhci_virt_ep
*) arg
;
678 spin_lock(&xhci
->lock
);
680 ep
->stop_cmds_pending
--;
681 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
682 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
683 "xHCI as DYING, exiting.\n");
684 spin_unlock(&xhci
->lock
);
687 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
688 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
690 spin_unlock(&xhci
->lock
);
694 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
695 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
696 /* Oops, HC is dead or dying or at least not responding to the stop
699 xhci
->xhc_state
|= XHCI_STATE_DYING
;
700 /* Disable interrupts from the host controller and start halting it */
702 spin_unlock(&xhci
->lock
);
704 ret
= xhci_halt(xhci
);
706 spin_lock(&xhci
->lock
);
708 /* This is bad; the host is not responding to commands and it's
709 * not allowing itself to be halted. At least interrupts are
710 * disabled, so we can set HC_STATE_HALT and notify the
711 * USB core. But if we call usb_hc_died(), it will attempt to
712 * disconnect all device drivers under this host. Those
713 * disconnect() methods will wait for all URBs to be unlinked,
714 * so we must complete them.
716 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
717 xhci_warn(xhci
, "Completing active URBs anyway.\n");
718 /* We could turn all TDs on the rings to no-ops. This won't
719 * help if the host has cached part of the ring, and is slow if
720 * we want to preserve the cycle bit. Skip it and hope the host
721 * doesn't touch the memory.
724 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
727 for (j
= 0; j
< 31; j
++) {
728 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
729 ring
= temp_ep
->ring
;
732 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
733 "ep index %u\n", i
, j
);
734 while (!list_empty(&ring
->td_list
)) {
735 cur_td
= list_first_entry(&ring
->td_list
,
738 list_del(&cur_td
->td_list
);
739 if (!list_empty(&cur_td
->cancelled_td_list
))
740 list_del(&cur_td
->cancelled_td_list
);
741 xhci_giveback_urb_in_irq(xhci
, cur_td
,
742 -ESHUTDOWN
, "killed");
744 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
745 cur_td
= list_first_entry(
746 &temp_ep
->cancelled_td_list
,
749 list_del(&cur_td
->cancelled_td_list
);
750 xhci_giveback_urb_in_irq(xhci
, cur_td
,
751 -ESHUTDOWN
, "killed");
755 spin_unlock(&xhci
->lock
);
756 xhci_to_hcd(xhci
)->state
= HC_STATE_HALT
;
757 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
758 usb_hc_died(xhci_to_hcd(xhci
));
759 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
763 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
764 * we need to clear the set deq pending flag in the endpoint ring state, so that
765 * the TD queueing code can ring the doorbell again. We also need to ring the
766 * endpoint doorbell to restart the ring, but only if there aren't more
767 * cancellations pending.
769 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
770 struct xhci_event_cmd
*event
,
773 unsigned int slot_id
;
774 unsigned int ep_index
;
775 struct xhci_ring
*ep_ring
;
776 struct xhci_virt_device
*dev
;
777 struct xhci_ep_ctx
*ep_ctx
;
778 struct xhci_slot_ctx
*slot_ctx
;
780 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
781 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
782 dev
= xhci
->devs
[slot_id
];
783 ep_ring
= dev
->eps
[ep_index
].ring
;
784 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
785 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
787 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
788 unsigned int ep_state
;
789 unsigned int slot_state
;
791 switch (GET_COMP_CODE(event
->status
)) {
793 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
794 "of stream ID configuration\n");
797 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
798 "to incorrect slot or ep state.\n");
799 ep_state
= ep_ctx
->ep_info
;
800 ep_state
&= EP_STATE_MASK
;
801 slot_state
= slot_ctx
->dev_state
;
802 slot_state
= GET_SLOT_STATE(slot_state
);
803 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
804 slot_state
, ep_state
);
807 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
808 "slot %u was not enabled.\n", slot_id
);
811 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
812 "completion code of %u.\n",
813 GET_COMP_CODE(event
->status
));
816 /* OK what do we do now? The endpoint state is hosed, and we
817 * should never get to this point if the synchronization between
818 * queueing, and endpoint state are correct. This might happen
819 * if the device gets disconnected after we've finished
820 * cancelling URBs, which might not be an error...
823 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
827 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
828 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
831 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
832 struct xhci_event_cmd
*event
,
836 unsigned int ep_index
;
837 struct xhci_ring
*ep_ring
;
839 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
840 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
841 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
842 /* This command will only fail if the endpoint wasn't halted,
845 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
846 (unsigned int) GET_COMP_CODE(event
->status
));
848 /* HW with the reset endpoint quirk needs to have a configure endpoint
849 * command complete before the endpoint can be used. Queue that here
850 * because the HW can't handle two commands being queued in a row.
852 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
853 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
854 xhci_queue_configure_endpoint(xhci
,
855 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
857 xhci_ring_cmd_db(xhci
);
859 /* Clear our internal halted state and restart the ring */
860 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
861 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
865 /* Check to see if a command in the device's command queue matches this one.
866 * Signal the completion or free the command, and return 1. Return 0 if the
867 * completed command isn't at the head of the command list.
869 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
870 struct xhci_virt_device
*virt_dev
,
871 struct xhci_event_cmd
*event
)
873 struct xhci_command
*command
;
875 if (list_empty(&virt_dev
->cmd_list
))
878 command
= list_entry(virt_dev
->cmd_list
.next
,
879 struct xhci_command
, cmd_list
);
880 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
884 GET_COMP_CODE(event
->status
);
885 list_del(&command
->cmd_list
);
886 if (command
->completion
)
887 complete(command
->completion
);
889 xhci_free_command(xhci
, command
);
893 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
894 struct xhci_event_cmd
*event
)
896 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
898 dma_addr_t cmd_dequeue_dma
;
899 struct xhci_input_control_ctx
*ctrl_ctx
;
900 struct xhci_virt_device
*virt_dev
;
901 unsigned int ep_index
;
902 struct xhci_ring
*ep_ring
;
903 unsigned int ep_state
;
905 cmd_dma
= event
->cmd_trb
;
906 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
907 xhci
->cmd_ring
->dequeue
);
908 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
909 if (cmd_dequeue_dma
== 0) {
910 xhci
->error_bitmask
|= 1 << 4;
913 /* Does the DMA address match our internal dequeue pointer address? */
914 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
915 xhci
->error_bitmask
|= 1 << 5;
918 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
919 case TRB_TYPE(TRB_ENABLE_SLOT
):
920 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
921 xhci
->slot_id
= slot_id
;
924 complete(&xhci
->addr_dev
);
926 case TRB_TYPE(TRB_DISABLE_SLOT
):
927 if (xhci
->devs
[slot_id
])
928 xhci_free_virt_device(xhci
, slot_id
);
930 case TRB_TYPE(TRB_CONFIG_EP
):
931 virt_dev
= xhci
->devs
[slot_id
];
932 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
935 * Configure endpoint commands can come from the USB core
936 * configuration or alt setting changes, or because the HW
937 * needed an extra configure endpoint command after a reset
938 * endpoint command. In the latter case, the xHCI driver is
939 * not waiting on the configure endpoint command.
941 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
943 /* Input ctx add_flags are the endpoint index plus one */
944 ep_index
= xhci_last_valid_endpoint(ctrl_ctx
->add_flags
) - 1;
945 /* A usb_set_interface() call directly after clearing a halted
946 * condition may race on this quirky hardware.
947 * Not worth worrying about, since this is prototype hardware.
949 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
950 ep_index
!= (unsigned int) -1 &&
951 ctrl_ctx
->add_flags
- SLOT_FLAG
==
952 ctrl_ctx
->drop_flags
) {
953 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
954 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
955 if (!(ep_state
& EP_HALTED
))
956 goto bandwidth_change
;
957 xhci_dbg(xhci
, "Completed config ep cmd - "
958 "last ep index = %d, state = %d\n",
960 /* Clear our internal halted state and restart ring */
961 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
963 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
967 xhci_dbg(xhci
, "Completed config ep cmd\n");
968 xhci
->devs
[slot_id
]->cmd_status
=
969 GET_COMP_CODE(event
->status
);
970 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
972 case TRB_TYPE(TRB_EVAL_CONTEXT
):
973 virt_dev
= xhci
->devs
[slot_id
];
974 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
976 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
977 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
979 case TRB_TYPE(TRB_ADDR_DEV
):
980 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
981 complete(&xhci
->addr_dev
);
983 case TRB_TYPE(TRB_STOP_RING
):
984 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
986 case TRB_TYPE(TRB_SET_DEQ
):
987 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
989 case TRB_TYPE(TRB_CMD_NOOP
):
990 ++xhci
->noops_handled
;
992 case TRB_TYPE(TRB_RESET_EP
):
993 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
996 /* Skip over unknown commands on the event ring */
997 xhci
->error_bitmask
|= 1 << 6;
1000 inc_deq(xhci
, xhci
->cmd_ring
, false);
1003 static void handle_port_status(struct xhci_hcd
*xhci
,
1004 union xhci_trb
*event
)
1008 /* Port status change events always have a successful completion code */
1009 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
1010 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1011 xhci
->error_bitmask
|= 1 << 8;
1013 /* FIXME: core doesn't care about all port link state changes yet */
1014 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
1015 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1017 /* Update event ring dequeue pointer before dropping the lock */
1018 inc_deq(xhci
, xhci
->event_ring
, true);
1019 xhci_set_hc_event_deq(xhci
);
1021 spin_unlock(&xhci
->lock
);
1022 /* Pass this up to the core */
1023 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
1024 spin_lock(&xhci
->lock
);
1028 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1029 * at end_trb, which may be in another segment. If the suspect DMA address is a
1030 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1033 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1034 union xhci_trb
*start_trb
,
1035 union xhci_trb
*end_trb
,
1036 dma_addr_t suspect_dma
)
1038 dma_addr_t start_dma
;
1039 dma_addr_t end_seg_dma
;
1040 dma_addr_t end_trb_dma
;
1041 struct xhci_segment
*cur_seg
;
1043 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1044 cur_seg
= start_seg
;
1049 /* We may get an event for a Link TRB in the middle of a TD */
1050 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1051 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1052 /* If the end TRB isn't in this segment, this is set to 0 */
1053 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1055 if (end_trb_dma
> 0) {
1056 /* The end TRB is in this segment, so suspect should be here */
1057 if (start_dma
<= end_trb_dma
) {
1058 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1061 /* Case for one segment with
1062 * a TD wrapped around to the top
1064 if ((suspect_dma
>= start_dma
&&
1065 suspect_dma
<= end_seg_dma
) ||
1066 (suspect_dma
>= cur_seg
->dma
&&
1067 suspect_dma
<= end_trb_dma
))
1072 /* Might still be somewhere in this segment */
1073 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1076 cur_seg
= cur_seg
->next
;
1077 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1078 } while (cur_seg
!= start_seg
);
1083 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1084 unsigned int slot_id
, unsigned int ep_index
,
1085 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1087 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1088 ep
->ep_state
|= EP_HALTED
;
1089 ep
->stopped_td
= td
;
1090 ep
->stopped_trb
= event_trb
;
1092 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1093 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1095 ep
->stopped_td
= NULL
;
1096 ep
->stopped_trb
= NULL
;
1098 xhci_ring_cmd_db(xhci
);
1101 /* Check if an error has halted the endpoint ring. The class driver will
1102 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1103 * However, a babble and other errors also halt the endpoint ring, and the class
1104 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1105 * Ring Dequeue Pointer command manually.
1107 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1108 struct xhci_ep_ctx
*ep_ctx
,
1109 unsigned int trb_comp_code
)
1111 /* TRB completion codes that may require a manual halt cleanup */
1112 if (trb_comp_code
== COMP_TX_ERR
||
1113 trb_comp_code
== COMP_BABBLE
||
1114 trb_comp_code
== COMP_SPLIT_ERR
)
1115 /* The 0.96 spec says a babbling control endpoint
1116 * is not halted. The 0.96 spec says it is. Some HW
1117 * claims to be 0.95 compliant, but it halts the control
1118 * endpoint anyway. Check if a babble halted the
1121 if ((ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_HALTED
)
1128 * If this function returns an error condition, it means it got a Transfer
1129 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1130 * At this point, the host controller is probably hosed and should be reset.
1132 static int handle_tx_event(struct xhci_hcd
*xhci
,
1133 struct xhci_transfer_event
*event
)
1135 struct xhci_virt_device
*xdev
;
1136 struct xhci_virt_ep
*ep
;
1137 struct xhci_ring
*ep_ring
;
1138 unsigned int slot_id
;
1140 struct xhci_td
*td
= 0;
1141 dma_addr_t event_dma
;
1142 struct xhci_segment
*event_seg
;
1143 union xhci_trb
*event_trb
;
1144 struct urb
*urb
= 0;
1145 int status
= -EINPROGRESS
;
1146 struct xhci_ep_ctx
*ep_ctx
;
1149 xhci_dbg(xhci
, "In %s\n", __func__
);
1150 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
1151 xdev
= xhci
->devs
[slot_id
];
1153 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
1157 /* Endpoint ID is 1 based, our index is zero based */
1158 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
1159 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
1160 ep
= &xdev
->eps
[ep_index
];
1162 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1163 if (!ep_ring
|| (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
1164 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
1168 event_dma
= event
->buffer
;
1169 /* This TRB should be in the TD at the head of this ring's TD list */
1170 xhci_dbg(xhci
, "%s - checking for list empty\n", __func__
);
1171 if (list_empty(&ep_ring
->td_list
)) {
1172 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
1173 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
1174 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
1175 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
1176 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
1180 xhci_dbg(xhci
, "%s - getting list entry\n", __func__
);
1181 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
1183 /* Is this a TRB in the currently executing TD? */
1184 xhci_dbg(xhci
, "%s - looking for TD\n", __func__
);
1185 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
1186 td
->last_trb
, event_dma
);
1187 xhci_dbg(xhci
, "%s - found event_seg = %p\n", __func__
, event_seg
);
1189 /* HC is busted, give up! */
1190 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1193 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
1194 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
1195 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
1196 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
1197 lower_32_bits(event
->buffer
));
1198 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
1199 upper_32_bits(event
->buffer
));
1200 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
1201 (unsigned int) event
->transfer_len
);
1202 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
1203 (unsigned int) event
->flags
);
1205 /* Look for common error cases */
1206 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
1207 switch (trb_comp_code
) {
1208 /* Skip codes that require special handling depending on
1215 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
1217 case COMP_STOP_INVAL
:
1218 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1221 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1222 ep
->ep_state
|= EP_HALTED
;
1226 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1229 case COMP_SPLIT_ERR
:
1231 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1235 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1236 status
= -EOVERFLOW
;
1239 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1243 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1244 /* Vendor defined "informational" completion code,
1245 * treat as not-an-error.
1247 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1249 xhci_dbg(xhci
, "Treating code as success.\n");
1253 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
1257 /* Now update the urb's actual_length and give back to the core */
1258 /* Was this a control transfer? */
1259 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
1260 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1261 switch (trb_comp_code
) {
1263 if (event_trb
== ep_ring
->dequeue
) {
1264 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
1265 status
= -ESHUTDOWN
;
1266 } else if (event_trb
!= td
->last_trb
) {
1267 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
1268 status
= -ESHUTDOWN
;
1270 xhci_dbg(xhci
, "Successful control transfer!\n");
1275 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1276 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1277 status
= -EREMOTEIO
;
1283 if (!xhci_requires_manual_halt_cleanup(xhci
,
1284 ep_ctx
, trb_comp_code
))
1286 xhci_dbg(xhci
, "TRB error code %u, "
1287 "halted endpoint index = %u\n",
1288 trb_comp_code
, ep_index
);
1289 /* else fall through */
1291 /* Did we transfer part of the data (middle) phase? */
1292 if (event_trb
!= ep_ring
->dequeue
&&
1293 event_trb
!= td
->last_trb
)
1294 td
->urb
->actual_length
=
1295 td
->urb
->transfer_buffer_length
1296 - TRB_LEN(event
->transfer_len
);
1298 td
->urb
->actual_length
= 0;
1300 xhci_cleanup_halted_endpoint(xhci
,
1301 slot_id
, ep_index
, td
, event_trb
);
1305 * Did we transfer any data, despite the errors that might have
1306 * happened? I.e. did we get past the setup stage?
1308 if (event_trb
!= ep_ring
->dequeue
) {
1309 /* The event was for the status stage */
1310 if (event_trb
== td
->last_trb
) {
1311 if (td
->urb
->actual_length
!= 0) {
1312 /* Don't overwrite a previously set error code */
1313 if ((status
== -EINPROGRESS
||
1315 (td
->urb
->transfer_flags
1316 & URB_SHORT_NOT_OK
))
1317 /* Did we already see a short data stage? */
1318 status
= -EREMOTEIO
;
1320 td
->urb
->actual_length
=
1321 td
->urb
->transfer_buffer_length
;
1324 /* Maybe the event was for the data stage? */
1325 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1326 /* We didn't stop on a link TRB in the middle */
1327 td
->urb
->actual_length
=
1328 td
->urb
->transfer_buffer_length
-
1329 TRB_LEN(event
->transfer_len
);
1330 xhci_dbg(xhci
, "Waiting for status stage event\n");
1337 switch (trb_comp_code
) {
1339 /* Double check that the HW transferred everything. */
1340 if (event_trb
!= td
->last_trb
) {
1341 xhci_warn(xhci
, "WARN Successful completion "
1343 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1344 status
= -EREMOTEIO
;
1348 if (usb_endpoint_xfer_bulk(&td
->urb
->ep
->desc
))
1349 xhci_dbg(xhci
, "Successful bulk "
1352 xhci_dbg(xhci
, "Successful interrupt "
1358 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1359 status
= -EREMOTEIO
;
1364 /* Others already handled above */
1367 dev_dbg(&td
->urb
->dev
->dev
,
1368 "ep %#x - asked for %d bytes, "
1369 "%d bytes untransferred\n",
1370 td
->urb
->ep
->desc
.bEndpointAddress
,
1371 td
->urb
->transfer_buffer_length
,
1372 TRB_LEN(event
->transfer_len
));
1373 /* Fast path - was this the last TRB in the TD for this URB? */
1374 if (event_trb
== td
->last_trb
) {
1375 if (TRB_LEN(event
->transfer_len
) != 0) {
1376 td
->urb
->actual_length
=
1377 td
->urb
->transfer_buffer_length
-
1378 TRB_LEN(event
->transfer_len
);
1379 if (td
->urb
->transfer_buffer_length
<
1380 td
->urb
->actual_length
) {
1381 xhci_warn(xhci
, "HC gave bad length "
1382 "of %d bytes left\n",
1383 TRB_LEN(event
->transfer_len
));
1384 td
->urb
->actual_length
= 0;
1385 if (td
->urb
->transfer_flags
&
1387 status
= -EREMOTEIO
;
1391 /* Don't overwrite a previously set error code */
1392 if (status
== -EINPROGRESS
) {
1393 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1394 status
= -EREMOTEIO
;
1399 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
1400 /* Ignore a short packet completion if the
1401 * untransferred length was zero.
1403 if (status
== -EREMOTEIO
)
1407 /* Slow path - walk the list, starting from the dequeue
1408 * pointer, to get the actual length transferred.
1410 union xhci_trb
*cur_trb
;
1411 struct xhci_segment
*cur_seg
;
1413 td
->urb
->actual_length
= 0;
1414 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1415 cur_trb
!= event_trb
;
1416 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1417 if ((cur_trb
->generic
.field
[3] &
1418 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_TR_NOOP
) &&
1419 (cur_trb
->generic
.field
[3] &
1420 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_LINK
))
1421 td
->urb
->actual_length
+=
1422 TRB_LEN(cur_trb
->generic
.field
[2]);
1424 /* If the ring didn't stop on a Link or No-op TRB, add
1425 * in the actual bytes transferred from the Normal TRB
1427 if (trb_comp_code
!= COMP_STOP_INVAL
)
1428 td
->urb
->actual_length
+=
1429 TRB_LEN(cur_trb
->generic
.field
[2]) -
1430 TRB_LEN(event
->transfer_len
);
1433 if (trb_comp_code
== COMP_STOP_INVAL
||
1434 trb_comp_code
== COMP_STOP
) {
1435 /* The Endpoint Stop Command completion will take care of any
1436 * stopped TDs. A stopped TD may be restarted, so don't update
1437 * the ring dequeue pointer or take this TD off any lists yet.
1439 ep
->stopped_td
= td
;
1440 ep
->stopped_trb
= event_trb
;
1442 if (trb_comp_code
== COMP_STALL
) {
1443 /* The transfer is completed from the driver's
1444 * perspective, but we need to issue a set dequeue
1445 * command for this stalled endpoint to move the dequeue
1446 * pointer past the TD. We can't do that here because
1447 * the halt condition must be cleared first. Let the
1448 * USB class driver clear the stall later.
1450 ep
->stopped_td
= td
;
1451 ep
->stopped_trb
= event_trb
;
1452 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1453 ep_ctx
, trb_comp_code
)) {
1454 /* Other types of errors halt the endpoint, but the
1455 * class driver doesn't call usb_reset_endpoint() unless
1456 * the error is -EPIPE. Clear the halted status in the
1457 * xHCI hardware manually.
1459 xhci_cleanup_halted_endpoint(xhci
,
1460 slot_id
, ep_index
, td
, event_trb
);
1462 /* Update ring dequeue pointer */
1463 while (ep_ring
->dequeue
!= td
->last_trb
)
1464 inc_deq(xhci
, ep_ring
, false);
1465 inc_deq(xhci
, ep_ring
, false);
1469 /* Clean up the endpoint's TD list */
1471 /* Do one last check of the actual transfer length.
1472 * If the host controller said we transferred more data than
1473 * the buffer length, urb->actual_length will be a very big
1474 * number (since it's unsigned). Play it safe and say we didn't
1475 * transfer anything.
1477 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1478 xhci_warn(xhci
, "URB transfer length is wrong, "
1479 "xHC issue? req. len = %u, "
1481 urb
->transfer_buffer_length
,
1482 urb
->actual_length
);
1483 urb
->actual_length
= 0;
1484 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1485 status
= -EREMOTEIO
;
1489 list_del(&td
->td_list
);
1490 /* Was this TD slated to be cancelled but completed anyway? */
1491 if (!list_empty(&td
->cancelled_td_list
))
1492 list_del(&td
->cancelled_td_list
);
1494 /* Leave the TD around for the reset endpoint function to use
1495 * (but only if it's not a control endpoint, since we already
1496 * queued the Set TR dequeue pointer command for stalled
1497 * control endpoints).
1499 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
1500 (trb_comp_code
!= COMP_STALL
&&
1501 trb_comp_code
!= COMP_BABBLE
)) {
1507 inc_deq(xhci
, xhci
->event_ring
, true);
1508 xhci_set_hc_event_deq(xhci
);
1510 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1512 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1513 xhci_dbg(xhci
, "Giveback URB %p, len = %d, status = %d\n",
1514 urb
, urb
->actual_length
, status
);
1515 spin_unlock(&xhci
->lock
);
1516 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1517 spin_lock(&xhci
->lock
);
1523 * This function handles all OS-owned events on the event ring. It may drop
1524 * xhci->lock between event processing (e.g. to pass up port status changes).
1526 void xhci_handle_event(struct xhci_hcd
*xhci
)
1528 union xhci_trb
*event
;
1529 int update_ptrs
= 1;
1532 xhci_dbg(xhci
, "In %s\n", __func__
);
1533 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1534 xhci
->error_bitmask
|= 1 << 1;
1538 event
= xhci
->event_ring
->dequeue
;
1539 /* Does the HC or OS own the TRB? */
1540 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1541 xhci
->event_ring
->cycle_state
) {
1542 xhci
->error_bitmask
|= 1 << 2;
1545 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1547 /* FIXME: Handle more event types. */
1548 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1549 case TRB_TYPE(TRB_COMPLETION
):
1550 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1551 handle_cmd_completion(xhci
, &event
->event_cmd
);
1552 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1554 case TRB_TYPE(TRB_PORT_STATUS
):
1555 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1556 handle_port_status(xhci
, event
);
1557 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
1560 case TRB_TYPE(TRB_TRANSFER
):
1561 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
1562 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1563 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
1565 xhci
->error_bitmask
|= 1 << 9;
1570 xhci
->error_bitmask
|= 1 << 3;
1572 /* Any of the above functions may drop and re-acquire the lock, so check
1573 * to make sure a watchdog timer didn't mark the host as non-responsive.
1575 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
1576 xhci_dbg(xhci
, "xHCI host dying, returning from "
1577 "event handler.\n");
1582 /* Update SW and HC event ring dequeue pointer */
1583 inc_deq(xhci
, xhci
->event_ring
, true);
1584 xhci_set_hc_event_deq(xhci
);
1586 /* Are there more items on the event ring? */
1587 xhci_handle_event(xhci
);
1590 /**** Endpoint Ring Operations ****/
1593 * Generic function for queueing a TRB on a ring.
1594 * The caller must have checked to make sure there's room on the ring.
1596 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1598 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1600 struct xhci_generic_trb
*trb
;
1602 trb
= &ring
->enqueue
->generic
;
1603 trb
->field
[0] = field1
;
1604 trb
->field
[1] = field2
;
1605 trb
->field
[2] = field3
;
1606 trb
->field
[3] = field4
;
1607 inc_enq(xhci
, ring
, consumer
);
1611 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1612 * FIXME allocate segments if the ring is full.
1614 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1615 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1617 /* Make sure the endpoint has been added to xHC schedule */
1618 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1620 case EP_STATE_DISABLED
:
1622 * USB core changed config/interfaces without notifying us,
1623 * or hardware is reporting the wrong state.
1625 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1627 case EP_STATE_ERROR
:
1628 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
1629 /* FIXME event handling code for error needs to clear it */
1630 /* XXX not sure if this should be -ENOENT or not */
1632 case EP_STATE_HALTED
:
1633 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
1634 case EP_STATE_STOPPED
:
1635 case EP_STATE_RUNNING
:
1638 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1640 * FIXME issue Configure Endpoint command to try to get the HC
1641 * back into a known state.
1645 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1646 /* FIXME allocate more room */
1647 xhci_err(xhci
, "ERROR no room on ep ring\n");
1653 static int prepare_transfer(struct xhci_hcd
*xhci
,
1654 struct xhci_virt_device
*xdev
,
1655 unsigned int ep_index
,
1656 unsigned int num_trbs
,
1658 struct xhci_td
**td
,
1662 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1663 ret
= prepare_ring(xhci
, xdev
->eps
[ep_index
].ring
,
1664 ep_ctx
->ep_info
& EP_STATE_MASK
,
1665 num_trbs
, mem_flags
);
1668 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1671 INIT_LIST_HEAD(&(*td
)->td_list
);
1672 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1674 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1675 if (unlikely(ret
)) {
1681 urb
->hcpriv
= (void *) (*td
);
1682 /* Add this TD to the tail of the endpoint ring's TD list */
1683 list_add_tail(&(*td
)->td_list
, &xdev
->eps
[ep_index
].ring
->td_list
);
1684 (*td
)->start_seg
= xdev
->eps
[ep_index
].ring
->enq_seg
;
1685 (*td
)->first_trb
= xdev
->eps
[ep_index
].ring
->enqueue
;
1690 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1692 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1693 struct scatterlist
*sg
;
1696 num_sgs
= urb
->num_sgs
;
1697 temp
= urb
->transfer_buffer_length
;
1699 xhci_dbg(xhci
, "count sg list trbs: \n");
1701 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1702 unsigned int previous_total_trbs
= num_trbs
;
1703 unsigned int len
= sg_dma_len(sg
);
1705 /* Scatter gather list entries may cross 64KB boundaries */
1706 running_total
= TRB_MAX_BUFF_SIZE
-
1707 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
1708 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
1709 if (running_total
!= 0)
1712 /* How many more 64KB chunks to transfer, how many more TRBs? */
1713 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
1715 running_total
+= TRB_MAX_BUFF_SIZE
;
1717 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1718 i
, (unsigned long long)sg_dma_address(sg
),
1719 len
, len
, num_trbs
- previous_total_trbs
);
1721 len
= min_t(int, len
, temp
);
1726 xhci_dbg(xhci
, "\n");
1727 if (!in_interrupt())
1728 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1729 urb
->ep
->desc
.bEndpointAddress
,
1730 urb
->transfer_buffer_length
,
1735 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1738 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1739 "TRBs, %d left\n", __func__
,
1740 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1741 if (running_total
!= urb
->transfer_buffer_length
)
1742 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1743 "queued %#x (%d), asked for %#x (%d)\n",
1745 urb
->ep
->desc
.bEndpointAddress
,
1746 running_total
, running_total
,
1747 urb
->transfer_buffer_length
,
1748 urb
->transfer_buffer_length
);
1751 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1752 unsigned int ep_index
, int start_cycle
,
1753 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1756 * Pass all the TRBs to the hardware at once and make sure this write
1760 start_trb
->field
[3] |= start_cycle
;
1761 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1765 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1766 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1767 * (comprised of sg list entries) can take several service intervals to
1770 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1771 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1773 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
1774 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1778 xhci_interval
= EP_INTERVAL_TO_UFRAMES(ep_ctx
->ep_info
);
1779 ep_interval
= urb
->interval
;
1780 /* Convert to microframes */
1781 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1782 urb
->dev
->speed
== USB_SPEED_FULL
)
1784 /* FIXME change this to a warning and a suggestion to use the new API
1785 * to set the polling interval (once the API is added).
1787 if (xhci_interval
!= ep_interval
) {
1788 if (!printk_ratelimit())
1789 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
1790 " (%d microframe%s) than xHCI "
1791 "(%d microframe%s)\n",
1793 ep_interval
== 1 ? "" : "s",
1795 xhci_interval
== 1 ? "" : "s");
1796 urb
->interval
= xhci_interval
;
1797 /* Convert back to frames for LS/FS devices */
1798 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1799 urb
->dev
->speed
== USB_SPEED_FULL
)
1802 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
1806 * The TD size is the number of bytes remaining in the TD (including this TRB),
1807 * right shifted by 10.
1808 * It must fit in bits 21:17, so it can't be bigger than 31.
1810 static u32
xhci_td_remainder(unsigned int remainder
)
1812 u32 max
= (1 << (21 - 17 + 1)) - 1;
1814 if ((remainder
>> 10) >= max
)
1817 return (remainder
>> 10) << 17;
1820 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1821 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1823 struct xhci_ring
*ep_ring
;
1824 unsigned int num_trbs
;
1826 struct scatterlist
*sg
;
1828 int trb_buff_len
, this_sg_len
, running_total
;
1832 struct xhci_generic_trb
*start_trb
;
1835 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1836 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1837 num_sgs
= urb
->num_sgs
;
1839 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1840 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1841 if (trb_buff_len
< 0)
1842 return trb_buff_len
;
1844 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1845 * until we've finished creating all the other TRBs. The ring's cycle
1846 * state may change as we enqueue the other TRBs, so save it too.
1848 start_trb
= &ep_ring
->enqueue
->generic
;
1849 start_cycle
= ep_ring
->cycle_state
;
1853 * How much data is in the first TRB?
1855 * There are three forces at work for TRB buffer pointers and lengths:
1856 * 1. We don't want to walk off the end of this sg-list entry buffer.
1857 * 2. The transfer length that the driver requested may be smaller than
1858 * the amount of memory allocated for this scatter-gather list.
1859 * 3. TRBs buffers can't cross 64KB boundaries.
1862 addr
= (u64
) sg_dma_address(sg
);
1863 this_sg_len
= sg_dma_len(sg
);
1864 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
1865 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1866 if (trb_buff_len
> urb
->transfer_buffer_length
)
1867 trb_buff_len
= urb
->transfer_buffer_length
;
1868 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1872 /* Queue the first TRB, even if it's zero-length */
1875 u32 length_field
= 0;
1878 /* Don't change the cycle bit of the first TRB until later */
1882 field
|= ep_ring
->cycle_state
;
1884 /* Chain all the TRBs together; clear the chain bit in the last
1885 * TRB to indicate it's the last TRB in the chain.
1890 /* FIXME - add check for ZERO_PACKET flag before this */
1891 td
->last_trb
= ep_ring
->enqueue
;
1894 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1895 "64KB boundary at %#x, end dma = %#x\n",
1896 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1897 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1898 (unsigned int) addr
+ trb_buff_len
);
1899 if (TRB_MAX_BUFF_SIZE
-
1900 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
1901 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1902 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1903 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1904 (unsigned int) addr
+ trb_buff_len
);
1906 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
-
1908 length_field
= TRB_LEN(trb_buff_len
) |
1911 queue_trb(xhci
, ep_ring
, false,
1912 lower_32_bits(addr
),
1913 upper_32_bits(addr
),
1915 /* We always want to know if the TRB was short,
1916 * or we won't get an event when it completes.
1917 * (Unless we use event data TRBs, which are a
1918 * waste of space and HC resources.)
1920 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1922 running_total
+= trb_buff_len
;
1924 /* Calculate length for next transfer --
1925 * Are we done queueing all the TRBs for this sg entry?
1927 this_sg_len
-= trb_buff_len
;
1928 if (this_sg_len
== 0) {
1933 addr
= (u64
) sg_dma_address(sg
);
1934 this_sg_len
= sg_dma_len(sg
);
1936 addr
+= trb_buff_len
;
1939 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1940 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
1941 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1942 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1944 urb
->transfer_buffer_length
- running_total
;
1945 } while (running_total
< urb
->transfer_buffer_length
);
1947 check_trb_math(urb
, num_trbs
, running_total
);
1948 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1952 /* This is very similar to what ehci-q.c qtd_fill() does */
1953 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1954 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1956 struct xhci_ring
*ep_ring
;
1959 struct xhci_generic_trb
*start_trb
;
1962 u32 field
, length_field
;
1964 int running_total
, trb_buff_len
, ret
;
1968 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1970 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1973 /* How much data is (potentially) left before the 64KB boundary? */
1974 running_total
= TRB_MAX_BUFF_SIZE
-
1975 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
1976 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
1978 /* If there's some data on this 64KB chunk, or we have to send a
1979 * zero-length transfer, we need at least one TRB
1981 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1983 /* How many more 64KB chunks to transfer, how many more TRBs? */
1984 while (running_total
< urb
->transfer_buffer_length
) {
1986 running_total
+= TRB_MAX_BUFF_SIZE
;
1988 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1990 if (!in_interrupt())
1991 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1992 urb
->ep
->desc
.bEndpointAddress
,
1993 urb
->transfer_buffer_length
,
1994 urb
->transfer_buffer_length
,
1995 (unsigned long long)urb
->transfer_dma
,
1998 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1999 num_trbs
, urb
, &td
, mem_flags
);
2004 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2005 * until we've finished creating all the other TRBs. The ring's cycle
2006 * state may change as we enqueue the other TRBs, so save it too.
2008 start_trb
= &ep_ring
->enqueue
->generic
;
2009 start_cycle
= ep_ring
->cycle_state
;
2012 /* How much data is in the first TRB? */
2013 addr
= (u64
) urb
->transfer_dma
;
2014 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2015 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2016 if (trb_buff_len
> urb
->transfer_buffer_length
)
2017 trb_buff_len
= urb
->transfer_buffer_length
;
2021 /* Queue the first TRB, even if it's zero-length */
2026 /* Don't change the cycle bit of the first TRB until later */
2030 field
|= ep_ring
->cycle_state
;
2032 /* Chain all the TRBs together; clear the chain bit in the last
2033 * TRB to indicate it's the last TRB in the chain.
2038 /* FIXME - add check for ZERO_PACKET flag before this */
2039 td
->last_trb
= ep_ring
->enqueue
;
2042 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
-
2044 length_field
= TRB_LEN(trb_buff_len
) |
2047 queue_trb(xhci
, ep_ring
, false,
2048 lower_32_bits(addr
),
2049 upper_32_bits(addr
),
2051 /* We always want to know if the TRB was short,
2052 * or we won't get an event when it completes.
2053 * (Unless we use event data TRBs, which are a
2054 * waste of space and HC resources.)
2056 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
2058 running_total
+= trb_buff_len
;
2060 /* Calculate length for next transfer */
2061 addr
+= trb_buff_len
;
2062 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
2063 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
2064 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
2065 } while (running_total
< urb
->transfer_buffer_length
);
2067 check_trb_math(urb
, num_trbs
, running_total
);
2068 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
2072 /* Caller must have locked xhci->lock */
2073 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2074 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2076 struct xhci_ring
*ep_ring
;
2079 struct usb_ctrlrequest
*setup
;
2080 struct xhci_generic_trb
*start_trb
;
2082 u32 field
, length_field
;
2085 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
2088 * Need to copy setup packet into setup TRB, so we can't use the setup
2091 if (!urb
->setup_packet
)
2094 if (!in_interrupt())
2095 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
2097 /* 1 TRB for setup, 1 for status */
2100 * Don't need to check if we need additional event data and normal TRBs,
2101 * since data in control transfers will never get bigger than 16MB
2102 * XXX: can we get a buffer that crosses 64KB boundaries?
2104 if (urb
->transfer_buffer_length
> 0)
2106 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
2107 urb
, &td
, mem_flags
);
2112 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2113 * until we've finished creating all the other TRBs. The ring's cycle
2114 * state may change as we enqueue the other TRBs, so save it too.
2116 start_trb
= &ep_ring
->enqueue
->generic
;
2117 start_cycle
= ep_ring
->cycle_state
;
2119 /* Queue setup TRB - see section 6.4.1.2.1 */
2120 /* FIXME better way to translate setup_packet into two u32 fields? */
2121 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
2122 queue_trb(xhci
, ep_ring
, false,
2123 /* FIXME endianness is probably going to bite my ass here. */
2124 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
2125 setup
->wIndex
| setup
->wLength
<< 16,
2126 TRB_LEN(8) | TRB_INTR_TARGET(0),
2127 /* Immediate data in pointer */
2128 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
2130 /* If there's data, queue data TRBs */
2132 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
2133 xhci_td_remainder(urb
->transfer_buffer_length
) |
2135 if (urb
->transfer_buffer_length
> 0) {
2136 if (setup
->bRequestType
& USB_DIR_IN
)
2137 field
|= TRB_DIR_IN
;
2138 queue_trb(xhci
, ep_ring
, false,
2139 lower_32_bits(urb
->transfer_dma
),
2140 upper_32_bits(urb
->transfer_dma
),
2142 /* Event on short tx */
2143 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
2146 /* Save the DMA address of the last TRB in the TD */
2147 td
->last_trb
= ep_ring
->enqueue
;
2149 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2150 /* If the device sent data, the status stage is an OUT transfer */
2151 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
2155 queue_trb(xhci
, ep_ring
, false,
2159 /* Event on completion */
2160 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
2162 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
2166 /**** Command Ring Operations ****/
2168 /* Generic function for queueing a command TRB on the command ring.
2169 * Check to make sure there's room on the command ring for one command TRB.
2170 * Also check that there's room reserved for commands that must not fail.
2171 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2172 * then only check for the number of reserved spots.
2173 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2174 * because the command event handler may want to resubmit a failed command.
2176 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
2177 u32 field3
, u32 field4
, bool command_must_succeed
)
2179 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
2180 if (!command_must_succeed
)
2183 if (!room_on_ring(xhci
, xhci
->cmd_ring
, reserved_trbs
)) {
2184 if (!in_interrupt())
2185 xhci_err(xhci
, "ERR: No room for command on command ring\n");
2186 if (command_must_succeed
)
2187 xhci_err(xhci
, "ERR: Reserved TRB counting for "
2188 "unfailable commands failed.\n");
2191 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
2192 field4
| xhci
->cmd_ring
->cycle_state
);
2196 /* Queue a no-op command on the command ring */
2197 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
2199 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
), false);
2203 * Place a no-op command on the command ring to test the command and
2206 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
2208 if (queue_cmd_noop(xhci
) < 0)
2210 xhci
->noops_submitted
++;
2211 return xhci_ring_cmd_db
;
2214 /* Queue a slot enable or disable request on the command ring */
2215 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
2217 return queue_command(xhci
, 0, 0, 0,
2218 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
2221 /* Queue an address device command TRB */
2222 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2225 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2226 upper_32_bits(in_ctx_ptr
), 0,
2227 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
2231 /* Queue a configure endpoint command TRB */
2232 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2233 u32 slot_id
, bool command_must_succeed
)
2235 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2236 upper_32_bits(in_ctx_ptr
), 0,
2237 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
2238 command_must_succeed
);
2241 /* Queue an evaluate context command TRB */
2242 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2245 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2246 upper_32_bits(in_ctx_ptr
), 0,
2247 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
2251 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
2252 unsigned int ep_index
)
2254 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2255 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2256 u32 type
= TRB_TYPE(TRB_STOP_RING
);
2258 return queue_command(xhci
, 0, 0, 0,
2259 trb_slot_id
| trb_ep_index
| type
, false);
2262 /* Set Transfer Ring Dequeue Pointer command.
2263 * This should not be used for endpoints that have streams enabled.
2265 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
2266 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
2267 union xhci_trb
*deq_ptr
, u32 cycle_state
)
2270 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2271 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2272 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
2274 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
2276 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
2277 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
2281 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
2282 upper_32_bits(addr
), 0,
2283 trb_slot_id
| trb_ep_index
| type
, false);
2286 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
2287 unsigned int ep_index
)
2289 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2290 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2291 u32 type
= TRB_TYPE(TRB_RESET_EP
);
2293 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,