Fix gcc 4.5.1 miscompiling drivers/char/i8k.c (again)
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / host / ehci.h
blob556c0b48f3abd73278206e5c1581eb3d32b73850
1 /*
2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
35 #else
36 #define __hc32 __le32
37 #define __hc16 __le16
38 #endif
40 /* statistics can be kept for tuning/monitoring */
41 struct ehci_stats {
42 /* irq usage */
43 unsigned long normal;
44 unsigned long error;
45 unsigned long reclaim;
46 unsigned long lost_iaa;
48 /* termination of urbs from core */
49 unsigned long complete;
50 unsigned long unlink;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
57 * ehci_qtd: qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
65 struct ehci_hcd { /* one per controller */
66 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
71 __u32 hcs_params; /* cached register copy */
72 spinlock_t lock;
74 /* async schedule support */
75 struct ehci_qh *async;
76 struct ehci_qh *reclaim;
77 unsigned scanning : 1;
79 /* periodic schedule support */
80 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
81 unsigned periodic_size;
82 __hc32 *periodic; /* hw periodic table */
83 dma_addr_t periodic_dma;
84 unsigned i_thresh; /* uframes HC might cache */
86 union ehci_shadow *pshadow; /* mirror hw periodic table */
87 int next_uframe; /* scan periodic, start here */
88 unsigned periodic_sched; /* periodic activity count */
90 /* list of itds & sitds completed while clock_frame was still active */
91 struct list_head cached_itd_list;
92 struct list_head cached_sitd_list;
93 unsigned clock_frame;
95 /* per root hub port */
96 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
98 /* bit vectors (one bit per port) */
99 unsigned long bus_suspended; /* which ports were
100 already suspended at the start of a bus suspend */
101 unsigned long companion_ports; /* which ports are
102 dedicated to the companion controller */
103 unsigned long owned_ports; /* which ports are
104 owned by the companion during a bus suspend */
105 unsigned long port_c_suspend; /* which ports have
106 the change-suspend feature turned on */
107 unsigned long suspended_ports; /* which ports are
108 suspended */
110 /* per-HC memory pools (could be per-bus, but ...) */
111 struct dma_pool *qh_pool; /* qh per active urb */
112 struct dma_pool *qtd_pool; /* one or more per qh */
113 struct dma_pool *itd_pool; /* itd per iso urb */
114 struct dma_pool *sitd_pool; /* sitd per split iso urb */
116 struct timer_list iaa_watchdog;
117 struct timer_list watchdog;
118 unsigned long actions;
119 unsigned stamp;
120 unsigned random_frame;
121 unsigned long next_statechange;
122 ktime_t last_periodic_enable;
123 u32 command;
125 /* SILICON QUIRKS */
126 unsigned no_selective_suspend:1;
127 unsigned has_fsl_port_bug:1; /* FreeScale */
128 unsigned big_endian_mmio:1;
129 unsigned big_endian_desc:1;
130 unsigned has_amcc_usb23:1;
131 unsigned need_io_watchdog:1;
132 unsigned broken_periodic:1;
134 /* required for usb32 quirk */
135 #define OHCI_CTRL_HCFS (3 << 6)
136 #define OHCI_USB_OPER (2 << 6)
137 #define OHCI_USB_SUSPEND (3 << 6)
139 #define OHCI_HCCTRL_OFFSET 0x4
140 #define OHCI_HCCTRL_LEN 0x4
141 __hc32 *ohci_hcctrl_reg;
142 unsigned has_hostpc:1;
144 u8 sbrn; /* packed release number */
146 /* irq statistics */
147 #ifdef EHCI_STATS
148 struct ehci_stats stats;
149 # define COUNT(x) do { (x)++; } while (0)
150 #else
151 # define COUNT(x) do {} while (0)
152 #endif
154 /* debug files */
155 #ifdef DEBUG
156 struct dentry *debug_dir;
157 struct dentry *debug_async;
158 struct dentry *debug_periodic;
159 struct dentry *debug_registers;
160 #endif
163 /* convert between an HCD pointer and the corresponding EHCI_HCD */
164 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
166 return (struct ehci_hcd *) (hcd->hcd_priv);
168 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
170 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
174 static inline void
175 iaa_watchdog_start(struct ehci_hcd *ehci)
177 WARN_ON(timer_pending(&ehci->iaa_watchdog));
178 mod_timer(&ehci->iaa_watchdog,
179 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
182 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
184 del_timer(&ehci->iaa_watchdog);
187 enum ehci_timer_action {
188 TIMER_IO_WATCHDOG,
189 TIMER_ASYNC_SHRINK,
190 TIMER_ASYNC_OFF,
193 static inline void
194 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
196 clear_bit (action, &ehci->actions);
199 static void free_cached_lists(struct ehci_hcd *ehci);
201 /*-------------------------------------------------------------------------*/
203 #include <linux/usb/ehci_def.h>
205 /*-------------------------------------------------------------------------*/
207 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
210 * EHCI Specification 0.95 Section 3.5
211 * QTD: describe data transfer components (buffer, direction, ...)
212 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
214 * These are associated only with "QH" (Queue Head) structures,
215 * used with control, bulk, and interrupt transfers.
217 struct ehci_qtd {
218 /* first part defined by EHCI spec */
219 __hc32 hw_next; /* see EHCI 3.5.1 */
220 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
221 __hc32 hw_token; /* see EHCI 3.5.3 */
222 #define QTD_TOGGLE (1 << 31) /* data toggle */
223 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
224 #define QTD_IOC (1 << 15) /* interrupt on complete */
225 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
226 #define QTD_PID(tok) (((tok)>>8) & 0x3)
227 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
228 #define QTD_STS_HALT (1 << 6) /* halted on error */
229 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
230 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
231 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
232 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
233 #define QTD_STS_STS (1 << 1) /* split transaction state */
234 #define QTD_STS_PING (1 << 0) /* issue PING? */
236 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
237 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
238 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
240 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
241 __hc32 hw_buf_hi [5]; /* Appendix B */
243 /* the rest is HCD-private */
244 dma_addr_t qtd_dma; /* qtd address */
245 struct list_head qtd_list; /* sw qtd list */
246 struct urb *urb; /* qtd's urb */
247 size_t length; /* length of buffer */
248 } __attribute__ ((aligned (32)));
250 /* mask NakCnt+T in qh->hw_alt_next */
251 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
253 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
255 /*-------------------------------------------------------------------------*/
257 /* type tag from {qh,itd,sitd,fstn}->hw_next */
258 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
261 * Now the following defines are not converted using the
262 * cpu_to_le32() macro anymore, since we have to support
263 * "dynamic" switching between be and le support, so that the driver
264 * can be used on one system with SoC EHCI controller using big-endian
265 * descriptors as well as a normal little-endian PCI EHCI controller.
267 /* values for that type tag */
268 #define Q_TYPE_ITD (0 << 1)
269 #define Q_TYPE_QH (1 << 1)
270 #define Q_TYPE_SITD (2 << 1)
271 #define Q_TYPE_FSTN (3 << 1)
273 /* next async queue entry, or pointer to interrupt/periodic QH */
274 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
276 /* for periodic/async schedules and qtd lists, mark end of list */
277 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
280 * Entries in periodic shadow table are pointers to one of four kinds
281 * of data structure. That's dictated by the hardware; a type tag is
282 * encoded in the low bits of the hardware's periodic schedule. Use
283 * Q_NEXT_TYPE to get the tag.
285 * For entries in the async schedule, the type tag always says "qh".
287 union ehci_shadow {
288 struct ehci_qh *qh; /* Q_TYPE_QH */
289 struct ehci_itd *itd; /* Q_TYPE_ITD */
290 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
291 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
292 __hc32 *hw_next; /* (all types) */
293 void *ptr;
296 /*-------------------------------------------------------------------------*/
299 * EHCI Specification 0.95 Section 3.6
300 * QH: describes control/bulk/interrupt endpoints
301 * See Fig 3-7 "Queue Head Structure Layout".
303 * These appear in both the async and (for interrupt) periodic schedules.
306 /* first part defined by EHCI spec */
307 struct ehci_qh_hw {
308 __hc32 hw_next; /* see EHCI 3.6.1 */
309 __hc32 hw_info1; /* see EHCI 3.6.2 */
310 #define QH_HEAD 0x00008000
311 __hc32 hw_info2; /* see EHCI 3.6.2 */
312 #define QH_SMASK 0x000000ff
313 #define QH_CMASK 0x0000ff00
314 #define QH_HUBADDR 0x007f0000
315 #define QH_HUBPORT 0x3f800000
316 #define QH_MULT 0xc0000000
317 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
319 /* qtd overlay (hardware parts of a struct ehci_qtd) */
320 __hc32 hw_qtd_next;
321 __hc32 hw_alt_next;
322 __hc32 hw_token;
323 __hc32 hw_buf [5];
324 __hc32 hw_buf_hi [5];
325 } __attribute__ ((aligned(32)));
327 struct ehci_qh {
328 struct ehci_qh_hw *hw;
329 /* the rest is HCD-private */
330 dma_addr_t qh_dma; /* address of qh */
331 union ehci_shadow qh_next; /* ptr to qh; or periodic */
332 struct list_head qtd_list; /* sw qtd list */
333 struct ehci_qtd *dummy;
334 struct ehci_qh *reclaim; /* next to reclaim */
336 struct ehci_hcd *ehci;
339 * Do NOT use atomic operations for QH refcounting. On some CPUs
340 * (PPC7448 for example), atomic operations cannot be performed on
341 * memory that is cache-inhibited (i.e. being used for DMA).
342 * Spinlocks are used to protect all QH fields.
344 u32 refcount;
345 unsigned stamp;
347 u8 needs_rescan; /* Dequeue during giveback */
348 u8 qh_state;
349 #define QH_STATE_LINKED 1 /* HC sees this */
350 #define QH_STATE_UNLINK 2 /* HC may still see this */
351 #define QH_STATE_IDLE 3 /* HC doesn't see this */
352 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
353 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
355 u8 xacterrs; /* XactErr retry counter */
356 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
358 /* periodic schedule info */
359 u8 usecs; /* intr bandwidth */
360 u8 gap_uf; /* uframes split/csplit gap */
361 u8 c_usecs; /* ... split completion bw */
362 u16 tt_usecs; /* tt downstream bandwidth */
363 unsigned short period; /* polling interval */
364 unsigned short start; /* where polling starts */
365 #define NO_FRAME ((unsigned short)~0) /* pick new start */
367 struct usb_device *dev; /* access to TT */
368 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
371 /*-------------------------------------------------------------------------*/
373 /* description of one iso transaction (up to 3 KB data if highspeed) */
374 struct ehci_iso_packet {
375 /* These will be copied to iTD when scheduling */
376 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
377 __hc32 transaction; /* itd->hw_transaction[i] |= */
378 u8 cross; /* buf crosses pages */
379 /* for full speed OUT splits */
380 u32 buf1;
383 /* temporary schedule data for packets from iso urbs (both speeds)
384 * each packet is one logical usb transaction to the device (not TT),
385 * beginning at stream->next_uframe
387 struct ehci_iso_sched {
388 struct list_head td_list;
389 unsigned span;
390 struct ehci_iso_packet packet [0];
394 * ehci_iso_stream - groups all (s)itds for this endpoint.
395 * acts like a qh would, if EHCI had them for ISO.
397 struct ehci_iso_stream {
398 /* first field matches ehci_hq, but is NULL */
399 struct ehci_qh_hw *hw;
401 u32 refcount;
402 u8 bEndpointAddress;
403 u8 highspeed;
404 u16 depth; /* depth in uframes */
405 struct list_head td_list; /* queued itds/sitds */
406 struct list_head free_list; /* list of unused itds/sitds */
407 struct usb_device *udev;
408 struct usb_host_endpoint *ep;
410 /* output of (re)scheduling */
411 unsigned long start; /* jiffies */
412 unsigned long rescheduled;
413 int next_uframe;
414 __hc32 splits;
416 /* the rest is derived from the endpoint descriptor,
417 * trusting urb->interval == f(epdesc->bInterval) and
418 * including the extra info for hw_bufp[0..2]
420 u8 usecs, c_usecs;
421 u16 interval;
422 u16 tt_usecs;
423 u16 maxp;
424 u16 raw_mask;
425 unsigned bandwidth;
427 /* This is used to initialize iTD's hw_bufp fields */
428 __hc32 buf0;
429 __hc32 buf1;
430 __hc32 buf2;
432 /* this is used to initialize sITD's tt info */
433 __hc32 address;
436 /*-------------------------------------------------------------------------*/
439 * EHCI Specification 0.95 Section 3.3
440 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
442 * Schedule records for high speed iso xfers
444 struct ehci_itd {
445 /* first part defined by EHCI spec */
446 __hc32 hw_next; /* see EHCI 3.3.1 */
447 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
448 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
449 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
450 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
451 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
452 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
453 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
455 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
457 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
458 __hc32 hw_bufp_hi [7]; /* Appendix B */
460 /* the rest is HCD-private */
461 dma_addr_t itd_dma; /* for this itd */
462 union ehci_shadow itd_next; /* ptr to periodic q entry */
464 struct urb *urb;
465 struct ehci_iso_stream *stream; /* endpoint's queue */
466 struct list_head itd_list; /* list of stream's itds */
468 /* any/all hw_transactions here may be used by that urb */
469 unsigned frame; /* where scheduled */
470 unsigned pg;
471 unsigned index[8]; /* in urb->iso_frame_desc */
472 } __attribute__ ((aligned (32)));
474 /*-------------------------------------------------------------------------*/
477 * EHCI Specification 0.95 Section 3.4
478 * siTD, aka split-transaction isochronous Transfer Descriptor
479 * ... describe full speed iso xfers through TT in hubs
480 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
482 struct ehci_sitd {
483 /* first part defined by EHCI spec */
484 __hc32 hw_next;
485 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
486 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
487 __hc32 hw_uframe; /* EHCI table 3-10 */
488 __hc32 hw_results; /* EHCI table 3-11 */
489 #define SITD_IOC (1 << 31) /* interrupt on completion */
490 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
491 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
492 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
493 #define SITD_STS_ERR (1 << 6) /* error from TT */
494 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
495 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
496 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
497 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
498 #define SITD_STS_STS (1 << 1) /* split transaction state */
500 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
502 __hc32 hw_buf [2]; /* EHCI table 3-12 */
503 __hc32 hw_backpointer; /* EHCI table 3-13 */
504 __hc32 hw_buf_hi [2]; /* Appendix B */
506 /* the rest is HCD-private */
507 dma_addr_t sitd_dma;
508 union ehci_shadow sitd_next; /* ptr to periodic q entry */
510 struct urb *urb;
511 struct ehci_iso_stream *stream; /* endpoint's queue */
512 struct list_head sitd_list; /* list of stream's sitds */
513 unsigned frame;
514 unsigned index;
515 } __attribute__ ((aligned (32)));
517 /*-------------------------------------------------------------------------*/
520 * EHCI Specification 0.96 Section 3.7
521 * Periodic Frame Span Traversal Node (FSTN)
523 * Manages split interrupt transactions (using TT) that span frame boundaries
524 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
525 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
526 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
528 struct ehci_fstn {
529 __hc32 hw_next; /* any periodic q entry */
530 __hc32 hw_prev; /* qh or EHCI_LIST_END */
532 /* the rest is HCD-private */
533 dma_addr_t fstn_dma;
534 union ehci_shadow fstn_next; /* ptr to periodic q entry */
535 } __attribute__ ((aligned (32)));
537 /*-------------------------------------------------------------------------*/
539 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
542 * Some EHCI controllers have a Transaction Translator built into the
543 * root hub. This is a non-standard feature. Each controller will need
544 * to add code to the following inline functions, and call them as
545 * needed (mostly in root hub code).
548 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
550 /* Returns the speed of a device attached to a port on the root hub. */
551 static inline unsigned int
552 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
554 if (ehci_is_TDI(ehci)) {
555 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
556 case 0:
557 return 0;
558 case 1:
559 return (1<<USB_PORT_FEAT_LOWSPEED);
560 case 2:
561 default:
562 return (1<<USB_PORT_FEAT_HIGHSPEED);
565 return (1<<USB_PORT_FEAT_HIGHSPEED);
568 #else
570 #define ehci_is_TDI(e) (0)
572 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
573 #endif
575 /*-------------------------------------------------------------------------*/
577 #ifdef CONFIG_PPC_83xx
578 /* Some Freescale processors have an erratum in which the TT
579 * port number in the queue head was 0..N-1 instead of 1..N.
581 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
582 #else
583 #define ehci_has_fsl_portno_bug(e) (0)
584 #endif
587 * While most USB host controllers implement their registers in
588 * little-endian format, a minority (celleb companion chip) implement
589 * them in big endian format.
591 * This attempts to support either format at compile time without a
592 * runtime penalty, or both formats with the additional overhead
593 * of checking a flag bit.
596 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
597 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
598 #else
599 #define ehci_big_endian_mmio(e) 0
600 #endif
603 * Big-endian read/write functions are arch-specific.
604 * Other arches can be added if/when they're needed.
606 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
607 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
608 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
609 #endif
611 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
612 __u32 __iomem * regs)
614 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
615 return ehci_big_endian_mmio(ehci) ?
616 readl_be(regs) :
617 readl(regs);
618 #else
619 return readl(regs);
620 #endif
623 static inline void ehci_writel(const struct ehci_hcd *ehci,
624 const unsigned int val, __u32 __iomem *regs)
626 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
627 ehci_big_endian_mmio(ehci) ?
628 writel_be(val, regs) :
629 writel(val, regs);
630 #else
631 writel(val, regs);
632 #endif
636 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
637 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
638 * Other common bits are dependant on has_amcc_usb23 quirk flag.
640 #ifdef CONFIG_44x
641 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
643 u32 hc_control;
645 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
646 if (operational)
647 hc_control |= OHCI_USB_OPER;
648 else
649 hc_control |= OHCI_USB_SUSPEND;
651 writel_be(hc_control, ehci->ohci_hcctrl_reg);
652 (void) readl_be(ehci->ohci_hcctrl_reg);
654 #else
655 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
657 #endif
659 /*-------------------------------------------------------------------------*/
662 * The AMCC 440EPx not only implements its EHCI registers in big-endian
663 * format, but also its DMA data structures (descriptors).
665 * EHCI controllers accessed through PCI work normally (little-endian
666 * everywhere), so we won't bother supporting a BE-only mode for now.
668 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
669 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
671 /* cpu to ehci */
672 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
674 return ehci_big_endian_desc(ehci)
675 ? (__force __hc32)cpu_to_be32(x)
676 : (__force __hc32)cpu_to_le32(x);
679 /* ehci to cpu */
680 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
682 return ehci_big_endian_desc(ehci)
683 ? be32_to_cpu((__force __be32)x)
684 : le32_to_cpu((__force __le32)x);
687 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
689 return ehci_big_endian_desc(ehci)
690 ? be32_to_cpup((__force __be32 *)x)
691 : le32_to_cpup((__force __le32 *)x);
694 #else
696 /* cpu to ehci */
697 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
699 return cpu_to_le32(x);
702 /* ehci to cpu */
703 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
705 return le32_to_cpu(x);
708 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
710 return le32_to_cpup(x);
713 #endif
715 /*-------------------------------------------------------------------------*/
717 #ifndef DEBUG
718 #define STUB_DEBUG_FILES
719 #endif /* DEBUG */
721 /*-------------------------------------------------------------------------*/
723 #endif /* __LINUX_EHCI_HCD_H */