drivers/net/wireless/bcm43xx/bcm43xx.h

   1 #ifndef BCM43xx_H_
   2 #define BCM43xx_H_
   3
   4 #include <linux/version.h>
   5 #include <linux/kernel.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/stringify.h>
   9 #include <linux/pci.h>
  10 #include <net/ieee80211.h>
  11 #include <net/ieee80211softmac.h>
  12 #include <asm/atomic.h>
  13 #include <asm/io.h>
  14
  15
  16 #include "bcm43xx_debugfs.h"
  17 #include "bcm43xx_leds.h"
  18 #include "bcm43xx_sysfs.h"
  19
  20
  21 #define PFX                             KBUILD_MODNAME ": "
  22
  23 #define BCM43xx_SWITCH_CORE_MAX_RETRIES 50
  24 #define BCM43xx_IRQWAIT_MAX_RETRIES     50
  25
  26 #define BCM43xx_IO_SIZE                 8192
  27
  28 /* Active Core PCI Configuration Register. */
  29 #define BCM43xx_PCICFG_ACTIVE_CORE      0x80
  30 /* SPROM control register. */
  31 #define BCM43xx_PCICFG_SPROMCTL         0x88
  32 /* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
  33 #define BCM43xx_PCICFG_ICR              0x94
  34
  35 /* MMIO offsets */
  36 #define BCM43xx_MMIO_DMA1_REASON        0x20
  37 #define BCM43xx_MMIO_DMA1_IRQ_MASK      0x24
  38 #define BCM43xx_MMIO_DMA2_REASON        0x28
  39 #define BCM43xx_MMIO_DMA2_IRQ_MASK      0x2C
  40 #define BCM43xx_MMIO_DMA3_REASON        0x30
  41 #define BCM43xx_MMIO_DMA3_IRQ_MASK      0x34
  42 #define BCM43xx_MMIO_DMA4_REASON        0x38
  43 #define BCM43xx_MMIO_DMA4_IRQ_MASK      0x3C
  44 #define BCM43xx_MMIO_STATUS_BITFIELD    0x120
  45 #define BCM43xx_MMIO_STATUS2_BITFIELD   0x124
  46 #define BCM43xx_MMIO_GEN_IRQ_REASON     0x128
  47 #define BCM43xx_MMIO_GEN_IRQ_MASK       0x12C
  48 #define BCM43xx_MMIO_RAM_CONTROL        0x130
  49 #define BCM43xx_MMIO_RAM_DATA           0x134
  50 #define BCM43xx_MMIO_PS_STATUS          0x140
  51 #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
  52 #define BCM43xx_MMIO_SHM_CONTROL        0x160
  53 #define BCM43xx_MMIO_SHM_DATA           0x164
  54 #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
  55 #define BCM43xx_MMIO_XMITSTAT_0         0x170
  56 #define BCM43xx_MMIO_XMITSTAT_1         0x174
  57 #define BCM43xx_MMIO_REV3PLUS_TSF_LOW   0x180 /* core rev >= 3 only */
  58 #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH  0x184 /* core rev >= 3 only */
  59 #define BCM43xx_MMIO_DMA1_BASE          0x200
  60 #define BCM43xx_MMIO_DMA2_BASE          0x220
  61 #define BCM43xx_MMIO_DMA3_BASE          0x240
  62 #define BCM43xx_MMIO_DMA4_BASE          0x260
  63 #define BCM43xx_MMIO_PIO1_BASE          0x300
  64 #define BCM43xx_MMIO_PIO2_BASE          0x310
  65 #define BCM43xx_MMIO_PIO3_BASE          0x320
  66 #define BCM43xx_MMIO_PIO4_BASE          0x330
  67 #define BCM43xx_MMIO_PHY_VER            0x3E0
  68 #define BCM43xx_MMIO_PHY_RADIO          0x3E2
  69 #define BCM43xx_MMIO_ANTENNA            0x3E8
  70 #define BCM43xx_MMIO_CHANNEL            0x3F0
  71 #define BCM43xx_MMIO_CHANNEL_EXT        0x3F4
  72 #define BCM43xx_MMIO_RADIO_CONTROL      0x3F6
  73 #define BCM43xx_MMIO_RADIO_DATA_HIGH    0x3F8
  74 #define BCM43xx_MMIO_RADIO_DATA_LOW     0x3FA
  75 #define BCM43xx_MMIO_PHY_CONTROL        0x3FC
  76 #define BCM43xx_MMIO_PHY_DATA           0x3FE
  77 #define BCM43xx_MMIO_MACFILTER_CONTROL  0x420
  78 #define BCM43xx_MMIO_MACFILTER_DATA     0x422
  79 #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
  80 #define BCM43xx_MMIO_GPIO_CONTROL       0x49C
  81 #define BCM43xx_MMIO_GPIO_MASK          0x49E
  82 #define BCM43xx_MMIO_TSF_0              0x632 /* core rev < 3 only */
  83 #define BCM43xx_MMIO_TSF_1              0x634 /* core rev < 3 only */
  84 #define BCM43xx_MMIO_TSF_2              0x636 /* core rev < 3 only */
  85 #define BCM43xx_MMIO_TSF_3              0x638 /* core rev < 3 only */
  86 #define BCM43xx_MMIO_POWERUP_DELAY      0x6A8
  87
  88 /* SPROM offsets. */
  89 #define BCM43xx_SPROM_BASE              0x1000
  90 #define BCM43xx_SPROM_BOARDFLAGS2       0x1c
  91 #define BCM43xx_SPROM_IL0MACADDR        0x24
  92 #define BCM43xx_SPROM_ET0MACADDR        0x27
  93 #define BCM43xx_SPROM_ET1MACADDR        0x2a
  94 #define BCM43xx_SPROM_ETHPHY            0x2d
  95 #define BCM43xx_SPROM_BOARDREV          0x2e
  96 #define BCM43xx_SPROM_PA0B0             0x2f
  97 #define BCM43xx_SPROM_PA0B1             0x30
  98 #define BCM43xx_SPROM_PA0B2             0x31
  99 #define BCM43xx_SPROM_WL0GPIO0          0x32
 100 #define BCM43xx_SPROM_WL0GPIO2          0x33
 101 #define BCM43xx_SPROM_MAXPWR            0x34
 102 #define BCM43xx_SPROM_PA1B0             0x35
 103 #define BCM43xx_SPROM_PA1B1             0x36
 104 #define BCM43xx_SPROM_PA1B2             0x37
 105 #define BCM43xx_SPROM_IDL_TSSI_TGT      0x38
 106 #define BCM43xx_SPROM_BOARDFLAGS        0x39
 107 #define BCM43xx_SPROM_ANTENNA_GAIN      0x3a
 108 #define BCM43xx_SPROM_VERSION           0x3f
 109
 110 /* BCM43xx_SPROM_BOARDFLAGS values */
 111 #define BCM43xx_BFL_BTCOEXIST           0x0001 /* implements Bluetooth coexistance */
 112 #define BCM43xx_BFL_PACTRL              0x0002 /* GPIO 9 controlling the PA */
 113 #define BCM43xx_BFL_AIRLINEMODE         0x0004 /* implements GPIO 13 radio disable indication */
 114 #define BCM43xx_BFL_RSSI                0x0008 /* software calculates nrssi slope. */
 115 #define BCM43xx_BFL_ENETSPI             0x0010 /* has ephy roboswitch spi */
 116 #define BCM43xx_BFL_XTAL_NOSLOW         0x0020 /* no slow clock available */
 117 #define BCM43xx_BFL_CCKHIPWR            0x0040 /* can do high power CCK transmission */
 118 #define BCM43xx_BFL_ENETADM             0x0080 /* has ADMtek switch */
 119 #define BCM43xx_BFL_ENETVLAN            0x0100 /* can do vlan */
 120 #define BCM43xx_BFL_AFTERBURNER         0x0200 /* supports Afterburner mode */
 121 #define BCM43xx_BFL_NOPCI               0x0400 /* leaves PCI floating */
 122 #define BCM43xx_BFL_FEM                 0x0800 /* supports the Front End Module */
 123
 124 /* GPIO register offset, in both ChipCommon and PCI core. */
 125 #define BCM43xx_GPIO_CONTROL            0x6c
 126
 127 /* SHM Routing */
 128 #define BCM43xx_SHM_SHARED              0x0001
 129 #define BCM43xx_SHM_WIRELESS            0x0002
 130 #define BCM43xx_SHM_PCM                 0x0003
 131 #define BCM43xx_SHM_HWMAC               0x0004
 132 #define BCM43xx_SHM_UCODE               0x0300
 133
 134 /* MacFilter offsets. */
 135 #define BCM43xx_MACFILTER_SELF          0x0000
 136 #define BCM43xx_MACFILTER_ASSOC         0x0003
 137
 138 /* Chipcommon registers. */
 139 #define BCM43xx_CHIPCOMMON_CAPABILITIES         0x04
 140 #define BCM43xx_CHIPCOMMON_PLLONDELAY           0xB0
 141 #define BCM43xx_CHIPCOMMON_FREFSELDELAY         0xB4
 142 #define BCM43xx_CHIPCOMMON_SLOWCLKCTL           0xB8
 143 #define BCM43xx_CHIPCOMMON_SYSCLKCTL            0xC0
 144
 145 /* PCI core specific registers. */
 146 #define BCM43xx_PCICORE_BCAST_ADDR      0x50
 147 #define BCM43xx_PCICORE_BCAST_DATA      0x54
 148 #define BCM43xx_PCICORE_SBTOPCI2        0x108
 149
 150 /* SBTOPCI2 values. */
 151 #define BCM43xx_SBTOPCI2_PREFETCH       0x4
 152 #define BCM43xx_SBTOPCI2_BURST          0x8
 153
 154 /* Chipcommon capabilities. */
 155 #define BCM43xx_CAPABILITIES_PCTL               0x00040000
 156 #define BCM43xx_CAPABILITIES_PLLMASK            0x00030000
 157 #define BCM43xx_CAPABILITIES_PLLSHIFT           16
 158 #define BCM43xx_CAPABILITIES_FLASHMASK          0x00000700
 159 #define BCM43xx_CAPABILITIES_FLASHSHIFT         8
 160 #define BCM43xx_CAPABILITIES_EXTBUSPRESENT      0x00000040
 161 #define BCM43xx_CAPABILITIES_UARTGPIO           0x00000020
 162 #define BCM43xx_CAPABILITIES_UARTCLOCKMASK      0x00000018
 163 #define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT     3
 164 #define BCM43xx_CAPABILITIES_MIPSBIGENDIAN      0x00000004
 165 #define BCM43xx_CAPABILITIES_NRUARTSMASK        0x00000003
 166
 167 /* PowerControl */
 168 #define BCM43xx_PCTL_IN                 0xB0
 169 #define BCM43xx_PCTL_OUT                0xB4
 170 #define BCM43xx_PCTL_OUTENABLE          0xB8
 171 #define BCM43xx_PCTL_XTAL_POWERUP       0x40
 172 #define BCM43xx_PCTL_PLL_POWERDOWN      0x80
 173
 174 /* PowerControl Clock Modes */
 175 #define BCM43xx_PCTL_CLK_FAST           0x00
 176 #define BCM43xx_PCTL_CLK_SLOW           0x01
 177 #define BCM43xx_PCTL_CLK_DYNAMIC        0x02
 178
 179 #define BCM43xx_PCTL_FORCE_SLOW         0x0800
 180 #define BCM43xx_PCTL_FORCE_PLL          0x1000
 181 #define BCM43xx_PCTL_DYN_XTAL           0x2000
 182
 183 /* COREIDs */
 184 #define BCM43xx_COREID_CHIPCOMMON       0x800
 185 #define BCM43xx_COREID_ILINE20          0x801
 186 #define BCM43xx_COREID_SDRAM            0x803
 187 #define BCM43xx_COREID_PCI              0x804
 188 #define BCM43xx_COREID_MIPS             0x805
 189 #define BCM43xx_COREID_ETHERNET         0x806
 190 #define BCM43xx_COREID_V90              0x807
 191 #define BCM43xx_COREID_USB11_HOSTDEV    0x80a
 192 #define BCM43xx_COREID_IPSEC            0x80b
 193 #define BCM43xx_COREID_PCMCIA           0x80d
 194 #define BCM43xx_COREID_EXT_IF           0x80f
 195 #define BCM43xx_COREID_80211            0x812
 196 #define BCM43xx_COREID_MIPS_3302        0x816
 197 #define BCM43xx_COREID_USB11_HOST       0x817
 198 #define BCM43xx_COREID_USB11_DEV        0x818
 199 #define BCM43xx_COREID_USB20_HOST       0x819
 200 #define BCM43xx_COREID_USB20_DEV        0x81a
 201 #define BCM43xx_COREID_SDIO_HOST        0x81b
 202
 203 /* Core Information Registers */
 204 #define BCM43xx_CIR_BASE                0xf00
 205 #define BCM43xx_CIR_SBTPSFLAG           (BCM43xx_CIR_BASE + 0x18)
 206 #define BCM43xx_CIR_SBIMSTATE           (BCM43xx_CIR_BASE + 0x90)
 207 #define BCM43xx_CIR_SBINTVEC            (BCM43xx_CIR_BASE + 0x94)
 208 #define BCM43xx_CIR_SBTMSTATELOW        (BCM43xx_CIR_BASE + 0x98)
 209 #define BCM43xx_CIR_SBTMSTATEHIGH       (BCM43xx_CIR_BASE + 0x9c)
 210 #define BCM43xx_CIR_SBIMCONFIGLOW       (BCM43xx_CIR_BASE + 0xa8)
 211 #define BCM43xx_CIR_SB_ID_HI            (BCM43xx_CIR_BASE + 0xfc)
 212
 213 /* Mask to get the Backplane Flag Number from SBTPSFLAG. */
 214 #define BCM43xx_BACKPLANE_FLAG_NR_MASK  0x3f
 215
 216 /* SBIMCONFIGLOW values/masks. */
 217 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK         0x00000007
 218 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT        0
 219 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK         0x00000070
 220 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT        4
 221 #define BCM43xx_SBIMCONFIGLOW_CONNID_MASK               0x00ff0000
 222 #define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT              16
 223
 224 /* sbtmstatelow state flags */
 225 #define BCM43xx_SBTMSTATELOW_RESET              0x01
 226 #define BCM43xx_SBTMSTATELOW_REJECT             0x02
 227 #define BCM43xx_SBTMSTATELOW_CLOCK              0x10000
 228 #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK   0x20000
 229
 230 /* sbtmstatehigh state flags */
 231 #define BCM43xx_SBTMSTATEHIGH_SERROR            0x1
 232 #define BCM43xx_SBTMSTATEHIGH_BUSY              0x4
 233
 234 /* sbimstate flags */
 235 #define BCM43xx_SBIMSTATE_IB_ERROR              0x20000
 236 #define BCM43xx_SBIMSTATE_TIMEOUT               0x40000
 237
 238 /* PHYVersioning */
 239 #define BCM43xx_PHYTYPE_A               0x00
 240 #define BCM43xx_PHYTYPE_B               0x01
 241 #define BCM43xx_PHYTYPE_G               0x02
 242
 243 /* PHYRegisters */
 244 #define BCM43xx_PHY_ILT_A_CTRL          0x0072
 245 #define BCM43xx_PHY_ILT_A_DATA1         0x0073
 246 #define BCM43xx_PHY_ILT_A_DATA2         0x0074
 247 #define BCM43xx_PHY_G_LO_CONTROL        0x0810
 248 #define BCM43xx_PHY_ILT_G_CTRL          0x0472
 249 #define BCM43xx_PHY_ILT_G_DATA1         0x0473
 250 #define BCM43xx_PHY_ILT_G_DATA2         0x0474
 251 #define BCM43xx_PHY_A_PCTL              0x007B
 252 #define BCM43xx_PHY_G_PCTL              0x0029
 253 #define BCM43xx_PHY_A_CRS               0x0029
 254 #define BCM43xx_PHY_RADIO_BITFIELD      0x0401
 255 #define BCM43xx_PHY_G_CRS               0x0429
 256 #define BCM43xx_PHY_NRSSILT_CTRL        0x0803
 257 #define BCM43xx_PHY_NRSSILT_DATA        0x0804
 258
 259 /* RadioRegisters */
 260 #define BCM43xx_RADIOCTL_ID             0x01
 261
 262 /* StatusBitField */
 263 #define BCM43xx_SBF_MAC_ENABLED         0x00000001
 264 #define BCM43xx_SBF_2                   0x00000002 /*FIXME: fix name*/
 265 #define BCM43xx_SBF_CORE_READY          0x00000004
 266 #define BCM43xx_SBF_400                 0x00000400 /*FIXME: fix name*/
 267 #define BCM43xx_SBF_4000                0x00004000 /*FIXME: fix name*/
 268 #define BCM43xx_SBF_8000                0x00008000 /*FIXME: fix name*/
 269 #define BCM43xx_SBF_XFER_REG_BYTESWAP   0x00010000
 270 #define BCM43xx_SBF_MODE_NOTADHOC       0x00020000
 271 #define BCM43xx_SBF_MODE_AP             0x00040000
 272 #define BCM43xx_SBF_RADIOREG_LOCK       0x00080000
 273 #define BCM43xx_SBF_MODE_MONITOR        0x00400000
 274 #define BCM43xx_SBF_MODE_PROMISC        0x01000000
 275 #define BCM43xx_SBF_PS1                 0x02000000
 276 #define BCM43xx_SBF_PS2                 0x04000000
 277 #define BCM43xx_SBF_NO_SSID_BCAST       0x08000000
 278 #define BCM43xx_SBF_TIME_UPDATE         0x10000000
 279 #define BCM43xx_SBF_80000000            0x80000000 /*FIXME: fix name*/
 280
 281 /* MicrocodeFlagsBitfield (addr + lo-word values?)*/
 282 #define BCM43xx_UCODEFLAGS_OFFSET       0x005E
 283
 284 #define BCM43xx_UCODEFLAG_AUTODIV       0x0001
 285 #define BCM43xx_UCODEFLAG_UNKBGPHY      0x0002
 286 #define BCM43xx_UCODEFLAG_UNKBPHY       0x0004
 287 #define BCM43xx_UCODEFLAG_UNKGPHY       0x0020
 288 #define BCM43xx_UCODEFLAG_UNKPACTRL     0x0040
 289 #define BCM43xx_UCODEFLAG_JAPAN         0x0080
 290
 291 /* Generic-Interrupt reasons. */
 292 #define BCM43xx_IRQ_READY               (1 << 0)
 293 #define BCM43xx_IRQ_BEACON              (1 << 1)
 294 #define BCM43xx_IRQ_PS                  (1 << 2)
 295 #define BCM43xx_IRQ_REG124              (1 << 5)
 296 #define BCM43xx_IRQ_PMQ                 (1 << 6)
 297 #define BCM43xx_IRQ_PIO_WORKAROUND      (1 << 8)
 298 #define BCM43xx_IRQ_XMIT_ERROR          (1 << 11)
 299 #define BCM43xx_IRQ_RX                  (1 << 15)
 300 #define BCM43xx_IRQ_SCAN                (1 << 16)
 301 #define BCM43xx_IRQ_NOISE               (1 << 18)
 302 #define BCM43xx_IRQ_XMIT_STATUS         (1 << 29)
 303
 304 #define BCM43xx_IRQ_ALL                 0xffffffff
 305 #define BCM43xx_IRQ_INITIAL             (BCM43xx_IRQ_PS |               \
 306                                          BCM43xx_IRQ_REG124 |           \
 307                                          BCM43xx_IRQ_PMQ |              \
 308                                          BCM43xx_IRQ_XMIT_ERROR |       \
 309                                          BCM43xx_IRQ_RX |               \
 310                                          BCM43xx_IRQ_SCAN |             \
 311                                          BCM43xx_IRQ_NOISE |            \
 312                                          BCM43xx_IRQ_XMIT_STATUS)
 313
 314
 315 /* Initial default iw_mode */
 316 #define BCM43xx_INITIAL_IWMODE                  IW_MODE_INFRA
 317
 318 /* Bus type PCI. */
 319 #define BCM43xx_BUSTYPE_PCI     0
 320 /* Bus type Silicone Backplane Bus. */
 321 #define BCM43xx_BUSTYPE_SB      1
 322 /* Bus type PCMCIA. */
 323 #define BCM43xx_BUSTYPE_PCMCIA  2
 324
 325 /* Threshold values. */
 326 #define BCM43xx_MIN_RTS_THRESHOLD               1U
 327 #define BCM43xx_MAX_RTS_THRESHOLD               2304U
 328 #define BCM43xx_DEFAULT_RTS_THRESHOLD           BCM43xx_MAX_RTS_THRESHOLD
 329
 330 #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT       7
 331 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT        4
 332
 333 /* Max size of a security key */
 334 #define BCM43xx_SEC_KEYSIZE                     16
 335 /* Security algorithms. */
 336 enum {
 337         BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
 338         BCM43xx_SEC_ALGO_WEP,
 339         BCM43xx_SEC_ALGO_UNKNOWN,
 340         BCM43xx_SEC_ALGO_AES,
 341         BCM43xx_SEC_ALGO_WEP104,
 342         BCM43xx_SEC_ALGO_TKIP,
 343 };
 344
 345 #ifdef assert
 346 # undef assert
 347 #endif
 348 #ifdef CONFIG_BCM43XX_DEBUG
 349 #define assert(expr) \
 350         do {                                                                    \
 351                 if (unlikely(!(expr))) {                                        \
 352                 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n",   \
 353                         #expr, __FILE__, __LINE__, __FUNCTION__);               \
 354                 }                                                               \
 355         } while (0)
 356 #else
 357 #define assert(expr)    do { /* nothing */ } while (0)
 358 #endif
 359
 360 /* rate limited printk(). */
 361 #ifdef printkl
 362 # undef printkl
 363 #endif
 364 #define printkl(f, x...)  do { if (printk_ratelimit()) printk(f ,##x); } while (0)
 365 /* rate limited printk() for debugging */
 366 #ifdef dprintkl
 367 # undef dprintkl
 368 #endif
 369 #ifdef CONFIG_BCM43XX_DEBUG
 370 # define dprintkl               printkl
 371 #else
 372 # define dprintkl(f, x...)      do { /* nothing */ } while (0)
 373 #endif
 374
 375 /* Helper macro for if branches.
 376  * An if branch marked with this macro is only taken in DEBUG mode.
 377  * Example:
 378  *      if (DEBUG_ONLY(foo == bar)) {
 379  *              do something
 380  *      }
 381  *      In DEBUG mode, the branch will be taken if (foo == bar).
 382  *      In non-DEBUG mode, the branch will never be taken.
 383  */
 384 #ifdef DEBUG_ONLY
 385 # undef DEBUG_ONLY
 386 #endif
 387 #ifdef CONFIG_BCM43XX_DEBUG
 388 # define DEBUG_ONLY(x)  (x)
 389 #else
 390 # define DEBUG_ONLY(x)  0
 391 #endif
 392
 393 /* debugging printk() */
 394 #ifdef dprintk
 395 # undef dprintk
 396 #endif
 397 #ifdef CONFIG_BCM43XX_DEBUG
 398 # define dprintk(f, x...)  do { printk(f ,##x); } while (0)
 399 #else
 400 # define dprintk(f, x...)  do { /* nothing */ } while (0)
 401 #endif
 402
 403
 404 struct net_device;
 405 struct pci_dev;
 406 struct bcm43xx_dmaring;
 407 struct bcm43xx_pioqueue;
 408
 409 struct bcm43xx_initval {
 410         u16 offset;
 411         u16 size;
 412         u32 value;
 413 } __attribute__((__packed__));
 414
 415 /* Values for bcm430x_sprominfo.locale */
 416 enum {
 417         BCM43xx_LOCALE_WORLD = 0,
 418         BCM43xx_LOCALE_THAILAND,
 419         BCM43xx_LOCALE_ISRAEL,
 420         BCM43xx_LOCALE_JORDAN,
 421         BCM43xx_LOCALE_CHINA,
 422         BCM43xx_LOCALE_JAPAN,
 423         BCM43xx_LOCALE_USA_CANADA_ANZ,
 424         BCM43xx_LOCALE_EUROPE,
 425         BCM43xx_LOCALE_USA_LOW,
 426         BCM43xx_LOCALE_JAPAN_HIGH,
 427         BCM43xx_LOCALE_ALL,
 428         BCM43xx_LOCALE_NONE,
 429 };
 430
 431 #define BCM43xx_SPROM_SIZE      64 /* in 16-bit words. */
 432 struct bcm43xx_sprominfo {
 433         u16 boardflags2;
 434         u8 il0macaddr[6];
 435         u8 et0macaddr[6];
 436         u8 et1macaddr[6];
 437         u8 et0phyaddr:5;
 438         u8 et1phyaddr:5;
 439         u8 et0mdcport:1;
 440         u8 et1mdcport:1;
 441         u8 boardrev;
 442         u8 locale:4;
 443         u8 antennas_aphy:2;
 444         u8 antennas_bgphy:2;
 445         u16 pa0b0;
 446         u16 pa0b1;
 447         u16 pa0b2;
 448         u8 wl0gpio0;
 449         u8 wl0gpio1;
 450         u8 wl0gpio2;
 451         u8 wl0gpio3;
 452         u8 maxpower_aphy;
 453         u8 maxpower_bgphy;
 454         u16 pa1b0;
 455         u16 pa1b1;
 456         u16 pa1b2;
 457         u8 idle_tssi_tgt_aphy;
 458         u8 idle_tssi_tgt_bgphy;
 459         u16 boardflags;
 460         u16 antennagain_aphy;
 461         u16 antennagain_bgphy;
 462 };
 463
 464 /* Value pair to measure the LocalOscillator. */
 465 struct bcm43xx_lopair {
 466         s8 low;
 467         s8 high;
 468         u8 used:1;
 469 };
 470 #define BCM43xx_LO_COUNT        (14*4)
 471
 472 struct bcm43xx_phyinfo {
 473         /* Hardware Data */
 474         u8 version;
 475         u8 type;
 476         u8 rev;
 477         u16 antenna_diversity;
 478         u16 savedpctlreg;
 479         u16 minlowsig[2];
 480         u16 minlowsigpos[2];
 481         u8 connected:1,
 482            calibrated:1,
 483            is_locked:1, /* used in bcm43xx_phy_{un}lock() */
 484            dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */
 485         /* LO Measurement Data.
 486          * Use bcm43xx_get_lopair() to get a value.
 487          */
 488         struct bcm43xx_lopair *_lo_pairs;
 489
 490         /* TSSI to dBm table in use */
 491         const s8 *tssi2dbm;
 492         /* idle TSSI value */
 493         s8 idle_tssi;
 494         /* PHY lock for core.rev < 3
 495          * This lock is only used by bcm43xx_phy_{un}lock()
 496          */
 497         spinlock_t lock;
 498 };
 499
 500
 501 struct bcm43xx_radioinfo {
 502         u16 manufact;
 503         u16 version;
 504         u8 revision;
 505
 506         /* 0: baseband attenuation,
 507          * 1: radio attenuation,
 508          * 2: tx_CTL1
 509          * 3: tx_CTL2
 510          */
 511         u16 txpower[4];
 512         /* Desired TX power in dBm Q5.2 */
 513         u16 txpower_desired;
 514         /* Current Interference Mitigation mode */
 515         int interfmode;
 516         /* Stack of saved values from the Interference Mitigation code */
 517         u16 interfstack[20];
 518         /* Saved values from the NRSSI Slope calculation */
 519         s16 nrssi[2];
 520         s32 nrssislope;
 521         /* In memory nrssi lookup table. */
 522         s8 nrssi_lt[64];
 523
 524         /* current channel */
 525         u8 channel;
 526         u8 initial_channel;
 527
 528         u16 lofcal;
 529
 530         u16 initval;
 531
 532         u8 enabled:1;
 533         /* ACI (adjacent channel interference) flags. */
 534         u8 aci_enable:1,
 535            aci_wlan_automatic:1,
 536            aci_hw_rssi:1;
 537 };
 538
 539 /* Data structures for DMA transmission, per 80211 core. */
 540 struct bcm43xx_dma {
 541         struct bcm43xx_dmaring *tx_ring0;
 542         struct bcm43xx_dmaring *tx_ring1;
 543         struct bcm43xx_dmaring *tx_ring2;
 544         struct bcm43xx_dmaring *tx_ring3;
 545         struct bcm43xx_dmaring *rx_ring0;
 546         struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */
 547 };
 548
 549 /* Data structures for PIO transmission, per 80211 core. */
 550 struct bcm43xx_pio {
 551         struct bcm43xx_pioqueue *queue0;
 552         struct bcm43xx_pioqueue *queue1;
 553         struct bcm43xx_pioqueue *queue2;
 554         struct bcm43xx_pioqueue *queue3;
 555 };
 556
 557 #define BCM43xx_MAX_80211_CORES         2
 558
 559 #define BCM43xx_COREFLAG_AVAILABLE      (1 << 0)
 560 #define BCM43xx_COREFLAG_ENABLED        (1 << 1)
 561 #define BCM43xx_COREFLAG_INITIALIZED    (1 << 2)
 562
 563 #ifdef CONFIG_BCM947XX
 564 #define core_offset(bcm) (bcm)->current_core_offset
 565 #else
 566 #define core_offset(bcm) 0
 567 #endif
 568
 569 struct bcm43xx_coreinfo {
 570         /** Driver internal flags. See BCM43xx_COREFLAG_* */
 571         u32 flags;
 572         /** core_id ID number */
 573         u16 id;
 574         /** core_rev revision number */
 575         u8 rev;
 576         /** Index number for _switch_core() */
 577         u8 index;
 578         /* Pointer to the PHYinfo, which belongs to this core (if 80211 core) */
 579         struct bcm43xx_phyinfo *phy;
 580         /* Pointer to the RadioInfo, which belongs to this core (if 80211 core) */
 581         struct bcm43xx_radioinfo *radio;
 582         /* Pointer to the DMA rings, which belong to this core (if 80211 core) */
 583         struct bcm43xx_dma *dma;
 584         /* Pointer to the PIO queues, which belong to this core (if 80211 core) */
 585         struct bcm43xx_pio *pio;
 586 };
 587
 588 /* Context information for a noise calculation (Link Quality). */
 589 struct bcm43xx_noise_calculation {
 590         struct bcm43xx_coreinfo *core_at_start;
 591         u8 channel_at_start;
 592         u8 calculation_running:1;
 593         u8 nr_samples;
 594         s8 samples[8][4];
 595 };
 596
 597 struct bcm43xx_stats {
 598         u8 link_quality;
 599         /* Store the last TX/RX times here for updating the leds. */
 600         unsigned long last_tx;
 601         unsigned long last_rx;
 602 };
 603
 604 struct bcm43xx_key {
 605         u8 enabled:1;
 606         u8 algorithm;
 607 };
 608
 609 struct bcm43xx_private {
 610         struct bcm43xx_sysfs sysfs;
 611
 612         struct ieee80211_device *ieee;
 613         struct ieee80211softmac_device *softmac;
 614
 615         struct net_device *net_dev;
 616         struct pci_dev *pci_dev;
 617         unsigned int irq;
 618
 619         void __iomem *mmio_addr;
 620         unsigned int mmio_len;
 621
 622         /* Do not use the lock directly. Use the bcm43xx_lock* helper
 623          * functions, to be MMIO-safe. */
 624         spinlock_t _lock;
 625
 626         /* Driver status flags. */
 627         u32 initialized:1,              /* init_board() succeed */
 628             was_initialized:1,          /* for PCI suspend/resume. */
 629             shutting_down:1,            /* free_board() in progress */
 630             __using_pio:1,              /* Internal, use bcm43xx_using_pio(). */
 631             bad_frames_preempt:1,       /* Use "Bad Frames Preemption" (default off) */
 632             reg124_set_0x4:1,           /* Some variable to keep track of IRQ stuff. */
 633             powersaving:1,              /* TRUE if we are in PowerSaving mode. FALSE otherwise. */
 634             short_preamble:1,           /* TRUE, if short preamble is enabled. */
 635             firmware_norelease:1;       /* Do not release the firmware. Used on suspend. */
 636
 637         struct bcm43xx_stats stats;
 638
 639         /* Bus type we are connected to.
 640          * This is currently always BCM43xx_BUSTYPE_PCI
 641          */
 642         u8 bustype;
 643
 644         u16 board_vendor;
 645         u16 board_type;
 646         u16 board_revision;
 647
 648         u16 chip_id;
 649         u8 chip_rev;
 650
 651         struct bcm43xx_sprominfo sprom;
 652 #define BCM43xx_NR_LEDS         4
 653         struct bcm43xx_led leds[BCM43xx_NR_LEDS];
 654
 655         /* The currently active core. NULL if not initialized, yet. */
 656         struct bcm43xx_coreinfo *current_core;
 657 #ifdef CONFIG_BCM947XX
 658         /** current core memory offset */
 659         u32 current_core_offset;
 660 #endif
 661         struct bcm43xx_coreinfo *active_80211_core;
 662         /* coreinfo structs for all possible cores follow.
 663          * Note that a core might not exist.
 664          * So check the coreinfo flags before using it.
 665          */
 666         struct bcm43xx_coreinfo core_chipcommon;
 667         struct bcm43xx_coreinfo core_pci;
 668         struct bcm43xx_coreinfo core_v90;
 669         struct bcm43xx_coreinfo core_pcmcia;
 670         struct bcm43xx_coreinfo core_ethernet;
 671         struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ];
 672         /* Info about the PHY for each 80211 core. */
 673         struct bcm43xx_phyinfo phy[ BCM43xx_MAX_80211_CORES ];
 674         /* Info about the Radio for each 80211 core. */
 675         struct bcm43xx_radioinfo radio[ BCM43xx_MAX_80211_CORES ];
 676         /* DMA */
 677         struct bcm43xx_dma dma[ BCM43xx_MAX_80211_CORES ];
 678         /* PIO */
 679         struct bcm43xx_pio pio[ BCM43xx_MAX_80211_CORES ];
 680
 681         u32 chipcommon_capabilities;
 682
 683         /* Reason code of the last interrupt. */
 684         u32 irq_reason;
 685         u32 dma_reason[4];
 686         /* saved irq enable/disable state bitfield. */
 687         u32 irq_savedstate;
 688         /* Link Quality calculation context. */
 689         struct bcm43xx_noise_calculation noisecalc;
 690
 691         /* Threshold values. */
 692         //TODO: The RTS thr has to be _used_. Currently, it is only set via WX.
 693         u32 rts_threshold;
 694
 695         /* Interrupt Service Routine tasklet (bottom-half) */
 696         struct tasklet_struct isr_tasklet;
 697
 698         /* Periodic tasks */
 699         struct timer_list periodic_tasks;
 700         unsigned int periodic_state;
 701
 702         struct work_struct restart_work;
 703
 704         /* Informational stuff. */
 705         char nick[IW_ESSID_MAX_SIZE + 1];
 706
 707         /* encryption/decryption */
 708         u16 security_offset;
 709         struct bcm43xx_key key[54];
 710         u8 default_key_idx;
 711
 712         /* Firmware. */
 713         const struct firmware *ucode;
 714         const struct firmware *pcm;
 715         const struct firmware *initvals0;
 716         const struct firmware *initvals1;
 717
 718         /* Debugging stuff follows. */
 719 #ifdef CONFIG_BCM43XX_DEBUG
 720         struct bcm43xx_dfsentry *dfsentry;
 721 #endif
 722 };
 723
 724 /* bcm43xx_(un)lock() protect struct bcm43xx_private.
 725  * Note that _NO_ MMIO writes are allowed. If you want to
 726  * write to the device through MMIO in the critical section, use
 727  * the *_mmio lock functions.
 728  * MMIO read-access is allowed, though.
 729  */
 730 #define bcm43xx_lock(bcm, flags)        spin_lock_irqsave(&(bcm)->_lock, flags)
 731 #define bcm43xx_unlock(bcm, flags)      spin_unlock_irqrestore(&(bcm)->_lock, flags)
 732 /* bcm43xx_(un)lock_mmio() protect struct bcm43xx_private and MMIO.
 733  * MMIO write-access to the device is allowed.
 734  * All MMIO writes are flushed on unlock, so it is guaranteed to not
 735  * interfere with other threads writing MMIO registers.
 736  */
 737 #define bcm43xx_lock_mmio(bcm, flags)   bcm43xx_lock(bcm, flags)
 738 #define bcm43xx_unlock_mmio(bcm, flags) do { mmiowb(); bcm43xx_unlock(bcm, flags); } while (0)
 739
 740 static inline
 741 struct bcm43xx_private * bcm43xx_priv(struct net_device *dev)
 742 {
 743         return ieee80211softmac_priv(dev);
 744 }
 745
 746
 747 /* Helper function, which returns a boolean.
 748  * TRUE, if PIO is used; FALSE, if DMA is used.
 749  */
 750 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
 751 static inline
 752 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
 753 {
 754         return bcm->__using_pio;
 755 }
 756 #elif defined(CONFIG_BCM43XX_DMA)
 757 static inline
 758 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
 759 {
 760         return 0;
 761 }
 762 #elif defined(CONFIG_BCM43XX_PIO)
 763 static inline
 764 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
 765 {
 766         return 1;
 767 }
 768 #else
 769 # error "Using neither DMA nor PIO? Confused..."
 770 #endif
 771
 772
 773 static inline
 774 int bcm43xx_num_80211_cores(struct bcm43xx_private *bcm)
 775 {
 776         int i, cnt = 0;
 777
 778         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
 779                 if (bcm->core_80211[i].flags & BCM43xx_COREFLAG_AVAILABLE)
 780                         cnt++;
 781         }
 782
 783         return cnt;
 784 }
 785
 786 /* Are we running in init_board() context? */
 787 static inline
 788 int bcm43xx_is_initializing(struct bcm43xx_private *bcm)
 789 {
 790         if (bcm->initialized)
 791                 return 0;
 792         if (bcm->shutting_down)
 793                 return 0;
 794         return 1;
 795 }
 796
 797 static inline
 798 struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy,
 799                                            u16 radio_attenuation,
 800                                            u16 baseband_attenuation)
 801 {
 802         return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2));
 803 }
 804
 805
 806 static inline
 807 u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset)
 808 {
 809         return ioread16(bcm->mmio_addr + core_offset(bcm) + offset);
 810 }
 811
 812 static inline
 813 void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value)
 814 {
 815         iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset);
 816 }
 817
 818 static inline
 819 u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset)
 820 {
 821         return ioread32(bcm->mmio_addr + core_offset(bcm) + offset);
 822 }
 823
 824 static inline
 825 void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value)
 826 {
 827         iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset);
 828 }
 829
 830 static inline
 831 int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value)
 832 {
 833         return pci_read_config_word(bcm->pci_dev, offset, value);
 834 }
 835
 836 static inline
 837 int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value)
 838 {
 839         return pci_read_config_dword(bcm->pci_dev, offset, value);
 840 }
 841
 842 static inline
 843 int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value)
 844 {
 845         return pci_write_config_word(bcm->pci_dev, offset, value);
 846 }
 847
 848 static inline
 849 int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value)
 850 {
 851         return pci_write_config_dword(bcm->pci_dev, offset, value);
 852 }
 853
 854 /** Limit a value between two limits */
 855 #ifdef limit_value
 856 # undef limit_value
 857 #endif
 858 #define limit_value(value, min, max)  \
 859         ({                                              \
 860                 typeof(value) __value = (value);        \
 861                 typeof(value) __min = (min);            \
 862                 typeof(value) __max = (max);            \
 863                 if (__value < __min)                    \
 864                         __value = __min;                \
 865                 else if (__value > __max)               \
 866                         __value = __max;                \
 867                 __value;                                \
 868         })
 869
 870 /** Helpers to print MAC addresses. */
 871 #define BCM43xx_MACFMT          "%02x:%02x:%02x:%02x:%02x:%02x"
 872 #define BCM43xx_MACARG(x)       ((u8*)(x))[0], ((u8*)(x))[1], \
 873                                 ((u8*)(x))[2], ((u8*)(x))[3], \
 874                                 ((u8*)(x))[4], ((u8*)(x))[5]
 875
 876 #endif /* BCM43xx_H_ */