4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <linux/seq_file.h>
35 #include "intel_drv.h"
37 /* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41 #define IMAGE_MAX_WIDTH 2048
42 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43 /* on 830 and 845 these large limits result in the card hanging */
44 #define IMAGE_MAX_WIDTH_LEGACY 1024
45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
47 /* overlay register definitions */
49 #define OCMD_TILED_SURFACE (0x1<<19)
50 #define OCMD_MIRROR_MASK (0x3<<17)
51 #define OCMD_MIRROR_MODE (0x3<<17)
52 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53 #define OCMD_MIRROR_VERTICAL (0x2<<17)
54 #define OCMD_MIRROR_BOTH (0x3<<17)
55 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_422_PACKED (0x8<<10)
64 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_420_PLANAR (0xc<<10)
66 #define OCMD_YUV_422_PLANAR (0xd<<10)
67 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
70 #define OCMD_BUF_TYPE_MASK (0x1<<5)
71 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
72 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
73 #define OCMD_TEST_MODE (0x1<<4)
74 #define OCMD_BUFFER_SELECT (0x3<<2)
75 #define OCMD_BUFFER0 (0x0<<2)
76 #define OCMD_BUFFER1 (0x1<<2)
77 #define OCMD_FIELD_SELECT (0x1<<2)
78 #define OCMD_FIELD0 (0x0<<1)
79 #define OCMD_FIELD1 (0x1<<1)
80 #define OCMD_ENABLE (0x1<<0)
82 /* OCONFIG register */
83 #define OCONF_PIPE_MASK (0x1<<18)
84 #define OCONF_PIPE_A (0x0<<18)
85 #define OCONF_PIPE_B (0x1<<18)
86 #define OCONF_GAMMA2_ENABLE (0x1<<16)
87 #define OCONF_CSC_MODE_BT601 (0x0<<5)
88 #define OCONF_CSC_MODE_BT709 (0x1<<5)
89 #define OCONF_CSC_BYPASS (0x1<<4)
90 #define OCONF_CC_OUT_8BIT (0x1<<3)
91 #define OCONF_TEST_MODE (0x1<<2)
92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
93 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
95 /* DCLRKM (dst-key) register */
96 #define DST_KEY_ENABLE (0x1<<31)
97 #define CLK_RGB24_MASK 0x0
98 #define CLK_RGB16_MASK 0x070307
99 #define CLK_RGB15_MASK 0x070707
100 #define CLK_RGB8I_MASK 0xffffff
102 #define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104 #define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
107 /* overlay flip addr flag */
108 #define OFC_UPDATE 0x1
110 /* polyphase filter coefficients */
111 #define N_HORIZ_Y_TAPS 5
112 #define N_VERT_Y_TAPS 3
113 #define N_HORIZ_UV_TAPS 3
114 #define N_VERT_UV_TAPS 3
118 /* memory bufferd overlay registers */
119 struct overlay_registers
{
147 u32 RESERVED1
; /* 0x6C */
160 u32 FASTHSCALE
; /* 0xA0 */
161 u32 UVSCALEV
; /* 0xA4 */
162 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
164 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
165 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
166 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
167 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
168 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
169 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
170 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
173 static struct overlay_registers
*
174 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
,
177 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
178 struct overlay_registers
*regs
;
180 /* no recursive mappings */
181 BUG_ON(overlay
->virt_addr
);
183 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
)) {
184 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
186 regs
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
187 overlay
->reg_bo
->gtt_offset
,
191 DRM_ERROR("failed to map overlay regs in GTT\n");
196 return overlay
->virt_addr
= regs
;
199 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
202 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
203 io_mapping_unmap_atomic(overlay
->virt_addr
, slot
);
205 overlay
->virt_addr
= NULL
;
210 static struct overlay_registers
*
211 intel_overlay_map_regs(struct intel_overlay
*overlay
)
213 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
214 struct overlay_registers
*regs
;
216 /* no recursive mappings */
217 BUG_ON(overlay
->virt_addr
);
219 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
)) {
220 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
222 regs
= io_mapping_map_wc(dev_priv
->mm
.gtt_mapping
,
223 overlay
->reg_bo
->gtt_offset
);
226 DRM_ERROR("failed to map overlay regs in GTT\n");
231 return overlay
->virt_addr
= regs
;
234 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
)
236 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
237 io_mapping_unmap(overlay
->virt_addr
);
239 overlay
->virt_addr
= NULL
;
244 /* overlay needs to be disable in OCMD reg */
245 static int intel_overlay_on(struct intel_overlay
*overlay
)
247 struct drm_device
*dev
= overlay
->dev
;
249 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
251 BUG_ON(overlay
->active
);
254 overlay
->hw_wedged
= NEEDS_WAIT_FOR_FLIP
;
257 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
258 OUT_RING(overlay
->flip_addr
| OFC_UPDATE
);
259 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
263 overlay
->last_flip_req
=
264 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
265 if (overlay
->last_flip_req
== 0)
268 ret
= i915_do_wait_request(dev
,
269 overlay
->last_flip_req
, true,
270 &dev_priv
->render_ring
);
274 overlay
->hw_wedged
= 0;
275 overlay
->last_flip_req
= 0;
279 /* overlay needs to be enabled in OCMD reg */
280 static void intel_overlay_continue(struct intel_overlay
*overlay
,
281 bool load_polyphase_filter
)
283 struct drm_device
*dev
= overlay
->dev
;
284 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
285 u32 flip_addr
= overlay
->flip_addr
;
288 BUG_ON(!overlay
->active
);
290 if (load_polyphase_filter
)
291 flip_addr
|= OFC_UPDATE
;
293 /* check for underruns */
294 tmp
= I915_READ(DOVSTA
);
296 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
299 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
303 overlay
->last_flip_req
=
304 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
307 static int intel_overlay_wait_flip(struct intel_overlay
*overlay
)
309 struct drm_device
*dev
= overlay
->dev
;
310 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
314 if (overlay
->last_flip_req
!= 0) {
315 ret
= i915_do_wait_request(dev
,
316 overlay
->last_flip_req
, true,
317 &dev_priv
->render_ring
);
319 overlay
->last_flip_req
= 0;
321 tmp
= I915_READ(ISR
);
323 if (!(tmp
& I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
))
328 /* synchronous slowpath */
329 overlay
->hw_wedged
= RELEASE_OLD_VID
;
332 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
336 overlay
->last_flip_req
=
337 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
338 if (overlay
->last_flip_req
== 0)
341 ret
= i915_do_wait_request(dev
,
342 overlay
->last_flip_req
, true,
343 &dev_priv
->render_ring
);
347 overlay
->hw_wedged
= 0;
348 overlay
->last_flip_req
= 0;
352 /* overlay needs to be disabled in OCMD reg */
353 static int intel_overlay_off(struct intel_overlay
*overlay
)
355 u32 flip_addr
= overlay
->flip_addr
;
356 struct drm_device
*dev
= overlay
->dev
;
357 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
360 BUG_ON(!overlay
->active
);
362 /* According to intel docs the overlay hw may hang (when switching
363 * off) without loading the filter coeffs. It is however unclear whether
364 * this applies to the disabling of the overlay or to the switching off
365 * of the hw. Do it in both cases */
366 flip_addr
|= OFC_UPDATE
;
368 /* wait for overlay to go idle */
369 overlay
->hw_wedged
= SWITCH_OFF_STAGE_1
;
372 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
374 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
378 overlay
->last_flip_req
=
379 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
380 if (overlay
->last_flip_req
== 0)
383 ret
= i915_do_wait_request(dev
,
384 overlay
->last_flip_req
, true,
385 &dev_priv
->render_ring
);
389 /* turn overlay off */
390 overlay
->hw_wedged
= SWITCH_OFF_STAGE_2
;
393 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
395 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
399 overlay
->last_flip_req
=
400 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
401 if (overlay
->last_flip_req
== 0)
404 ret
= i915_do_wait_request(dev
,
405 overlay
->last_flip_req
, true,
406 &dev_priv
->render_ring
);
410 overlay
->hw_wedged
= 0;
411 overlay
->last_flip_req
= 0;
415 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
417 struct drm_gem_object
*obj
;
419 /* never have the overlay hw on without showing a frame */
420 BUG_ON(!overlay
->vid_bo
);
421 obj
= &overlay
->vid_bo
->base
;
423 i915_gem_object_unpin(obj
);
424 drm_gem_object_unreference(obj
);
425 overlay
->vid_bo
= NULL
;
427 overlay
->crtc
->overlay
= NULL
;
428 overlay
->crtc
= NULL
;
432 /* recover from an interruption due to a signal
433 * We have to be careful not to repeat work forever an make forward progess. */
434 int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
,
437 struct drm_device
*dev
= overlay
->dev
;
438 struct drm_gem_object
*obj
;
439 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
443 if (overlay
->hw_wedged
== HW_WEDGED
)
446 if (overlay
->last_flip_req
== 0) {
447 overlay
->last_flip_req
=
448 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
449 if (overlay
->last_flip_req
== 0)
453 ret
= i915_do_wait_request(dev
, overlay
->last_flip_req
,
454 interruptible
, &dev_priv
->render_ring
);
458 switch (overlay
->hw_wedged
) {
459 case RELEASE_OLD_VID
:
460 obj
= &overlay
->old_vid_bo
->base
;
461 i915_gem_object_unpin(obj
);
462 drm_gem_object_unreference(obj
);
463 overlay
->old_vid_bo
= NULL
;
465 case SWITCH_OFF_STAGE_1
:
466 flip_addr
= overlay
->flip_addr
;
467 flip_addr
|= OFC_UPDATE
;
469 overlay
->hw_wedged
= SWITCH_OFF_STAGE_2
;
472 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
474 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
478 overlay
->last_flip_req
=
479 i915_add_request(dev
, NULL
,
480 &dev_priv
->render_ring
);
481 if (overlay
->last_flip_req
== 0)
484 ret
= i915_do_wait_request(dev
, overlay
->last_flip_req
,
486 &dev_priv
->render_ring
);
490 case SWITCH_OFF_STAGE_2
:
491 intel_overlay_off_tail(overlay
);
494 BUG_ON(overlay
->hw_wedged
!= NEEDS_WAIT_FOR_FLIP
);
497 overlay
->hw_wedged
= 0;
498 overlay
->last_flip_req
= 0;
502 /* Wait for pending overlay flip and release old frame.
503 * Needs to be called before the overlay register are changed
504 * via intel_overlay_(un)map_regs
506 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
509 struct drm_gem_object
*obj
;
511 /* only wait if there is actually an old frame to release to
512 * guarantee forward progress */
513 if (!overlay
->old_vid_bo
)
516 ret
= intel_overlay_wait_flip(overlay
);
520 obj
= &overlay
->old_vid_bo
->base
;
521 i915_gem_object_unpin(obj
);
522 drm_gem_object_unreference(obj
);
523 overlay
->old_vid_bo
= NULL
;
528 struct put_image_params
{
545 static int packed_depth_bytes(u32 format
)
547 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
548 case I915_OVERLAY_YUV422
:
550 case I915_OVERLAY_YUV411
:
551 /* return 6; not implemented */
557 static int packed_width_bytes(u32 format
, short width
)
559 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
560 case I915_OVERLAY_YUV422
:
567 static int uv_hsubsampling(u32 format
)
569 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
570 case I915_OVERLAY_YUV422
:
571 case I915_OVERLAY_YUV420
:
573 case I915_OVERLAY_YUV411
:
574 case I915_OVERLAY_YUV410
:
581 static int uv_vsubsampling(u32 format
)
583 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
584 case I915_OVERLAY_YUV420
:
585 case I915_OVERLAY_YUV410
:
587 case I915_OVERLAY_YUV422
:
588 case I915_OVERLAY_YUV411
:
595 static u32
calc_swidthsw(struct drm_device
*dev
, u32 offset
, u32 width
)
597 u32 mask
, shift
, ret
;
605 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
612 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
613 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
614 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
615 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
616 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
617 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
618 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
619 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
620 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
621 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
622 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
623 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
624 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
625 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
626 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
627 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
628 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
629 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
632 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
633 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
634 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
635 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
636 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
637 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
638 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
639 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
640 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
641 0x3000, 0x0800, 0x3000
644 static void update_polyphase_filter(struct overlay_registers
*regs
)
646 memcpy(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
647 memcpy(regs
->UV_HCOEFS
, uv_static_hcoeffs
, sizeof(uv_static_hcoeffs
));
650 static bool update_scaling_factors(struct intel_overlay
*overlay
,
651 struct overlay_registers
*regs
,
652 struct put_image_params
*params
)
654 /* fixed point with a 12 bit shift */
655 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
657 #define FRACT_MASK 0xfff
658 bool scale_changed
= false;
659 int uv_hscale
= uv_hsubsampling(params
->format
);
660 int uv_vscale
= uv_vsubsampling(params
->format
);
662 if (params
->dst_w
> 1)
663 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
666 xscale
= 1 << FP_SHIFT
;
668 if (params
->dst_h
> 1)
669 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
672 yscale
= 1 << FP_SHIFT
;
674 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
675 xscale_UV
= xscale
/uv_hscale
;
676 yscale_UV
= yscale
/uv_vscale
;
677 /* make the Y scale to UV scale ratio an exact multiply */
678 xscale
= xscale_UV
* uv_hscale
;
679 yscale
= yscale_UV
* uv_vscale
;
685 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
686 scale_changed
= true;
687 overlay
->old_xscale
= xscale
;
688 overlay
->old_yscale
= yscale
;
690 regs
->YRGBSCALE
= (((yscale
& FRACT_MASK
) << 20) |
691 ((xscale
>> FP_SHIFT
) << 16) |
692 ((xscale
& FRACT_MASK
) << 3));
694 regs
->UVSCALE
= (((yscale_UV
& FRACT_MASK
) << 20) |
695 ((xscale_UV
>> FP_SHIFT
) << 16) |
696 ((xscale_UV
& FRACT_MASK
) << 3));
698 regs
->UVSCALEV
= ((((yscale
>> FP_SHIFT
) << 16) |
699 ((yscale_UV
>> FP_SHIFT
) << 0)));
702 update_polyphase_filter(regs
);
704 return scale_changed
;
707 static void update_colorkey(struct intel_overlay
*overlay
,
708 struct overlay_registers
*regs
)
710 u32 key
= overlay
->color_key
;
712 switch (overlay
->crtc
->base
.fb
->bits_per_pixel
) {
715 regs
->DCLRKM
= CLK_RGB8I_MASK
| DST_KEY_ENABLE
;
719 if (overlay
->crtc
->base
.fb
->depth
== 15) {
720 regs
->DCLRKV
= RGB15_TO_COLORKEY(key
);
721 regs
->DCLRKM
= CLK_RGB15_MASK
| DST_KEY_ENABLE
;
723 regs
->DCLRKV
= RGB16_TO_COLORKEY(key
);
724 regs
->DCLRKM
= CLK_RGB16_MASK
| DST_KEY_ENABLE
;
731 regs
->DCLRKM
= CLK_RGB24_MASK
| DST_KEY_ENABLE
;
736 static u32
overlay_cmd_reg(struct put_image_params
*params
)
738 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
740 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
741 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
742 case I915_OVERLAY_YUV422
:
743 cmd
|= OCMD_YUV_422_PLANAR
;
745 case I915_OVERLAY_YUV420
:
746 cmd
|= OCMD_YUV_420_PLANAR
;
748 case I915_OVERLAY_YUV411
:
749 case I915_OVERLAY_YUV410
:
750 cmd
|= OCMD_YUV_410_PLANAR
;
753 } else { /* YUV packed */
754 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
755 case I915_OVERLAY_YUV422
:
756 cmd
|= OCMD_YUV_422_PACKED
;
758 case I915_OVERLAY_YUV411
:
759 cmd
|= OCMD_YUV_411_PACKED
;
763 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
764 case I915_OVERLAY_NO_SWAP
:
766 case I915_OVERLAY_UV_SWAP
:
769 case I915_OVERLAY_Y_SWAP
:
772 case I915_OVERLAY_Y_AND_UV_SWAP
:
773 cmd
|= OCMD_Y_AND_UV_SWAP
;
781 int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
782 struct drm_gem_object
*new_bo
,
783 struct put_image_params
*params
)
786 struct overlay_registers
*regs
;
787 bool scale_changed
= false;
788 struct drm_i915_gem_object
*bo_priv
= to_intel_bo(new_bo
);
789 struct drm_device
*dev
= overlay
->dev
;
791 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
792 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
795 ret
= intel_overlay_release_old_vid(overlay
);
799 ret
= i915_gem_object_pin(new_bo
, PAGE_SIZE
);
803 ret
= i915_gem_object_set_to_gtt_domain(new_bo
, 0);
807 if (!overlay
->active
) {
808 regs
= intel_overlay_map_regs(overlay
);
813 regs
->OCONFIG
= OCONF_CC_OUT_8BIT
;
814 if (IS_I965GM(overlay
->dev
))
815 regs
->OCONFIG
|= OCONF_CSC_MODE_BT709
;
816 regs
->OCONFIG
|= overlay
->crtc
->pipe
== 0 ?
817 OCONF_PIPE_A
: OCONF_PIPE_B
;
818 intel_overlay_unmap_regs(overlay
);
820 ret
= intel_overlay_on(overlay
);
825 regs
= intel_overlay_map_regs(overlay
);
831 regs
->DWINPOS
= (params
->dst_y
<< 16) | params
->dst_x
;
832 regs
->DWINSZ
= (params
->dst_h
<< 16) | params
->dst_w
;
834 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
835 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
837 tmp_width
= params
->src_w
;
839 regs
->SWIDTH
= params
->src_w
;
840 regs
->SWIDTHSW
= calc_swidthsw(overlay
->dev
,
841 params
->offset_Y
, tmp_width
);
842 regs
->SHEIGHT
= params
->src_h
;
843 regs
->OBUF_0Y
= bo_priv
->gtt_offset
+ params
-> offset_Y
;
844 regs
->OSTRIDE
= params
->stride_Y
;
846 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
847 int uv_hscale
= uv_hsubsampling(params
->format
);
848 int uv_vscale
= uv_vsubsampling(params
->format
);
850 regs
->SWIDTH
|= (params
->src_w
/uv_hscale
) << 16;
851 tmp_U
= calc_swidthsw(overlay
->dev
, params
->offset_U
,
852 params
->src_w
/uv_hscale
);
853 tmp_V
= calc_swidthsw(overlay
->dev
, params
->offset_V
,
854 params
->src_w
/uv_hscale
);
855 regs
->SWIDTHSW
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
856 regs
->SHEIGHT
|= (params
->src_h
/uv_vscale
) << 16;
857 regs
->OBUF_0U
= bo_priv
->gtt_offset
+ params
->offset_U
;
858 regs
->OBUF_0V
= bo_priv
->gtt_offset
+ params
->offset_V
;
859 regs
->OSTRIDE
|= params
->stride_UV
<< 16;
862 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
864 update_colorkey(overlay
, regs
);
866 regs
->OCMD
= overlay_cmd_reg(params
);
868 intel_overlay_unmap_regs(overlay
);
870 intel_overlay_continue(overlay
, scale_changed
);
872 overlay
->old_vid_bo
= overlay
->vid_bo
;
873 overlay
->vid_bo
= to_intel_bo(new_bo
);
878 i915_gem_object_unpin(new_bo
);
882 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
885 struct overlay_registers
*regs
;
886 struct drm_device
*dev
= overlay
->dev
;
888 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
889 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
891 if (overlay
->hw_wedged
) {
892 ret
= intel_overlay_recover_from_interrupt(overlay
, 1);
897 if (!overlay
->active
)
900 ret
= intel_overlay_release_old_vid(overlay
);
904 regs
= intel_overlay_map_regs(overlay
);
906 intel_overlay_unmap_regs(overlay
);
908 ret
= intel_overlay_off(overlay
);
912 intel_overlay_off_tail(overlay
);
917 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
918 struct intel_crtc
*crtc
)
920 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
922 int pipeconf_reg
= (crtc
->pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
924 if (!crtc
->base
.enabled
|| crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
)
927 pipeconf
= I915_READ(pipeconf_reg
);
929 /* can't use the overlay with double wide pipe */
930 if (!IS_I965G(overlay
->dev
) && pipeconf
& PIPEACONF_DOUBLE_WIDE
)
936 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
938 struct drm_device
*dev
= overlay
->dev
;
939 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
941 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
943 /* XXX: This is not the same logic as in the xorg driver, but more in
944 * line with the intel documentation for the i965 */
945 if (!IS_I965G(dev
) && (pfit_control
& VERT_AUTO_SCALE
)) {
946 ratio
= I915_READ(PFIT_AUTO_RATIOS
) >> PFIT_VERT_SCALE_SHIFT
;
947 } else { /* on i965 use the PGM reg to read out the autoscaler values */
948 ratio
= I915_READ(PFIT_PGM_RATIOS
);
950 ratio
>>= PFIT_VERT_SCALE_SHIFT_965
;
952 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
955 overlay
->pfit_vscale_ratio
= ratio
;
958 static int check_overlay_dst(struct intel_overlay
*overlay
,
959 struct drm_intel_overlay_put_image
*rec
)
961 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
963 if (rec
->dst_x
< mode
->crtc_hdisplay
&&
964 rec
->dst_x
+ rec
->dst_width
<= mode
->crtc_hdisplay
&&
965 rec
->dst_y
< mode
->crtc_vdisplay
&&
966 rec
->dst_y
+ rec
->dst_height
<= mode
->crtc_vdisplay
)
972 static int check_overlay_scaling(struct put_image_params
*rec
)
976 /* downscaling limit is 8.0 */
977 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
980 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
987 static int check_overlay_src(struct drm_device
*dev
,
988 struct drm_intel_overlay_put_image
*rec
,
989 struct drm_gem_object
*new_bo
)
993 int uv_hscale
= uv_hsubsampling(rec
->flags
);
994 int uv_vscale
= uv_vsubsampling(rec
->flags
);
997 /* check src dimensions */
998 if (IS_845G(dev
) || IS_I830(dev
)) {
999 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
1000 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
1003 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
1004 rec
->src_width
> IMAGE_MAX_WIDTH
)
1007 /* better safe than sorry, use 4 as the maximal subsampling ratio */
1008 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
1009 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
1012 /* check alignment constraints */
1013 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1014 case I915_OVERLAY_RGB
:
1015 /* not implemented */
1017 case I915_OVERLAY_YUV_PACKED
:
1018 depth
= packed_depth_bytes(rec
->flags
);
1023 /* ignore UV planes */
1027 /* check pixel alignment */
1028 if (rec
->offset_Y
% depth
)
1031 case I915_OVERLAY_YUV_PLANAR
:
1032 if (uv_vscale
< 0 || uv_hscale
< 0)
1034 /* no offset restrictions for planar formats */
1040 if (rec
->src_width
% uv_hscale
)
1043 /* stride checking */
1044 if (IS_I830(dev
) || IS_845G(dev
))
1049 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1051 if (IS_I965G(dev
) && rec
->stride_Y
< 512)
1054 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1056 if (rec
->stride_Y
> tmp
*1024 || rec
->stride_UV
> 2*1024)
1059 /* check buffer dimensions */
1060 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1061 case I915_OVERLAY_RGB
:
1062 case I915_OVERLAY_YUV_PACKED
:
1063 /* always 4 Y values per depth pixels */
1064 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1067 tmp
= rec
->stride_Y
*rec
->src_height
;
1068 if (rec
->offset_Y
+ tmp
> new_bo
->size
)
1072 case I915_OVERLAY_YUV_PLANAR
:
1073 if (rec
->src_width
> rec
->stride_Y
)
1075 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1078 tmp
= rec
->stride_Y
*rec
->src_height
;
1079 if (rec
->offset_Y
+ tmp
> new_bo
->size
)
1081 tmp
= rec
->stride_UV
*rec
->src_height
;
1083 if (rec
->offset_U
+ tmp
> new_bo
->size
||
1084 rec
->offset_V
+ tmp
> new_bo
->size
)
1092 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1093 struct drm_file
*file_priv
)
1095 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1096 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1097 struct intel_overlay
*overlay
;
1098 struct drm_mode_object
*drmmode_obj
;
1099 struct intel_crtc
*crtc
;
1100 struct drm_gem_object
*new_bo
;
1101 struct put_image_params
*params
;
1105 DRM_ERROR("called with no initialization\n");
1109 overlay
= dev_priv
->overlay
;
1111 DRM_DEBUG("userspace bug: no overlay\n");
1115 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1116 mutex_lock(&dev
->mode_config
.mutex
);
1117 mutex_lock(&dev
->struct_mutex
);
1119 ret
= intel_overlay_switch_off(overlay
);
1121 mutex_unlock(&dev
->struct_mutex
);
1122 mutex_unlock(&dev
->mode_config
.mutex
);
1127 params
= kmalloc(sizeof(struct put_image_params
), GFP_KERNEL
);
1131 drmmode_obj
= drm_mode_object_find(dev
, put_image_rec
->crtc_id
,
1132 DRM_MODE_OBJECT_CRTC
);
1137 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
1139 new_bo
= drm_gem_object_lookup(dev
, file_priv
,
1140 put_image_rec
->bo_handle
);
1146 mutex_lock(&dev
->mode_config
.mutex
);
1147 mutex_lock(&dev
->struct_mutex
);
1149 if (overlay
->hw_wedged
) {
1150 ret
= intel_overlay_recover_from_interrupt(overlay
, 1);
1155 if (overlay
->crtc
!= crtc
) {
1156 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1157 ret
= intel_overlay_switch_off(overlay
);
1161 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1165 overlay
->crtc
= crtc
;
1166 crtc
->overlay
= overlay
;
1168 if (intel_panel_fitter_pipe(dev
) == crtc
->pipe
1169 /* and line to wide, i.e. one-line-mode */
1170 && mode
->hdisplay
> 1024) {
1171 overlay
->pfit_active
= 1;
1172 update_pfit_vscale_ratio(overlay
);
1174 overlay
->pfit_active
= 0;
1177 ret
= check_overlay_dst(overlay
, put_image_rec
);
1181 if (overlay
->pfit_active
) {
1182 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1183 overlay
->pfit_vscale_ratio
);
1184 /* shifting right rounds downwards, so add 1 */
1185 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1186 overlay
->pfit_vscale_ratio
) + 1;
1188 params
->dst_y
= put_image_rec
->dst_y
;
1189 params
->dst_h
= put_image_rec
->dst_height
;
1191 params
->dst_x
= put_image_rec
->dst_x
;
1192 params
->dst_w
= put_image_rec
->dst_width
;
1194 params
->src_w
= put_image_rec
->src_width
;
1195 params
->src_h
= put_image_rec
->src_height
;
1196 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1197 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1198 if (params
->src_scan_h
> params
->src_h
||
1199 params
->src_scan_w
> params
->src_w
) {
1204 ret
= check_overlay_src(dev
, put_image_rec
, new_bo
);
1207 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1208 params
->stride_Y
= put_image_rec
->stride_Y
;
1209 params
->stride_UV
= put_image_rec
->stride_UV
;
1210 params
->offset_Y
= put_image_rec
->offset_Y
;
1211 params
->offset_U
= put_image_rec
->offset_U
;
1212 params
->offset_V
= put_image_rec
->offset_V
;
1214 /* Check scaling after src size to prevent a divide-by-zero. */
1215 ret
= check_overlay_scaling(params
);
1219 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1223 mutex_unlock(&dev
->struct_mutex
);
1224 mutex_unlock(&dev
->mode_config
.mutex
);
1231 mutex_unlock(&dev
->struct_mutex
);
1232 mutex_unlock(&dev
->mode_config
.mutex
);
1233 drm_gem_object_unreference_unlocked(new_bo
);
1240 static void update_reg_attrs(struct intel_overlay
*overlay
,
1241 struct overlay_registers
*regs
)
1243 regs
->OCLRC0
= (overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff);
1244 regs
->OCLRC1
= overlay
->saturation
;
1247 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1251 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1254 for (i
= 0; i
< 3; i
++) {
1255 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1262 static bool check_gamma5_errata(u32 gamma5
)
1266 for (i
= 0; i
< 3; i
++) {
1267 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1274 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1276 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1277 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1278 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1279 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1280 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1281 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1282 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1285 if (!check_gamma5_errata(attrs
->gamma5
))
1291 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1292 struct drm_file
*file_priv
)
1294 struct drm_intel_overlay_attrs
*attrs
= data
;
1295 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1296 struct intel_overlay
*overlay
;
1297 struct overlay_registers
*regs
;
1301 DRM_ERROR("called with no initialization\n");
1305 overlay
= dev_priv
->overlay
;
1307 DRM_DEBUG("userspace bug: no overlay\n");
1311 mutex_lock(&dev
->mode_config
.mutex
);
1312 mutex_lock(&dev
->struct_mutex
);
1315 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1316 attrs
->color_key
= overlay
->color_key
;
1317 attrs
->brightness
= overlay
->brightness
;
1318 attrs
->contrast
= overlay
->contrast
;
1319 attrs
->saturation
= overlay
->saturation
;
1322 attrs
->gamma0
= I915_READ(OGAMC0
);
1323 attrs
->gamma1
= I915_READ(OGAMC1
);
1324 attrs
->gamma2
= I915_READ(OGAMC2
);
1325 attrs
->gamma3
= I915_READ(OGAMC3
);
1326 attrs
->gamma4
= I915_READ(OGAMC4
);
1327 attrs
->gamma5
= I915_READ(OGAMC5
);
1330 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1332 if (attrs
->contrast
> 255)
1334 if (attrs
->saturation
> 1023)
1337 overlay
->color_key
= attrs
->color_key
;
1338 overlay
->brightness
= attrs
->brightness
;
1339 overlay
->contrast
= attrs
->contrast
;
1340 overlay
->saturation
= attrs
->saturation
;
1342 regs
= intel_overlay_map_regs(overlay
);
1348 update_reg_attrs(overlay
, regs
);
1350 intel_overlay_unmap_regs(overlay
);
1352 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1356 if (overlay
->active
) {
1361 ret
= check_gamma(attrs
);
1365 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1366 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1367 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1368 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1369 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1370 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1376 mutex_unlock(&dev
->struct_mutex
);
1377 mutex_unlock(&dev
->mode_config
.mutex
);
1382 void intel_setup_overlay(struct drm_device
*dev
)
1384 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1385 struct intel_overlay
*overlay
;
1386 struct drm_gem_object
*reg_bo
;
1387 struct overlay_registers
*regs
;
1390 if (!HAS_OVERLAY(dev
))
1393 overlay
= kzalloc(sizeof(struct intel_overlay
), GFP_KERNEL
);
1398 reg_bo
= i915_gem_alloc_object(dev
, PAGE_SIZE
);
1401 overlay
->reg_bo
= to_intel_bo(reg_bo
);
1403 if (OVERLAY_NEEDS_PHYSICAL(dev
)) {
1404 ret
= i915_gem_attach_phys_object(dev
, reg_bo
,
1405 I915_GEM_PHYS_OVERLAY_REGS
,
1408 DRM_ERROR("failed to attach phys overlay regs\n");
1411 overlay
->flip_addr
= overlay
->reg_bo
->phys_obj
->handle
->busaddr
;
1413 ret
= i915_gem_object_pin(reg_bo
, PAGE_SIZE
);
1415 DRM_ERROR("failed to pin overlay register bo\n");
1418 overlay
->flip_addr
= overlay
->reg_bo
->gtt_offset
;
1420 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1422 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1427 /* init all values */
1428 overlay
->color_key
= 0x0101fe;
1429 overlay
->brightness
= -19;
1430 overlay
->contrast
= 75;
1431 overlay
->saturation
= 146;
1433 regs
= intel_overlay_map_regs(overlay
);
1437 memset(regs
, 0, sizeof(struct overlay_registers
));
1438 update_polyphase_filter(regs
);
1440 update_reg_attrs(overlay
, regs
);
1442 intel_overlay_unmap_regs(overlay
);
1444 dev_priv
->overlay
= overlay
;
1445 DRM_INFO("initialized overlay support\n");
1449 i915_gem_object_unpin(reg_bo
);
1451 drm_gem_object_unreference(reg_bo
);
1457 void intel_cleanup_overlay(struct drm_device
*dev
)
1459 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1461 if (!dev_priv
->overlay
)
1464 /* The bo's should be free'd by the generic code already.
1465 * Furthermore modesetting teardown happens beforehand so the
1466 * hardware should be off already */
1467 BUG_ON(dev_priv
->overlay
->active
);
1469 drm_gem_object_unreference_unlocked(&dev_priv
->overlay
->reg_bo
->base
);
1470 kfree(dev_priv
->overlay
);
1473 struct intel_overlay_error_state
{
1474 struct overlay_registers regs
;
1480 struct intel_overlay_error_state
*
1481 intel_overlay_capture_error_state(struct drm_device
*dev
)
1483 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1484 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1485 struct intel_overlay_error_state
*error
;
1486 struct overlay_registers __iomem
*regs
;
1488 if (!overlay
|| !overlay
->active
)
1491 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1495 error
->dovsta
= I915_READ(DOVSTA
);
1496 error
->isr
= I915_READ(ISR
);
1497 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1498 error
->base
= (long) overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1500 error
->base
= (long) overlay
->reg_bo
->gtt_offset
;
1502 regs
= intel_overlay_map_regs_atomic(overlay
, KM_IRQ0
);
1506 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1507 intel_overlay_unmap_regs_atomic(overlay
, KM_IRQ0
);
1517 intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
)
1519 seq_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1520 error
->dovsta
, error
->isr
);
1521 seq_printf(m
, " Register file at 0x%08lx:\n",
1524 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)