arch/x86/kernel/cpu/amd.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/mm.h>
   4 #include <asm/io.h>
   5 #include <asm/processor.h>
   6 #include <asm/apic.h>
   7
   8 #include <mach_apic.h>
   9 #include "cpu.h"
  10
  11 /*
  12  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  13  *      misexecution of code under Linux. Owners of such processors should
  14  *      contact AMD for precise details and a CPU swap.
  15  *
  16  *      See     http://www.multimania.com/poulot/k6bug.html
  17  *              http://www.amd.com/K6/k6docs/revgd.html
  18  *
  19  *      The following test is erm.. interesting. AMD neglected to up
  20  *      the chip setting when fixing the bug but they also tweaked some
  21  *      performance at the same time..
  22  */
  23
  24 extern void vide(void);
  25 __asm__(".align 4\nvide: ret");
  26
  27 #ifdef CONFIG_X86_LOCAL_APIC
  28
  29 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
  30 static __cpuinit int amd_apic_timer_broken(struct cpuinfo_x86 *c)
  31 {
  32         u32 lo, hi;
  33
  34         if (c->x86 < 0x0F)
  35                 return 0;
  36
  37         /* Family 0x0f models < rev F do not have this MSR */
  38         if (c->x86 == 0x0f && c->x86_model < 0x40)
  39                 return 0;
  40
  41         rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
  42         if (lo & K8_INTP_C1E_ACTIVE_MASK) {
  43                 if (smp_processor_id() != boot_cpu_physical_apicid)
  44                         printk(KERN_INFO "AMD C1E detected late. "
  45                                "Force timer broadcast.\n");
  46                 return 1;
  47         }
  48         return 0;
  49 }
  50 #endif
  51
  52 int force_mwait __cpuinitdata;
  53
  54 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
  55 {
  56         if (cpuid_eax(0x80000000) >= 0x80000007) {
  57                 c->x86_power = cpuid_edx(0x80000007);
  58                 if (c->x86_power & (1<<8))
  59                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  60         }
  61 }
  62
  63 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
  64 {
  65         u32 l, h;
  66         int mbytes = num_physpages >> (20-PAGE_SHIFT);
  67         int r;
  68
  69 #ifdef CONFIG_SMP
  70         unsigned long long value;
  71
  72         /*
  73          * Disable TLB flush filter by setting HWCR.FFDIS on K8
  74          * bit 6 of msr C001_0015
  75          *
  76          * Errata 63 for SH-B3 steppings
  77          * Errata 122 for all steppings (F+ have it disabled by default)
  78          */
  79         if (c->x86 == 15) {
  80                 rdmsrl(MSR_K7_HWCR, value);
  81                 value |= 1 << 6;
  82                 wrmsrl(MSR_K7_HWCR, value);
  83         }
  84 #endif
  85
  86         early_init_amd(c);
  87
  88         /*
  89          *      FIXME: We should handle the K5 here. Set up the write
  90          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
  91          *      no bus pipeline)
  92          */
  93
  94         /*
  95          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
  96          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
  97          */
  98         clear_cpu_cap(c, 0*32+31);
  99
 100         r = get_model_name(c);
 101
 102         switch (c->x86) {
 103         case 4:
 104                 /*
 105                  * General Systems BIOSen alias the cpu frequency registers
 106                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
 107                  * drivers subsequently pokes it, and changes the CPU speed.
 108                  * Workaround : Remove the unneeded alias.
 109                  */
 110 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
 111 #define CBAR_ENB        (0x80000000)
 112 #define CBAR_KEY        (0X000000CB)
 113                         if (c->x86_model == 9 || c->x86_model == 10) {
 114                                 if (inl (CBAR) & CBAR_ENB)
 115                                         outl (0 | CBAR_KEY, CBAR);
 116                         }
 117                         break;
 118         case 5:
 119                         if (c->x86_model < 6) {
 120                                 /* Based on AMD doc 20734R - June 2000 */
 121                                 if (c->x86_model == 0) {
 122                                         clear_cpu_cap(c, X86_FEATURE_APIC);
 123                                         set_cpu_cap(c, X86_FEATURE_PGE);
 124                                 }
 125                                 break;
 126                         }
 127
 128                         if (c->x86_model == 6 && c->x86_mask == 1) {
 129                                 const int K6_BUG_LOOP = 1000000;
 130                                 int n;
 131                                 void (*f_vide)(void);
 132                                 unsigned long d, d2;
 133
 134                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
 135
 136                                 /*
 137                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
 138                                  * calls at the same time.
 139                                  */
 140
 141                                 n = K6_BUG_LOOP;
 142                                 f_vide = vide;
 143                                 rdtscl(d);
 144                                 while (n--)
 145                                         f_vide();
 146                                 rdtscl(d2);
 147                                 d = d2-d;
 148
 149                                 if (d > 20*K6_BUG_LOOP)
 150                                         printk("system stability may be impaired when more than 32 MB are used.\n");
 151                                 else
 152                                         printk("probably OK (after B9730xxxx).\n");
 153                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
 154                         }
 155
 156                         /* K6 with old style WHCR */
 157                         if (c->x86_model < 8 ||
 158                            (c->x86_model == 8 && c->x86_mask < 8)) {
 159                                 /* We can only write allocate on the low 508Mb */
 160                                 if (mbytes > 508)
 161                                         mbytes = 508;
 162
 163                                 rdmsr(MSR_K6_WHCR, l, h);
 164                                 if ((l&0x0000FFFF) == 0) {
 165                                         unsigned long flags;
 166                                         l = (1<<0)|((mbytes/4)<<1);
 167                                         local_irq_save(flags);
 168                                         wbinvd();
 169                                         wrmsr(MSR_K6_WHCR, l, h);
 170                                         local_irq_restore(flags);
 171                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 172                                                 mbytes);
 173                                 }
 174                                 break;
 175                         }
 176
 177                         if ((c->x86_model == 8 && c->x86_mask > 7) ||
 178                              c->x86_model == 9 || c->x86_model == 13) {
 179                                 /* The more serious chips .. */
 180
 181                                 if (mbytes > 4092)
 182                                         mbytes = 4092;
 183
 184                                 rdmsr(MSR_K6_WHCR, l, h);
 185                                 if ((l&0xFFFF0000) == 0) {
 186                                         unsigned long flags;
 187                                         l = ((mbytes>>2)<<22)|(1<<16);
 188                                         local_irq_save(flags);
 189                                         wbinvd();
 190                                         wrmsr(MSR_K6_WHCR, l, h);
 191                                         local_irq_restore(flags);
 192                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 193                                                 mbytes);
 194                                 }
 195
 196                                 /*  Set MTRR capability flag if appropriate */
 197                                 if (c->x86_model == 13 || c->x86_model == 9 ||
 198                                    (c->x86_model == 8 && c->x86_mask >= 8))
 199                                         set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 200                                 break;
 201                         }
 202
 203                         if (c->x86_model == 10) {
 204                                 /* AMD Geode LX is model 10 */
 205                                 /* placeholder for any needed mods */
 206                                 break;
 207                         }
 208                         break;
 209         case 6: /* An Athlon/Duron */
 210
 211                         /*
 212                          * Bit 15 of Athlon specific MSR 15, needs to be 0
 213                          * to enable SSE on Palomino/Morgan/Barton CPU's.
 214                          * If the BIOS didn't enable it already, enable it here.
 215                          */
 216                         if (c->x86_model >= 6 && c->x86_model <= 10) {
 217                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
 218                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
 219                                         rdmsr(MSR_K7_HWCR, l, h);
 220                                         l &= ~0x00008000;
 221                                         wrmsr(MSR_K7_HWCR, l, h);
 222                                         set_cpu_cap(c, X86_FEATURE_XMM);
 223                                 }
 224                         }
 225
 226                         /*
 227                          * It's been determined by AMD that Athlons since model 8 stepping 1
 228                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
 229                          * As per AMD technical note 27212 0.2
 230                          */
 231                         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
 232                                 rdmsr(MSR_K7_CLK_CTL, l, h);
 233                                 if ((l & 0xfff00000) != 0x20000000) {
 234                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
 235                                                 ((l & 0x000fffff)|0x20000000));
 236                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
 237                                 }
 238                         }
 239                         break;
 240         }
 241
 242         switch (c->x86) {
 243         case 15:
 244         /* Use K8 tuning for Fam10h and Fam11h */
 245         case 0x10:
 246         case 0x11:
 247                 set_cpu_cap(c, X86_FEATURE_K8);
 248                 break;
 249         case 6:
 250                 set_cpu_cap(c, X86_FEATURE_K7);
 251                 break;
 252         }
 253         if (c->x86 >= 6)
 254                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 255
 256         display_cacheinfo(c);
 257
 258         if (cpuid_eax(0x80000000) >= 0x80000008)
 259                 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
 260
 261 #ifdef CONFIG_X86_HT
 262         /*
 263          * On a AMD multi core setup the lower bits of the APIC id
 264          * distinguish the cores.
 265          */
 266         if (c->x86_max_cores > 1) {
 267                 int cpu = smp_processor_id();
 268                 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
 269
 270                 if (bits == 0) {
 271                         while ((1 << bits) < c->x86_max_cores)
 272                                 bits++;
 273                 }
 274                 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
 275                 c->phys_proc_id >>= bits;
 276                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
 277                        cpu, c->x86_max_cores, c->cpu_core_id);
 278         }
 279 #endif
 280
 281         if (cpuid_eax(0x80000000) >= 0x80000006) {
 282                 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
 283                         num_cache_leaves = 4;
 284                 else
 285                         num_cache_leaves = 3;
 286         }
 287
 288 #ifdef CONFIG_X86_LOCAL_APIC
 289         if (amd_apic_timer_broken(c))
 290                 local_apic_timer_disabled = 1;
 291 #endif
 292
 293         /* K6s reports MCEs but don't actually have all the MSRs */
 294         if (c->x86 < 6)
 295                 clear_cpu_cap(c, X86_FEATURE_MCE);
 296
 297         if (cpu_has_xmm2)
 298                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 299
 300         if (c->x86 == 0x10)
 301                 amd_enable_pci_ext_cfg(c);
 302 }
 303
 304 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 305 {
 306         /* AMD errata T13 (order #21922) */
 307         if ((c->x86 == 6)) {
 308                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
 309                         size = 64;
 310                 if (c->x86_model == 4 &&
 311                     (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
 312                         size = 256;
 313         }
 314         return size;
 315 }
 316
 317 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
 318         .c_vendor       = "AMD",
 319         .c_ident        = { "AuthenticAMD" },
 320         .c_models = {
 321                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
 322                   {
 323                           [3] = "486 DX/2",
 324                           [7] = "486 DX/2-WB",
 325                           [8] = "486 DX/4",
 326                           [9] = "486 DX/4-WB",
 327                           [14] = "Am5x86-WT",
 328                           [15] = "Am5x86-WB"
 329                   }
 330                 },
 331         },
 332         .c_early_init   = early_init_amd,
 333         .c_init         = init_amd,
 334         .c_size_cache   = amd_size_cache,
 335 };
 336
 337 cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);