2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
77 static DEFINE_RAW_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing
[MAX_IO_APICS
];
91 /* The one past the highest gsi number used */
94 /* MP IRQ source entries */
95 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
97 /* # of MP IRQ source entries */
101 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
103 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
104 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
107 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
109 int skip_ioapic_setup
;
111 void arch_disable_smp_support(void)
115 noioapicreroute
= -1;
117 skip_ioapic_setup
= 1;
120 static int __init
parse_noapic(char *str
)
122 /* disable IO-APIC */
123 arch_disable_smp_support();
126 early_param("noapic", parse_noapic
);
128 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
129 void mp_save_irq(struct mpc_intsrc
*m
)
133 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
134 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
135 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
136 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
138 for (i
= 0; i
< mp_irq_entries
; i
++) {
139 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
143 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
144 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
145 panic("Max # of irq sources exceeded!!\n");
148 struct irq_pin_list
{
150 struct irq_pin_list
*next
;
153 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
155 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
159 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
160 #ifdef CONFIG_SPARSE_IRQ
161 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
163 static struct irq_cfg irq_cfgx
[NR_IRQS
];
166 int __init
arch_early_irq_init(void)
171 if (!legacy_pic
->nr_legacy_irqs
) {
177 count
= ARRAY_SIZE(irq_cfgx
);
178 node
= cpu_to_node(0);
180 /* Make sure the legacy interrupts are marked in the bitmap */
181 irq_reserve_irqs(0, legacy_pic
->nr_legacy_irqs
);
183 for (i
= 0; i
< count
; i
++) {
184 set_irq_chip_data(i
, &cfg
[i
]);
185 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_KERNEL
, node
);
186 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_KERNEL
, node
);
188 * For legacy IRQ's, start with assigning irq0 to irq15 to
189 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
191 if (i
< legacy_pic
->nr_legacy_irqs
) {
192 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
193 cpumask_set_cpu(0, cfg
[i
].domain
);
200 #ifdef CONFIG_SPARSE_IRQ
201 static struct irq_cfg
*irq_cfg(unsigned int irq
)
203 return get_irq_chip_data(irq
);
206 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
210 cfg
= kzalloc_node(sizeof(*cfg
), GFP_KERNEL
, node
);
213 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_KERNEL
, node
))
215 if (!zalloc_cpumask_var_node(&cfg
->old_domain
, GFP_KERNEL
, node
))
219 free_cpumask_var(cfg
->domain
);
225 static void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
)
229 set_irq_chip_data(at
, NULL
);
230 free_cpumask_var(cfg
->domain
);
231 free_cpumask_var(cfg
->old_domain
);
237 struct irq_cfg
*irq_cfg(unsigned int irq
)
239 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
242 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
244 return irq_cfgx
+ irq
;
247 static inline void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
) { }
251 static struct irq_cfg
*alloc_irq_and_cfg_at(unsigned int at
, int node
)
253 int res
= irq_alloc_desc_at(at
, node
);
259 cfg
= get_irq_chip_data(at
);
264 cfg
= alloc_irq_cfg(at
, node
);
266 set_irq_chip_data(at
, cfg
);
272 static int alloc_irq_from(unsigned int from
, int node
)
274 return irq_alloc_desc_from(from
, node
);
277 static void free_irq_at(unsigned int at
, struct irq_cfg
*cfg
)
279 free_irq_cfg(at
, cfg
);
285 unsigned int unused
[3];
287 unsigned int unused2
[11];
291 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
293 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
294 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
297 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
299 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
300 writel(vector
, &io_apic
->eoi
);
303 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
305 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
306 writel(reg
, &io_apic
->index
);
307 return readl(&io_apic
->data
);
310 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
312 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
313 writel(reg
, &io_apic
->index
);
314 writel(value
, &io_apic
->data
);
318 * Re-write a value: to be used for read-modify-write
319 * cycles where the read already set up the index register.
321 * Older SiS APIC requires we rewrite the index register
323 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
325 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
328 writel(reg
, &io_apic
->index
);
329 writel(value
, &io_apic
->data
);
332 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
334 struct irq_pin_list
*entry
;
337 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
338 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
343 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
344 /* Is the remote IRR bit set? */
345 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
346 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
350 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
356 struct { u32 w1
, w2
; };
357 struct IO_APIC_route_entry entry
;
360 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
362 union entry_union eu
;
364 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
365 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
366 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
367 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
372 * When we write a new IO APIC routing entry, we need to write the high
373 * word first! If the mask bit in the low word is clear, we will enable
374 * the interrupt, and we need to make sure the entry is fully populated
375 * before that happens.
378 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
380 union entry_union eu
= {{0, 0}};
383 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
384 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
387 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
390 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
391 __ioapic_write_entry(apic
, pin
, e
);
392 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
396 * When we mask an IO APIC routing entry, we need to write the low
397 * word first, in order to set the mask bit before we change the
400 static void ioapic_mask_entry(int apic
, int pin
)
403 union entry_union eu
= { .entry
.mask
= 1 };
405 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
406 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
407 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
408 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
412 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
413 * shared ISA-space IRQs, so we have to support them. We are super
414 * fast in the common case, and fast for shared ISA-space IRQs.
417 __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
419 struct irq_pin_list
**last
, *entry
;
421 /* don't allow duplicates */
422 last
= &cfg
->irq_2_pin
;
423 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
424 if (entry
->apic
== apic
&& entry
->pin
== pin
)
429 entry
= alloc_irq_pin_list(node
);
431 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
442 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
444 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
445 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
449 * Reroute an IRQ to a different pin.
451 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
452 int oldapic
, int oldpin
,
453 int newapic
, int newpin
)
455 struct irq_pin_list
*entry
;
457 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
458 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
459 entry
->apic
= newapic
;
461 /* every one is different, right? */
466 /* old apic/pin didn't exist, so just add new ones */
467 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
470 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
471 int mask_and
, int mask_or
,
472 void (*final
)(struct irq_pin_list
*entry
))
474 unsigned int reg
, pin
;
477 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
480 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
485 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
486 int mask_and
, int mask_or
,
487 void (*final
)(struct irq_pin_list
*entry
))
489 struct irq_pin_list
*entry
;
491 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
492 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
495 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list
*entry
)
497 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
498 IO_APIC_REDIR_MASKED
, NULL
);
501 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list
*entry
)
503 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_MASKED
,
504 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
507 static void io_apic_sync(struct irq_pin_list
*entry
)
510 * Synchronize the IO-APIC and the CPU by doing
511 * a dummy read from the IO-APIC
513 struct io_apic __iomem
*io_apic
;
514 io_apic
= io_apic_base(entry
->apic
);
515 readl(&io_apic
->data
);
518 static void mask_ioapic(struct irq_cfg
*cfg
)
522 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
523 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
524 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
527 static void mask_ioapic_irq(struct irq_data
*data
)
529 mask_ioapic(data
->chip_data
);
532 static void __unmask_ioapic(struct irq_cfg
*cfg
)
534 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
537 static void unmask_ioapic(struct irq_cfg
*cfg
)
541 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
542 __unmask_ioapic(cfg
);
543 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
546 static void unmask_ioapic_irq(struct irq_data
*data
)
548 unmask_ioapic(data
->chip_data
);
551 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
553 struct IO_APIC_route_entry entry
;
555 /* Check delivery_mode to be sure we're not clearing an SMI pin */
556 entry
= ioapic_read_entry(apic
, pin
);
557 if (entry
.delivery_mode
== dest_SMI
)
560 * Disable it in the IO-APIC irq-routing table:
562 ioapic_mask_entry(apic
, pin
);
565 static void clear_IO_APIC (void)
569 for (apic
= 0; apic
< nr_ioapics
; apic
++)
570 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
571 clear_IO_APIC_pin(apic
, pin
);
576 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
577 * specific CPU-side IRQs.
581 static int pirq_entries
[MAX_PIRQS
] = {
582 [0 ... MAX_PIRQS
- 1] = -1
585 static int __init
ioapic_pirq_setup(char *str
)
588 int ints
[MAX_PIRQS
+1];
590 get_options(str
, ARRAY_SIZE(ints
), ints
);
592 apic_printk(APIC_VERBOSE
, KERN_INFO
593 "PIRQ redirection, working around broken MP-BIOS.\n");
595 if (ints
[0] < MAX_PIRQS
)
598 for (i
= 0; i
< max
; i
++) {
599 apic_printk(APIC_VERBOSE
, KERN_DEBUG
600 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
602 * PIRQs are mapped upside down, usually.
604 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
609 __setup("pirq=", ioapic_pirq_setup
);
610 #endif /* CONFIG_X86_32 */
612 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
615 struct IO_APIC_route_entry
**ioapic_entries
;
617 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
622 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
623 ioapic_entries
[apic
] =
624 kzalloc(sizeof(struct IO_APIC_route_entry
) *
625 nr_ioapic_registers
[apic
], GFP_KERNEL
);
626 if (!ioapic_entries
[apic
])
630 return ioapic_entries
;
634 kfree(ioapic_entries
[apic
]);
635 kfree(ioapic_entries
);
641 * Saves all the IO-APIC RTE's
643 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
650 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
651 if (!ioapic_entries
[apic
])
654 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
655 ioapic_entries
[apic
][pin
] =
656 ioapic_read_entry(apic
, pin
);
663 * Mask all IO APIC entries.
665 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
672 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
673 if (!ioapic_entries
[apic
])
676 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
677 struct IO_APIC_route_entry entry
;
679 entry
= ioapic_entries
[apic
][pin
];
682 ioapic_write_entry(apic
, pin
, entry
);
689 * Restore IO APIC entries which was saved in ioapic_entries.
691 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
698 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
699 if (!ioapic_entries
[apic
])
702 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
703 ioapic_write_entry(apic
, pin
,
704 ioapic_entries
[apic
][pin
]);
709 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
713 for (apic
= 0; apic
< nr_ioapics
; apic
++)
714 kfree(ioapic_entries
[apic
]);
716 kfree(ioapic_entries
);
720 * Find the IRQ entry number of a certain pin.
722 static int find_irq_entry(int apic
, int pin
, int type
)
726 for (i
= 0; i
< mp_irq_entries
; i
++)
727 if (mp_irqs
[i
].irqtype
== type
&&
728 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
729 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
730 mp_irqs
[i
].dstirq
== pin
)
737 * Find the pin to which IRQ[irq] (ISA) is connected
739 static int __init
find_isa_irq_pin(int irq
, int type
)
743 for (i
= 0; i
< mp_irq_entries
; i
++) {
744 int lbus
= mp_irqs
[i
].srcbus
;
746 if (test_bit(lbus
, mp_bus_not_pci
) &&
747 (mp_irqs
[i
].irqtype
== type
) &&
748 (mp_irqs
[i
].srcbusirq
== irq
))
750 return mp_irqs
[i
].dstirq
;
755 static int __init
find_isa_irq_apic(int irq
, int type
)
759 for (i
= 0; i
< mp_irq_entries
; i
++) {
760 int lbus
= mp_irqs
[i
].srcbus
;
762 if (test_bit(lbus
, mp_bus_not_pci
) &&
763 (mp_irqs
[i
].irqtype
== type
) &&
764 (mp_irqs
[i
].srcbusirq
== irq
))
767 if (i
< mp_irq_entries
) {
769 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
770 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
778 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
780 * EISA Edge/Level control register, ELCR
782 static int EISA_ELCR(unsigned int irq
)
784 if (irq
< legacy_pic
->nr_legacy_irqs
) {
785 unsigned int port
= 0x4d0 + (irq
>> 3);
786 return (inb(port
) >> (irq
& 7)) & 1;
788 apic_printk(APIC_VERBOSE
, KERN_INFO
789 "Broken MPtable reports ISA irq %d\n", irq
);
795 /* ISA interrupts are always polarity zero edge triggered,
796 * when listed as conforming in the MP table. */
798 #define default_ISA_trigger(idx) (0)
799 #define default_ISA_polarity(idx) (0)
801 /* EISA interrupts are always polarity zero and can be edge or level
802 * trigger depending on the ELCR value. If an interrupt is listed as
803 * EISA conforming in the MP table, that means its trigger type must
804 * be read in from the ELCR */
806 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
807 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
809 /* PCI interrupts are always polarity one level triggered,
810 * when listed as conforming in the MP table. */
812 #define default_PCI_trigger(idx) (1)
813 #define default_PCI_polarity(idx) (1)
815 /* MCA interrupts are always polarity zero level triggered,
816 * when listed as conforming in the MP table. */
818 #define default_MCA_trigger(idx) (1)
819 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
821 static int MPBIOS_polarity(int idx
)
823 int bus
= mp_irqs
[idx
].srcbus
;
827 * Determine IRQ line polarity (high active or low active):
829 switch (mp_irqs
[idx
].irqflag
& 3)
831 case 0: /* conforms, ie. bus-type dependent polarity */
832 if (test_bit(bus
, mp_bus_not_pci
))
833 polarity
= default_ISA_polarity(idx
);
835 polarity
= default_PCI_polarity(idx
);
837 case 1: /* high active */
842 case 2: /* reserved */
844 printk(KERN_WARNING
"broken BIOS!!\n");
848 case 3: /* low active */
853 default: /* invalid */
855 printk(KERN_WARNING
"broken BIOS!!\n");
863 static int MPBIOS_trigger(int idx
)
865 int bus
= mp_irqs
[idx
].srcbus
;
869 * Determine IRQ trigger mode (edge or level sensitive):
871 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
873 case 0: /* conforms, ie. bus-type dependent */
874 if (test_bit(bus
, mp_bus_not_pci
))
875 trigger
= default_ISA_trigger(idx
);
877 trigger
= default_PCI_trigger(idx
);
878 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
879 switch (mp_bus_id_to_type
[bus
]) {
880 case MP_BUS_ISA
: /* ISA pin */
882 /* set before the switch */
885 case MP_BUS_EISA
: /* EISA pin */
887 trigger
= default_EISA_trigger(idx
);
890 case MP_BUS_PCI
: /* PCI pin */
892 /* set before the switch */
895 case MP_BUS_MCA
: /* MCA pin */
897 trigger
= default_MCA_trigger(idx
);
902 printk(KERN_WARNING
"broken BIOS!!\n");
914 case 2: /* reserved */
916 printk(KERN_WARNING
"broken BIOS!!\n");
925 default: /* invalid */
927 printk(KERN_WARNING
"broken BIOS!!\n");
935 static inline int irq_polarity(int idx
)
937 return MPBIOS_polarity(idx
);
940 static inline int irq_trigger(int idx
)
942 return MPBIOS_trigger(idx
);
945 static int pin_2_irq(int idx
, int apic
, int pin
)
948 int bus
= mp_irqs
[idx
].srcbus
;
951 * Debugging check, we are in big trouble if this message pops up!
953 if (mp_irqs
[idx
].dstirq
!= pin
)
954 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
956 if (test_bit(bus
, mp_bus_not_pci
)) {
957 irq
= mp_irqs
[idx
].srcbusirq
;
959 u32 gsi
= mp_gsi_routing
[apic
].gsi_base
+ pin
;
961 if (gsi
>= NR_IRQS_LEGACY
)
969 * PCI IRQ command line redirection. Yes, limits are hardcoded.
971 if ((pin
>= 16) && (pin
<= 23)) {
972 if (pirq_entries
[pin
-16] != -1) {
973 if (!pirq_entries
[pin
-16]) {
974 apic_printk(APIC_VERBOSE
, KERN_DEBUG
975 "disabling PIRQ%d\n", pin
-16);
977 irq
= pirq_entries
[pin
-16];
978 apic_printk(APIC_VERBOSE
, KERN_DEBUG
979 "using PIRQ%d -> IRQ %d\n",
990 * Find a specific PCI IRQ entry.
991 * Not an __init, possibly needed by modules
993 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
994 struct io_apic_irq_attr
*irq_attr
)
996 int apic
, i
, best_guess
= -1;
998 apic_printk(APIC_DEBUG
,
999 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1001 if (test_bit(bus
, mp_bus_not_pci
)) {
1002 apic_printk(APIC_VERBOSE
,
1003 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1006 for (i
= 0; i
< mp_irq_entries
; i
++) {
1007 int lbus
= mp_irqs
[i
].srcbus
;
1009 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1010 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1011 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1014 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1015 !mp_irqs
[i
].irqtype
&&
1017 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1018 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1020 if (!(apic
|| IO_APIC_IRQ(irq
)))
1023 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1024 set_io_apic_irq_attr(irq_attr
, apic
,
1031 * Use the first all-but-pin matching entry as a
1032 * best-guess fuzzy result for broken mptables.
1034 if (best_guess
< 0) {
1035 set_io_apic_irq_attr(irq_attr
, apic
,
1045 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1047 void lock_vector_lock(void)
1049 /* Used to the online set of cpus does not change
1050 * during assign_irq_vector.
1052 raw_spin_lock(&vector_lock
);
1055 void unlock_vector_lock(void)
1057 raw_spin_unlock(&vector_lock
);
1061 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1064 * NOTE! The local APIC isn't very good at handling
1065 * multiple interrupts at the same interrupt level.
1066 * As the interrupt level is determined by taking the
1067 * vector number and shifting that right by 4, we
1068 * want to spread these out a bit so that they don't
1069 * all fall in the same interrupt level.
1071 * Also, we've got to be careful not to trash gate
1072 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1074 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1075 static int current_offset
= VECTOR_OFFSET_START
% 8;
1076 unsigned int old_vector
;
1078 cpumask_var_t tmp_mask
;
1080 if (cfg
->move_in_progress
)
1083 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1086 old_vector
= cfg
->vector
;
1088 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1089 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1090 if (!cpumask_empty(tmp_mask
)) {
1091 free_cpumask_var(tmp_mask
);
1096 /* Only try and allocate irqs on cpus that are present */
1098 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1102 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1104 vector
= current_vector
;
1105 offset
= current_offset
;
1108 if (vector
>= first_system_vector
) {
1109 /* If out of vectors on large boxen, must share them. */
1110 offset
= (offset
+ 1) % 8;
1111 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1113 if (unlikely(current_vector
== vector
))
1116 if (test_bit(vector
, used_vectors
))
1119 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1120 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1123 current_vector
= vector
;
1124 current_offset
= offset
;
1126 cfg
->move_in_progress
= 1;
1127 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1129 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1130 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1131 cfg
->vector
= vector
;
1132 cpumask_copy(cfg
->domain
, tmp_mask
);
1136 free_cpumask_var(tmp_mask
);
1140 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1143 unsigned long flags
;
1145 raw_spin_lock_irqsave(&vector_lock
, flags
);
1146 err
= __assign_irq_vector(irq
, cfg
, mask
);
1147 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1151 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1155 BUG_ON(!cfg
->vector
);
1157 vector
= cfg
->vector
;
1158 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1159 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1162 cpumask_clear(cfg
->domain
);
1164 if (likely(!cfg
->move_in_progress
))
1166 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1167 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1169 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1171 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1175 cfg
->move_in_progress
= 0;
1178 void __setup_vector_irq(int cpu
)
1180 /* Initialize vector_irq on a new cpu */
1182 struct irq_cfg
*cfg
;
1185 * vector_lock will make sure that we don't run into irq vector
1186 * assignments that might be happening on another cpu in parallel,
1187 * while we setup our initial vector to irq mappings.
1189 raw_spin_lock(&vector_lock
);
1190 /* Mark the inuse vectors */
1191 for_each_active_irq(irq
) {
1192 cfg
= get_irq_chip_data(irq
);
1196 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1197 * will be part of the irq_cfg's domain.
1199 if (irq
< legacy_pic
->nr_legacy_irqs
&& !IO_APIC_IRQ(irq
))
1200 cpumask_set_cpu(cpu
, cfg
->domain
);
1202 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1204 vector
= cfg
->vector
;
1205 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1207 /* Mark the free vectors */
1208 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1209 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1214 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1215 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1217 raw_spin_unlock(&vector_lock
);
1220 static struct irq_chip ioapic_chip
;
1221 static struct irq_chip ir_ioapic_chip
;
1223 #define IOAPIC_AUTO -1
1224 #define IOAPIC_EDGE 0
1225 #define IOAPIC_LEVEL 1
1227 #ifdef CONFIG_X86_32
1228 static inline int IO_APIC_irq_trigger(int irq
)
1232 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1233 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1234 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1235 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1236 return irq_trigger(idx
);
1240 * nonexistent IRQs are edge default
1245 static inline int IO_APIC_irq_trigger(int irq
)
1251 static void ioapic_register_intr(unsigned int irq
, unsigned long trigger
)
1254 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1255 trigger
== IOAPIC_LEVEL
)
1256 irq_set_status_flags(irq
, IRQ_LEVEL
);
1258 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1260 if (irq_remapped(get_irq_chip_data(irq
))) {
1261 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
1263 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1267 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1268 handle_edge_irq
, "edge");
1272 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1273 trigger
== IOAPIC_LEVEL
)
1274 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1278 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1279 handle_edge_irq
, "edge");
1282 static int setup_ioapic_entry(int apic_id
, int irq
,
1283 struct IO_APIC_route_entry
*entry
,
1284 unsigned int destination
, int trigger
,
1285 int polarity
, int vector
, int pin
)
1288 * add it to the IO-APIC irq-routing table:
1290 memset(entry
,0,sizeof(*entry
));
1292 if (intr_remapping_enabled
) {
1293 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1295 struct IR_IO_APIC_route_entry
*ir_entry
=
1296 (struct IR_IO_APIC_route_entry
*) entry
;
1300 panic("No mapping iommu for ioapic %d\n", apic_id
);
1302 index
= alloc_irte(iommu
, irq
, 1);
1304 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1306 prepare_irte(&irte
, vector
, destination
);
1308 /* Set source-id of interrupt request */
1309 set_ioapic_sid(&irte
, apic_id
);
1311 modify_irte(irq
, &irte
);
1313 ir_entry
->index2
= (index
>> 15) & 0x1;
1315 ir_entry
->format
= 1;
1316 ir_entry
->index
= (index
& 0x7fff);
1318 * IO-APIC RTE will be configured with virtual vector.
1319 * irq handler will do the explicit EOI to the io-apic.
1321 ir_entry
->vector
= pin
;
1323 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1324 entry
->dest_mode
= apic
->irq_dest_mode
;
1325 entry
->dest
= destination
;
1326 entry
->vector
= vector
;
1329 entry
->mask
= 0; /* enable IRQ */
1330 entry
->trigger
= trigger
;
1331 entry
->polarity
= polarity
;
1333 /* Mask level triggered irqs.
1334 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1341 static void setup_ioapic_irq(int apic_id
, int pin
, unsigned int irq
,
1342 struct irq_cfg
*cfg
, int trigger
, int polarity
)
1344 struct IO_APIC_route_entry entry
;
1347 if (!IO_APIC_IRQ(irq
))
1350 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1351 * controllers like 8259. Now that IO-APIC can handle this irq, update
1354 if (irq
< legacy_pic
->nr_legacy_irqs
&& cpumask_test_cpu(0, cfg
->domain
))
1355 apic
->vector_allocation_domain(0, cfg
->domain
);
1357 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1360 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1362 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1363 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1364 "IRQ %d Mode:%i Active:%i)\n",
1365 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1366 irq
, trigger
, polarity
);
1369 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1370 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1371 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1372 mp_ioapics
[apic_id
].apicid
, pin
);
1373 __clear_irq_vector(irq
, cfg
);
1377 ioapic_register_intr(irq
, trigger
);
1378 if (irq
< legacy_pic
->nr_legacy_irqs
)
1379 legacy_pic
->mask(irq
);
1381 ioapic_write_entry(apic_id
, pin
, entry
);
1385 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1386 } mp_ioapic_routing
[MAX_IO_APICS
];
1388 static void __init
setup_IO_APIC_irqs(void)
1390 int apic_id
, pin
, idx
, irq
, notcon
= 0;
1391 int node
= cpu_to_node(0);
1392 struct irq_cfg
*cfg
;
1394 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1396 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++)
1397 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1398 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1402 apic_printk(APIC_VERBOSE
,
1403 KERN_DEBUG
" %d-%d",
1404 mp_ioapics
[apic_id
].apicid
, pin
);
1406 apic_printk(APIC_VERBOSE
, " %d-%d",
1407 mp_ioapics
[apic_id
].apicid
, pin
);
1411 apic_printk(APIC_VERBOSE
,
1412 " (apicid-pin) not connected\n");
1416 irq
= pin_2_irq(idx
, apic_id
, pin
);
1418 if ((apic_id
> 0) && (irq
> 16))
1422 * Skip the timer IRQ if there's a quirk handler
1423 * installed and if it returns 1:
1425 if (apic
->multi_timer_check
&&
1426 apic
->multi_timer_check(apic_id
, irq
))
1429 cfg
= alloc_irq_and_cfg_at(irq
, node
);
1433 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1435 * don't mark it in pin_programmed, so later acpi could
1436 * set it correctly when irq < 16
1438 setup_ioapic_irq(apic_id
, pin
, irq
, cfg
, irq_trigger(idx
),
1443 apic_printk(APIC_VERBOSE
,
1444 " (apicid-pin) not connected\n");
1448 * for the gsit that is not in first ioapic
1449 * but could not use acpi_register_gsi()
1450 * like some special sci in IBM x3330
1452 void setup_IO_APIC_irq_extra(u32 gsi
)
1454 int apic_id
= 0, pin
, idx
, irq
, node
= cpu_to_node(0);
1455 struct irq_cfg
*cfg
;
1458 * Convert 'gsi' to 'ioapic.pin'.
1460 apic_id
= mp_find_ioapic(gsi
);
1464 pin
= mp_find_ioapic_pin(apic_id
, gsi
);
1465 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1469 irq
= pin_2_irq(idx
, apic_id
, pin
);
1471 /* Only handle the non legacy irqs on secondary ioapics */
1472 if (apic_id
== 0 || irq
< NR_IRQS_LEGACY
)
1475 cfg
= alloc_irq_and_cfg_at(irq
, node
);
1479 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1481 if (test_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
)) {
1482 pr_debug("Pin %d-%d already programmed\n",
1483 mp_ioapics
[apic_id
].apicid
, pin
);
1486 set_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
);
1488 setup_ioapic_irq(apic_id
, pin
, irq
, cfg
,
1489 irq_trigger(idx
), irq_polarity(idx
));
1493 * Set up the timer pin, possibly with the 8259A-master behind.
1495 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1498 struct IO_APIC_route_entry entry
;
1500 if (intr_remapping_enabled
)
1503 memset(&entry
, 0, sizeof(entry
));
1506 * We use logical delivery to get the timer IRQ
1509 entry
.dest_mode
= apic
->irq_dest_mode
;
1510 entry
.mask
= 0; /* don't mask IRQ for edge */
1511 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1512 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1515 entry
.vector
= vector
;
1518 * The timer IRQ doesn't have to know that behind the
1519 * scene we may have a 8259A-master in AEOI mode ...
1521 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1524 * Add it to the IO-APIC irq-routing table:
1526 ioapic_write_entry(apic_id
, pin
, entry
);
1530 __apicdebuginit(void) print_IO_APIC(void)
1533 union IO_APIC_reg_00 reg_00
;
1534 union IO_APIC_reg_01 reg_01
;
1535 union IO_APIC_reg_02 reg_02
;
1536 union IO_APIC_reg_03 reg_03
;
1537 unsigned long flags
;
1538 struct irq_cfg
*cfg
;
1541 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1542 for (i
= 0; i
< nr_ioapics
; i
++)
1543 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1544 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1547 * We are a bit conservative about what we expect. We have to
1548 * know about every hardware change ASAP.
1550 printk(KERN_INFO
"testing the IO APIC.......................\n");
1552 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1554 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1555 reg_00
.raw
= io_apic_read(apic
, 0);
1556 reg_01
.raw
= io_apic_read(apic
, 1);
1557 if (reg_01
.bits
.version
>= 0x10)
1558 reg_02
.raw
= io_apic_read(apic
, 2);
1559 if (reg_01
.bits
.version
>= 0x20)
1560 reg_03
.raw
= io_apic_read(apic
, 3);
1561 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1564 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1565 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1566 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1567 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1568 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1570 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1571 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1573 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1574 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1577 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1578 * but the value of reg_02 is read as the previous read register
1579 * value, so ignore it if reg_02 == reg_01.
1581 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1582 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1583 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1587 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1588 * or reg_03, but the value of reg_0[23] is read as the previous read
1589 * register value, so ignore it if reg_03 == reg_0[12].
1591 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1592 reg_03
.raw
!= reg_01
.raw
) {
1593 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1594 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1597 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1599 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1600 " Stat Dmod Deli Vect:\n");
1602 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1603 struct IO_APIC_route_entry entry
;
1605 entry
= ioapic_read_entry(apic
, i
);
1607 printk(KERN_DEBUG
" %02x %03X ",
1612 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1617 entry
.delivery_status
,
1619 entry
.delivery_mode
,
1624 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1625 for_each_active_irq(irq
) {
1626 struct irq_pin_list
*entry
;
1628 cfg
= get_irq_chip_data(irq
);
1631 entry
= cfg
->irq_2_pin
;
1634 printk(KERN_DEBUG
"IRQ%d ", irq
);
1635 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1636 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1640 printk(KERN_INFO
".................................... done.\n");
1645 __apicdebuginit(void) print_APIC_field(int base
)
1651 for (i
= 0; i
< 8; i
++)
1652 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1654 printk(KERN_CONT
"\n");
1657 __apicdebuginit(void) print_local_APIC(void *dummy
)
1659 unsigned int i
, v
, ver
, maxlvt
;
1662 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1663 smp_processor_id(), hard_smp_processor_id());
1664 v
= apic_read(APIC_ID
);
1665 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1666 v
= apic_read(APIC_LVR
);
1667 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1668 ver
= GET_APIC_VERSION(v
);
1669 maxlvt
= lapic_get_maxlvt();
1671 v
= apic_read(APIC_TASKPRI
);
1672 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1674 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1675 if (!APIC_XAPIC(ver
)) {
1676 v
= apic_read(APIC_ARBPRI
);
1677 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1678 v
& APIC_ARBPRI_MASK
);
1680 v
= apic_read(APIC_PROCPRI
);
1681 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1685 * Remote read supported only in the 82489DX and local APIC for
1686 * Pentium processors.
1688 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1689 v
= apic_read(APIC_RRR
);
1690 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1693 v
= apic_read(APIC_LDR
);
1694 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1695 if (!x2apic_enabled()) {
1696 v
= apic_read(APIC_DFR
);
1697 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1699 v
= apic_read(APIC_SPIV
);
1700 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1702 printk(KERN_DEBUG
"... APIC ISR field:\n");
1703 print_APIC_field(APIC_ISR
);
1704 printk(KERN_DEBUG
"... APIC TMR field:\n");
1705 print_APIC_field(APIC_TMR
);
1706 printk(KERN_DEBUG
"... APIC IRR field:\n");
1707 print_APIC_field(APIC_IRR
);
1709 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1710 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1711 apic_write(APIC_ESR
, 0);
1713 v
= apic_read(APIC_ESR
);
1714 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1717 icr
= apic_icr_read();
1718 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1719 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1721 v
= apic_read(APIC_LVTT
);
1722 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1724 if (maxlvt
> 3) { /* PC is LVT#4. */
1725 v
= apic_read(APIC_LVTPC
);
1726 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1728 v
= apic_read(APIC_LVT0
);
1729 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1730 v
= apic_read(APIC_LVT1
);
1731 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1733 if (maxlvt
> 2) { /* ERR is LVT#3. */
1734 v
= apic_read(APIC_LVTERR
);
1735 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1738 v
= apic_read(APIC_TMICT
);
1739 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1740 v
= apic_read(APIC_TMCCT
);
1741 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1742 v
= apic_read(APIC_TDCR
);
1743 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1745 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1746 v
= apic_read(APIC_EFEAT
);
1747 maxlvt
= (v
>> 16) & 0xff;
1748 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1749 v
= apic_read(APIC_ECTRL
);
1750 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1751 for (i
= 0; i
< maxlvt
; i
++) {
1752 v
= apic_read(APIC_EILVTn(i
));
1753 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1759 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1767 for_each_online_cpu(cpu
) {
1770 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1775 __apicdebuginit(void) print_PIC(void)
1778 unsigned long flags
;
1780 if (!legacy_pic
->nr_legacy_irqs
)
1783 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1785 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1787 v
= inb(0xa1) << 8 | inb(0x21);
1788 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1790 v
= inb(0xa0) << 8 | inb(0x20);
1791 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1795 v
= inb(0xa0) << 8 | inb(0x20);
1799 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1801 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1803 v
= inb(0x4d1) << 8 | inb(0x4d0);
1804 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1807 static int __initdata show_lapic
= 1;
1808 static __init
int setup_show_lapic(char *arg
)
1812 if (strcmp(arg
, "all") == 0) {
1813 show_lapic
= CONFIG_NR_CPUS
;
1815 get_option(&arg
, &num
);
1822 __setup("show_lapic=", setup_show_lapic
);
1824 __apicdebuginit(int) print_ICs(void)
1826 if (apic_verbosity
== APIC_QUIET
)
1831 /* don't print out if apic is not there */
1832 if (!cpu_has_apic
&& !apic_from_smp_config())
1835 print_local_APICs(show_lapic
);
1841 fs_initcall(print_ICs
);
1844 /* Where if anywhere is the i8259 connect in external int mode */
1845 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1847 void __init
enable_IO_APIC(void)
1849 int i8259_apic
, i8259_pin
;
1852 if (!legacy_pic
->nr_legacy_irqs
)
1855 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1857 /* See if any of the pins is in ExtINT mode */
1858 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1859 struct IO_APIC_route_entry entry
;
1860 entry
= ioapic_read_entry(apic
, pin
);
1862 /* If the interrupt line is enabled and in ExtInt mode
1863 * I have found the pin where the i8259 is connected.
1865 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1866 ioapic_i8259
.apic
= apic
;
1867 ioapic_i8259
.pin
= pin
;
1873 /* Look to see what if the MP table has reported the ExtINT */
1874 /* If we could not find the appropriate pin by looking at the ioapic
1875 * the i8259 probably is not connected the ioapic but give the
1876 * mptable a chance anyway.
1878 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1879 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1880 /* Trust the MP table if nothing is setup in the hardware */
1881 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1882 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1883 ioapic_i8259
.pin
= i8259_pin
;
1884 ioapic_i8259
.apic
= i8259_apic
;
1886 /* Complain if the MP table and the hardware disagree */
1887 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1888 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1890 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1894 * Do not trust the IO-APIC being empty at bootup
1900 * Not an __init, needed by the reboot code
1902 void disable_IO_APIC(void)
1905 * Clear the IO-APIC before rebooting:
1909 if (!legacy_pic
->nr_legacy_irqs
)
1913 * If the i8259 is routed through an IOAPIC
1914 * Put that IOAPIC in virtual wire mode
1915 * so legacy interrupts can be delivered.
1917 * With interrupt-remapping, for now we will use virtual wire A mode,
1918 * as virtual wire B is little complex (need to configure both
1919 * IOAPIC RTE aswell as interrupt-remapping table entry).
1920 * As this gets called during crash dump, keep this simple for now.
1922 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
1923 struct IO_APIC_route_entry entry
;
1925 memset(&entry
, 0, sizeof(entry
));
1926 entry
.mask
= 0; /* Enabled */
1927 entry
.trigger
= 0; /* Edge */
1929 entry
.polarity
= 0; /* High */
1930 entry
.delivery_status
= 0;
1931 entry
.dest_mode
= 0; /* Physical */
1932 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1934 entry
.dest
= read_apic_id();
1937 * Add it to the IO-APIC irq-routing table:
1939 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1943 * Use virtual wire A mode when interrupt remapping is enabled.
1945 if (cpu_has_apic
|| apic_from_smp_config())
1946 disconnect_bsp_APIC(!intr_remapping_enabled
&&
1947 ioapic_i8259
.pin
!= -1);
1950 #ifdef CONFIG_X86_32
1952 * function to set the IO-APIC physical IDs based on the
1953 * values stored in the MPC table.
1955 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1957 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
1959 union IO_APIC_reg_00 reg_00
;
1960 physid_mask_t phys_id_present_map
;
1963 unsigned char old_id
;
1964 unsigned long flags
;
1967 * This is broken; anything with a real cpu count has to
1968 * circumvent this idiocy regardless.
1970 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
1973 * Set the IOAPIC ID to the value stored in the MPC table.
1975 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
1977 /* Read the register 0 value */
1978 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1979 reg_00
.raw
= io_apic_read(apic_id
, 0);
1980 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1982 old_id
= mp_ioapics
[apic_id
].apicid
;
1984 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
1985 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1986 apic_id
, mp_ioapics
[apic_id
].apicid
);
1987 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1989 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
1993 * Sanity check, is the ID really free? Every APIC in a
1994 * system must have a unique ID or we get lots of nice
1995 * 'stuck on smp_invalidate_needed IPI wait' messages.
1997 if (apic
->check_apicid_used(&phys_id_present_map
,
1998 mp_ioapics
[apic_id
].apicid
)) {
1999 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2000 apic_id
, mp_ioapics
[apic_id
].apicid
);
2001 for (i
= 0; i
< get_physical_broadcast(); i
++)
2002 if (!physid_isset(i
, phys_id_present_map
))
2004 if (i
>= get_physical_broadcast())
2005 panic("Max APIC ID exceeded!\n");
2006 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2008 physid_set(i
, phys_id_present_map
);
2009 mp_ioapics
[apic_id
].apicid
= i
;
2012 apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
, &tmp
);
2013 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2014 "phys_id_present_map\n",
2015 mp_ioapics
[apic_id
].apicid
);
2016 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2020 * We need to adjust the IRQ routing table
2021 * if the ID changed.
2023 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2024 for (i
= 0; i
< mp_irq_entries
; i
++)
2025 if (mp_irqs
[i
].dstapic
== old_id
)
2027 = mp_ioapics
[apic_id
].apicid
;
2030 * Update the ID register according to the right value
2031 * from the MPC table if they are different.
2033 if (mp_ioapics
[apic_id
].apicid
== reg_00
.bits
.ID
)
2036 apic_printk(APIC_VERBOSE
, KERN_INFO
2037 "...changing IO-APIC physical APIC ID to %d ...",
2038 mp_ioapics
[apic_id
].apicid
);
2040 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2041 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2042 io_apic_write(apic_id
, 0, reg_00
.raw
);
2043 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2048 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2049 reg_00
.raw
= io_apic_read(apic_id
, 0);
2050 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2051 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2052 printk("could not set ID!\n");
2054 apic_printk(APIC_VERBOSE
, " ok.\n");
2058 void __init
setup_ioapic_ids_from_mpc(void)
2064 * Don't check I/O APIC IDs for xAPIC systems. They have
2065 * no meaning without the serial APIC bus.
2067 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2068 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2070 setup_ioapic_ids_from_mpc_nocheck();
2074 int no_timer_check __initdata
;
2076 static int __init
notimercheck(char *s
)
2081 __setup("no_timer_check", notimercheck
);
2084 * There is a nasty bug in some older SMP boards, their mptable lies
2085 * about the timer IRQ. We do the following to work around the situation:
2087 * - timer IRQ defaults to IO-APIC IRQ
2088 * - if this function detects that timer IRQs are defunct, then we fall
2089 * back to ISA timer IRQs
2091 static int __init
timer_irq_works(void)
2093 unsigned long t1
= jiffies
;
2094 unsigned long flags
;
2099 local_save_flags(flags
);
2101 /* Let ten ticks pass... */
2102 mdelay((10 * 1000) / HZ
);
2103 local_irq_restore(flags
);
2106 * Expect a few ticks at least, to be sure some possible
2107 * glue logic does not lock up after one or two first
2108 * ticks in a non-ExtINT mode. Also the local APIC
2109 * might have cached one ExtINT interrupt. Finally, at
2110 * least one tick may be lost due to delays.
2114 if (time_after(jiffies
, t1
+ 4))
2120 * In the SMP+IOAPIC case it might happen that there are an unspecified
2121 * number of pending IRQ events unhandled. These cases are very rare,
2122 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2123 * better to do it this way as thus we do not have to be aware of
2124 * 'pending' interrupts in the IRQ path, except at this point.
2127 * Edge triggered needs to resend any interrupt
2128 * that was delayed but this is now handled in the device
2133 * Starting up a edge-triggered IO-APIC interrupt is
2134 * nasty - we need to make sure that we get the edge.
2135 * If it is already asserted for some reason, we need
2136 * return 1 to indicate that is was pending.
2138 * This is not complete - we should be able to fake
2139 * an edge even if it isn't on the 8259A...
2142 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
2144 int was_pending
= 0, irq
= data
->irq
;
2145 unsigned long flags
;
2147 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2148 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2149 legacy_pic
->mask(irq
);
2150 if (legacy_pic
->irq_pending(irq
))
2153 __unmask_ioapic(data
->chip_data
);
2154 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2159 static int ioapic_retrigger_irq(struct irq_data
*data
)
2161 struct irq_cfg
*cfg
= data
->chip_data
;
2162 unsigned long flags
;
2164 raw_spin_lock_irqsave(&vector_lock
, flags
);
2165 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2166 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2172 * Level and edge triggered IO-APIC interrupts need different handling,
2173 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2174 * handled with the level-triggered descriptor, but that one has slightly
2175 * more overhead. Level-triggered interrupts cannot be handled with the
2176 * edge-triggered handler, without risking IRQ storms and other ugly
2181 void send_cleanup_vector(struct irq_cfg
*cfg
)
2183 cpumask_var_t cleanup_mask
;
2185 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2187 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2188 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2190 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2191 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2192 free_cpumask_var(cleanup_mask
);
2194 cfg
->move_in_progress
= 0;
2197 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2200 struct irq_pin_list
*entry
;
2201 u8 vector
= cfg
->vector
;
2203 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2209 * With interrupt-remapping, destination information comes
2210 * from interrupt-remapping table entry.
2212 if (!irq_remapped(cfg
))
2213 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2214 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2215 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2217 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2222 * Either sets data->affinity to a valid value, and returns
2223 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2224 * leaves data->affinity untouched.
2226 int __ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2227 unsigned int *dest_id
)
2229 struct irq_cfg
*cfg
= data
->chip_data
;
2231 if (!cpumask_intersects(mask
, cpu_online_mask
))
2234 if (assign_irq_vector(data
->irq
, data
->chip_data
, mask
))
2237 cpumask_copy(data
->affinity
, mask
);
2239 *dest_id
= apic
->cpu_mask_to_apicid_and(mask
, cfg
->domain
);
2244 ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2247 unsigned int dest
, irq
= data
->irq
;
2248 unsigned long flags
;
2251 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2252 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
2254 /* Only the high 8 bits are valid. */
2255 dest
= SET_APIC_LOGICAL_ID(dest
);
2256 __target_IO_APIC_irq(irq
, dest
, data
->chip_data
);
2258 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2262 #ifdef CONFIG_INTR_REMAP
2265 * Migrate the IO-APIC irq in the presence of intr-remapping.
2267 * For both level and edge triggered, irq migration is a simple atomic
2268 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2270 * For level triggered, we eliminate the io-apic RTE modification (with the
2271 * updated vector information), by using a virtual vector (io-apic pin number).
2272 * Real vector that is used for interrupting cpu will be coming from
2273 * the interrupt-remapping table entry.
2276 ir_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2279 struct irq_cfg
*cfg
= data
->chip_data
;
2280 unsigned int dest
, irq
= data
->irq
;
2283 if (!cpumask_intersects(mask
, cpu_online_mask
))
2286 if (get_irte(irq
, &irte
))
2289 if (assign_irq_vector(irq
, cfg
, mask
))
2292 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2294 irte
.vector
= cfg
->vector
;
2295 irte
.dest_id
= IRTE_DEST(dest
);
2298 * Modified the IRTE and flushes the Interrupt entry cache.
2300 modify_irte(irq
, &irte
);
2302 if (cfg
->move_in_progress
)
2303 send_cleanup_vector(cfg
);
2305 cpumask_copy(data
->affinity
, mask
);
2311 ir_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2318 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2320 unsigned vector
, me
;
2326 me
= smp_processor_id();
2327 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2330 struct irq_desc
*desc
;
2331 struct irq_cfg
*cfg
;
2332 irq
= __this_cpu_read(vector_irq
[vector
]);
2337 desc
= irq_to_desc(irq
);
2342 raw_spin_lock(&desc
->lock
);
2345 * Check if the irq migration is in progress. If so, we
2346 * haven't received the cleanup request yet for this irq.
2348 if (cfg
->move_in_progress
)
2351 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2354 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2356 * Check if the vector that needs to be cleanedup is
2357 * registered at the cpu's IRR. If so, then this is not
2358 * the best time to clean it up. Lets clean it up in the
2359 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2362 if (irr
& (1 << (vector
% 32))) {
2363 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2366 __this_cpu_write(vector_irq
[vector
], -1);
2368 raw_spin_unlock(&desc
->lock
);
2374 static void __irq_complete_move(struct irq_cfg
*cfg
, unsigned vector
)
2378 if (likely(!cfg
->move_in_progress
))
2381 me
= smp_processor_id();
2383 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2384 send_cleanup_vector(cfg
);
2387 static void irq_complete_move(struct irq_cfg
*cfg
)
2389 __irq_complete_move(cfg
, ~get_irq_regs()->orig_ax
);
2392 void irq_force_complete_move(int irq
)
2394 struct irq_cfg
*cfg
= get_irq_chip_data(irq
);
2399 __irq_complete_move(cfg
, cfg
->vector
);
2402 static inline void irq_complete_move(struct irq_cfg
*cfg
) { }
2405 static void ack_apic_edge(struct irq_data
*data
)
2407 irq_complete_move(data
->chip_data
);
2408 move_native_irq(data
->irq
);
2412 atomic_t irq_mis_count
;
2415 * IO-APIC versions below 0x20 don't support EOI register.
2416 * For the record, here is the information about various versions:
2418 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2419 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2422 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2423 * version as 0x2. This is an error with documentation and these ICH chips
2424 * use io-apic's of version 0x20.
2426 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2427 * Otherwise, we simulate the EOI message manually by changing the trigger
2428 * mode to edge and then back to level, with RTE being masked during this.
2430 static void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2432 struct irq_pin_list
*entry
;
2433 unsigned long flags
;
2435 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2436 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2437 if (mp_ioapics
[entry
->apic
].apicver
>= 0x20) {
2439 * Intr-remapping uses pin number as the virtual vector
2440 * in the RTE. Actual vector is programmed in
2441 * intr-remapping table entry. Hence for the io-apic
2442 * EOI we use the pin number.
2444 if (irq_remapped(cfg
))
2445 io_apic_eoi(entry
->apic
, entry
->pin
);
2447 io_apic_eoi(entry
->apic
, cfg
->vector
);
2449 __mask_and_edge_IO_APIC_irq(entry
);
2450 __unmask_and_level_IO_APIC_irq(entry
);
2453 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2456 static void ack_apic_level(struct irq_data
*data
)
2458 struct irq_cfg
*cfg
= data
->chip_data
;
2459 int i
, do_unmask_irq
= 0, irq
= data
->irq
;
2462 irq_complete_move(cfg
);
2463 #ifdef CONFIG_GENERIC_PENDING_IRQ
2464 /* If we are moving the irq we need to mask it */
2465 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
2472 * It appears there is an erratum which affects at least version 0x11
2473 * of I/O APIC (that's the 82093AA and cores integrated into various
2474 * chipsets). Under certain conditions a level-triggered interrupt is
2475 * erroneously delivered as edge-triggered one but the respective IRR
2476 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2477 * message but it will never arrive and further interrupts are blocked
2478 * from the source. The exact reason is so far unknown, but the
2479 * phenomenon was observed when two consecutive interrupt requests
2480 * from a given source get delivered to the same CPU and the source is
2481 * temporarily disabled in between.
2483 * A workaround is to simulate an EOI message manually. We achieve it
2484 * by setting the trigger mode to edge and then to level when the edge
2485 * trigger mode gets detected in the TMR of a local APIC for a
2486 * level-triggered interrupt. We mask the source for the time of the
2487 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2488 * The idea is from Manfred Spraul. --macro
2490 * Also in the case when cpu goes offline, fixup_irqs() will forward
2491 * any unhandled interrupt on the offlined cpu to the new cpu
2492 * destination that is handling the corresponding interrupt. This
2493 * interrupt forwarding is done via IPI's. Hence, in this case also
2494 * level-triggered io-apic interrupt will be seen as an edge
2495 * interrupt in the IRR. And we can't rely on the cpu's EOI
2496 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2497 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2498 * supporting EOI register, we do an explicit EOI to clear the
2499 * remote IRR and on IO-APIC's which don't have an EOI register,
2500 * we use the above logic (mask+edge followed by unmask+level) from
2501 * Manfred Spraul to clear the remote IRR.
2504 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2507 * We must acknowledge the irq before we move it or the acknowledge will
2508 * not propagate properly.
2513 * Tail end of clearing remote IRR bit (either by delivering the EOI
2514 * message via io-apic EOI register write or simulating it using
2515 * mask+edge followed by unnask+level logic) manually when the
2516 * level triggered interrupt is seen as the edge triggered interrupt
2519 if (!(v
& (1 << (i
& 0x1f)))) {
2520 atomic_inc(&irq_mis_count
);
2522 eoi_ioapic_irq(irq
, cfg
);
2525 /* Now we can move and renable the irq */
2526 if (unlikely(do_unmask_irq
)) {
2527 /* Only migrate the irq if the ack has been received.
2529 * On rare occasions the broadcast level triggered ack gets
2530 * delayed going to ioapics, and if we reprogram the
2531 * vector while Remote IRR is still set the irq will never
2534 * To prevent this scenario we read the Remote IRR bit
2535 * of the ioapic. This has two effects.
2536 * - On any sane system the read of the ioapic will
2537 * flush writes (and acks) going to the ioapic from
2539 * - We get to see if the ACK has actually been delivered.
2541 * Based on failed experiments of reprogramming the
2542 * ioapic entry from outside of irq context starting
2543 * with masking the ioapic entry and then polling until
2544 * Remote IRR was clear before reprogramming the
2545 * ioapic I don't trust the Remote IRR bit to be
2546 * completey accurate.
2548 * However there appears to be no other way to plug
2549 * this race, so if the Remote IRR bit is not
2550 * accurate and is causing problems then it is a hardware bug
2551 * and you can go talk to the chipset vendor about it.
2553 if (!io_apic_level_ack_pending(cfg
))
2554 move_masked_irq(irq
);
2559 #ifdef CONFIG_INTR_REMAP
2560 static void ir_ack_apic_edge(struct irq_data
*data
)
2565 static void ir_ack_apic_level(struct irq_data
*data
)
2568 eoi_ioapic_irq(data
->irq
, data
->chip_data
);
2570 #endif /* CONFIG_INTR_REMAP */
2572 static struct irq_chip ioapic_chip __read_mostly
= {
2574 .irq_startup
= startup_ioapic_irq
,
2575 .irq_mask
= mask_ioapic_irq
,
2576 .irq_unmask
= unmask_ioapic_irq
,
2577 .irq_ack
= ack_apic_edge
,
2578 .irq_eoi
= ack_apic_level
,
2580 .irq_set_affinity
= ioapic_set_affinity
,
2582 .irq_retrigger
= ioapic_retrigger_irq
,
2585 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2586 .name
= "IR-IO-APIC",
2587 .irq_startup
= startup_ioapic_irq
,
2588 .irq_mask
= mask_ioapic_irq
,
2589 .irq_unmask
= unmask_ioapic_irq
,
2590 #ifdef CONFIG_INTR_REMAP
2591 .irq_ack
= ir_ack_apic_edge
,
2592 .irq_eoi
= ir_ack_apic_level
,
2594 .irq_set_affinity
= ir_ioapic_set_affinity
,
2597 .irq_retrigger
= ioapic_retrigger_irq
,
2600 static inline void init_IO_APIC_traps(void)
2602 struct irq_cfg
*cfg
;
2606 * NOTE! The local APIC isn't very good at handling
2607 * multiple interrupts at the same interrupt level.
2608 * As the interrupt level is determined by taking the
2609 * vector number and shifting that right by 4, we
2610 * want to spread these out a bit so that they don't
2611 * all fall in the same interrupt level.
2613 * Also, we've got to be careful not to trash gate
2614 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2616 for_each_active_irq(irq
) {
2617 cfg
= get_irq_chip_data(irq
);
2618 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2620 * Hmm.. We don't have an entry for this,
2621 * so default to an old-fashioned 8259
2622 * interrupt if we can..
2624 if (irq
< legacy_pic
->nr_legacy_irqs
)
2625 legacy_pic
->make_irq(irq
);
2627 /* Strange. Oh, well.. */
2628 set_irq_chip(irq
, &no_irq_chip
);
2634 * The local APIC irq-chip implementation:
2637 static void mask_lapic_irq(struct irq_data
*data
)
2641 v
= apic_read(APIC_LVT0
);
2642 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2645 static void unmask_lapic_irq(struct irq_data
*data
)
2649 v
= apic_read(APIC_LVT0
);
2650 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2653 static void ack_lapic_irq(struct irq_data
*data
)
2658 static struct irq_chip lapic_chip __read_mostly
= {
2659 .name
= "local-APIC",
2660 .irq_mask
= mask_lapic_irq
,
2661 .irq_unmask
= unmask_lapic_irq
,
2662 .irq_ack
= ack_lapic_irq
,
2665 static void lapic_register_intr(int irq
)
2667 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2668 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2673 * This looks a bit hackish but it's about the only one way of sending
2674 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2675 * not support the ExtINT mode, unfortunately. We need to send these
2676 * cycles as some i82489DX-based boards have glue logic that keeps the
2677 * 8259A interrupt line asserted until INTA. --macro
2679 static inline void __init
unlock_ExtINT_logic(void)
2682 struct IO_APIC_route_entry entry0
, entry1
;
2683 unsigned char save_control
, save_freq_select
;
2685 pin
= find_isa_irq_pin(8, mp_INT
);
2690 apic
= find_isa_irq_apic(8, mp_INT
);
2696 entry0
= ioapic_read_entry(apic
, pin
);
2697 clear_IO_APIC_pin(apic
, pin
);
2699 memset(&entry1
, 0, sizeof(entry1
));
2701 entry1
.dest_mode
= 0; /* physical delivery */
2702 entry1
.mask
= 0; /* unmask IRQ now */
2703 entry1
.dest
= hard_smp_processor_id();
2704 entry1
.delivery_mode
= dest_ExtINT
;
2705 entry1
.polarity
= entry0
.polarity
;
2709 ioapic_write_entry(apic
, pin
, entry1
);
2711 save_control
= CMOS_READ(RTC_CONTROL
);
2712 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2713 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2715 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2720 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2724 CMOS_WRITE(save_control
, RTC_CONTROL
);
2725 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2726 clear_IO_APIC_pin(apic
, pin
);
2728 ioapic_write_entry(apic
, pin
, entry0
);
2731 static int disable_timer_pin_1 __initdata
;
2732 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2733 static int __init
disable_timer_pin_setup(char *arg
)
2735 disable_timer_pin_1
= 1;
2738 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2740 int timer_through_8259 __initdata
;
2743 * This code may look a bit paranoid, but it's supposed to cooperate with
2744 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2745 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2746 * fanatically on his truly buggy board.
2748 * FIXME: really need to revamp this for all platforms.
2750 static inline void __init
check_timer(void)
2752 struct irq_cfg
*cfg
= get_irq_chip_data(0);
2753 int node
= cpu_to_node(0);
2754 int apic1
, pin1
, apic2
, pin2
;
2755 unsigned long flags
;
2758 local_irq_save(flags
);
2761 * get/set the timer IRQ vector:
2763 legacy_pic
->mask(0);
2764 assign_irq_vector(0, cfg
, apic
->target_cpus());
2767 * As IRQ0 is to be enabled in the 8259A, the virtual
2768 * wire has to be disabled in the local APIC. Also
2769 * timer interrupts need to be acknowledged manually in
2770 * the 8259A for the i82489DX when using the NMI
2771 * watchdog as that APIC treats NMIs as level-triggered.
2772 * The AEOI mode will finish them in the 8259A
2775 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2776 legacy_pic
->init(1);
2778 pin1
= find_isa_irq_pin(0, mp_INT
);
2779 apic1
= find_isa_irq_apic(0, mp_INT
);
2780 pin2
= ioapic_i8259
.pin
;
2781 apic2
= ioapic_i8259
.apic
;
2783 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2784 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2785 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2788 * Some BIOS writers are clueless and report the ExtINTA
2789 * I/O APIC input from the cascaded 8259A as the timer
2790 * interrupt input. So just in case, if only one pin
2791 * was found above, try it both directly and through the
2795 if (intr_remapping_enabled
)
2796 panic("BIOS bug: timer not connected to IO-APIC");
2800 } else if (pin2
== -1) {
2807 * Ok, does IRQ0 through the IOAPIC work?
2810 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2811 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2813 /* for edge trigger, setup_ioapic_irq already
2814 * leave it unmasked.
2815 * so only need to unmask if it is level-trigger
2816 * do we really have level trigger timer?
2819 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2820 if (idx
!= -1 && irq_trigger(idx
))
2823 if (timer_irq_works()) {
2824 if (disable_timer_pin_1
> 0)
2825 clear_IO_APIC_pin(0, pin1
);
2828 if (intr_remapping_enabled
)
2829 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2830 local_irq_disable();
2831 clear_IO_APIC_pin(apic1
, pin1
);
2833 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2834 "8254 timer not connected to IO-APIC\n");
2836 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2837 "(IRQ0) through the 8259A ...\n");
2838 apic_printk(APIC_QUIET
, KERN_INFO
2839 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2841 * legacy devices should be connected to IO APIC #0
2843 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2844 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2845 legacy_pic
->unmask(0);
2846 if (timer_irq_works()) {
2847 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2848 timer_through_8259
= 1;
2852 * Cleanup, just in case ...
2854 local_irq_disable();
2855 legacy_pic
->mask(0);
2856 clear_IO_APIC_pin(apic2
, pin2
);
2857 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2860 apic_printk(APIC_QUIET
, KERN_INFO
2861 "...trying to set up timer as Virtual Wire IRQ...\n");
2863 lapic_register_intr(0);
2864 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2865 legacy_pic
->unmask(0);
2867 if (timer_irq_works()) {
2868 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2871 local_irq_disable();
2872 legacy_pic
->mask(0);
2873 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2874 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2876 apic_printk(APIC_QUIET
, KERN_INFO
2877 "...trying to set up timer as ExtINT IRQ...\n");
2879 legacy_pic
->init(0);
2880 legacy_pic
->make_irq(0);
2881 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2883 unlock_ExtINT_logic();
2885 if (timer_irq_works()) {
2886 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2889 local_irq_disable();
2890 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2891 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2892 "report. Then try booting with the 'noapic' option.\n");
2894 local_irq_restore(flags
);
2898 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2899 * to devices. However there may be an I/O APIC pin available for
2900 * this interrupt regardless. The pin may be left unconnected, but
2901 * typically it will be reused as an ExtINT cascade interrupt for
2902 * the master 8259A. In the MPS case such a pin will normally be
2903 * reported as an ExtINT interrupt in the MP table. With ACPI
2904 * there is no provision for ExtINT interrupts, and in the absence
2905 * of an override it would be treated as an ordinary ISA I/O APIC
2906 * interrupt, that is edge-triggered and unmasked by default. We
2907 * used to do this, but it caused problems on some systems because
2908 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2909 * the same ExtINT cascade interrupt to drive the local APIC of the
2910 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2911 * the I/O APIC in all cases now. No actual device should request
2912 * it anyway. --macro
2914 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2916 void __init
setup_IO_APIC(void)
2920 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2922 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
2924 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2926 * Set up IO-APIC IRQ routing.
2928 x86_init
.mpparse
.setup_ioapic_ids();
2931 setup_IO_APIC_irqs();
2932 init_IO_APIC_traps();
2933 if (legacy_pic
->nr_legacy_irqs
)
2938 * Called after all the initialization is done. If we didnt find any
2939 * APIC bugs then we can allow the modify fast path
2942 static int __init
io_apic_bug_finalize(void)
2944 if (sis_apic_bug
== -1)
2949 late_initcall(io_apic_bug_finalize
);
2951 struct sysfs_ioapic_data
{
2952 struct sys_device dev
;
2953 struct IO_APIC_route_entry entry
[0];
2955 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2957 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2959 struct IO_APIC_route_entry
*entry
;
2960 struct sysfs_ioapic_data
*data
;
2963 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2964 entry
= data
->entry
;
2965 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2966 *entry
= ioapic_read_entry(dev
->id
, i
);
2971 static int ioapic_resume(struct sys_device
*dev
)
2973 struct IO_APIC_route_entry
*entry
;
2974 struct sysfs_ioapic_data
*data
;
2975 unsigned long flags
;
2976 union IO_APIC_reg_00 reg_00
;
2979 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2980 entry
= data
->entry
;
2982 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2983 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2984 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
2985 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
2986 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2988 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2989 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2990 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2995 static struct sysdev_class ioapic_sysdev_class
= {
2997 .suspend
= ioapic_suspend
,
2998 .resume
= ioapic_resume
,
3001 static int __init
ioapic_init_sysfs(void)
3003 struct sys_device
* dev
;
3006 error
= sysdev_class_register(&ioapic_sysdev_class
);
3010 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3011 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3012 * sizeof(struct IO_APIC_route_entry
);
3013 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3014 if (!mp_ioapic_data
[i
]) {
3015 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3018 dev
= &mp_ioapic_data
[i
]->dev
;
3020 dev
->cls
= &ioapic_sysdev_class
;
3021 error
= sysdev_register(dev
);
3023 kfree(mp_ioapic_data
[i
]);
3024 mp_ioapic_data
[i
] = NULL
;
3025 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3033 device_initcall(ioapic_init_sysfs
);
3036 * Dynamic irq allocate and deallocation
3038 unsigned int create_irq_nr(unsigned int from
, int node
)
3040 struct irq_cfg
*cfg
;
3041 unsigned long flags
;
3042 unsigned int ret
= 0;
3045 if (from
< nr_irqs_gsi
)
3048 irq
= alloc_irq_from(from
, node
);
3051 cfg
= alloc_irq_cfg(irq
, node
);
3053 free_irq_at(irq
, NULL
);
3057 raw_spin_lock_irqsave(&vector_lock
, flags
);
3058 if (!__assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
3060 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3063 set_irq_chip_data(irq
, cfg
);
3064 irq_clear_status_flags(irq
, IRQ_NOREQUEST
);
3066 free_irq_at(irq
, cfg
);
3071 int create_irq(void)
3073 int node
= cpu_to_node(0);
3074 unsigned int irq_want
;
3077 irq_want
= nr_irqs_gsi
;
3078 irq
= create_irq_nr(irq_want
, node
);
3086 void destroy_irq(unsigned int irq
)
3088 struct irq_cfg
*cfg
= get_irq_chip_data(irq
);
3089 unsigned long flags
;
3091 irq_set_status_flags(irq
, IRQ_NOREQUEST
|IRQ_NOPROBE
);
3093 if (irq_remapped(cfg
))
3095 raw_spin_lock_irqsave(&vector_lock
, flags
);
3096 __clear_irq_vector(irq
, cfg
);
3097 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3098 free_irq_at(irq
, cfg
);
3102 * MSI message composition
3104 #ifdef CONFIG_PCI_MSI
3105 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3106 struct msi_msg
*msg
, u8 hpet_id
)
3108 struct irq_cfg
*cfg
;
3116 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3120 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3122 if (irq_remapped(get_irq_chip_data(irq
))) {
3127 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3128 BUG_ON(ir_index
== -1);
3130 prepare_irte(&irte
, cfg
->vector
, dest
);
3132 /* Set source-id of interrupt request */
3134 set_msi_sid(&irte
, pdev
);
3136 set_hpet_sid(&irte
, hpet_id
);
3138 modify_irte(irq
, &irte
);
3140 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3141 msg
->data
= sub_handle
;
3142 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3144 MSI_ADDR_IR_INDEX1(ir_index
) |
3145 MSI_ADDR_IR_INDEX2(ir_index
);
3147 if (x2apic_enabled())
3148 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3149 MSI_ADDR_EXT_DEST_ID(dest
);
3151 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3155 ((apic
->irq_dest_mode
== 0) ?
3156 MSI_ADDR_DEST_MODE_PHYSICAL
:
3157 MSI_ADDR_DEST_MODE_LOGICAL
) |
3158 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3159 MSI_ADDR_REDIRECTION_CPU
:
3160 MSI_ADDR_REDIRECTION_LOWPRI
) |
3161 MSI_ADDR_DEST_ID(dest
);
3164 MSI_DATA_TRIGGER_EDGE
|
3165 MSI_DATA_LEVEL_ASSERT
|
3166 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3167 MSI_DATA_DELIVERY_FIXED
:
3168 MSI_DATA_DELIVERY_LOWPRI
) |
3169 MSI_DATA_VECTOR(cfg
->vector
);
3176 msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3178 struct irq_cfg
*cfg
= data
->chip_data
;
3182 if (__ioapic_set_affinity(data
, mask
, &dest
))
3185 __get_cached_msi_msg(data
->msi_desc
, &msg
);
3187 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3188 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3189 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3190 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3192 __write_msi_msg(data
->msi_desc
, &msg
);
3196 #ifdef CONFIG_INTR_REMAP
3198 * Migrate the MSI irq to another cpumask. This migration is
3199 * done in the process context using interrupt-remapping hardware.
3202 ir_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3205 struct irq_cfg
*cfg
= data
->chip_data
;
3206 unsigned int dest
, irq
= data
->irq
;
3209 if (get_irte(irq
, &irte
))
3212 if (__ioapic_set_affinity(data
, mask
, &dest
))
3215 irte
.vector
= cfg
->vector
;
3216 irte
.dest_id
= IRTE_DEST(dest
);
3219 * atomically update the IRTE with the new destination and vector.
3221 modify_irte(irq
, &irte
);
3224 * After this point, all the interrupts will start arriving
3225 * at the new destination. So, time to cleanup the previous
3226 * vector allocation.
3228 if (cfg
->move_in_progress
)
3229 send_cleanup_vector(cfg
);
3235 #endif /* CONFIG_SMP */
3238 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3239 * which implement the MSI or MSI-X Capability Structure.
3241 static struct irq_chip msi_chip
= {
3243 .irq_unmask
= unmask_msi_irq
,
3244 .irq_mask
= mask_msi_irq
,
3245 .irq_ack
= ack_apic_edge
,
3247 .irq_set_affinity
= msi_set_affinity
,
3249 .irq_retrigger
= ioapic_retrigger_irq
,
3252 static struct irq_chip msi_ir_chip
= {
3253 .name
= "IR-PCI-MSI",
3254 .irq_unmask
= unmask_msi_irq
,
3255 .irq_mask
= mask_msi_irq
,
3256 #ifdef CONFIG_INTR_REMAP
3257 .irq_ack
= ir_ack_apic_edge
,
3259 .irq_set_affinity
= ir_msi_set_affinity
,
3262 .irq_retrigger
= ioapic_retrigger_irq
,
3266 * Map the PCI dev to the corresponding remapping hardware unit
3267 * and allocate 'nvec' consecutive interrupt-remapping table entries
3270 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3272 struct intel_iommu
*iommu
;
3275 iommu
= map_dev_to_ir(dev
);
3278 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3282 index
= alloc_irte(iommu
, irq
, nvec
);
3285 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3292 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3297 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3301 set_irq_msi(irq
, msidesc
);
3302 write_msi_msg(irq
, &msg
);
3304 if (irq_remapped(get_irq_chip_data(irq
))) {
3305 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3306 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3308 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3310 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3315 int native_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3317 int node
, ret
, sub_handle
, index
= 0;
3318 unsigned int irq
, irq_want
;
3319 struct msi_desc
*msidesc
;
3320 struct intel_iommu
*iommu
= NULL
;
3322 /* x86 doesn't support multiple MSI yet */
3323 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3326 node
= dev_to_node(&dev
->dev
);
3327 irq_want
= nr_irqs_gsi
;
3329 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3330 irq
= create_irq_nr(irq_want
, node
);
3334 if (!intr_remapping_enabled
)
3339 * allocate the consecutive block of IRTE's
3342 index
= msi_alloc_irte(dev
, irq
, nvec
);
3348 iommu
= map_dev_to_ir(dev
);
3354 * setup the mapping between the irq and the IRTE
3355 * base index, the sub_handle pointing to the
3356 * appropriate interrupt remap table entry.
3358 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3361 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3373 void native_teardown_msi_irq(unsigned int irq
)
3378 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3381 dmar_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3384 struct irq_cfg
*cfg
= data
->chip_data
;
3385 unsigned int dest
, irq
= data
->irq
;
3388 if (__ioapic_set_affinity(data
, mask
, &dest
))
3391 dmar_msi_read(irq
, &msg
);
3393 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3394 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3395 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3396 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3397 msg
.address_hi
= MSI_ADDR_BASE_HI
| MSI_ADDR_EXT_DEST_ID(dest
);
3399 dmar_msi_write(irq
, &msg
);
3404 #endif /* CONFIG_SMP */
3406 static struct irq_chip dmar_msi_type
= {
3408 .irq_unmask
= dmar_msi_unmask
,
3409 .irq_mask
= dmar_msi_mask
,
3410 .irq_ack
= ack_apic_edge
,
3412 .irq_set_affinity
= dmar_msi_set_affinity
,
3414 .irq_retrigger
= ioapic_retrigger_irq
,
3417 int arch_setup_dmar_msi(unsigned int irq
)
3422 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3425 dmar_msi_write(irq
, &msg
);
3426 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3432 #ifdef CONFIG_HPET_TIMER
3435 static int hpet_msi_set_affinity(struct irq_data
*data
,
3436 const struct cpumask
*mask
, bool force
)
3438 struct irq_cfg
*cfg
= data
->chip_data
;
3442 if (__ioapic_set_affinity(data
, mask
, &dest
))
3445 hpet_msi_read(data
->handler_data
, &msg
);
3447 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3448 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3449 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3450 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3452 hpet_msi_write(data
->handler_data
, &msg
);
3457 #endif /* CONFIG_SMP */
3459 static struct irq_chip ir_hpet_msi_type
= {
3460 .name
= "IR-HPET_MSI",
3461 .irq_unmask
= hpet_msi_unmask
,
3462 .irq_mask
= hpet_msi_mask
,
3463 #ifdef CONFIG_INTR_REMAP
3464 .irq_ack
= ir_ack_apic_edge
,
3466 .irq_set_affinity
= ir_msi_set_affinity
,
3469 .irq_retrigger
= ioapic_retrigger_irq
,
3472 static struct irq_chip hpet_msi_type
= {
3474 .irq_unmask
= hpet_msi_unmask
,
3475 .irq_mask
= hpet_msi_mask
,
3476 .irq_ack
= ack_apic_edge
,
3478 .irq_set_affinity
= hpet_msi_set_affinity
,
3480 .irq_retrigger
= ioapic_retrigger_irq
,
3483 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3488 if (intr_remapping_enabled
) {
3489 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
3495 index
= alloc_irte(iommu
, irq
, 1);
3500 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3504 hpet_msi_write(get_irq_data(irq
), &msg
);
3505 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3506 if (irq_remapped(get_irq_chip_data(irq
)))
3507 set_irq_chip_and_handler_name(irq
, &ir_hpet_msi_type
,
3508 handle_edge_irq
, "edge");
3510 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
,
3511 handle_edge_irq
, "edge");
3517 #endif /* CONFIG_PCI_MSI */
3519 * Hypertransport interrupt support
3521 #ifdef CONFIG_HT_IRQ
3525 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3527 struct ht_irq_msg msg
;
3528 fetch_ht_irq_msg(irq
, &msg
);
3530 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3531 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3533 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3534 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3536 write_ht_irq_msg(irq
, &msg
);
3540 ht_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3542 struct irq_cfg
*cfg
= data
->chip_data
;
3545 if (__ioapic_set_affinity(data
, mask
, &dest
))
3548 target_ht_irq(data
->irq
, dest
, cfg
->vector
);
3554 static struct irq_chip ht_irq_chip
= {
3556 .irq_mask
= mask_ht_irq
,
3557 .irq_unmask
= unmask_ht_irq
,
3558 .irq_ack
= ack_apic_edge
,
3560 .irq_set_affinity
= ht_set_affinity
,
3562 .irq_retrigger
= ioapic_retrigger_irq
,
3565 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3567 struct irq_cfg
*cfg
;
3574 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3576 struct ht_irq_msg msg
;
3579 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3580 apic
->target_cpus());
3582 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3586 HT_IRQ_LOW_DEST_ID(dest
) |
3587 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3588 ((apic
->irq_dest_mode
== 0) ?
3589 HT_IRQ_LOW_DM_PHYSICAL
:
3590 HT_IRQ_LOW_DM_LOGICAL
) |
3591 HT_IRQ_LOW_RQEOI_EDGE
|
3592 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3593 HT_IRQ_LOW_MT_FIXED
:
3594 HT_IRQ_LOW_MT_ARBITRATED
) |
3595 HT_IRQ_LOW_IRQ_MASKED
;
3597 write_ht_irq_msg(irq
, &msg
);
3599 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3600 handle_edge_irq
, "edge");
3602 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3606 #endif /* CONFIG_HT_IRQ */
3608 int __init
io_apic_get_redir_entries (int ioapic
)
3610 union IO_APIC_reg_01 reg_01
;
3611 unsigned long flags
;
3613 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3614 reg_01
.raw
= io_apic_read(ioapic
, 1);
3615 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3617 /* The register returns the maximum index redir index
3618 * supported, which is one less than the total number of redir
3621 return reg_01
.bits
.entries
+ 1;
3624 static void __init
probe_nr_irqs_gsi(void)
3628 nr
= gsi_top
+ NR_IRQS_LEGACY
;
3629 if (nr
> nr_irqs_gsi
)
3632 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3635 int get_nr_irqs_gsi(void)
3640 #ifdef CONFIG_SPARSE_IRQ
3641 int __init
arch_probe_nr_irqs(void)
3645 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3646 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3648 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3649 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3651 * for MSI and HT dyn irq
3653 nr
+= nr_irqs_gsi
* 16;
3658 return NR_IRQS_LEGACY
;
3662 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3663 struct io_apic_irq_attr
*irq_attr
)
3665 struct irq_cfg
*cfg
;
3668 int trigger
, polarity
;
3670 ioapic
= irq_attr
->ioapic
;
3671 if (!IO_APIC_IRQ(irq
)) {
3672 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3678 node
= dev_to_node(dev
);
3680 node
= cpu_to_node(0);
3682 cfg
= alloc_irq_and_cfg_at(irq
, node
);
3686 pin
= irq_attr
->ioapic_pin
;
3687 trigger
= irq_attr
->trigger
;
3688 polarity
= irq_attr
->polarity
;
3691 * IRQs < 16 are already in the irq_2_pin[] map
3693 if (irq
>= legacy_pic
->nr_legacy_irqs
) {
3694 if (__add_pin_to_irq_node(cfg
, node
, ioapic
, pin
)) {
3695 printk(KERN_INFO
"can not add pin %d for irq %d\n",
3701 setup_ioapic_irq(ioapic
, pin
, irq
, cfg
, trigger
, polarity
);
3706 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3707 struct io_apic_irq_attr
*irq_attr
)
3711 * Avoid pin reprogramming. PRTs typically include entries
3712 * with redundant pin->gsi mappings (but unique PCI devices);
3713 * we only program the IOAPIC on the first.
3715 ioapic
= irq_attr
->ioapic
;
3716 pin
= irq_attr
->ioapic_pin
;
3717 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3718 pr_debug("Pin %d-%d already programmed\n",
3719 mp_ioapics
[ioapic
].apicid
, pin
);
3722 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3724 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3727 u8 __init
io_apic_unique_id(u8 id
)
3729 #ifdef CONFIG_X86_32
3730 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3731 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3732 return io_apic_get_unique_id(nr_ioapics
, id
);
3737 DECLARE_BITMAP(used
, 256);
3739 bitmap_zero(used
, 256);
3740 for (i
= 0; i
< nr_ioapics
; i
++) {
3741 struct mpc_ioapic
*ia
= &mp_ioapics
[i
];
3742 __set_bit(ia
->apicid
, used
);
3744 if (!test_bit(id
, used
))
3746 return find_first_zero_bit(used
, 256);
3750 #ifdef CONFIG_X86_32
3751 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3753 union IO_APIC_reg_00 reg_00
;
3754 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3756 unsigned long flags
;
3760 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3761 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3762 * supports up to 16 on one shared APIC bus.
3764 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3765 * advantage of new APIC bus architecture.
3768 if (physids_empty(apic_id_map
))
3769 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3771 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3772 reg_00
.raw
= io_apic_read(ioapic
, 0);
3773 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3775 if (apic_id
>= get_physical_broadcast()) {
3776 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3777 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3778 apic_id
= reg_00
.bits
.ID
;
3782 * Every APIC in a system must have a unique ID or we get lots of nice
3783 * 'stuck on smp_invalidate_needed IPI wait' messages.
3785 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
3787 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3788 if (!apic
->check_apicid_used(&apic_id_map
, i
))
3792 if (i
== get_physical_broadcast())
3793 panic("Max apic_id exceeded!\n");
3795 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3796 "trying %d\n", ioapic
, apic_id
, i
);
3801 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
3802 physids_or(apic_id_map
, apic_id_map
, tmp
);
3804 if (reg_00
.bits
.ID
!= apic_id
) {
3805 reg_00
.bits
.ID
= apic_id
;
3807 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3808 io_apic_write(ioapic
, 0, reg_00
.raw
);
3809 reg_00
.raw
= io_apic_read(ioapic
, 0);
3810 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3813 if (reg_00
.bits
.ID
!= apic_id
) {
3814 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3819 apic_printk(APIC_VERBOSE
, KERN_INFO
3820 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3826 int __init
io_apic_get_version(int ioapic
)
3828 union IO_APIC_reg_01 reg_01
;
3829 unsigned long flags
;
3831 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3832 reg_01
.raw
= io_apic_read(ioapic
, 1);
3833 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3835 return reg_01
.bits
.version
;
3838 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
3840 int ioapic
, pin
, idx
;
3842 if (skip_ioapic_setup
)
3845 ioapic
= mp_find_ioapic(gsi
);
3849 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3853 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
3857 *trigger
= irq_trigger(idx
);
3858 *polarity
= irq_polarity(idx
);
3863 * This function currently is only a helper for the i386 smp boot process where
3864 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3865 * so mask in all cases should simply be apic->target_cpus()
3868 void __init
setup_ioapic_dest(void)
3870 int pin
, ioapic
, irq
, irq_entry
;
3871 struct irq_desc
*desc
;
3872 const struct cpumask
*mask
;
3874 if (skip_ioapic_setup
== 1)
3877 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
3878 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3879 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3880 if (irq_entry
== -1)
3882 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3884 if ((ioapic
> 0) && (irq
> 16))
3887 desc
= irq_to_desc(irq
);
3890 * Honour affinities which have been set in early boot
3893 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
3894 mask
= desc
->irq_data
.affinity
;
3896 mask
= apic
->target_cpus();
3898 if (intr_remapping_enabled
)
3899 ir_ioapic_set_affinity(&desc
->irq_data
, mask
, false);
3901 ioapic_set_affinity(&desc
->irq_data
, mask
, false);
3907 #define IOAPIC_RESOURCE_NAME_SIZE 11
3909 static struct resource
*ioapic_resources
;
3911 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
3914 struct resource
*res
;
3918 if (nr_ioapics
<= 0)
3921 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3924 mem
= alloc_bootmem(n
);
3927 mem
+= sizeof(struct resource
) * nr_ioapics
;
3929 for (i
= 0; i
< nr_ioapics
; i
++) {
3931 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3932 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
3933 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3936 ioapic_resources
= res
;
3941 void __init
ioapic_and_gsi_init(void)
3943 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3944 struct resource
*ioapic_res
;
3947 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
3948 for (i
= 0; i
< nr_ioapics
; i
++) {
3949 if (smp_found_config
) {
3950 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
3951 #ifdef CONFIG_X86_32
3954 "WARNING: bogus zero IO-APIC "
3955 "address found in MPTABLE, "
3956 "disabling IO/APIC support!\n");
3957 smp_found_config
= 0;
3958 skip_ioapic_setup
= 1;
3959 goto fake_ioapic_page
;
3963 #ifdef CONFIG_X86_32
3966 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
3967 ioapic_phys
= __pa(ioapic_phys
);
3969 set_fixmap_nocache(idx
, ioapic_phys
);
3970 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
3971 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
3975 ioapic_res
->start
= ioapic_phys
;
3976 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
3980 probe_nr_irqs_gsi();
3983 void __init
ioapic_insert_resources(void)
3986 struct resource
*r
= ioapic_resources
;
3991 "IO APIC resources couldn't be allocated.\n");
3995 for (i
= 0; i
< nr_ioapics
; i
++) {
3996 insert_resource(&iomem_resource
, r
);
4001 int mp_find_ioapic(u32 gsi
)
4005 /* Find the IOAPIC that manages this GSI. */
4006 for (i
= 0; i
< nr_ioapics
; i
++) {
4007 if ((gsi
>= mp_gsi_routing
[i
].gsi_base
)
4008 && (gsi
<= mp_gsi_routing
[i
].gsi_end
))
4012 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
4016 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
4018 if (WARN_ON(ioapic
== -1))
4020 if (WARN_ON(gsi
> mp_gsi_routing
[ioapic
].gsi_end
))
4023 return gsi
- mp_gsi_routing
[ioapic
].gsi_base
;
4026 static int bad_ioapic(unsigned long address
)
4028 if (nr_ioapics
>= MAX_IO_APICS
) {
4029 printk(KERN_WARNING
"WARING: Max # of I/O APICs (%d) exceeded "
4030 "(found %d), skipping\n", MAX_IO_APICS
, nr_ioapics
);
4034 printk(KERN_WARNING
"WARNING: Bogus (zero) I/O APIC address"
4035 " found in table, skipping!\n");
4041 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
4046 if (bad_ioapic(address
))
4051 mp_ioapics
[idx
].type
= MP_IOAPIC
;
4052 mp_ioapics
[idx
].flags
= MPC_APIC_USABLE
;
4053 mp_ioapics
[idx
].apicaddr
= address
;
4055 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
4056 mp_ioapics
[idx
].apicid
= io_apic_unique_id(id
);
4057 mp_ioapics
[idx
].apicver
= io_apic_get_version(idx
);
4060 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4061 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4063 entries
= io_apic_get_redir_entries(idx
);
4064 mp_gsi_routing
[idx
].gsi_base
= gsi_base
;
4065 mp_gsi_routing
[idx
].gsi_end
= gsi_base
+ entries
- 1;
4068 * The number of IO-APIC IRQ registers (== #pins):
4070 nr_ioapic_registers
[idx
] = entries
;
4072 if (mp_gsi_routing
[idx
].gsi_end
>= gsi_top
)
4073 gsi_top
= mp_gsi_routing
[idx
].gsi_end
+ 1;
4075 printk(KERN_INFO
"IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4076 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].apicid
,
4077 mp_ioapics
[idx
].apicver
, mp_ioapics
[idx
].apicaddr
,
4078 mp_gsi_routing
[idx
].gsi_base
, mp_gsi_routing
[idx
].gsi_end
);
4083 /* Enable IOAPIC early just for system timer */
4084 void __init
pre_init_apic_IRQ0(void)
4086 struct irq_cfg
*cfg
;
4088 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4090 physid_set_mask_of_physid(boot_cpu_physical_apicid
,
4091 &phys_cpu_present_map
);
4093 /* Make sure the irq descriptor is set up */
4094 cfg
= alloc_irq_and_cfg_at(0, 0);
4098 add_pin_to_irq_node(cfg
, 0, 0, 0);
4099 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
4101 setup_ioapic_irq(0, 0, 0, cfg
, 0, 0);