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net-sched: cls_flow: add perturbation support
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / asm-x86 / processor.h
blob559105220a477e2be9cfbd87eee62d1cd68767c2
1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
18 #include <asm/page.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23
24 #include <linux/personality.h>
25 #include <linux/cpumask.h>
26 #include <linux/cache.h>
27 #include <linux/threads.h>
28 #include <linux/init.h>
29
30 /*
31 * Default implementation of macro that returns current
32 * instruction pointer ("program counter").
33 */
34 static inline void *current_text_addr(void)
35 {
36 void *pc;
37
38 asm volatile("mov $1f, %0; 1:":"=r" (pc));
39
40 return pc;
41 }
42
43 #ifdef CONFIG_X86_VSMP
44 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
45 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
46 #else
47 # define ARCH_MIN_TASKALIGN 16
48 # define ARCH_MIN_MMSTRUCT_ALIGN 0
49 #endif
50
51 /*
52 * CPU type and hardware bug flags. Kept separately for each CPU.
53 * Members of this structure are referenced in head.S, so think twice
54 * before touching them. [mj]
55 */
56
57 struct cpuinfo_x86 {
58 __u8 x86; /* CPU family */
59 __u8 x86_vendor; /* CPU vendor */
60 __u8 x86_model;
61 __u8 x86_mask;
62 #ifdef CONFIG_X86_32
63 char wp_works_ok; /* It doesn't on 386's */
64
65 /* Problems on some 486Dx4's and old 386's: */
66 char hlt_works_ok;
67 char hard_math;
68 char rfu;
69 char fdiv_bug;
70 char f00f_bug;
71 char coma_bug;
72 char pad0;
73 #else
74 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
75 int x86_tlbsize;
76 __u8 x86_virt_bits;
77 __u8 x86_phys_bits;
78 /* CPUID returned core id bits: */
79 __u8 x86_coreid_bits;
80 /* Max extended CPUID function supported: */
81 __u32 extended_cpuid_level;
82 #endif
83 /* Maximum supported CPUID level, -1=no CPUID: */
84 int cpuid_level;
85 __u32 x86_capability[NCAPINTS];
86 char x86_vendor_id[16];
87 char x86_model_id[64];
88 /* in KB - valid for CPUS which support this call: */
89 int x86_cache_size;
90 int x86_cache_alignment; /* In bytes */
91 int x86_power;
92 unsigned long loops_per_jiffy;
93 #ifdef CONFIG_SMP
94 /* cpus sharing the last level cache: */
95 cpumask_t llc_shared_map;
96 #endif
97 /* cpuid returned max cores value: */
98 u16 x86_max_cores;
99 u16 apicid;
100 u16 initial_apicid;
101 u16 x86_clflush_size;
102 #ifdef CONFIG_SMP
103 /* number of cores as seen by the OS: */
104 u16 booted_cores;
105 /* Physical processor id: */
106 u16 phys_proc_id;
107 /* Core id: */
108 u16 cpu_core_id;
109 /* Index into per_cpu list: */
110 u16 cpu_index;
111 #endif
112 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
113
114 #define X86_VENDOR_INTEL 0
115 #define X86_VENDOR_CYRIX 1
116 #define X86_VENDOR_AMD 2
117 #define X86_VENDOR_UMC 3
118 #define X86_VENDOR_CENTAUR 5
119 #define X86_VENDOR_TRANSMETA 7
120 #define X86_VENDOR_NSC 8
121 #define X86_VENDOR_NUM 9
122
123 #define X86_VENDOR_UNKNOWN 0xff
124
125 /*
126 * capabilities of CPUs
127 */
128 extern struct cpuinfo_x86 boot_cpu_data;
129 extern struct cpuinfo_x86 new_cpu_data;
130
131 extern struct tss_struct doublefault_tss;
132 extern __u32 cleared_cpu_caps[NCAPINTS];
133
134 #ifdef CONFIG_SMP
135 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
136 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
137 #define current_cpu_data cpu_data(smp_processor_id())
138 #else
139 #define cpu_data(cpu) boot_cpu_data
140 #define current_cpu_data boot_cpu_data
141 #endif
142
143 static inline int hlt_works(int cpu)
144 {
145 #ifdef CONFIG_X86_32
146 return cpu_data(cpu).hlt_works_ok;
147 #else
148 return 1;
149 #endif
150 }
151
152 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
153
154 extern void cpu_detect(struct cpuinfo_x86 *c);
155
156 extern void identify_cpu(struct cpuinfo_x86 *);
157 extern void identify_boot_cpu(void);
158 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
159 extern void print_cpu_info(struct cpuinfo_x86 *);
160 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
161 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
162 extern unsigned short num_cache_leaves;
163
164 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
165 extern void detect_ht(struct cpuinfo_x86 *c);
166 #else
167 static inline void detect_ht(struct cpuinfo_x86 *c) {}
168 #endif
169
170 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
171 unsigned int *ecx, unsigned int *edx)
172 {
173 /* ecx is often an input as well as an output. */
174 asm("cpuid"
175 : "=a" (*eax),
176 "=b" (*ebx),
177 "=c" (*ecx),
178 "=d" (*edx)
179 : "0" (*eax), "2" (*ecx));
180 }
181
182 static inline void load_cr3(pgd_t *pgdir)
183 {
184 write_cr3(__pa(pgdir));
185 }
186
187 #ifdef CONFIG_X86_32
188 /* This is the TSS defined by the hardware. */
189 struct x86_hw_tss {
190 unsigned short back_link, __blh;
191 unsigned long sp0;
192 unsigned short ss0, __ss0h;
193 unsigned long sp1;
194 /* ss1 caches MSR_IA32_SYSENTER_CS: */
195 unsigned short ss1, __ss1h;
196 unsigned long sp2;
197 unsigned short ss2, __ss2h;
198 unsigned long __cr3;
199 unsigned long ip;
200 unsigned long flags;
201 unsigned long ax;
202 unsigned long cx;
203 unsigned long dx;
204 unsigned long bx;
205 unsigned long sp;
206 unsigned long bp;
207 unsigned long si;
208 unsigned long di;
209 unsigned short es, __esh;
210 unsigned short cs, __csh;
211 unsigned short ss, __ssh;
212 unsigned short ds, __dsh;
213 unsigned short fs, __fsh;
214 unsigned short gs, __gsh;
215 unsigned short ldt, __ldth;
216 unsigned short trace;
217 unsigned short io_bitmap_base;
218
219 } __attribute__((packed));
220 #else
221 struct x86_hw_tss {
222 u32 reserved1;
223 u64 sp0;
224 u64 sp1;
225 u64 sp2;
226 u64 reserved2;
227 u64 ist[7];
228 u32 reserved3;
229 u32 reserved4;
230 u16 reserved5;
231 u16 io_bitmap_base;
232
233 } __attribute__((packed)) ____cacheline_aligned;
234 #endif
235
236 /*
237 * IO-bitmap sizes:
238 */
239 #define IO_BITMAP_BITS 65536
240 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
241 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
242 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
243 #define INVALID_IO_BITMAP_OFFSET 0x8000
244 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
245
246 struct tss_struct {
247 /*
248 * The hardware state:
249 */
250 struct x86_hw_tss x86_tss;
251
252 /*
253 * The extra 1 is there because the CPU will access an
254 * additional byte beyond the end of the IO permission
255 * bitmap. The extra byte must be all 1 bits, and must
256 * be within the limit.
257 */
258 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
259 /*
260 * Cache the current maximum and the last task that used the bitmap:
261 */
262 unsigned long io_bitmap_max;
263 struct thread_struct *io_bitmap_owner;
264
265 /*
266 * Pad the TSS to be cacheline-aligned (size is 0x100):
267 */
268 unsigned long __cacheline_filler[35];
269 /*
270 * .. and then another 0x100 bytes for the emergency kernel stack:
271 */
272 unsigned long stack[64];
273
274 } __attribute__((packed));
275
276 DECLARE_PER_CPU(struct tss_struct, init_tss);
277
278 /*
279 * Save the original ist values for checking stack pointers during debugging
280 */
281 struct orig_ist {
282 unsigned long ist[7];
283 };
284
285 #define MXCSR_DEFAULT 0x1f80
286
287 struct i387_fsave_struct {
288 u32 cwd; /* FPU Control Word */
289 u32 swd; /* FPU Status Word */
290 u32 twd; /* FPU Tag Word */
291 u32 fip; /* FPU IP Offset */
292 u32 fcs; /* FPU IP Selector */
293 u32 foo; /* FPU Operand Pointer Offset */
294 u32 fos; /* FPU Operand Pointer Selector */
295
296 /* 8*10 bytes for each FP-reg = 80 bytes: */
297 u32 st_space[20];
298
299 /* Software status information [not touched by FSAVE ]: */
300 u32 status;
301 };
302
303 struct i387_fxsave_struct {
304 u16 cwd; /* Control Word */
305 u16 swd; /* Status Word */
306 u16 twd; /* Tag Word */
307 u16 fop; /* Last Instruction Opcode */
308 union {
309 struct {
310 u64 rip; /* Instruction Pointer */
311 u64 rdp; /* Data Pointer */
312 };
313 struct {
314 u32 fip; /* FPU IP Offset */
315 u32 fcs; /* FPU IP Selector */
316 u32 foo; /* FPU Operand Offset */
317 u32 fos; /* FPU Operand Selector */
318 };
319 };
320 u32 mxcsr; /* MXCSR Register State */
321 u32 mxcsr_mask; /* MXCSR Mask */
322
323 /* 8*16 bytes for each FP-reg = 128 bytes: */
324 u32 st_space[32];
325
326 /* 16*16 bytes for each XMM-reg = 256 bytes: */
327 u32 xmm_space[64];
328
329 u32 padding[24];
330
331 } __attribute__((aligned(16)));
332
333 struct i387_soft_struct {
334 u32 cwd;
335 u32 swd;
336 u32 twd;
337 u32 fip;
338 u32 fcs;
339 u32 foo;
340 u32 fos;
341 /* 8*10 bytes for each FP-reg = 80 bytes: */
342 u32 st_space[20];
343 u8 ftop;
344 u8 changed;
345 u8 lookahead;
346 u8 no_update;
347 u8 rm;
348 u8 alimit;
349 struct info *info;
350 u32 entry_eip;
351 };
352
353 union thread_xstate {
354 struct i387_fsave_struct fsave;
355 struct i387_fxsave_struct fxsave;
356 struct i387_soft_struct soft;
357 };
358
359 #ifdef CONFIG_X86_64
360 DECLARE_PER_CPU(struct orig_ist, orig_ist);
361 #endif
362
363 extern void print_cpu_info(struct cpuinfo_x86 *);
364 extern unsigned int xstate_size;
365 extern void free_thread_xstate(struct task_struct *);
366 extern struct kmem_cache *task_xstate_cachep;
367 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
368 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
369 extern unsigned short num_cache_leaves;
370
371 struct thread_struct {
372 /* Cached TLS descriptors: */
373 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
374 unsigned long sp0;
375 unsigned long sp;
376 #ifdef CONFIG_X86_32
377 unsigned long sysenter_cs;
378 #else
379 unsigned long usersp; /* Copy from PDA */
380 unsigned short es;
381 unsigned short ds;
382 unsigned short fsindex;
383 unsigned short gsindex;
384 #endif
385 unsigned long ip;
386 unsigned long fs;
387 unsigned long gs;
388 /* Hardware debugging registers: */
389 unsigned long debugreg0;
390 unsigned long debugreg1;
391 unsigned long debugreg2;
392 unsigned long debugreg3;
393 unsigned long debugreg6;
394 unsigned long debugreg7;
395 /* Fault info: */
396 unsigned long cr2;
397 unsigned long trap_no;
398 unsigned long error_code;
399 /* floating point and extended processor state */
400 union thread_xstate *xstate;
401 #ifdef CONFIG_X86_32
402 /* Virtual 86 mode info */
403 struct vm86_struct __user *vm86_info;
404 unsigned long screen_bitmap;
405 unsigned long v86flags;
406 unsigned long v86mask;
407 unsigned long saved_sp0;
408 unsigned int saved_fs;
409 unsigned int saved_gs;
410 #endif
411 /* IO permissions: */
412 unsigned long *io_bitmap_ptr;
413 unsigned long iopl;
414 /* Max allowed port in the bitmap, in bytes: */
415 unsigned io_bitmap_max;
416 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
417 unsigned long debugctlmsr;
418 /* Debug Store - if not 0 points to a DS Save Area configuration;
419 * goes into MSR_IA32_DS_AREA */
420 unsigned long ds_area_msr;
421 };
422
423 static inline unsigned long native_get_debugreg(int regno)
424 {
425 unsigned long val = 0; /* Damn you, gcc! */
426
427 switch (regno) {
428 case 0:
429 asm("mov %%db0, %0" :"=r" (val));
430 break;
431 case 1:
432 asm("mov %%db1, %0" :"=r" (val));
433 break;
434 case 2:
435 asm("mov %%db2, %0" :"=r" (val));
436 break;
437 case 3:
438 asm("mov %%db3, %0" :"=r" (val));
439 break;
440 case 6:
441 asm("mov %%db6, %0" :"=r" (val));
442 break;
443 case 7:
444 asm("mov %%db7, %0" :"=r" (val));
445 break;
446 default:
447 BUG();
448 }
449 return val;
450 }
451
452 static inline void native_set_debugreg(int regno, unsigned long value)
453 {
454 switch (regno) {
455 case 0:
456 asm("mov %0, %%db0" ::"r" (value));
457 break;
458 case 1:
459 asm("mov %0, %%db1" ::"r" (value));
460 break;
461 case 2:
462 asm("mov %0, %%db2" ::"r" (value));
463 break;
464 case 3:
465 asm("mov %0, %%db3" ::"r" (value));
466 break;
467 case 6:
468 asm("mov %0, %%db6" ::"r" (value));
469 break;
470 case 7:
471 asm("mov %0, %%db7" ::"r" (value));
472 break;
473 default:
474 BUG();
475 }
476 }
477
478 /*
479 * Set IOPL bits in EFLAGS from given mask
480 */
481 static inline void native_set_iopl_mask(unsigned mask)
482 {
483 #ifdef CONFIG_X86_32
484 unsigned int reg;
485
486 asm volatile ("pushfl;"
487 "popl %0;"
488 "andl %1, %0;"
489 "orl %2, %0;"
490 "pushl %0;"
491 "popfl"
492 : "=&r" (reg)
493 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
494 #endif
495 }
496
497 static inline void
498 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
499 {
500 tss->x86_tss.sp0 = thread->sp0;
501 #ifdef CONFIG_X86_32
502 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
503 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
504 tss->x86_tss.ss1 = thread->sysenter_cs;
505 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
506 }
507 #endif
508 }
509
510 static inline void native_swapgs(void)
511 {
512 #ifdef CONFIG_X86_64
513 asm volatile("swapgs" ::: "memory");
514 #endif
515 }
516
517 #ifdef CONFIG_PARAVIRT
518 #include <asm/paravirt.h>
519 #else
520 #define __cpuid native_cpuid
521 #define paravirt_enabled() 0
522
523 /*
524 * These special macros can be used to get or set a debugging register
525 */
526 #define get_debugreg(var, register) \
527 (var) = native_get_debugreg(register)
528 #define set_debugreg(value, register) \
529 native_set_debugreg(register, value)
530
531 static inline void load_sp0(struct tss_struct *tss,
532 struct thread_struct *thread)
533 {
534 native_load_sp0(tss, thread);
535 }
536
537 #define set_iopl_mask native_set_iopl_mask
538 #define SWAPGS swapgs
539 #endif /* CONFIG_PARAVIRT */
540
541 /*
542 * Save the cr4 feature set we're using (ie
543 * Pentium 4MB enable and PPro Global page
544 * enable), so that any CPU's that boot up
545 * after us can get the correct flags.
546 */
547 extern unsigned long mmu_cr4_features;
548
549 static inline void set_in_cr4(unsigned long mask)
550 {
551 unsigned cr4;
552
553 mmu_cr4_features |= mask;
554 cr4 = read_cr4();
555 cr4 |= mask;
556 write_cr4(cr4);
557 }
558
559 static inline void clear_in_cr4(unsigned long mask)
560 {
561 unsigned cr4;
562
563 mmu_cr4_features &= ~mask;
564 cr4 = read_cr4();
565 cr4 &= ~mask;
566 write_cr4(cr4);
567 }
568
569 struct microcode_header {
570 unsigned int hdrver;
571 unsigned int rev;
572 unsigned int date;
573 unsigned int sig;
574 unsigned int cksum;
575 unsigned int ldrver;
576 unsigned int pf;
577 unsigned int datasize;
578 unsigned int totalsize;
579 unsigned int reserved[3];
580 };
581
582 struct microcode {
583 struct microcode_header hdr;
584 unsigned int bits[0];
585 };
586
587 typedef struct microcode microcode_t;
588 typedef struct microcode_header microcode_header_t;
589
590 /* microcode format is extended from prescott processors */
591 struct extended_signature {
592 unsigned int sig;
593 unsigned int pf;
594 unsigned int cksum;
595 };
596
597 struct extended_sigtable {
598 unsigned int count;
599 unsigned int cksum;
600 unsigned int reserved[3];
601 struct extended_signature sigs[0];
602 };
603
604 typedef struct {
605 unsigned long seg;
606 } mm_segment_t;
607
608
609 /*
610 * create a kernel thread without removing it from tasklists
611 */
612 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
613
614 /* Free all resources held by a thread. */
615 extern void release_thread(struct task_struct *);
616
617 /* Prepare to copy thread state - unlazy all lazy state */
618 extern void prepare_to_copy(struct task_struct *tsk);
619
620 unsigned long get_wchan(struct task_struct *p);
621
622 /*
623 * Generic CPUID function
624 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
625 * resulting in stale register contents being returned.
626 */
627 static inline void cpuid(unsigned int op,
628 unsigned int *eax, unsigned int *ebx,
629 unsigned int *ecx, unsigned int *edx)
630 {
631 *eax = op;
632 *ecx = 0;
633 __cpuid(eax, ebx, ecx, edx);
634 }
635
636 /* Some CPUID calls want 'count' to be placed in ecx */
637 static inline void cpuid_count(unsigned int op, int count,
638 unsigned int *eax, unsigned int *ebx,
639 unsigned int *ecx, unsigned int *edx)
640 {
641 *eax = op;
642 *ecx = count;
643 __cpuid(eax, ebx, ecx, edx);
644 }
645
646 /*
647 * CPUID functions returning a single datum
648 */
649 static inline unsigned int cpuid_eax(unsigned int op)
650 {
651 unsigned int eax, ebx, ecx, edx;
652
653 cpuid(op, &eax, &ebx, &ecx, &edx);
654
655 return eax;
656 }
657
658 static inline unsigned int cpuid_ebx(unsigned int op)
659 {
660 unsigned int eax, ebx, ecx, edx;
661
662 cpuid(op, &eax, &ebx, &ecx, &edx);
663
664 return ebx;
665 }
666
667 static inline unsigned int cpuid_ecx(unsigned int op)
668 {
669 unsigned int eax, ebx, ecx, edx;
670
671 cpuid(op, &eax, &ebx, &ecx, &edx);
672
673 return ecx;
674 }
675
676 static inline unsigned int cpuid_edx(unsigned int op)
677 {
678 unsigned int eax, ebx, ecx, edx;
679
680 cpuid(op, &eax, &ebx, &ecx, &edx);
681
682 return edx;
683 }
684
685 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
686 static inline void rep_nop(void)
687 {
688 asm volatile("rep; nop" ::: "memory");
689 }
690
691 static inline void cpu_relax(void)
692 {
693 rep_nop();
694 }
695
696 /* Stop speculative execution: */
697 static inline void sync_core(void)
698 {
699 int tmp;
700
701 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
702 : "ebx", "ecx", "edx", "memory");
703 }
704
705 static inline void __monitor(const void *eax, unsigned long ecx,
706 unsigned long edx)
707 {
708 /* "monitor %eax, %ecx, %edx;" */
709 asm volatile(".byte 0x0f, 0x01, 0xc8;"
710 :: "a" (eax), "c" (ecx), "d"(edx));
711 }
712
713 static inline void __mwait(unsigned long eax, unsigned long ecx)
714 {
715 /* "mwait %eax, %ecx;" */
716 asm volatile(".byte 0x0f, 0x01, 0xc9;"
717 :: "a" (eax), "c" (ecx));
718 }
719
720 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
721 {
722 trace_hardirqs_on();
723 /* "mwait %eax, %ecx;" */
724 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
725 :: "a" (eax), "c" (ecx));
726 }
727
728 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
729
730 extern int force_mwait;
731
732 extern void select_idle_routine(const struct cpuinfo_x86 *c);
733
734 extern unsigned long boot_option_idle_override;
735
736 extern void enable_sep_cpu(void);
737 extern int sysenter_setup(void);
738
739 /* Defined in head.S */
740 extern struct desc_ptr early_gdt_descr;
741
742 extern void cpu_set_gdt(int);
743 extern void switch_to_new_gdt(void);
744 extern void cpu_init(void);
745 extern void init_gdt(int cpu);
746
747 static inline void update_debugctlmsr(unsigned long debugctlmsr)
748 {
749 #ifndef CONFIG_X86_DEBUGCTLMSR
750 if (boot_cpu_data.x86 < 6)
751 return;
752 #endif
753 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
754 }
755
756 /*
757 * from system description table in BIOS. Mostly for MCA use, but
758 * others may find it useful:
759 */
760 extern unsigned int machine_id;
761 extern unsigned int machine_submodel_id;
762 extern unsigned int BIOS_revision;
763
764 /* Boot loader type from the setup header: */
765 extern int bootloader_type;
766
767 extern char ignore_fpu_irq;
768
769 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
770 #define ARCH_HAS_PREFETCHW
771 #define ARCH_HAS_SPINLOCK_PREFETCH
772
773 #ifdef CONFIG_X86_32
774 # define BASE_PREFETCH ASM_NOP4
775 # define ARCH_HAS_PREFETCH
776 #else
777 # define BASE_PREFETCH "prefetcht0 (%1)"
778 #endif
779
780 /*
781 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
782 *
783 * It's not worth to care about 3dnow prefetches for the K6
784 * because they are microcoded there and very slow.
785 */
786 static inline void prefetch(const void *x)
787 {
788 alternative_input(BASE_PREFETCH,
789 "prefetchnta (%1)",
790 X86_FEATURE_XMM,
791 "r" (x));
792 }
793
794 /*
795 * 3dnow prefetch to get an exclusive cache line.
796 * Useful for spinlocks to avoid one state transition in the
797 * cache coherency protocol:
798 */
799 static inline void prefetchw(const void *x)
800 {
801 alternative_input(BASE_PREFETCH,
802 "prefetchw (%1)",
803 X86_FEATURE_3DNOW,
804 "r" (x));
805 }
806
807 static inline void spin_lock_prefetch(const void *x)
808 {
809 prefetchw(x);
810 }
811
812 #ifdef CONFIG_X86_32
813 /*
814 * User space process size: 3GB (default).
815 */
816 #define TASK_SIZE PAGE_OFFSET
817 #define STACK_TOP TASK_SIZE
818 #define STACK_TOP_MAX STACK_TOP
819
820 #define INIT_THREAD { \
821 .sp0 = sizeof(init_stack) + (long)&init_stack, \
822 .vm86_info = NULL, \
823 .sysenter_cs = __KERNEL_CS, \
824 .io_bitmap_ptr = NULL, \
825 .fs = __KERNEL_PERCPU, \
826 }
827
828 /*
829 * Note that the .io_bitmap member must be extra-big. This is because
830 * the CPU will access an additional byte beyond the end of the IO
831 * permission bitmap. The extra byte must be all 1 bits, and must
832 * be within the limit.
833 */
834 #define INIT_TSS { \
835 .x86_tss = { \
836 .sp0 = sizeof(init_stack) + (long)&init_stack, \
837 .ss0 = __KERNEL_DS, \
838 .ss1 = __KERNEL_CS, \
839 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
840 }, \
841 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
842 }
843
844 extern unsigned long thread_saved_pc(struct task_struct *tsk);
845
846 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
847 #define KSTK_TOP(info) \
848 ({ \
849 unsigned long *__ptr = (unsigned long *)(info); \
850 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
851 })
852
853 /*
854 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
855 * This is necessary to guarantee that the entire "struct pt_regs"
856 * is accessable even if the CPU haven't stored the SS/ESP registers
857 * on the stack (interrupt gate does not save these registers
858 * when switching to the same priv ring).
859 * Therefore beware: accessing the ss/esp fields of the
860 * "struct pt_regs" is possible, but they may contain the
861 * completely wrong values.
862 */
863 #define task_pt_regs(task) \
864 ({ \
865 struct pt_regs *__regs__; \
866 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
867 __regs__ - 1; \
868 })
869
870 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
871
872 #else
873 /*
874 * User space process size. 47bits minus one guard page.
875 */
876 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
877
878 /* This decides where the kernel will search for a free chunk of vm
879 * space during mmap's.
880 */
881 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
882 0xc0000000 : 0xFFFFe000)
883
884 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
885 IA32_PAGE_OFFSET : TASK_SIZE64)
886 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
887 IA32_PAGE_OFFSET : TASK_SIZE64)
888
889 #define STACK_TOP TASK_SIZE
890 #define STACK_TOP_MAX TASK_SIZE64
891
892 #define INIT_THREAD { \
893 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
894 }
895
896 #define INIT_TSS { \
897 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
898 }
899
900 /*
901 * Return saved PC of a blocked thread.
902 * What is this good for? it will be always the scheduler or ret_from_fork.
903 */
904 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
905
906 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
907 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
908 #endif /* CONFIG_X86_64 */
909
910 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
911 unsigned long new_sp);
912
913 /*
914 * This decides where the kernel will search for a free chunk of vm
915 * space during mmap's.
916 */
917 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
918
919 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
920
921 /* Get/set a process' ability to use the timestamp counter instruction */
922 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
923 #define SET_TSC_CTL(val) set_tsc_mode((val))
924
925 extern int get_tsc_mode(unsigned long adr);
926 extern int set_tsc_mode(unsigned int val);
927
928 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree