2 * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework
4 * Largely derived from at91_dataflash.c:
5 * Copyright (C) 2003-2005 SAN People (Pty) Ltd
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/err.h>
19 #include <linux/math64.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/flash.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
29 * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
30 * each chip, which may be used for double buffered I/O; but this driver
31 * doesn't (yet) use these for any kind of i/o overlap or prefetching.
33 * Sometimes DataFlash is packaged in MMC-format cards, although the
34 * MMC stack can't (yet?) distinguish between MMC and DataFlash
35 * protocols during enumeration.
38 /* reads can bypass the buffers */
39 #define OP_READ_CONTINUOUS 0xE8
40 #define OP_READ_PAGE 0xD2
42 /* group B requests can run even while status reports "busy" */
43 #define OP_READ_STATUS 0xD7 /* group B */
45 /* move data between host and buffer */
46 #define OP_READ_BUFFER1 0xD4 /* group B */
47 #define OP_READ_BUFFER2 0xD6 /* group B */
48 #define OP_WRITE_BUFFER1 0x84 /* group B */
49 #define OP_WRITE_BUFFER2 0x87 /* group B */
52 #define OP_ERASE_PAGE 0x81
53 #define OP_ERASE_BLOCK 0x50
55 /* move data between buffer and flash */
56 #define OP_TRANSFER_BUF1 0x53
57 #define OP_TRANSFER_BUF2 0x55
58 #define OP_MREAD_BUFFER1 0xD4
59 #define OP_MREAD_BUFFER2 0xD6
60 #define OP_MWERASE_BUFFER1 0x83
61 #define OP_MWERASE_BUFFER2 0x86
62 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
63 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
65 /* write to buffer, then write-erase to flash */
66 #define OP_PROGRAM_VIA_BUF1 0x82
67 #define OP_PROGRAM_VIA_BUF2 0x85
69 /* compare buffer to flash */
70 #define OP_COMPARE_BUF1 0x60
71 #define OP_COMPARE_BUF2 0x61
73 /* read flash to buffer, then write-erase to flash */
74 #define OP_REWRITE_VIA_BUF1 0x58
75 #define OP_REWRITE_VIA_BUF2 0x59
77 /* newer chips report JEDEC manufacturer and device IDs; chip
78 * serial number and OTP bits; and per-sector writeprotect.
80 #define OP_READ_ID 0x9F
81 #define OP_READ_SECURITY 0x77
82 #define OP_WRITE_SECURITY_REVC 0x9A
83 #define OP_WRITE_SECURITY 0x9B /* revision D */
90 unsigned partitioned
:1;
92 unsigned short page_offset
; /* offset in flash address */
93 unsigned int page_size
; /* of bytes per page */
96 struct spi_device
*spi
;
101 /* ......................................................................... */
104 * Return the status of the DataFlash device.
106 static inline int dataflash_status(struct spi_device
*spi
)
108 /* NOTE: at45db321c over 25 MHz wants to write
109 * a dummy byte after the opcode...
111 return spi_w8r8(spi
, OP_READ_STATUS
);
115 * Poll the DataFlash device until it is READY.
116 * This usually takes 5-20 msec or so; more for sector erase.
118 static int dataflash_waitready(struct spi_device
*spi
)
123 status
= dataflash_status(spi
);
125 DEBUG(MTD_DEBUG_LEVEL1
, "%s: status %d?\n",
126 dev_name(&spi
->dev
), status
);
130 if (status
& (1 << 7)) /* RDY/nBSY */
137 /* ......................................................................... */
140 * Erase pages of flash.
142 static int dataflash_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
144 struct dataflash
*priv
= mtd
->priv
;
145 struct spi_device
*spi
= priv
->spi
;
146 struct spi_transfer x
= { .tx_dma
= 0, };
147 struct spi_message msg
;
148 unsigned blocksize
= priv
->page_size
<< 3;
152 DEBUG(MTD_DEBUG_LEVEL2
, "%s: erase addr=0x%llx len 0x%llx\n",
153 dev_name(&spi
->dev
), (long long)instr
->addr
,
154 (long long)instr
->len
);
157 if (instr
->addr
+ instr
->len
> mtd
->size
)
159 div_u64_rem(instr
->len
, priv
->page_size
, &rem
);
162 div_u64_rem(instr
->addr
, priv
->page_size
, &rem
);
166 spi_message_init(&msg
);
168 x
.tx_buf
= command
= priv
->command
;
170 spi_message_add_tail(&x
, &msg
);
172 mutex_lock(&priv
->lock
);
173 while (instr
->len
> 0) {
174 unsigned int pageaddr
;
178 /* Calculate flash page address; use block erase (for speed) if
179 * we're at a block boundary and need to erase the whole block.
181 pageaddr
= div_u64(instr
->addr
, priv
->page_size
);
182 do_block
= (pageaddr
& 0x7) == 0 && instr
->len
>= blocksize
;
183 pageaddr
= pageaddr
<< priv
->page_offset
;
185 command
[0] = do_block
? OP_ERASE_BLOCK
: OP_ERASE_PAGE
;
186 command
[1] = (uint8_t)(pageaddr
>> 16);
187 command
[2] = (uint8_t)(pageaddr
>> 8);
190 DEBUG(MTD_DEBUG_LEVEL3
, "ERASE %s: (%x) %x %x %x [%i]\n",
191 do_block
? "block" : "page",
192 command
[0], command
[1], command
[2], command
[3],
195 status
= spi_sync(spi
, &msg
);
196 (void) dataflash_waitready(spi
);
199 printk(KERN_ERR
"%s: erase %x, err %d\n",
200 dev_name(&spi
->dev
), pageaddr
, status
);
201 /* REVISIT: can retry instr->retries times; or
202 * giveup and instr->fail_addr = instr->addr;
208 instr
->addr
+= blocksize
;
209 instr
->len
-= blocksize
;
211 instr
->addr
+= priv
->page_size
;
212 instr
->len
-= priv
->page_size
;
215 mutex_unlock(&priv
->lock
);
217 /* Inform MTD subsystem that erase is complete */
218 instr
->state
= MTD_ERASE_DONE
;
219 mtd_erase_callback(instr
);
225 * Read from the DataFlash device.
226 * from : Start offset in flash device
227 * len : Amount to read
228 * retlen : About of data actually read
229 * buf : Buffer containing the data
231 static int dataflash_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
232 size_t *retlen
, u_char
*buf
)
234 struct dataflash
*priv
= mtd
->priv
;
235 struct spi_transfer x
[2] = { { .tx_dma
= 0, }, };
236 struct spi_message msg
;
241 DEBUG(MTD_DEBUG_LEVEL2
, "%s: read 0x%x..0x%x\n",
242 dev_name(&priv
->spi
->dev
), (unsigned)from
, (unsigned)(from
+ len
));
249 if (from
+ len
> mtd
->size
)
252 /* Calculate flash page/byte address */
253 addr
= (((unsigned)from
/ priv
->page_size
) << priv
->page_offset
)
254 + ((unsigned)from
% priv
->page_size
);
256 command
= priv
->command
;
258 DEBUG(MTD_DEBUG_LEVEL3
, "READ: (%x) %x %x %x\n",
259 command
[0], command
[1], command
[2], command
[3]);
261 spi_message_init(&msg
);
263 x
[0].tx_buf
= command
;
265 spi_message_add_tail(&x
[0], &msg
);
269 spi_message_add_tail(&x
[1], &msg
);
271 mutex_lock(&priv
->lock
);
273 /* Continuous read, max clock = f(car) which may be less than
274 * the peak rate available. Some chips support commands with
275 * fewer "don't care" bytes. Both buffers stay unchanged.
277 command
[0] = OP_READ_CONTINUOUS
;
278 command
[1] = (uint8_t)(addr
>> 16);
279 command
[2] = (uint8_t)(addr
>> 8);
280 command
[3] = (uint8_t)(addr
>> 0);
281 /* plus 4 "don't care" bytes */
283 status
= spi_sync(priv
->spi
, &msg
);
284 mutex_unlock(&priv
->lock
);
287 *retlen
= msg
.actual_length
- 8;
290 DEBUG(MTD_DEBUG_LEVEL1
, "%s: read %x..%x --> %d\n",
291 dev_name(&priv
->spi
->dev
),
292 (unsigned)from
, (unsigned)(from
+ len
),
298 * Write to the DataFlash device.
299 * to : Start offset in flash device
300 * len : Amount to write
301 * retlen : Amount of data actually written
302 * buf : Buffer containing the data
304 static int dataflash_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
305 size_t * retlen
, const u_char
* buf
)
307 struct dataflash
*priv
= mtd
->priv
;
308 struct spi_device
*spi
= priv
->spi
;
309 struct spi_transfer x
[2] = { { .tx_dma
= 0, }, };
310 struct spi_message msg
;
311 unsigned int pageaddr
, addr
, offset
, writelen
;
312 size_t remaining
= len
;
313 u_char
*writebuf
= (u_char
*) buf
;
314 int status
= -EINVAL
;
317 DEBUG(MTD_DEBUG_LEVEL2
, "%s: write 0x%x..0x%x\n",
318 dev_name(&spi
->dev
), (unsigned)to
, (unsigned)(to
+ len
));
325 if ((to
+ len
) > mtd
->size
)
328 spi_message_init(&msg
);
330 x
[0].tx_buf
= command
= priv
->command
;
332 spi_message_add_tail(&x
[0], &msg
);
334 pageaddr
= ((unsigned)to
/ priv
->page_size
);
335 offset
= ((unsigned)to
% priv
->page_size
);
336 if (offset
+ len
> priv
->page_size
)
337 writelen
= priv
->page_size
- offset
;
341 mutex_lock(&priv
->lock
);
342 while (remaining
> 0) {
343 DEBUG(MTD_DEBUG_LEVEL3
, "write @ %i:%i len=%i\n",
344 pageaddr
, offset
, writelen
);
347 * (a) each page in a sector must be rewritten at least
348 * once every 10K sibling erase/program operations.
349 * (b) for pages that are already erased, we could
350 * use WRITE+MWRITE not PROGRAM for ~30% speedup.
351 * (c) WRITE to buffer could be done while waiting for
352 * a previous MWRITE/MWERASE to complete ...
353 * (d) error handling here seems to be mostly missing.
355 * Two persistent bits per page, plus a per-sector counter,
356 * could support (a) and (b) ... we might consider using
357 * the second half of sector zero, which is just one block,
358 * to track that state. (On AT91, that sector should also
359 * support boot-from-DataFlash.)
362 addr
= pageaddr
<< priv
->page_offset
;
364 /* (1) Maybe transfer partial page to Buffer1 */
365 if (writelen
!= priv
->page_size
) {
366 command
[0] = OP_TRANSFER_BUF1
;
367 command
[1] = (addr
& 0x00FF0000) >> 16;
368 command
[2] = (addr
& 0x0000FF00) >> 8;
371 DEBUG(MTD_DEBUG_LEVEL3
, "TRANSFER: (%x) %x %x %x\n",
372 command
[0], command
[1], command
[2], command
[3]);
374 status
= spi_sync(spi
, &msg
);
376 DEBUG(MTD_DEBUG_LEVEL1
, "%s: xfer %u -> %d \n",
377 dev_name(&spi
->dev
), addr
, status
);
379 (void) dataflash_waitready(priv
->spi
);
382 /* (2) Program full page via Buffer1 */
384 command
[0] = OP_PROGRAM_VIA_BUF1
;
385 command
[1] = (addr
& 0x00FF0000) >> 16;
386 command
[2] = (addr
& 0x0000FF00) >> 8;
387 command
[3] = (addr
& 0x000000FF);
389 DEBUG(MTD_DEBUG_LEVEL3
, "PROGRAM: (%x) %x %x %x\n",
390 command
[0], command
[1], command
[2], command
[3]);
392 x
[1].tx_buf
= writebuf
;
394 spi_message_add_tail(x
+ 1, &msg
);
395 status
= spi_sync(spi
, &msg
);
396 spi_transfer_del(x
+ 1);
398 DEBUG(MTD_DEBUG_LEVEL1
, "%s: pgm %u/%u -> %d \n",
399 dev_name(&spi
->dev
), addr
, writelen
, status
);
401 (void) dataflash_waitready(priv
->spi
);
404 #ifdef CONFIG_MTD_DATAFLASH_WRITE_VERIFY
406 /* (3) Compare to Buffer1 */
407 addr
= pageaddr
<< priv
->page_offset
;
408 command
[0] = OP_COMPARE_BUF1
;
409 command
[1] = (addr
& 0x00FF0000) >> 16;
410 command
[2] = (addr
& 0x0000FF00) >> 8;
413 DEBUG(MTD_DEBUG_LEVEL3
, "COMPARE: (%x) %x %x %x\n",
414 command
[0], command
[1], command
[2], command
[3]);
416 status
= spi_sync(spi
, &msg
);
418 DEBUG(MTD_DEBUG_LEVEL1
, "%s: compare %u -> %d \n",
419 dev_name(&spi
->dev
), addr
, status
);
421 status
= dataflash_waitready(priv
->spi
);
423 /* Check result of the compare operation */
424 if (status
& (1 << 6)) {
425 printk(KERN_ERR
"%s: compare page %u, err %d\n",
426 dev_name(&spi
->dev
), pageaddr
, status
);
433 #endif /* CONFIG_MTD_DATAFLASH_WRITE_VERIFY */
435 remaining
= remaining
- writelen
;
438 writebuf
+= writelen
;
441 if (remaining
> priv
->page_size
)
442 writelen
= priv
->page_size
;
444 writelen
= remaining
;
446 mutex_unlock(&priv
->lock
);
451 /* ......................................................................... */
453 #ifdef CONFIG_MTD_DATAFLASH_OTP
455 static int dataflash_get_otp_info(struct mtd_info
*mtd
,
456 struct otp_info
*info
, size_t len
)
458 /* Report both blocks as identical: bytes 0..64, locked.
459 * Unless the user block changed from all-ones, we can't
460 * tell whether it's still writable; so we assume it isn't.
465 return sizeof(*info
);
468 static ssize_t
otp_read(struct spi_device
*spi
, unsigned base
,
469 uint8_t *buf
, loff_t off
, size_t len
)
471 struct spi_message m
;
474 struct spi_transfer t
;
480 if ((off
+ len
) > 64)
485 spi_message_init(&m
);
487 l
= 4 + base
+ off
+ len
;
488 scratch
= kzalloc(l
, GFP_KERNEL
);
492 /* OUT: OP_READ_SECURITY, 3 don't-care bytes, zeroes
493 * IN: ignore 4 bytes, data bytes 0..N (max 127)
495 scratch
[0] = OP_READ_SECURITY
;
497 memset(&t
, 0, sizeof t
);
501 spi_message_add_tail(&t
, &m
);
503 dataflash_waitready(spi
);
505 status
= spi_sync(spi
, &m
);
507 memcpy(buf
, scratch
+ 4 + base
+ off
, len
);
515 static int dataflash_read_fact_otp(struct mtd_info
*mtd
,
516 loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
518 struct dataflash
*priv
= mtd
->priv
;
521 /* 64 bytes, from 0..63 ... start at 64 on-chip */
522 mutex_lock(&priv
->lock
);
523 status
= otp_read(priv
->spi
, 64, buf
, from
, len
);
524 mutex_unlock(&priv
->lock
);
532 static int dataflash_read_user_otp(struct mtd_info
*mtd
,
533 loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
535 struct dataflash
*priv
= mtd
->priv
;
538 /* 64 bytes, from 0..63 ... start at 0 on-chip */
539 mutex_lock(&priv
->lock
);
540 status
= otp_read(priv
->spi
, 0, buf
, from
, len
);
541 mutex_unlock(&priv
->lock
);
549 static int dataflash_write_user_otp(struct mtd_info
*mtd
,
550 loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
552 struct spi_message m
;
553 const size_t l
= 4 + 64;
555 struct spi_transfer t
;
556 struct dataflash
*priv
= mtd
->priv
;
562 /* Strictly speaking, we *could* truncate the write ... but
563 * let's not do that for the only write that's ever possible.
565 if ((from
+ len
) > 64)
568 /* OUT: OP_WRITE_SECURITY, 3 zeroes, 64 data-or-zero bytes
571 scratch
= kzalloc(l
, GFP_KERNEL
);
574 scratch
[0] = OP_WRITE_SECURITY
;
575 memcpy(scratch
+ 4 + from
, buf
, len
);
577 spi_message_init(&m
);
579 memset(&t
, 0, sizeof t
);
582 spi_message_add_tail(&t
, &m
);
584 /* Write the OTP bits, if they've not yet been written.
585 * This modifies SRAM buffer1.
587 mutex_lock(&priv
->lock
);
588 dataflash_waitready(priv
->spi
);
589 status
= spi_sync(priv
->spi
, &m
);
590 mutex_unlock(&priv
->lock
);
601 static char *otp_setup(struct mtd_info
*device
, char revision
)
603 device
->get_fact_prot_info
= dataflash_get_otp_info
;
604 device
->read_fact_prot_reg
= dataflash_read_fact_otp
;
605 device
->get_user_prot_info
= dataflash_get_otp_info
;
606 device
->read_user_prot_reg
= dataflash_read_user_otp
;
608 /* rev c parts (at45db321c and at45db1281 only!) use a
609 * different write procedure; not (yet?) implemented.
612 device
->write_user_prot_reg
= dataflash_write_user_otp
;
619 static char *otp_setup(struct mtd_info
*device
, char revision
)
626 /* ......................................................................... */
629 * Register DataFlash device with MTD subsystem.
632 add_dataflash_otp(struct spi_device
*spi
, char *name
,
633 int nr_pages
, int pagesize
, int pageoffset
, char revision
)
635 struct dataflash
*priv
;
636 struct mtd_info
*device
;
637 struct flash_platform_data
*pdata
= spi
->dev
.platform_data
;
641 priv
= kzalloc(sizeof *priv
, GFP_KERNEL
);
645 mutex_init(&priv
->lock
);
647 priv
->page_size
= pagesize
;
648 priv
->page_offset
= pageoffset
;
650 /* name must be usable with cmdlinepart */
651 sprintf(priv
->name
, "spi%d.%d-%s",
652 spi
->master
->bus_num
, spi
->chip_select
,
656 device
->name
= (pdata
&& pdata
->name
) ? pdata
->name
: priv
->name
;
657 device
->size
= nr_pages
* pagesize
;
658 device
->erasesize
= pagesize
;
659 device
->writesize
= pagesize
;
660 device
->owner
= THIS_MODULE
;
661 device
->type
= MTD_DATAFLASH
;
662 device
->flags
= MTD_WRITEABLE
;
663 device
->erase
= dataflash_erase
;
664 device
->read
= dataflash_read
;
665 device
->write
= dataflash_write
;
668 device
->dev
.parent
= &spi
->dev
;
671 otp_tag
= otp_setup(device
, revision
);
673 dev_info(&spi
->dev
, "%s (%lld KBytes) pagesize %d bytes%s\n",
674 name
, (long long)((device
->size
+ 1023) >> 10),
676 dev_set_drvdata(&spi
->dev
, priv
);
678 if (mtd_has_partitions()) {
679 struct mtd_partition
*parts
;
682 if (mtd_has_cmdlinepart()) {
683 static const char *part_probes
[]
684 = { "cmdlinepart", NULL
, };
686 nr_parts
= parse_mtd_partitions(device
,
687 part_probes
, &parts
, 0);
690 if (nr_parts
<= 0 && pdata
&& pdata
->parts
) {
691 parts
= pdata
->parts
;
692 nr_parts
= pdata
->nr_parts
;
696 priv
->partitioned
= 1;
697 err
= add_mtd_partitions(device
, parts
, nr_parts
);
700 } else if (pdata
&& pdata
->nr_parts
)
701 dev_warn(&spi
->dev
, "ignoring %d default partitions on %s\n",
702 pdata
->nr_parts
, device
->name
);
704 if (add_mtd_device(device
) == 1)
711 dev_set_drvdata(&spi
->dev
, NULL
);
716 static inline int __devinit
717 add_dataflash(struct spi_device
*spi
, char *name
,
718 int nr_pages
, int pagesize
, int pageoffset
)
720 return add_dataflash_otp(spi
, name
, nr_pages
, pagesize
,
727 /* JEDEC id has a high byte of zero plus three data bytes:
728 * the manufacturer id, then a two byte device id.
732 /* The size listed here is what works with OP_ERASE_PAGE. */
738 #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
739 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
742 static struct flash_info __devinitdata dataflash_data
[] = {
745 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
746 * one with IS_POW2PS and the other without. The entry with the
747 * non-2^N byte page size can't name exact chip revisions without
748 * losing backwards compatibility for cmdlinepart.
750 * These newer chips also support 128-byte security registers (with
751 * 64 bytes one-time-programmable) and software write-protection.
753 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS
},
754 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS
| IS_POW2PS
},
756 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS
},
757 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS
| IS_POW2PS
},
759 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS
},
760 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS
| IS_POW2PS
},
762 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS
},
763 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS
| IS_POW2PS
},
765 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS
},
766 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS
| IS_POW2PS
},
768 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
770 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS
},
771 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS
| IS_POW2PS
},
773 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS
},
774 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS
| IS_POW2PS
},
777 static struct flash_info
*__devinit
jedec_probe(struct spi_device
*spi
)
780 uint8_t code
= OP_READ_ID
;
783 struct flash_info
*info
;
786 /* JEDEC also defines an optional "extended device information"
787 * string for after vendor-specific data, after the three bytes
788 * we use here. Supporting some chips might require using it.
790 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
791 * That's not an error; only rev C and newer chips handle it, and
792 * only Atmel sells these chips.
794 tmp
= spi_write_then_read(spi
, &code
, 1, id
, 3);
796 DEBUG(MTD_DEBUG_LEVEL0
, "%s: error %d reading JEDEC ID\n",
797 dev_name(&spi
->dev
), tmp
);
809 for (tmp
= 0, info
= dataflash_data
;
810 tmp
< ARRAY_SIZE(dataflash_data
);
812 if (info
->jedec_id
== jedec
) {
813 DEBUG(MTD_DEBUG_LEVEL1
, "%s: OTP, sector protect%s\n",
815 (info
->flags
& SUP_POW2PS
)
816 ? ", binary pagesize" : ""
818 if (info
->flags
& SUP_POW2PS
) {
819 status
= dataflash_status(spi
);
821 DEBUG(MTD_DEBUG_LEVEL1
,
822 "%s: status error %d\n",
823 dev_name(&spi
->dev
), status
);
824 return ERR_PTR(status
);
827 if (info
->flags
& IS_POW2PS
)
830 if (!(info
->flags
& IS_POW2PS
))
839 * Treat other chips as errors ... we won't know the right page
840 * size (it might be binary) even when we can tell which density
841 * class is involved (legacy chip id scheme).
843 dev_warn(&spi
->dev
, "JEDEC id %06x not handled\n", jedec
);
844 return ERR_PTR(-ENODEV
);
848 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
849 * or else the ID code embedded in the status bits:
851 * Device Density ID code #Pages PageSize Offset
852 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
853 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
854 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
855 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
856 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
857 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
858 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
859 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
861 static int __devinit
dataflash_probe(struct spi_device
*spi
)
864 struct flash_info
*info
;
867 * Try to detect dataflash by JEDEC ID.
868 * If it succeeds we know we have either a C or D part.
869 * D will support power of 2 pagesize option.
870 * Both support the security register, though with different
873 info
= jedec_probe(spi
);
875 return PTR_ERR(info
);
877 return add_dataflash_otp(spi
, info
->name
, info
->nr_pages
,
878 info
->pagesize
, info
->pageoffset
,
879 (info
->flags
& SUP_POW2PS
) ? 'd' : 'c');
882 * Older chips support only legacy commands, identifing
883 * capacity using bits in the status byte.
885 status
= dataflash_status(spi
);
886 if (status
<= 0 || status
== 0xff) {
887 DEBUG(MTD_DEBUG_LEVEL1
, "%s: status error %d\n",
888 dev_name(&spi
->dev
), status
);
889 if (status
== 0 || status
== 0xff)
894 /* if there's a device there, assume it's dataflash.
895 * board setup should have set spi->max_speed_max to
896 * match f(car) for continuous reads, mode 0 or 3.
898 switch (status
& 0x3c) {
899 case 0x0c: /* 0 0 1 1 x x */
900 status
= add_dataflash(spi
, "AT45DB011B", 512, 264, 9);
902 case 0x14: /* 0 1 0 1 x x */
903 status
= add_dataflash(spi
, "AT45DB021B", 1024, 264, 9);
905 case 0x1c: /* 0 1 1 1 x x */
906 status
= add_dataflash(spi
, "AT45DB041x", 2048, 264, 9);
908 case 0x24: /* 1 0 0 1 x x */
909 status
= add_dataflash(spi
, "AT45DB081B", 4096, 264, 9);
911 case 0x2c: /* 1 0 1 1 x x */
912 status
= add_dataflash(spi
, "AT45DB161x", 4096, 528, 10);
914 case 0x34: /* 1 1 0 1 x x */
915 status
= add_dataflash(spi
, "AT45DB321x", 8192, 528, 10);
917 case 0x38: /* 1 1 1 x x x */
919 status
= add_dataflash(spi
, "AT45DB642x", 8192, 1056, 11);
921 /* obsolete AT45DB1282 not (yet?) supported */
923 DEBUG(MTD_DEBUG_LEVEL1
, "%s: unsupported device (%x)\n",
924 dev_name(&spi
->dev
), status
& 0x3c);
929 DEBUG(MTD_DEBUG_LEVEL1
, "%s: add_dataflash --> %d\n",
930 dev_name(&spi
->dev
), status
);
935 static int __devexit
dataflash_remove(struct spi_device
*spi
)
937 struct dataflash
*flash
= dev_get_drvdata(&spi
->dev
);
940 DEBUG(MTD_DEBUG_LEVEL1
, "%s: remove\n", dev_name(&spi
->dev
));
942 if (mtd_has_partitions() && flash
->partitioned
)
943 status
= del_mtd_partitions(&flash
->mtd
);
945 status
= del_mtd_device(&flash
->mtd
);
947 dev_set_drvdata(&spi
->dev
, NULL
);
953 static struct spi_driver dataflash_driver
= {
955 .name
= "mtd_dataflash",
956 .bus
= &spi_bus_type
,
957 .owner
= THIS_MODULE
,
960 .probe
= dataflash_probe
,
961 .remove
= __devexit_p(dataflash_remove
),
963 /* FIXME: investigate suspend and resume... */
966 static int __init
dataflash_init(void)
968 return spi_register_driver(&dataflash_driver
);
970 module_init(dataflash_init
);
972 static void __exit
dataflash_exit(void)
974 spi_unregister_driver(&dataflash_driver
);
976 module_exit(dataflash_exit
);
979 MODULE_LICENSE("GPL");
980 MODULE_AUTHOR("Andrew Victor, David Brownell");
981 MODULE_DESCRIPTION("MTD DataFlash driver");
982 MODULE_ALIAS("spi:mtd_dataflash");