drivers/ata/pata_scc.c

   1 /*
   2  * Support for IDE interfaces on Celleb platform
   3  *
   4  * (C) Copyright 2006 TOSHIBA CORPORATION
   5  *
   6  * This code is based on drivers/ata/ata_piix.c:
   7  *  Copyright 2003-2005 Red Hat Inc
   8  *  Copyright 2003-2005 Jeff Garzik
   9  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  10  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  11  *  Copyright (C) 2003 Red Hat Inc
  12  *
  13  * and drivers/ata/ahci.c:
  14  *  Copyright 2004-2005 Red Hat, Inc.
  15  *
  16  * and drivers/ata/libata-core.c:
  17  *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
  18  *  Copyright 2003-2004 Jeff Garzik
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2 of the License, or
  23  * (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License along
  31  * with this program; if not, write to the Free Software Foundation, Inc.,
  32  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/init.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/delay.h>
  41 #include <linux/device.h>
  42 #include <scsi/scsi_host.h>
  43 #include <linux/libata.h>
  44
  45 #define DRV_NAME                "pata_scc"
  46 #define DRV_VERSION             "0.3"
  47
  48 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA           0x01b4
  49
  50 /* PCI BARs */
  51 #define SCC_CTRL_BAR            0
  52 #define SCC_BMID_BAR            1
  53
  54 /* offset of CTRL registers */
  55 #define SCC_CTL_PIOSHT          0x000
  56 #define SCC_CTL_PIOCT           0x004
  57 #define SCC_CTL_MDMACT          0x008
  58 #define SCC_CTL_MCRCST          0x00C
  59 #define SCC_CTL_SDMACT          0x010
  60 #define SCC_CTL_SCRCST          0x014
  61 #define SCC_CTL_UDENVT          0x018
  62 #define SCC_CTL_TDVHSEL         0x020
  63 #define SCC_CTL_MODEREG         0x024
  64 #define SCC_CTL_ECMODE          0xF00
  65 #define SCC_CTL_MAEA0           0xF50
  66 #define SCC_CTL_MAEC0           0xF54
  67 #define SCC_CTL_CCKCTRL         0xFF0
  68
  69 /* offset of BMID registers */
  70 #define SCC_DMA_CMD             0x000
  71 #define SCC_DMA_STATUS          0x004
  72 #define SCC_DMA_TABLE_OFS       0x008
  73 #define SCC_DMA_INTMASK         0x010
  74 #define SCC_DMA_INTST           0x014
  75 #define SCC_DMA_PTERADD         0x018
  76 #define SCC_REG_CMD_ADDR        0x020
  77 #define SCC_REG_DATA            0x000
  78 #define SCC_REG_ERR             0x004
  79 #define SCC_REG_FEATURE         0x004
  80 #define SCC_REG_NSECT           0x008
  81 #define SCC_REG_LBAL            0x00C
  82 #define SCC_REG_LBAM            0x010
  83 #define SCC_REG_LBAH            0x014
  84 #define SCC_REG_DEVICE          0x018
  85 #define SCC_REG_STATUS          0x01C
  86 #define SCC_REG_CMD             0x01C
  87 #define SCC_REG_ALTSTATUS       0x020
  88
  89 /* register value */
  90 #define TDVHSEL_MASTER          0x00000001
  91 #define TDVHSEL_SLAVE           0x00000004
  92
  93 #define MODE_JCUSFEN            0x00000080
  94
  95 #define ECMODE_VALUE            0x01
  96
  97 #define CCKCTRL_ATARESET        0x00040000
  98 #define CCKCTRL_BUFCNT          0x00020000
  99 #define CCKCTRL_CRST            0x00010000
 100 #define CCKCTRL_OCLKEN          0x00000100
 101 #define CCKCTRL_ATACLKOEN       0x00000002
 102 #define CCKCTRL_LCLKEN          0x00000001
 103
 104 #define QCHCD_IOS_SS            0x00000001
 105
 106 #define QCHSD_STPDIAG           0x00020000
 107
 108 #define INTMASK_MSK             0xD1000012
 109 #define INTSTS_SERROR           0x80000000
 110 #define INTSTS_PRERR            0x40000000
 111 #define INTSTS_RERR             0x10000000
 112 #define INTSTS_ICERR            0x01000000
 113 #define INTSTS_BMSINT           0x00000010
 114 #define INTSTS_BMHE             0x00000008
 115 #define INTSTS_IOIRQS           0x00000004
 116 #define INTSTS_INTRQ            0x00000002
 117 #define INTSTS_ACTEINT          0x00000001
 118
 119
 120 /* PIO transfer mode table */
 121 /* JCHST */
 122 static const unsigned long JCHSTtbl[2][7] = {
 123         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},     /* 100MHz */
 124         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}      /* 133MHz */
 125 };
 126
 127 /* JCHHT */
 128 static const unsigned long JCHHTtbl[2][7] = {
 129         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},     /* 100MHz */
 130         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}      /* 133MHz */
 131 };
 132
 133 /* JCHCT */
 134 static const unsigned long JCHCTtbl[2][7] = {
 135         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},     /* 100MHz */
 136         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}      /* 133MHz */
 137 };
 138
 139 /* DMA transfer mode  table */
 140 /* JCHDCTM/JCHDCTS */
 141 static const unsigned long JCHDCTxtbl[2][7] = {
 142         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},     /* 100MHz */
 143         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}      /* 133MHz */
 144 };
 145
 146 /* JCSTWTM/JCSTWTS  */
 147 static const unsigned long JCSTWTxtbl[2][7] = {
 148         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},     /* 100MHz */
 149         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}      /* 133MHz */
 150 };
 151
 152 /* JCTSS */
 153 static const unsigned long JCTSStbl[2][7] = {
 154         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},     /* 100MHz */
 155         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}      /* 133MHz */
 156 };
 157
 158 /* JCENVT */
 159 static const unsigned long JCENVTtbl[2][7] = {
 160         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},     /* 100MHz */
 161         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}      /* 133MHz */
 162 };
 163
 164 /* JCACTSELS/JCACTSELM */
 165 static const unsigned long JCACTSELtbl[2][7] = {
 166         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},     /* 100MHz */
 167         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}      /* 133MHz */
 168 };
 169
 170 static const struct pci_device_id scc_pci_tbl[] = {
 171         { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
 172         { }     /* terminate list */
 173 };
 174
 175 /**
 176  *      scc_set_piomode - Initialize host controller PATA PIO timings
 177  *      @ap: Port whose timings we are configuring
 178  *      @adev: um
 179  *
 180  *      Set PIO mode for device.
 181  *
 182  *      LOCKING:
 183  *      None (inherited from caller).
 184  */
 185
 186 static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
 187 {
 188         unsigned int pio = adev->pio_mode - XFER_PIO_0;
 189         void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
 190         void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
 191         void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
 192         void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
 193         unsigned long reg;
 194         int offset;
 195
 196         reg = in_be32(cckctrl_port);
 197         if (reg & CCKCTRL_ATACLKOEN)
 198                 offset = 1;     /* 133MHz */
 199         else
 200                 offset = 0;     /* 100MHz */
 201
 202         reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
 203         out_be32(piosht_port, reg);
 204         reg = JCHCTtbl[offset][pio];
 205         out_be32(pioct_port, reg);
 206 }
 207
 208 /**
 209  *      scc_set_dmamode - Initialize host controller PATA DMA timings
 210  *      @ap: Port whose timings we are configuring
 211  *      @adev: um
 212  *
 213  *      Set UDMA mode for device.
 214  *
 215  *      LOCKING:
 216  *      None (inherited from caller).
 217  */
 218
 219 static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 220 {
 221         unsigned int udma = adev->dma_mode;
 222         unsigned int is_slave = (adev->devno != 0);
 223         u8 speed = udma;
 224         void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
 225         void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
 226         void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
 227         void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
 228         void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
 229         void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
 230         void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
 231         void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
 232         int offset, idx;
 233
 234         if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
 235                 offset = 1;     /* 133MHz */
 236         else
 237                 offset = 0;     /* 100MHz */
 238
 239         if (speed >= XFER_UDMA_0)
 240                 idx = speed - XFER_UDMA_0;
 241         else
 242                 return;
 243
 244         if (is_slave) {
 245                 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
 246                 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
 247                 out_be32(tdvhsel_port,
 248                          (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
 249         } else {
 250                 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
 251                 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
 252                 out_be32(tdvhsel_port,
 253                          (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
 254         }
 255         out_be32(udenvt_port,
 256                  JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
 257 }
 258
 259 unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
 260 {
 261         /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
 262         if (adev->class == ATA_DEV_ATAPI &&
 263             (mask & (0xE0 << ATA_SHIFT_UDMA))) {
 264                 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
 265                 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
 266         }
 267         return mask;
 268 }
 269
 270 /**
 271  *      scc_tf_load - send taskfile registers to host controller
 272  *      @ap: Port to which output is sent
 273  *      @tf: ATA taskfile register set
 274  *
 275  *      Note: Original code is ata_sff_tf_load().
 276  */
 277
 278 static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
 279 {
 280         struct ata_ioports *ioaddr = &ap->ioaddr;
 281         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 282
 283         if (tf->ctl != ap->last_ctl) {
 284                 out_be32(ioaddr->ctl_addr, tf->ctl);
 285                 ap->last_ctl = tf->ctl;
 286                 ata_wait_idle(ap);
 287         }
 288
 289         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 290                 out_be32(ioaddr->feature_addr, tf->hob_feature);
 291                 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
 292                 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
 293                 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
 294                 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
 295                 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
 296                         tf->hob_feature,
 297                         tf->hob_nsect,
 298                         tf->hob_lbal,
 299                         tf->hob_lbam,
 300                         tf->hob_lbah);
 301         }
 302
 303         if (is_addr) {
 304                 out_be32(ioaddr->feature_addr, tf->feature);
 305                 out_be32(ioaddr->nsect_addr, tf->nsect);
 306                 out_be32(ioaddr->lbal_addr, tf->lbal);
 307                 out_be32(ioaddr->lbam_addr, tf->lbam);
 308                 out_be32(ioaddr->lbah_addr, tf->lbah);
 309                 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
 310                         tf->feature,
 311                         tf->nsect,
 312                         tf->lbal,
 313                         tf->lbam,
 314                         tf->lbah);
 315         }
 316
 317         if (tf->flags & ATA_TFLAG_DEVICE) {
 318                 out_be32(ioaddr->device_addr, tf->device);
 319                 VPRINTK("device 0x%X\n", tf->device);
 320         }
 321
 322         ata_wait_idle(ap);
 323 }
 324
 325 /**
 326  *      scc_check_status - Read device status reg & clear interrupt
 327  *      @ap: port where the device is
 328  *
 329  *      Note: Original code is ata_check_status().
 330  */
 331
 332 static u8 scc_check_status (struct ata_port *ap)
 333 {
 334         return in_be32(ap->ioaddr.status_addr);
 335 }
 336
 337 /**
 338  *      scc_tf_read - input device's ATA taskfile shadow registers
 339  *      @ap: Port from which input is read
 340  *      @tf: ATA taskfile register set for storing input
 341  *
 342  *      Note: Original code is ata_sff_tf_read().
 343  */
 344
 345 static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
 346 {
 347         struct ata_ioports *ioaddr = &ap->ioaddr;
 348
 349         tf->command = scc_check_status(ap);
 350         tf->feature = in_be32(ioaddr->error_addr);
 351         tf->nsect = in_be32(ioaddr->nsect_addr);
 352         tf->lbal = in_be32(ioaddr->lbal_addr);
 353         tf->lbam = in_be32(ioaddr->lbam_addr);
 354         tf->lbah = in_be32(ioaddr->lbah_addr);
 355         tf->device = in_be32(ioaddr->device_addr);
 356
 357         if (tf->flags & ATA_TFLAG_LBA48) {
 358                 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
 359                 tf->hob_feature = in_be32(ioaddr->error_addr);
 360                 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
 361                 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
 362                 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
 363                 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
 364                 out_be32(ioaddr->ctl_addr, tf->ctl);
 365                 ap->last_ctl = tf->ctl;
 366         }
 367 }
 368
 369 /**
 370  *      scc_exec_command - issue ATA command to host controller
 371  *      @ap: port to which command is being issued
 372  *      @tf: ATA taskfile register set
 373  *
 374  *      Note: Original code is ata_sff_exec_command().
 375  */
 376
 377 static void scc_exec_command (struct ata_port *ap,
 378                               const struct ata_taskfile *tf)
 379 {
 380         DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
 381
 382         out_be32(ap->ioaddr.command_addr, tf->command);
 383         ata_sff_pause(ap);
 384 }
 385
 386 /**
 387  *      scc_check_altstatus - Read device alternate status reg
 388  *      @ap: port where the device is
 389  */
 390
 391 static u8 scc_check_altstatus (struct ata_port *ap)
 392 {
 393         return in_be32(ap->ioaddr.altstatus_addr);
 394 }
 395
 396 /**
 397  *      scc_dev_select - Select device 0/1 on ATA bus
 398  *      @ap: ATA channel to manipulate
 399  *      @device: ATA device (numbered from zero) to select
 400  *
 401  *      Note: Original code is ata_sff_dev_select().
 402  */
 403
 404 static void scc_dev_select (struct ata_port *ap, unsigned int device)
 405 {
 406         u8 tmp;
 407
 408         if (device == 0)
 409                 tmp = ATA_DEVICE_OBS;
 410         else
 411                 tmp = ATA_DEVICE_OBS | ATA_DEV1;
 412
 413         out_be32(ap->ioaddr.device_addr, tmp);
 414         ata_sff_pause(ap);
 415 }
 416
 417 /**
 418  *      scc_set_devctl - Write device control reg
 419  *      @ap: port where the device is
 420  *      @ctl: value to write
 421  */
 422
 423 static void scc_set_devctl(struct ata_port *ap, u8 ctl)
 424 {
 425         out_be32(ap->ioaddr.ctl_addr, ctl);
 426 }
 427
 428 /**
 429  *      scc_bmdma_setup - Set up PCI IDE BMDMA transaction
 430  *      @qc: Info associated with this ATA transaction.
 431  *
 432  *      Note: Original code is ata_bmdma_setup().
 433  */
 434
 435 static void scc_bmdma_setup (struct ata_queued_cmd *qc)
 436 {
 437         struct ata_port *ap = qc->ap;
 438         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 439         u8 dmactl;
 440         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 441
 442         /* load PRD table addr */
 443         out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma);
 444
 445         /* specify data direction, triple-check start bit is clear */
 446         dmactl = in_be32(mmio + SCC_DMA_CMD);
 447         dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
 448         if (!rw)
 449                 dmactl |= ATA_DMA_WR;
 450         out_be32(mmio + SCC_DMA_CMD, dmactl);
 451
 452         /* issue r/w command */
 453         ap->ops->sff_exec_command(ap, &qc->tf);
 454 }
 455
 456 /**
 457  *      scc_bmdma_start - Start a PCI IDE BMDMA transaction
 458  *      @qc: Info associated with this ATA transaction.
 459  *
 460  *      Note: Original code is ata_bmdma_start().
 461  */
 462
 463 static void scc_bmdma_start (struct ata_queued_cmd *qc)
 464 {
 465         struct ata_port *ap = qc->ap;
 466         u8 dmactl;
 467         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 468
 469         /* start host DMA transaction */
 470         dmactl = in_be32(mmio + SCC_DMA_CMD);
 471         out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
 472 }
 473
 474 /**
 475  *      scc_devchk - PATA device presence detection
 476  *      @ap: ATA channel to examine
 477  *      @device: Device to examine (starting at zero)
 478  *
 479  *      Note: Original code is ata_devchk().
 480  */
 481
 482 static unsigned int scc_devchk (struct ata_port *ap,
 483                                 unsigned int device)
 484 {
 485         struct ata_ioports *ioaddr = &ap->ioaddr;
 486         u8 nsect, lbal;
 487
 488         ap->ops->sff_dev_select(ap, device);
 489
 490         out_be32(ioaddr->nsect_addr, 0x55);
 491         out_be32(ioaddr->lbal_addr, 0xaa);
 492
 493         out_be32(ioaddr->nsect_addr, 0xaa);
 494         out_be32(ioaddr->lbal_addr, 0x55);
 495
 496         out_be32(ioaddr->nsect_addr, 0x55);
 497         out_be32(ioaddr->lbal_addr, 0xaa);
 498
 499         nsect = in_be32(ioaddr->nsect_addr);
 500         lbal = in_be32(ioaddr->lbal_addr);
 501
 502         if ((nsect == 0x55) && (lbal == 0xaa))
 503                 return 1;       /* we found a device */
 504
 505         return 0;               /* nothing found */
 506 }
 507
 508 /**
 509  *      scc_wait_after_reset - wait for devices to become ready after reset
 510  *
 511  *      Note: Original code is ata_sff_wait_after_reset
 512  */
 513
 514 static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
 515                                 unsigned long deadline)
 516 {
 517         struct ata_port *ap = link->ap;
 518         struct ata_ioports *ioaddr = &ap->ioaddr;
 519         unsigned int dev0 = devmask & (1 << 0);
 520         unsigned int dev1 = devmask & (1 << 1);
 521         int rc, ret = 0;
 522
 523         /* Spec mandates ">= 2ms" before checking status.  We wait
 524          * 150ms, because that was the magic delay used for ATAPI
 525          * devices in Hale Landis's ATADRVR, for the period of time
 526          * between when the ATA command register is written, and then
 527          * status is checked.  Because waiting for "a while" before
 528          * checking status is fine, post SRST, we perform this magic
 529          * delay here as well.
 530          *
 531          * Old drivers/ide uses the 2mS rule and then waits for ready.
 532          */
 533         ata_msleep(ap, 150);
 534
 535         /* always check readiness of the master device */
 536         rc = ata_sff_wait_ready(link, deadline);
 537         /* -ENODEV means the odd clown forgot the D7 pulldown resistor
 538          * and TF status is 0xff, bail out on it too.
 539          */
 540         if (rc)
 541                 return rc;
 542
 543         /* if device 1 was found in ata_devchk, wait for register
 544          * access briefly, then wait for BSY to clear.
 545          */
 546         if (dev1) {
 547                 int i;
 548
 549                 ap->ops->sff_dev_select(ap, 1);
 550
 551                 /* Wait for register access.  Some ATAPI devices fail
 552                  * to set nsect/lbal after reset, so don't waste too
 553                  * much time on it.  We're gonna wait for !BSY anyway.
 554                  */
 555                 for (i = 0; i < 2; i++) {
 556                         u8 nsect, lbal;
 557
 558                         nsect = in_be32(ioaddr->nsect_addr);
 559                         lbal = in_be32(ioaddr->lbal_addr);
 560                         if ((nsect == 1) && (lbal == 1))
 561                                 break;
 562                         ata_msleep(ap, 50);     /* give drive a breather */
 563                 }
 564
 565                 rc = ata_sff_wait_ready(link, deadline);
 566                 if (rc) {
 567                         if (rc != -ENODEV)
 568                                 return rc;
 569                         ret = rc;
 570                 }
 571         }
 572
 573         /* is all this really necessary? */
 574         ap->ops->sff_dev_select(ap, 0);
 575         if (dev1)
 576                 ap->ops->sff_dev_select(ap, 1);
 577         if (dev0)
 578                 ap->ops->sff_dev_select(ap, 0);
 579
 580         return ret;
 581 }
 582
 583 /**
 584  *      scc_bus_softreset - PATA device software reset
 585  *
 586  *      Note: Original code is ata_bus_softreset().
 587  */
 588
 589 static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
 590                                       unsigned long deadline)
 591 {
 592         struct ata_ioports *ioaddr = &ap->ioaddr;
 593
 594         DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
 595
 596         /* software reset.  causes dev0 to be selected */
 597         out_be32(ioaddr->ctl_addr, ap->ctl);
 598         udelay(20);
 599         out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
 600         udelay(20);
 601         out_be32(ioaddr->ctl_addr, ap->ctl);
 602
 603         scc_wait_after_reset(&ap->link, devmask, deadline);
 604
 605         return 0;
 606 }
 607
 608 /**
 609  *      scc_softreset - reset host port via ATA SRST
 610  *      @ap: port to reset
 611  *      @classes: resulting classes of attached devices
 612  *      @deadline: deadline jiffies for the operation
 613  *
 614  *      Note: Original code is ata_sff_softreset().
 615  */
 616
 617 static int scc_softreset(struct ata_link *link, unsigned int *classes,
 618                          unsigned long deadline)
 619 {
 620         struct ata_port *ap = link->ap;
 621         unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
 622         unsigned int devmask = 0, err_mask;
 623         u8 err;
 624
 625         DPRINTK("ENTER\n");
 626
 627         /* determine if device 0/1 are present */
 628         if (scc_devchk(ap, 0))
 629                 devmask |= (1 << 0);
 630         if (slave_possible && scc_devchk(ap, 1))
 631                 devmask |= (1 << 1);
 632
 633         /* select device 0 again */
 634         ap->ops->sff_dev_select(ap, 0);
 635
 636         /* issue bus reset */
 637         DPRINTK("about to softreset, devmask=%x\n", devmask);
 638         err_mask = scc_bus_softreset(ap, devmask, deadline);
 639         if (err_mask) {
 640                 ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", err_mask);
 641                 return -EIO;
 642         }
 643
 644         /* determine by signature whether we have ATA or ATAPI devices */
 645         classes[0] = ata_sff_dev_classify(&ap->link.device[0],
 646                                           devmask & (1 << 0), &err);
 647         if (slave_possible && err != 0x81)
 648                 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
 649                                                   devmask & (1 << 1), &err);
 650
 651         DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
 652         return 0;
 653 }
 654
 655 /**
 656  *      scc_bmdma_stop - Stop PCI IDE BMDMA transfer
 657  *      @qc: Command we are ending DMA for
 658  */
 659
 660 static void scc_bmdma_stop (struct ata_queued_cmd *qc)
 661 {
 662         struct ata_port *ap = qc->ap;
 663         void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
 664         void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
 665         u32 reg;
 666
 667         while (1) {
 668                 reg = in_be32(bmid_base + SCC_DMA_INTST);
 669
 670                 if (reg & INTSTS_SERROR) {
 671                         printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
 672                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
 673                         out_be32(bmid_base + SCC_DMA_CMD,
 674                                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
 675                         continue;
 676                 }
 677
 678                 if (reg & INTSTS_PRERR) {
 679                         u32 maea0, maec0;
 680                         maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
 681                         maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
 682                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
 683                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
 684                         out_be32(bmid_base + SCC_DMA_CMD,
 685                                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
 686                         continue;
 687                 }
 688
 689                 if (reg & INTSTS_RERR) {
 690                         printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
 691                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
 692                         out_be32(bmid_base + SCC_DMA_CMD,
 693                                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
 694                         continue;
 695                 }
 696
 697                 if (reg & INTSTS_ICERR) {
 698                         out_be32(bmid_base + SCC_DMA_CMD,
 699                                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
 700                         printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
 701                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
 702                         continue;
 703                 }
 704
 705                 if (reg & INTSTS_BMSINT) {
 706                         unsigned int classes;
 707                         unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
 708                         printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
 709                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
 710                         /* TBD: SW reset */
 711                         scc_softreset(&ap->link, &classes, deadline);
 712                         continue;
 713                 }
 714
 715                 if (reg & INTSTS_BMHE) {
 716                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
 717                         continue;
 718                 }
 719
 720                 if (reg & INTSTS_ACTEINT) {
 721                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
 722                         continue;
 723                 }
 724
 725                 if (reg & INTSTS_IOIRQS) {
 726                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
 727                         continue;
 728                 }
 729                 break;
 730         }
 731
 732         /* clear start/stop bit */
 733         out_be32(bmid_base + SCC_DMA_CMD,
 734                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
 735
 736         /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
 737         ata_sff_dma_pause(ap);  /* dummy read */
 738 }
 739
 740 /**
 741  *      scc_bmdma_status - Read PCI IDE BMDMA status
 742  *      @ap: Port associated with this ATA transaction.
 743  */
 744
 745 static u8 scc_bmdma_status (struct ata_port *ap)
 746 {
 747         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 748         u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
 749         u32 int_status = in_be32(mmio + SCC_DMA_INTST);
 750         struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
 751         static int retry = 0;
 752
 753         /* return if IOS_SS is cleared */
 754         if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
 755                 return host_stat;
 756
 757         /* errata A252,A308 workaround: Step4 */
 758         if ((scc_check_altstatus(ap) & ATA_ERR)
 759                                         && (int_status & INTSTS_INTRQ))
 760                 return (host_stat | ATA_DMA_INTR);
 761
 762         /* errata A308 workaround Step5 */
 763         if (int_status & INTSTS_IOIRQS) {
 764                 host_stat |= ATA_DMA_INTR;
 765
 766                 /* We don't check ATAPI DMA because it is limited to UDMA4 */
 767                 if ((qc->tf.protocol == ATA_PROT_DMA &&
 768                      qc->dev->xfer_mode > XFER_UDMA_4)) {
 769                         if (!(int_status & INTSTS_ACTEINT)) {
 770                                 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
 771                                        ap->print_id);
 772                                 host_stat |= ATA_DMA_ERR;
 773                                 if (retry++)
 774                                         ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
 775                         } else
 776                                 retry = 0;
 777                 }
 778         }
 779
 780         return host_stat;
 781 }
 782
 783 /**
 784  *      scc_data_xfer - Transfer data by PIO
 785  *      @dev: device for this I/O
 786  *      @buf: data buffer
 787  *      @buflen: buffer length
 788  *      @rw: read/write
 789  *
 790  *      Note: Original code is ata_sff_data_xfer().
 791  */
 792
 793 static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
 794                                    unsigned int buflen, int rw)
 795 {
 796         struct ata_port *ap = dev->link->ap;
 797         unsigned int words = buflen >> 1;
 798         unsigned int i;
 799         __le16 *buf16 = (__le16 *) buf;
 800         void __iomem *mmio = ap->ioaddr.data_addr;
 801
 802         /* Transfer multiple of 2 bytes */
 803         if (rw == READ)
 804                 for (i = 0; i < words; i++)
 805                         buf16[i] = cpu_to_le16(in_be32(mmio));
 806         else
 807                 for (i = 0; i < words; i++)
 808                         out_be32(mmio, le16_to_cpu(buf16[i]));
 809
 810         /* Transfer trailing 1 byte, if any. */
 811         if (unlikely(buflen & 0x01)) {
 812                 __le16 align_buf[1] = { 0 };
 813                 unsigned char *trailing_buf = buf + buflen - 1;
 814
 815                 if (rw == READ) {
 816                         align_buf[0] = cpu_to_le16(in_be32(mmio));
 817                         memcpy(trailing_buf, align_buf, 1);
 818                 } else {
 819                         memcpy(align_buf, trailing_buf, 1);
 820                         out_be32(mmio, le16_to_cpu(align_buf[0]));
 821                 }
 822                 words++;
 823         }
 824
 825         return words << 1;
 826 }
 827
 828 /**
 829  *      scc_postreset - standard postreset callback
 830  *      @ap: the target ata_port
 831  *      @classes: classes of attached devices
 832  *
 833  *      Note: Original code is ata_sff_postreset().
 834  */
 835
 836 static void scc_postreset(struct ata_link *link, unsigned int *classes)
 837 {
 838         struct ata_port *ap = link->ap;
 839
 840         DPRINTK("ENTER\n");
 841
 842         /* is double-select really necessary? */
 843         if (classes[0] != ATA_DEV_NONE)
 844                 ap->ops->sff_dev_select(ap, 1);
 845         if (classes[1] != ATA_DEV_NONE)
 846                 ap->ops->sff_dev_select(ap, 0);
 847
 848         /* bail out if no device is present */
 849         if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
 850                 DPRINTK("EXIT, no device\n");
 851                 return;
 852         }
 853
 854         /* set up device control */
 855         out_be32(ap->ioaddr.ctl_addr, ap->ctl);
 856
 857         DPRINTK("EXIT\n");
 858 }
 859
 860 /**
 861  *      scc_irq_clear - Clear PCI IDE BMDMA interrupt.
 862  *      @ap: Port associated with this ATA transaction.
 863  *
 864  *      Note: Original code is ata_bmdma_irq_clear().
 865  */
 866
 867 static void scc_irq_clear (struct ata_port *ap)
 868 {
 869         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 870
 871         if (!mmio)
 872                 return;
 873
 874         out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
 875 }
 876
 877 /**
 878  *      scc_port_start - Set port up for dma.
 879  *      @ap: Port to initialize
 880  *
 881  *      Allocate space for PRD table using ata_bmdma_port_start().
 882  *      Set PRD table address for PTERADD. (PRD Transfer End Read)
 883  */
 884
 885 static int scc_port_start (struct ata_port *ap)
 886 {
 887         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 888         int rc;
 889
 890         rc = ata_bmdma_port_start(ap);
 891         if (rc)
 892                 return rc;
 893
 894         out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma);
 895         return 0;
 896 }
 897
 898 /**
 899  *      scc_port_stop - Undo scc_port_start()
 900  *      @ap: Port to shut down
 901  *
 902  *      Reset PTERADD.
 903  */
 904
 905 static void scc_port_stop (struct ata_port *ap)
 906 {
 907         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 908
 909         out_be32(mmio + SCC_DMA_PTERADD, 0);
 910 }
 911
 912 static struct scsi_host_template scc_sht = {
 913         ATA_BMDMA_SHT(DRV_NAME),
 914 };
 915
 916 static struct ata_port_operations scc_pata_ops = {
 917         .inherits               = &ata_bmdma_port_ops,
 918
 919         .set_piomode            = scc_set_piomode,
 920         .set_dmamode            = scc_set_dmamode,
 921         .mode_filter            = scc_mode_filter,
 922
 923         .sff_tf_load            = scc_tf_load,
 924         .sff_tf_read            = scc_tf_read,
 925         .sff_exec_command       = scc_exec_command,
 926         .sff_check_status       = scc_check_status,
 927         .sff_check_altstatus    = scc_check_altstatus,
 928         .sff_dev_select         = scc_dev_select,
 929         .sff_set_devctl         = scc_set_devctl,
 930
 931         .bmdma_setup            = scc_bmdma_setup,
 932         .bmdma_start            = scc_bmdma_start,
 933         .bmdma_stop             = scc_bmdma_stop,
 934         .bmdma_status           = scc_bmdma_status,
 935         .sff_data_xfer          = scc_data_xfer,
 936
 937         .cable_detect           = ata_cable_80wire,
 938         .softreset              = scc_softreset,
 939         .postreset              = scc_postreset,
 940
 941         .sff_irq_clear          = scc_irq_clear,
 942
 943         .port_start             = scc_port_start,
 944         .port_stop              = scc_port_stop,
 945 };
 946
 947 static struct ata_port_info scc_port_info[] = {
 948         {
 949                 .flags          = ATA_FLAG_SLAVE_POSS,
 950                 .pio_mask       = ATA_PIO4,
 951                 /* No MWDMA */
 952                 .udma_mask      = ATA_UDMA6,
 953                 .port_ops       = &scc_pata_ops,
 954         },
 955 };
 956
 957 /**
 958  *      scc_reset_controller - initialize SCC PATA controller.
 959  */
 960
 961 static int scc_reset_controller(struct ata_host *host)
 962 {
 963         void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
 964         void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
 965         void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
 966         void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
 967         void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
 968         void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
 969         void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
 970         u32 reg = 0;
 971
 972         out_be32(cckctrl_port, reg);
 973         reg |= CCKCTRL_ATACLKOEN;
 974         out_be32(cckctrl_port, reg);
 975         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 976         out_be32(cckctrl_port, reg);
 977         reg |= CCKCTRL_CRST;
 978         out_be32(cckctrl_port, reg);
 979
 980         for (;;) {
 981                 reg = in_be32(cckctrl_port);
 982                 if (reg & CCKCTRL_CRST)
 983                         break;
 984                 udelay(5000);
 985         }
 986
 987         reg |= CCKCTRL_ATARESET;
 988         out_be32(cckctrl_port, reg);
 989         out_be32(ecmode_port, ECMODE_VALUE);
 990         out_be32(mode_port, MODE_JCUSFEN);
 991         out_be32(intmask_port, INTMASK_MSK);
 992
 993         if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
 994                 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
 995                 return -EIO;
 996         }
 997
 998         return 0;
 999 }
1000
1001 /**
1002  *      scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1003  *      @ioaddr: IO address structure to be initialized
1004  *      @base: base address of BMID region
1005  */
1006
1007 static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1008 {
1009         ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1010         ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1011         ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1012         ioaddr->bmdma_addr = base;
1013         ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1014         ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1015         ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1016         ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1017         ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1018         ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1019         ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1020         ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1021         ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1022         ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1023 }
1024
1025 static int scc_host_init(struct ata_host *host)
1026 {
1027         struct pci_dev *pdev = to_pci_dev(host->dev);
1028         int rc;
1029
1030         rc = scc_reset_controller(host);
1031         if (rc)
1032                 return rc;
1033
1034         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1035         if (rc)
1036                 return rc;
1037         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1038         if (rc)
1039                 return rc;
1040
1041         scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
1042
1043         pci_set_master(pdev);
1044
1045         return 0;
1046 }
1047
1048 /**
1049  *      scc_init_one - Register SCC PATA device with kernel services
1050  *      @pdev: PCI device to register
1051  *      @ent: Entry in scc_pci_tbl matching with @pdev
1052  *
1053  *      LOCKING:
1054  *      Inherited from PCI layer (may sleep).
1055  *
1056  *      RETURNS:
1057  *      Zero on success, or -ERRNO value.
1058  */
1059
1060 static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1061 {
1062         unsigned int board_idx = (unsigned int) ent->driver_data;
1063         const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
1064         struct ata_host *host;
1065         int rc;
1066
1067         ata_print_version_once(&pdev->dev, DRV_VERSION);
1068
1069         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1070         if (!host)
1071                 return -ENOMEM;
1072
1073         rc = pcim_enable_device(pdev);
1074         if (rc)
1075                 return rc;
1076
1077         rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1078         if (rc == -EBUSY)
1079                 pcim_pin_device(pdev);
1080         if (rc)
1081                 return rc;
1082         host->iomap = pcim_iomap_table(pdev);
1083
1084         ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1085         ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1086
1087         rc = scc_host_init(host);
1088         if (rc)
1089                 return rc;
1090
1091         return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
1092                                  IRQF_SHARED, &scc_sht);
1093 }
1094
1095 static struct pci_driver scc_pci_driver = {
1096         .name                   = DRV_NAME,
1097         .id_table               = scc_pci_tbl,
1098         .probe                  = scc_init_one,
1099         .remove                 = ata_pci_remove_one,
1100 #ifdef CONFIG_PM
1101         .suspend                = ata_pci_device_suspend,
1102         .resume                 = ata_pci_device_resume,
1103 #endif
1104 };
1105
1106 static int __init scc_init (void)
1107 {
1108         int rc;
1109
1110         DPRINTK("pci_register_driver\n");
1111         rc = pci_register_driver(&scc_pci_driver);
1112         if (rc)
1113                 return rc;
1114
1115         DPRINTK("done\n");
1116         return 0;
1117 }
1118
1119 static void __exit scc_exit (void)
1120 {
1121         pci_unregister_driver(&scc_pci_driver);
1122 }
1123
1124 module_init(scc_init);
1125 module_exit(scc_exit);
1126
1127 MODULE_AUTHOR("Toshiba corp");
1128 MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1129 MODULE_LICENSE("GPL");
1130 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1131 MODULE_VERSION(DRV_VERSION);