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drm/i915: Consolidate flushing the display plane
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob810ed2dca4c7a14b11f36308d5f1773cf8cd8e75
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
350 }
351
352 static const intel_limit_t intel_limits_i8xx_dvo = {
353 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
354 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
355 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
356 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
357 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
358 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
359 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
360 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
361 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
362 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
363 .find_pll = intel_find_best_PLL,
364 };
365
366 static const intel_limit_t intel_limits_i8xx_lvds = {
367 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
368 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
369 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
370 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
371 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
372 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
373 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
374 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
375 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
376 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
377 .find_pll = intel_find_best_PLL,
378 };
379
380 static const intel_limit_t intel_limits_i9xx_sdvo = {
381 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
382 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
383 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
384 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
385 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
386 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
387 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
388 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
389 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
390 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
391 .find_pll = intel_find_best_PLL,
392 };
393
394 static const intel_limit_t intel_limits_i9xx_lvds = {
395 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
396 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
397 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
398 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
399 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
400 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
401 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
402 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
403 /* The single-channel range is 25-112Mhz, and dual-channel
404 * is 80-224Mhz. Prefer single channel as much as possible.
405 */
406 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
407 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
408 .find_pll = intel_find_best_PLL,
409 };
410
411 /* below parameter and function is for G4X Chipset Family*/
412 static const intel_limit_t intel_limits_g4x_sdvo = {
413 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
414 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
415 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
416 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
417 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
418 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
419 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
420 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
421 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
422 .p2_slow = G4X_P2_SDVO_SLOW,
423 .p2_fast = G4X_P2_SDVO_FAST
424 },
425 .find_pll = intel_g4x_find_best_PLL,
426 };
427
428 static const intel_limit_t intel_limits_g4x_hdmi = {
429 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
430 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
431 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
432 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
433 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
434 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
435 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
436 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
437 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
438 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
439 .p2_fast = G4X_P2_HDMI_DAC_FAST
440 },
441 .find_pll = intel_g4x_find_best_PLL,
442 };
443
444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
445 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
447 .vco = { .min = G4X_VCO_MIN,
448 .max = G4X_VCO_MAX },
449 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
450 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
451 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
452 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
453 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
454 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
455 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
456 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
457 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
458 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
459 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
460 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
461 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
462 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
463 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
464 },
465 .find_pll = intel_g4x_find_best_PLL,
466 };
467
468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
469 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
471 .vco = { .min = G4X_VCO_MIN,
472 .max = G4X_VCO_MAX },
473 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
474 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
475 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
476 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
477 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
478 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
479 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
480 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
481 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
482 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
483 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
484 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
485 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
486 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
487 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
488 },
489 .find_pll = intel_g4x_find_best_PLL,
490 };
491
492 static const intel_limit_t intel_limits_g4x_display_port = {
493 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
494 .max = G4X_DOT_DISPLAY_PORT_MAX },
495 .vco = { .min = G4X_VCO_MIN,
496 .max = G4X_VCO_MAX},
497 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
498 .max = G4X_N_DISPLAY_PORT_MAX },
499 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
500 .max = G4X_M_DISPLAY_PORT_MAX },
501 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
502 .max = G4X_M1_DISPLAY_PORT_MAX },
503 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
504 .max = G4X_M2_DISPLAY_PORT_MAX },
505 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
506 .max = G4X_P_DISPLAY_PORT_MAX },
507 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
508 .max = G4X_P1_DISPLAY_PORT_MAX},
509 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
510 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
511 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
512 .find_pll = intel_find_pll_g4x_dp,
513 };
514
515 static const intel_limit_t intel_limits_pineview_sdvo = {
516 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
517 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
518 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
519 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
520 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
521 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
522 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
523 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
524 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
525 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
526 .find_pll = intel_find_best_PLL,
527 };
528
529 static const intel_limit_t intel_limits_pineview_lvds = {
530 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
531 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
532 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
533 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
534 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
535 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
536 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
537 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
538 /* Pineview only supports single-channel mode. */
539 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
540 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
541 .find_pll = intel_find_best_PLL,
542 };
543
544 static const intel_limit_t intel_limits_ironlake_dac = {
545 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
546 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
547 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
548 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
549 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
550 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
551 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
552 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
553 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
554 .p2_slow = IRONLAKE_DAC_P2_SLOW,
555 .p2_fast = IRONLAKE_DAC_P2_FAST },
556 .find_pll = intel_g4x_find_best_PLL,
557 };
558
559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
560 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
561 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
562 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
563 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
564 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
565 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
566 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
567 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
568 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
569 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
570 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
571 .find_pll = intel_g4x_find_best_PLL,
572 };
573
574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
575 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
576 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
577 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
578 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
579 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
580 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
581 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
582 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
583 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
584 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
585 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
586 .find_pll = intel_g4x_find_best_PLL,
587 };
588
589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
590 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
591 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
592 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
593 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
594 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
595 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
596 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
597 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
598 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
599 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
600 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
601 .find_pll = intel_g4x_find_best_PLL,
602 };
603
604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
605 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
606 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
607 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
608 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
609 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
610 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
611 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
612 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
613 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
614 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
615 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
616 .find_pll = intel_g4x_find_best_PLL,
617 };
618
619 static const intel_limit_t intel_limits_ironlake_display_port = {
620 .dot = { .min = IRONLAKE_DOT_MIN,
621 .max = IRONLAKE_DOT_MAX },
622 .vco = { .min = IRONLAKE_VCO_MIN,
623 .max = IRONLAKE_VCO_MAX},
624 .n = { .min = IRONLAKE_DP_N_MIN,
625 .max = IRONLAKE_DP_N_MAX },
626 .m = { .min = IRONLAKE_DP_M_MIN,
627 .max = IRONLAKE_DP_M_MAX },
628 .m1 = { .min = IRONLAKE_M1_MIN,
629 .max = IRONLAKE_M1_MAX },
630 .m2 = { .min = IRONLAKE_M2_MIN,
631 .max = IRONLAKE_M2_MAX },
632 .p = { .min = IRONLAKE_DP_P_MIN,
633 .max = IRONLAKE_DP_P_MAX },
634 .p1 = { .min = IRONLAKE_DP_P1_MIN,
635 .max = IRONLAKE_DP_P1_MAX},
636 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
637 .p2_slow = IRONLAKE_DP_P2_SLOW,
638 .p2_fast = IRONLAKE_DP_P2_FAST },
639 .find_pll = intel_find_pll_ironlake_dp,
640 };
641
642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
643 {
644 struct drm_device *dev = crtc->dev;
645 struct drm_i915_private *dev_priv = dev->dev_private;
646 const intel_limit_t *limit;
647 int refclk = 120;
648
649 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
650 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
651 refclk = 100;
652
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
661 if (refclk == 100)
662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
669 else
670 limit = &intel_limits_ironlake_dac;
671
672 return limit;
673 }
674
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676 {
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
686 else
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
698
699 return limit;
700 }
701
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
703 {
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_i9xx_lvds;
714 else
715 limit = &intel_limits_i9xx_sdvo;
716 } else if (IS_PINEVIEW(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_pineview_lvds;
719 else
720 limit = &intel_limits_pineview_sdvo;
721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
724 else
725 limit = &intel_limits_i8xx_dvo;
726 }
727 return limit;
728 }
729
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
732 {
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737 }
738
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740 {
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
743 return;
744 }
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749 }
750
751 /**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
755 {
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
759
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
765 }
766
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
768 /**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
774 {
775 const intel_limit_t *limit = intel_limit (crtc);
776 struct drm_device *dev = crtc->dev;
777
778 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
779 INTELPllInvalid ("p1 out of range\n");
780 if (clock->p < limit->p.min || limit->p.max < clock->p)
781 INTELPllInvalid ("p out of range\n");
782 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
783 INTELPllInvalid ("m2 out of range\n");
784 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
785 INTELPllInvalid ("m1 out of range\n");
786 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
787 INTELPllInvalid ("m1 <= m2\n");
788 if (clock->m < limit->m.min || limit->m.max < clock->m)
789 INTELPllInvalid ("m out of range\n");
790 if (clock->n < limit->n.min || limit->n.max < clock->n)
791 INTELPllInvalid ("n out of range\n");
792 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
793 INTELPllInvalid ("vco out of range\n");
794 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
795 * connector, etc., rather than just a single range.
796 */
797 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
798 INTELPllInvalid ("dot out of range\n");
799
800 return true;
801 }
802
803 static bool
804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
805 int target, int refclk, intel_clock_t *best_clock)
806
807 {
808 struct drm_device *dev = crtc->dev;
809 struct drm_i915_private *dev_priv = dev->dev_private;
810 intel_clock_t clock;
811 int err = target;
812
813 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
814 (I915_READ(LVDS)) != 0) {
815 /*
816 * For LVDS, if the panel is on, just rely on its current
817 * settings for dual-channel. We haven't figured out how to
818 * reliably set up different single/dual channel state, if we
819 * even can.
820 */
821 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
822 LVDS_CLKB_POWER_UP)
823 clock.p2 = limit->p2.p2_fast;
824 else
825 clock.p2 = limit->p2.p2_slow;
826 } else {
827 if (target < limit->p2.dot_limit)
828 clock.p2 = limit->p2.p2_slow;
829 else
830 clock.p2 = limit->p2.p2_fast;
831 }
832
833 memset (best_clock, 0, sizeof (*best_clock));
834
835 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
836 clock.m1++) {
837 for (clock.m2 = limit->m2.min;
838 clock.m2 <= limit->m2.max; clock.m2++) {
839 /* m1 is always 0 in Pineview */
840 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
841 break;
842 for (clock.n = limit->n.min;
843 clock.n <= limit->n.max; clock.n++) {
844 for (clock.p1 = limit->p1.min;
845 clock.p1 <= limit->p1.max; clock.p1++) {
846 int this_err;
847
848 intel_clock(dev, refclk, &clock);
849
850 if (!intel_PLL_is_valid(crtc, &clock))
851 continue;
852
853 this_err = abs(clock.dot - target);
854 if (this_err < err) {
855 *best_clock = clock;
856 err = this_err;
857 }
858 }
859 }
860 }
861 }
862
863 return (err != target);
864 }
865
866 static bool
867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
868 int target, int refclk, intel_clock_t *best_clock)
869 {
870 struct drm_device *dev = crtc->dev;
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 intel_clock_t clock;
873 int max_n;
874 bool found;
875 /* approximately equals target * 0.00585 */
876 int err_most = (target >> 8) + (target >> 9);
877 found = false;
878
879 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
880 int lvds_reg;
881
882 if (HAS_PCH_SPLIT(dev))
883 lvds_reg = PCH_LVDS;
884 else
885 lvds_reg = LVDS;
886 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
887 LVDS_CLKB_POWER_UP)
888 clock.p2 = limit->p2.p2_fast;
889 else
890 clock.p2 = limit->p2.p2_slow;
891 } else {
892 if (target < limit->p2.dot_limit)
893 clock.p2 = limit->p2.p2_slow;
894 else
895 clock.p2 = limit->p2.p2_fast;
896 }
897
898 memset(best_clock, 0, sizeof(*best_clock));
899 max_n = limit->n.max;
900 /* based on hardware requirement, prefer smaller n to precision */
901 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
902 /* based on hardware requirement, prefere larger m1,m2 */
903 for (clock.m1 = limit->m1.max;
904 clock.m1 >= limit->m1.min; clock.m1--) {
905 for (clock.m2 = limit->m2.max;
906 clock.m2 >= limit->m2.min; clock.m2--) {
907 for (clock.p1 = limit->p1.max;
908 clock.p1 >= limit->p1.min; clock.p1--) {
909 int this_err;
910
911 intel_clock(dev, refclk, &clock);
912 if (!intel_PLL_is_valid(crtc, &clock))
913 continue;
914 this_err = abs(clock.dot - target) ;
915 if (this_err < err_most) {
916 *best_clock = clock;
917 err_most = this_err;
918 max_n = clock.n;
919 found = true;
920 }
921 }
922 }
923 }
924 }
925 return found;
926 }
927
928 static bool
929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
930 int target, int refclk, intel_clock_t *best_clock)
931 {
932 struct drm_device *dev = crtc->dev;
933 intel_clock_t clock;
934
935 /* return directly when it is eDP */
936 if (HAS_eDP)
937 return true;
938
939 if (target < 200000) {
940 clock.n = 1;
941 clock.p1 = 2;
942 clock.p2 = 10;
943 clock.m1 = 12;
944 clock.m2 = 9;
945 } else {
946 clock.n = 2;
947 clock.p1 = 1;
948 clock.p2 = 10;
949 clock.m1 = 14;
950 clock.m2 = 8;
951 }
952 intel_clock(dev, refclk, &clock);
953 memcpy(best_clock, &clock, sizeof(intel_clock_t));
954 return true;
955 }
956
957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
958 static bool
959 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
960 int target, int refclk, intel_clock_t *best_clock)
961 {
962 intel_clock_t clock;
963 if (target < 200000) {
964 clock.p1 = 2;
965 clock.p2 = 10;
966 clock.n = 2;
967 clock.m1 = 23;
968 clock.m2 = 8;
969 } else {
970 clock.p1 = 1;
971 clock.p2 = 10;
972 clock.n = 1;
973 clock.m1 = 14;
974 clock.m2 = 2;
975 }
976 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
977 clock.p = (clock.p1 * clock.p2);
978 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
979 clock.vco = 0;
980 memcpy(best_clock, &clock, sizeof(intel_clock_t));
981 return true;
982 }
983
984 /**
985 * intel_wait_for_vblank - wait for vblank on a given pipe
986 * @dev: drm device
987 * @pipe: pipe to wait for
988 *
989 * Wait for vblank to occur on a given pipe. Needed for various bits of
990 * mode setting code.
991 */
992 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
993 {
994 struct drm_i915_private *dev_priv = dev->dev_private;
995 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
996
997 /* Clear existing vblank status. Note this will clear any other
998 * sticky status fields as well.
999 *
1000 * This races with i915_driver_irq_handler() with the result
1001 * that either function could miss a vblank event. Here it is not
1002 * fatal, as we will either wait upon the next vblank interrupt or
1003 * timeout. Generally speaking intel_wait_for_vblank() is only
1004 * called during modeset at which time the GPU should be idle and
1005 * should *not* be performing page flips and thus not waiting on
1006 * vblanks...
1007 * Currently, the result of us stealing a vblank from the irq
1008 * handler is that a single frame will be skipped during swapbuffers.
1009 */
1010 I915_WRITE(pipestat_reg,
1011 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1012
1013 /* Wait for vblank interrupt bit to set */
1014 if (wait_for(I915_READ(pipestat_reg) &
1015 PIPE_VBLANK_INTERRUPT_STATUS,
1016 50))
1017 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 }
1019
1020 /**
1021 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1022 * @dev: drm device
1023 * @pipe: pipe to wait for
1024 *
1025 * After disabling a pipe, we can't wait for vblank in the usual way,
1026 * spinning on the vblank interrupt status bit, since we won't actually
1027 * see an interrupt when the pipe is disabled.
1028 *
1029 * So this function waits for the display line value to settle (it
1030 * usually ends up stopping at the start of the next frame).
1031 */
1032 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1033 {
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1035 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1036 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1037 u32 last_line, line;
1038
1039 /* Wait for the display line to settle */
1040 line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1041 do {
1042 last_line = line;
1043 MSLEEP(5);
1044 line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1045 } while (line != last_line && time_after(timeout, jiffies));
1046
1047 if (line != last_line)
1048 DRM_DEBUG_KMS("vblank wait timed out\n");
1049 }
1050
1051 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1052 {
1053 struct drm_device *dev = crtc->dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 struct drm_framebuffer *fb = crtc->fb;
1056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1057 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1059 int plane, i;
1060 u32 fbc_ctl, fbc_ctl2;
1061
1062 if (fb->pitch == dev_priv->cfb_pitch &&
1063 obj_priv->fence_reg == dev_priv->cfb_fence &&
1064 intel_crtc->plane == dev_priv->cfb_plane &&
1065 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1066 return;
1067
1068 i8xx_disable_fbc(dev);
1069
1070 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1071
1072 if (fb->pitch < dev_priv->cfb_pitch)
1073 dev_priv->cfb_pitch = fb->pitch;
1074
1075 /* FBC_CTL wants 64B units */
1076 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1077 dev_priv->cfb_fence = obj_priv->fence_reg;
1078 dev_priv->cfb_plane = intel_crtc->plane;
1079 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1080
1081 /* Clear old tags */
1082 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1083 I915_WRITE(FBC_TAG + (i * 4), 0);
1084
1085 /* Set it up... */
1086 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1087 if (obj_priv->tiling_mode != I915_TILING_NONE)
1088 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1089 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1090 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1091
1092 /* enable it... */
1093 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1094 if (IS_I945GM(dev))
1095 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1096 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1097 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1098 if (obj_priv->tiling_mode != I915_TILING_NONE)
1099 fbc_ctl |= dev_priv->cfb_fence;
1100 I915_WRITE(FBC_CONTROL, fbc_ctl);
1101
1102 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1103 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1104 }
1105
1106 void i8xx_disable_fbc(struct drm_device *dev)
1107 {
1108 struct drm_i915_private *dev_priv = dev->dev_private;
1109 u32 fbc_ctl;
1110
1111 /* Disable compression */
1112 fbc_ctl = I915_READ(FBC_CONTROL);
1113 fbc_ctl &= ~FBC_CTL_EN;
1114 I915_WRITE(FBC_CONTROL, fbc_ctl);
1115
1116 /* Wait for compressing bit to clear */
1117 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1118 DRM_DEBUG_KMS("FBC idle timed out\n");
1119 return;
1120 }
1121
1122 DRM_DEBUG_KMS("disabled FBC\n");
1123 }
1124
1125 static bool i8xx_fbc_enabled(struct drm_device *dev)
1126 {
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1130 }
1131
1132 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1133 {
1134 struct drm_device *dev = crtc->dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 struct drm_framebuffer *fb = crtc->fb;
1137 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1138 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1140 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1141 unsigned long stall_watermark = 200;
1142 u32 dpfc_ctl;
1143
1144 dpfc_ctl = I915_READ(DPFC_CONTROL);
1145 if (dpfc_ctl & DPFC_CTL_EN) {
1146 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1147 dev_priv->cfb_fence == obj_priv->fence_reg &&
1148 dev_priv->cfb_plane == intel_crtc->plane &&
1149 dev_priv->cfb_y == crtc->y)
1150 return;
1151
1152 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1153 POSTING_READ(DPFC_CONTROL);
1154 intel_wait_for_vblank(dev, intel_crtc->pipe);
1155 }
1156
1157 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1158 dev_priv->cfb_fence = obj_priv->fence_reg;
1159 dev_priv->cfb_plane = intel_crtc->plane;
1160 dev_priv->cfb_y = crtc->y;
1161
1162 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1163 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1164 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1165 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1166 } else {
1167 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1168 }
1169
1170 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1171 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1172 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1173 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1174
1175 /* enable it... */
1176 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1177
1178 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1179 }
1180
1181 void g4x_disable_fbc(struct drm_device *dev)
1182 {
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 u32 dpfc_ctl;
1185
1186 /* Disable compression */
1187 dpfc_ctl = I915_READ(DPFC_CONTROL);
1188 if (dpfc_ctl & DPFC_CTL_EN) {
1189 dpfc_ctl &= ~DPFC_CTL_EN;
1190 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1191
1192 DRM_DEBUG_KMS("disabled FBC\n");
1193 }
1194 }
1195
1196 static bool g4x_fbc_enabled(struct drm_device *dev)
1197 {
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199
1200 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1201 }
1202
1203 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1204 {
1205 struct drm_device *dev = crtc->dev;
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1207 struct drm_framebuffer *fb = crtc->fb;
1208 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1209 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1211 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1212 unsigned long stall_watermark = 200;
1213 u32 dpfc_ctl;
1214
1215 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1216 if (dpfc_ctl & DPFC_CTL_EN) {
1217 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1218 dev_priv->cfb_fence == obj_priv->fence_reg &&
1219 dev_priv->cfb_plane == intel_crtc->plane &&
1220 dev_priv->cfb_offset == obj_priv->gtt_offset &&
1221 dev_priv->cfb_y == crtc->y)
1222 return;
1223
1224 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1225 POSTING_READ(ILK_DPFC_CONTROL);
1226 intel_wait_for_vblank(dev, intel_crtc->pipe);
1227 }
1228
1229 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1230 dev_priv->cfb_fence = obj_priv->fence_reg;
1231 dev_priv->cfb_plane = intel_crtc->plane;
1232 dev_priv->cfb_offset = obj_priv->gtt_offset;
1233 dev_priv->cfb_y = crtc->y;
1234
1235 dpfc_ctl &= DPFC_RESERVED;
1236 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1237 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1238 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1239 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1240 } else {
1241 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1242 }
1243
1244 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1245 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1246 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1248 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1249 /* enable it... */
1250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1251
1252 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1253 }
1254
1255 void ironlake_disable_fbc(struct drm_device *dev)
1256 {
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 u32 dpfc_ctl;
1259
1260 /* Disable compression */
1261 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1262 if (dpfc_ctl & DPFC_CTL_EN) {
1263 dpfc_ctl &= ~DPFC_CTL_EN;
1264 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1265
1266 DRM_DEBUG_KMS("disabled FBC\n");
1267 }
1268 }
1269
1270 static bool ironlake_fbc_enabled(struct drm_device *dev)
1271 {
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273
1274 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1275 }
1276
1277 bool intel_fbc_enabled(struct drm_device *dev)
1278 {
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280
1281 if (!dev_priv->display.fbc_enabled)
1282 return false;
1283
1284 return dev_priv->display.fbc_enabled(dev);
1285 }
1286
1287 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1288 {
1289 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1290
1291 if (!dev_priv->display.enable_fbc)
1292 return;
1293
1294 dev_priv->display.enable_fbc(crtc, interval);
1295 }
1296
1297 void intel_disable_fbc(struct drm_device *dev)
1298 {
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300
1301 if (!dev_priv->display.disable_fbc)
1302 return;
1303
1304 dev_priv->display.disable_fbc(dev);
1305 }
1306
1307 /**
1308 * intel_update_fbc - enable/disable FBC as needed
1309 * @dev: the drm_device
1310 *
1311 * Set up the framebuffer compression hardware at mode set time. We
1312 * enable it if possible:
1313 * - plane A only (on pre-965)
1314 * - no pixel mulitply/line duplication
1315 * - no alpha buffer discard
1316 * - no dual wide
1317 * - framebuffer <= 2048 in width, 1536 in height
1318 *
1319 * We can't assume that any compression will take place (worst case),
1320 * so the compressed buffer has to be the same size as the uncompressed
1321 * one. It also must reside (along with the line length buffer) in
1322 * stolen memory.
1323 *
1324 * We need to enable/disable FBC on a global basis.
1325 */
1326 static void intel_update_fbc(struct drm_device *dev)
1327 {
1328 struct drm_i915_private *dev_priv = dev->dev_private;
1329 struct drm_crtc *crtc = NULL, *tmp_crtc;
1330 struct intel_crtc *intel_crtc;
1331 struct drm_framebuffer *fb;
1332 struct intel_framebuffer *intel_fb;
1333 struct drm_i915_gem_object *obj_priv;
1334
1335 DRM_DEBUG_KMS("\n");
1336
1337 if (!i915_powersave)
1338 return;
1339
1340 if (!I915_HAS_FBC(dev))
1341 return;
1342
1343 /*
1344 * If FBC is already on, we just have to verify that we can
1345 * keep it that way...
1346 * Need to disable if:
1347 * - more than one pipe is active
1348 * - changing FBC params (stride, fence, mode)
1349 * - new fb is too large to fit in compressed buffer
1350 * - going to an unsupported config (interlace, pixel multiply, etc.)
1351 */
1352 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1353 if (tmp_crtc->enabled) {
1354 if (crtc) {
1355 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1356 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1357 goto out_disable;
1358 }
1359 crtc = tmp_crtc;
1360 }
1361 }
1362
1363 if (!crtc || crtc->fb == NULL) {
1364 DRM_DEBUG_KMS("no output, disabling\n");
1365 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1366 goto out_disable;
1367 }
1368
1369 intel_crtc = to_intel_crtc(crtc);
1370 fb = crtc->fb;
1371 intel_fb = to_intel_framebuffer(fb);
1372 obj_priv = to_intel_bo(intel_fb->obj);
1373
1374 if (intel_fb->obj->size > dev_priv->cfb_size) {
1375 DRM_DEBUG_KMS("framebuffer too large, disabling "
1376 "compression\n");
1377 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1378 goto out_disable;
1379 }
1380 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1381 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1382 DRM_DEBUG_KMS("mode incompatible with compression, "
1383 "disabling\n");
1384 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1385 goto out_disable;
1386 }
1387 if ((crtc->mode.hdisplay > 2048) ||
1388 (crtc->mode.vdisplay > 1536)) {
1389 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1390 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1391 goto out_disable;
1392 }
1393 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1394 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1395 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1396 goto out_disable;
1397 }
1398 if (obj_priv->tiling_mode != I915_TILING_X) {
1399 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1400 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1401 goto out_disable;
1402 }
1403
1404 /* If the kernel debugger is active, always disable compression */
1405 if (in_dbg_master())
1406 goto out_disable;
1407
1408 intel_enable_fbc(crtc, 500);
1409 return;
1410
1411 out_disable:
1412 /* Multiple disables should be harmless */
1413 if (intel_fbc_enabled(dev)) {
1414 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1415 intel_disable_fbc(dev);
1416 }
1417 }
1418
1419 int
1420 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1421 {
1422 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1423 u32 alignment;
1424 int ret;
1425
1426 switch (obj_priv->tiling_mode) {
1427 case I915_TILING_NONE:
1428 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1429 alignment = 128 * 1024;
1430 else if (IS_I965G(dev))
1431 alignment = 4 * 1024;
1432 else
1433 alignment = 64 * 1024;
1434 break;
1435 case I915_TILING_X:
1436 /* pin() will align the object as required by fence */
1437 alignment = 0;
1438 break;
1439 case I915_TILING_Y:
1440 /* FIXME: Is this true? */
1441 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1442 return -EINVAL;
1443 default:
1444 BUG();
1445 }
1446
1447 ret = i915_gem_object_pin(obj, alignment);
1448 if (ret != 0)
1449 return ret;
1450
1451 ret = i915_gem_object_set_to_display_plane(obj);
1452 if (ret != 0) {
1453 i915_gem_object_unpin(obj);
1454 return ret;
1455 }
1456
1457 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1458 * fence, whereas 965+ only requires a fence if using
1459 * framebuffer compression. For simplicity, we always install
1460 * a fence as the cost is not that onerous.
1461 */
1462 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1463 obj_priv->tiling_mode != I915_TILING_NONE) {
1464 ret = i915_gem_object_get_fence_reg(obj);
1465 if (ret != 0) {
1466 i915_gem_object_unpin(obj);
1467 return ret;
1468 }
1469 }
1470
1471 return 0;
1472 }
1473
1474 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1475 static int
1476 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1477 int x, int y)
1478 {
1479 struct drm_device *dev = crtc->dev;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1482 struct intel_framebuffer *intel_fb;
1483 struct drm_i915_gem_object *obj_priv;
1484 struct drm_gem_object *obj;
1485 int plane = intel_crtc->plane;
1486 unsigned long Start, Offset;
1487 u32 dspcntr;
1488 u32 reg;
1489
1490 switch (plane) {
1491 case 0:
1492 case 1:
1493 break;
1494 default:
1495 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1496 return -EINVAL;
1497 }
1498
1499 intel_fb = to_intel_framebuffer(fb);
1500 obj = intel_fb->obj;
1501 obj_priv = to_intel_bo(obj);
1502
1503 reg = DSPCNTR(plane);
1504 dspcntr = I915_READ(reg);
1505 /* Mask out pixel format bits in case we change it */
1506 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1507 switch (fb->bits_per_pixel) {
1508 case 8:
1509 dspcntr |= DISPPLANE_8BPP;
1510 break;
1511 case 16:
1512 if (fb->depth == 15)
1513 dspcntr |= DISPPLANE_15_16BPP;
1514 else
1515 dspcntr |= DISPPLANE_16BPP;
1516 break;
1517 case 24:
1518 case 32:
1519 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1520 break;
1521 default:
1522 DRM_ERROR("Unknown color depth\n");
1523 return -EINVAL;
1524 }
1525 if (IS_I965G(dev)) {
1526 if (obj_priv->tiling_mode != I915_TILING_NONE)
1527 dspcntr |= DISPPLANE_TILED;
1528 else
1529 dspcntr &= ~DISPPLANE_TILED;
1530 }
1531
1532 if (HAS_PCH_SPLIT(dev))
1533 /* must disable */
1534 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1535
1536 I915_WRITE(reg, dspcntr);
1537
1538 Start = obj_priv->gtt_offset;
1539 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1540
1541 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1542 Start, Offset, x, y, fb->pitch);
1543 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1544 if (IS_I965G(dev)) {
1545 I915_WRITE(DSPSURF(plane), Start);
1546 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1547 I915_WRITE(DSPADDR(plane), Offset);
1548 } else
1549 I915_WRITE(DSPADDR(plane), Start + Offset);
1550 POSTING_READ(reg);
1551
1552 intel_update_fbc(dev);
1553 intel_increase_pllclock(crtc);
1554
1555 return 0;
1556 }
1557
1558 static int
1559 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1560 struct drm_framebuffer *old_fb)
1561 {
1562 struct drm_device *dev = crtc->dev;
1563 struct drm_i915_master_private *master_priv;
1564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1565 struct intel_framebuffer *intel_fb;
1566 struct drm_i915_gem_object *obj_priv;
1567 struct drm_gem_object *obj;
1568 int pipe = intel_crtc->pipe;
1569 int plane = intel_crtc->plane;
1570 int ret;
1571
1572 /* no fb bound */
1573 if (!crtc->fb) {
1574 DRM_DEBUG_KMS("No FB bound\n");
1575 return 0;
1576 }
1577
1578 switch (plane) {
1579 case 0:
1580 case 1:
1581 break;
1582 default:
1583 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1584 return -EINVAL;
1585 }
1586
1587 intel_fb = to_intel_framebuffer(crtc->fb);
1588 obj = intel_fb->obj;
1589 obj_priv = to_intel_bo(obj);
1590
1591 mutex_lock(&dev->struct_mutex);
1592 ret = intel_pin_and_fence_fb_obj(dev, obj);
1593 if (ret != 0) {
1594 mutex_unlock(&dev->struct_mutex);
1595 return ret;
1596 }
1597
1598 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1599 if (ret) {
1600 i915_gem_object_unpin(obj);
1601 mutex_unlock(&dev->struct_mutex);
1602 return ret;
1603 }
1604
1605 if (old_fb) {
1606 intel_fb = to_intel_framebuffer(old_fb);
1607 obj_priv = to_intel_bo(intel_fb->obj);
1608 i915_gem_object_unpin(intel_fb->obj);
1609 }
1610
1611 mutex_unlock(&dev->struct_mutex);
1612
1613 if (!dev->primary->master)
1614 return 0;
1615
1616 master_priv = dev->primary->master->driver_priv;
1617 if (!master_priv->sarea_priv)
1618 return 0;
1619
1620 if (pipe) {
1621 master_priv->sarea_priv->pipeB_x = x;
1622 master_priv->sarea_priv->pipeB_y = y;
1623 } else {
1624 master_priv->sarea_priv->pipeA_x = x;
1625 master_priv->sarea_priv->pipeA_y = y;
1626 }
1627
1628 return 0;
1629 }
1630
1631 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1632 {
1633 struct drm_device *dev = crtc->dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 u32 dpa_ctl;
1636
1637 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1638 dpa_ctl = I915_READ(DP_A);
1639 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1640
1641 if (clock < 200000) {
1642 u32 temp;
1643 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1644 /* workaround for 160Mhz:
1645 1) program 0x4600c bits 15:0 = 0x8124
1646 2) program 0x46010 bit 0 = 1
1647 3) program 0x46034 bit 24 = 1
1648 4) program 0x64000 bit 14 = 1
1649 */
1650 temp = I915_READ(0x4600c);
1651 temp &= 0xffff0000;
1652 I915_WRITE(0x4600c, temp | 0x8124);
1653
1654 temp = I915_READ(0x46010);
1655 I915_WRITE(0x46010, temp | 1);
1656
1657 temp = I915_READ(0x46034);
1658 I915_WRITE(0x46034, temp | (1 << 24));
1659 } else {
1660 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1661 }
1662 I915_WRITE(DP_A, dpa_ctl);
1663
1664 POSTING_READ(DP_A);
1665 udelay(500);
1666 }
1667
1668 /* The FDI link training functions for ILK/Ibexpeak. */
1669 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1670 {
1671 struct drm_device *dev = crtc->dev;
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1674 int pipe = intel_crtc->pipe;
1675 u32 reg, temp, tries;
1676
1677 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1678 for train result */
1679 reg = FDI_RX_IMR(pipe);
1680 temp = I915_READ(reg);
1681 temp &= ~FDI_RX_SYMBOL_LOCK;
1682 temp &= ~FDI_RX_BIT_LOCK;
1683 I915_WRITE(reg, temp);
1684 I915_READ(reg);
1685 udelay(150);
1686
1687 /* enable CPU FDI TX and PCH FDI RX */
1688 reg = FDI_TX_CTL(pipe);
1689 temp = I915_READ(reg);
1690 temp &= ~(7 << 19);
1691 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1692 temp &= ~FDI_LINK_TRAIN_NONE;
1693 temp |= FDI_LINK_TRAIN_PATTERN_1;
1694 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1695
1696 reg = FDI_RX_CTL(pipe);
1697 temp = I915_READ(reg);
1698 temp &= ~FDI_LINK_TRAIN_NONE;
1699 temp |= FDI_LINK_TRAIN_PATTERN_1;
1700 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1701
1702 POSTING_READ(reg);
1703 udelay(150);
1704
1705 reg = FDI_RX_IIR(pipe);
1706 for (tries = 0; tries < 5; tries++) {
1707 temp = I915_READ(reg);
1708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1709
1710 if ((temp & FDI_RX_BIT_LOCK)) {
1711 DRM_DEBUG_KMS("FDI train 1 done.\n");
1712 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1713 break;
1714 }
1715 }
1716 if (tries == 5)
1717 DRM_ERROR("FDI train 1 fail!\n");
1718
1719 /* Train 2 */
1720 reg = FDI_TX_CTL(pipe);
1721 temp = I915_READ(reg);
1722 temp &= ~FDI_LINK_TRAIN_NONE;
1723 temp |= FDI_LINK_TRAIN_PATTERN_2;
1724 I915_WRITE(reg, temp);
1725
1726 reg = FDI_RX_CTL(pipe);
1727 temp = I915_READ(reg);
1728 temp &= ~FDI_LINK_TRAIN_NONE;
1729 temp |= FDI_LINK_TRAIN_PATTERN_2;
1730 I915_WRITE(reg, temp);
1731
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 reg = FDI_RX_IIR(pipe);
1736 for (tries = 0; tries < 5; tries++) {
1737 temp = I915_READ(reg);
1738 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1739
1740 if (temp & FDI_RX_SYMBOL_LOCK) {
1741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1742 DRM_DEBUG_KMS("FDI train 2 done.\n");
1743 break;
1744 }
1745 }
1746 if (tries == 5)
1747 DRM_ERROR("FDI train 2 fail!\n");
1748
1749 DRM_DEBUG_KMS("FDI train done\n");
1750 }
1751
1752 static const int const snb_b_fdi_train_param [] = {
1753 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1754 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1755 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1756 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1757 };
1758
1759 /* The FDI link training functions for SNB/Cougarpoint. */
1760 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1761 {
1762 struct drm_device *dev = crtc->dev;
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1765 int pipe = intel_crtc->pipe;
1766 u32 reg, temp, i;
1767
1768 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1769 for train result */
1770 reg = FDI_RX_IMR(pipe);
1771 temp = I915_READ(reg);
1772 temp &= ~FDI_RX_SYMBOL_LOCK;
1773 temp &= ~FDI_RX_BIT_LOCK;
1774 I915_WRITE(reg, temp);
1775
1776 POSTING_READ(reg);
1777 udelay(150);
1778
1779 /* enable CPU FDI TX and PCH FDI RX */
1780 reg = FDI_TX_CTL(pipe);
1781 temp = I915_READ(reg);
1782 temp &= ~(7 << 19);
1783 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1784 temp &= ~FDI_LINK_TRAIN_NONE;
1785 temp |= FDI_LINK_TRAIN_PATTERN_1;
1786 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1787 /* SNB-B */
1788 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1789 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1790
1791 reg = FDI_RX_CTL(pipe);
1792 temp = I915_READ(reg);
1793 if (HAS_PCH_CPT(dev)) {
1794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1796 } else {
1797 temp &= ~FDI_LINK_TRAIN_NONE;
1798 temp |= FDI_LINK_TRAIN_PATTERN_1;
1799 }
1800 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1801
1802 POSTING_READ(reg);
1803 udelay(150);
1804
1805 for (i = 0; i < 4; i++ ) {
1806 reg = FDI_TX_CTL(pipe);
1807 temp = I915_READ(reg);
1808 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1809 temp |= snb_b_fdi_train_param[i];
1810 I915_WRITE(reg, temp);
1811
1812 POSTING_READ(reg);
1813 udelay(500);
1814
1815 reg = FDI_RX_IIR(pipe);
1816 temp = I915_READ(reg);
1817 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1818
1819 if (temp & FDI_RX_BIT_LOCK) {
1820 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1821 DRM_DEBUG_KMS("FDI train 1 done.\n");
1822 break;
1823 }
1824 }
1825 if (i == 4)
1826 DRM_ERROR("FDI train 1 fail!\n");
1827
1828 /* Train 2 */
1829 reg = FDI_TX_CTL(pipe);
1830 temp = I915_READ(reg);
1831 temp &= ~FDI_LINK_TRAIN_NONE;
1832 temp |= FDI_LINK_TRAIN_PATTERN_2;
1833 if (IS_GEN6(dev)) {
1834 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1835 /* SNB-B */
1836 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1837 }
1838 I915_WRITE(reg, temp);
1839
1840 reg = FDI_RX_CTL(pipe);
1841 temp = I915_READ(reg);
1842 if (HAS_PCH_CPT(dev)) {
1843 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1844 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1845 } else {
1846 temp &= ~FDI_LINK_TRAIN_NONE;
1847 temp |= FDI_LINK_TRAIN_PATTERN_2;
1848 }
1849 I915_WRITE(reg, temp);
1850
1851 POSTING_READ(reg);
1852 udelay(150);
1853
1854 for (i = 0; i < 4; i++ ) {
1855 reg = FDI_TX_CTL(pipe);
1856 temp = I915_READ(reg);
1857 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1858 temp |= snb_b_fdi_train_param[i];
1859 I915_WRITE(reg, temp);
1860
1861 POSTING_READ(reg);
1862 udelay(500);
1863
1864 reg = FDI_RX_IIR(pipe);
1865 temp = I915_READ(reg);
1866 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1867
1868 if (temp & FDI_RX_SYMBOL_LOCK) {
1869 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1870 DRM_DEBUG_KMS("FDI train 2 done.\n");
1871 break;
1872 }
1873 }
1874 if (i == 4)
1875 DRM_ERROR("FDI train 2 fail!\n");
1876
1877 DRM_DEBUG_KMS("FDI train done.\n");
1878 }
1879
1880 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1881 {
1882 struct drm_device *dev = crtc->dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1885 int pipe = intel_crtc->pipe;
1886 u32 reg, temp;
1887
1888 /* Write the TU size bits so error detection works */
1889 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1890 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1891
1892 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1893 reg = FDI_RX_CTL(pipe);
1894 temp = I915_READ(reg);
1895 temp &= ~((0x7 << 19) | (0x7 << 16));
1896 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1897 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1898 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1899
1900 POSTING_READ(reg);
1901 udelay(200);
1902
1903 /* Switch from Rawclk to PCDclk */
1904 temp = I915_READ(reg);
1905 I915_WRITE(reg, temp | FDI_PCDCLK);
1906
1907 POSTING_READ(reg);
1908 udelay(200);
1909
1910 /* Enable CPU FDI TX PLL, always on for Ironlake */
1911 reg = FDI_TX_CTL(pipe);
1912 temp = I915_READ(reg);
1913 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1914 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1915
1916 POSTING_READ(reg);
1917 udelay(100);
1918 }
1919 }
1920
1921 static void intel_flush_display_plane(struct drm_device *dev,
1922 int plane)
1923 {
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1925 u32 reg = DSPADDR(plane);
1926 I915_WRITE(reg, I915_READ(reg));
1927 }
1928
1929 /*
1930 * When we disable a pipe, we need to clear any pending scanline wait events
1931 * to avoid hanging the ring, which we assume we are waiting on.
1932 */
1933 static void intel_clear_scanline_wait(struct drm_device *dev)
1934 {
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 u32 tmp;
1937
1938 if (IS_GEN2(dev))
1939 /* Can't break the hang on i8xx */
1940 return;
1941
1942 tmp = I915_READ(PRB0_CTL);
1943 if (tmp & RING_WAIT) {
1944 I915_WRITE(PRB0_CTL, tmp);
1945 POSTING_READ(PRB0_CTL);
1946 }
1947 }
1948
1949 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1950 {
1951 struct drm_device *dev = crtc->dev;
1952 struct drm_i915_private *dev_priv = dev->dev_private;
1953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1954 int pipe = intel_crtc->pipe;
1955 int plane = intel_crtc->plane;
1956 u32 reg, temp;
1957
1958 if (intel_crtc->active)
1959 return;
1960
1961 intel_crtc->active = true;
1962 intel_update_watermarks(dev);
1963
1964 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1965 temp = I915_READ(PCH_LVDS);
1966 if ((temp & LVDS_PORT_EN) == 0)
1967 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1968 }
1969
1970 ironlake_fdi_enable(crtc);
1971
1972 /* Enable panel fitting for LVDS */
1973 if (dev_priv->pch_pf_size &&
1974 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1975 || HAS_eDP || intel_pch_has_edp(crtc))) {
1976 /* Force use of hard-coded filter coefficients
1977 * as some pre-programmed values are broken,
1978 * e.g. x201.
1979 */
1980 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1981 PF_ENABLE | PF_FILTER_MED_3x3);
1982 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1983 dev_priv->pch_pf_pos);
1984 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1985 dev_priv->pch_pf_size);
1986 }
1987
1988 /* Enable CPU pipe */
1989 reg = PIPECONF(pipe);
1990 temp = I915_READ(reg);
1991 if ((temp & PIPECONF_ENABLE) == 0) {
1992 I915_WRITE(reg, temp | PIPECONF_ENABLE);
1993 POSTING_READ(reg);
1994 udelay(100);
1995 }
1996
1997 /* configure and enable CPU plane */
1998 reg = DSPCNTR(plane);
1999 temp = I915_READ(reg);
2000 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2001 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2002 intel_flush_display_plane(dev, plane);
2003 }
2004
2005 /* For PCH output, training FDI link */
2006 if (IS_GEN6(dev))
2007 gen6_fdi_link_train(crtc);
2008 else
2009 ironlake_fdi_link_train(crtc);
2010
2011 /* enable PCH DPLL */
2012 reg = PCH_DPLL(pipe);
2013 temp = I915_READ(reg);
2014 if ((temp & DPLL_VCO_ENABLE) == 0) {
2015 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2016 POSTING_READ(reg);
2017 udelay(200);
2018 }
2019
2020 if (HAS_PCH_CPT(dev)) {
2021 /* Be sure PCH DPLL SEL is set */
2022 temp = I915_READ(PCH_DPLL_SEL);
2023 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2024 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2025 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2026 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2027 I915_WRITE(PCH_DPLL_SEL, temp);
2028 }
2029
2030 /* set transcoder timing */
2031 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2032 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2033 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2034
2035 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2036 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2037 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2038
2039 /* enable normal train */
2040 reg = FDI_TX_CTL(pipe);
2041 temp = I915_READ(reg);
2042 temp &= ~FDI_LINK_TRAIN_NONE;
2043 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2044 I915_WRITE(reg, temp);
2045
2046 reg = FDI_RX_CTL(pipe);
2047 temp = I915_READ(reg);
2048 if (HAS_PCH_CPT(dev)) {
2049 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2050 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2051 } else {
2052 temp &= ~FDI_LINK_TRAIN_NONE;
2053 temp |= FDI_LINK_TRAIN_NONE;
2054 }
2055 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2056
2057 /* wait one idle pattern time */
2058 POSTING_READ(reg);
2059 udelay(100);
2060
2061 /* For PCH DP, enable TRANS_DP_CTL */
2062 if (HAS_PCH_CPT(dev) &&
2063 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2064 reg = TRANS_DP_CTL(pipe);
2065 temp = I915_READ(reg);
2066 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2067 TRANS_DP_SYNC_MASK);
2068 temp |= (TRANS_DP_OUTPUT_ENABLE |
2069 TRANS_DP_ENH_FRAMING);
2070
2071 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2072 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2073 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2074 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2075
2076 switch (intel_trans_dp_port_sel(crtc)) {
2077 case PCH_DP_B:
2078 temp |= TRANS_DP_PORT_SEL_B;
2079 break;
2080 case PCH_DP_C:
2081 temp |= TRANS_DP_PORT_SEL_C;
2082 break;
2083 case PCH_DP_D:
2084 temp |= TRANS_DP_PORT_SEL_D;
2085 break;
2086 default:
2087 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2088 temp |= TRANS_DP_PORT_SEL_B;
2089 break;
2090 }
2091
2092 I915_WRITE(reg, temp);
2093 }
2094
2095 /* enable PCH transcoder */
2096 reg = TRANSCONF(pipe);
2097 temp = I915_READ(reg);
2098 /*
2099 * make the BPC in transcoder be consistent with
2100 * that in pipeconf reg.
2101 */
2102 temp &= ~PIPE_BPC_MASK;
2103 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2104 I915_WRITE(reg, temp | TRANS_ENABLE);
2105 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2106 DRM_ERROR("failed to enable transcoder\n");
2107
2108 intel_crtc_load_lut(crtc);
2109 intel_update_fbc(dev);
2110 intel_crtc_update_cursor(crtc, true);
2111 }
2112
2113 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2114 {
2115 struct drm_device *dev = crtc->dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2118 int pipe = intel_crtc->pipe;
2119 int plane = intel_crtc->plane;
2120 u32 reg, temp;
2121
2122 if (!intel_crtc->active)
2123 return;
2124
2125 drm_vblank_off(dev, pipe);
2126 intel_crtc_update_cursor(crtc, false);
2127
2128 /* Disable display plane */
2129 reg = DSPCNTR(plane);
2130 temp = I915_READ(reg);
2131 if (temp & DISPLAY_PLANE_ENABLE) {
2132 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2133 intel_flush_display_plane(dev, plane);
2134 }
2135
2136 if (dev_priv->cfb_plane == plane &&
2137 dev_priv->display.disable_fbc)
2138 dev_priv->display.disable_fbc(dev);
2139
2140 /* disable cpu pipe, disable after all planes disabled */
2141 reg = PIPECONF(pipe);
2142 temp = I915_READ(reg);
2143 if (temp & PIPECONF_ENABLE) {
2144 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2145 /* wait for cpu pipe off, pipe state */
2146 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2147 DRM_ERROR("failed to turn off cpu pipe\n");
2148 }
2149
2150 /* Disable PF */
2151 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2152 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2153
2154 /* disable CPU FDI tx and PCH FDI rx */
2155 reg = FDI_TX_CTL(pipe);
2156 temp = I915_READ(reg);
2157 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2158 POSTING_READ(reg);
2159
2160 reg = FDI_RX_CTL(pipe);
2161 temp = I915_READ(reg);
2162 temp &= ~(0x7 << 16);
2163 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2164 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2165
2166 POSTING_READ(reg);
2167 udelay(100);
2168
2169 /* still set train pattern 1 */
2170 reg = FDI_TX_CTL(pipe);
2171 temp = I915_READ(reg);
2172 temp &= ~FDI_LINK_TRAIN_NONE;
2173 temp |= FDI_LINK_TRAIN_PATTERN_1;
2174 I915_WRITE(reg, temp);
2175
2176 reg = FDI_RX_CTL(pipe);
2177 temp = I915_READ(reg);
2178 if (HAS_PCH_CPT(dev)) {
2179 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2180 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2181 } else {
2182 temp &= ~FDI_LINK_TRAIN_NONE;
2183 temp |= FDI_LINK_TRAIN_PATTERN_1;
2184 }
2185 /* BPC in FDI rx is consistent with that in PIPECONF */
2186 temp &= ~(0x07 << 16);
2187 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2188 I915_WRITE(reg, temp);
2189
2190 POSTING_READ(reg);
2191 udelay(100);
2192
2193 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2194 temp = I915_READ(PCH_LVDS);
2195 if (temp & LVDS_PORT_EN) {
2196 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2197 POSTING_READ(PCH_LVDS);
2198 udelay(100);
2199 }
2200 }
2201
2202 /* disable PCH transcoder */
2203 reg = TRANSCONF(plane);
2204 temp = I915_READ(reg);
2205 if (temp & TRANS_ENABLE) {
2206 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2207 /* wait for PCH transcoder off, transcoder state */
2208 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2209 DRM_ERROR("failed to disable transcoder\n");
2210 }
2211
2212 if (HAS_PCH_CPT(dev)) {
2213 /* disable TRANS_DP_CTL */
2214 reg = TRANS_DP_CTL(pipe);
2215 temp = I915_READ(reg);
2216 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2217 I915_WRITE(reg, temp);
2218
2219 /* disable DPLL_SEL */
2220 temp = I915_READ(PCH_DPLL_SEL);
2221 if (pipe == 0)
2222 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2223 else
2224 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2225 I915_WRITE(PCH_DPLL_SEL, temp);
2226 }
2227
2228 /* disable PCH DPLL */
2229 reg = PCH_DPLL(pipe);
2230 temp = I915_READ(reg);
2231 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2232
2233 /* Switch from PCDclk to Rawclk */
2234 reg = FDI_RX_CTL(pipe);
2235 temp = I915_READ(reg);
2236 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2237
2238 /* Disable CPU FDI TX PLL */
2239 reg = FDI_TX_CTL(pipe);
2240 temp = I915_READ(reg);
2241 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2242
2243 POSTING_READ(reg);
2244 udelay(100);
2245
2246 reg = FDI_RX_CTL(pipe);
2247 temp = I915_READ(reg);
2248 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2249
2250 /* Wait for the clocks to turn off. */
2251 POSTING_READ(reg);
2252 udelay(100);
2253
2254 intel_crtc->active = false;
2255 intel_update_watermarks(dev);
2256 intel_update_fbc(dev);
2257 intel_clear_scanline_wait(dev);
2258 }
2259
2260 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2261 {
2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263 int pipe = intel_crtc->pipe;
2264 int plane = intel_crtc->plane;
2265
2266 /* XXX: When our outputs are all unaware of DPMS modes other than off
2267 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2268 */
2269 switch (mode) {
2270 case DRM_MODE_DPMS_ON:
2271 case DRM_MODE_DPMS_STANDBY:
2272 case DRM_MODE_DPMS_SUSPEND:
2273 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2274 ironlake_crtc_enable(crtc);
2275 break;
2276
2277 case DRM_MODE_DPMS_OFF:
2278 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2279 ironlake_crtc_disable(crtc);
2280 break;
2281 }
2282 }
2283
2284 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2285 {
2286 if (!enable && intel_crtc->overlay) {
2287 struct drm_device *dev = intel_crtc->base.dev;
2288
2289 mutex_lock(&dev->struct_mutex);
2290 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2291 mutex_unlock(&dev->struct_mutex);
2292 }
2293
2294 /* Let userspace switch the overlay on again. In most cases userspace
2295 * has to recompute where to put it anyway.
2296 */
2297 }
2298
2299 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2300 {
2301 struct drm_device *dev = crtc->dev;
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2304 int pipe = intel_crtc->pipe;
2305 int plane = intel_crtc->plane;
2306 u32 reg, temp;
2307
2308 if (intel_crtc->active)
2309 return;
2310
2311 intel_crtc->active = true;
2312 intel_update_watermarks(dev);
2313
2314 /* Enable the DPLL */
2315 reg = DPLL(pipe);
2316 temp = I915_READ(reg);
2317 if ((temp & DPLL_VCO_ENABLE) == 0) {
2318 I915_WRITE(reg, temp);
2319
2320 /* Wait for the clocks to stabilize. */
2321 POSTING_READ(reg);
2322 udelay(150);
2323
2324 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2325
2326 /* Wait for the clocks to stabilize. */
2327 POSTING_READ(reg);
2328 udelay(150);
2329
2330 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2331
2332 /* Wait for the clocks to stabilize. */
2333 POSTING_READ(reg);
2334 udelay(150);
2335 }
2336
2337 /* Enable the pipe */
2338 reg = PIPECONF(pipe);
2339 temp = I915_READ(reg);
2340 if ((temp & PIPECONF_ENABLE) == 0)
2341 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2342
2343 /* Enable the plane */
2344 reg = DSPCNTR(plane);
2345 temp = I915_READ(reg);
2346 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2347 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2348 intel_flush_display_plane(dev, plane);
2349 }
2350
2351 intel_crtc_load_lut(crtc);
2352 intel_update_fbc(dev);
2353
2354 /* Give the overlay scaler a chance to enable if it's on this pipe */
2355 intel_crtc_dpms_overlay(intel_crtc, true);
2356 intel_crtc_update_cursor(crtc, true);
2357 }
2358
2359 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2360 {
2361 struct drm_device *dev = crtc->dev;
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2364 int pipe = intel_crtc->pipe;
2365 int plane = intel_crtc->plane;
2366 u32 reg, temp;
2367
2368 if (!intel_crtc->active)
2369 return;
2370
2371 /* Give the overlay scaler a chance to disable if it's on this pipe */
2372 intel_crtc_dpms_overlay(intel_crtc, false);
2373 intel_crtc_update_cursor(crtc, false);
2374 drm_vblank_off(dev, pipe);
2375
2376 if (dev_priv->cfb_plane == plane &&
2377 dev_priv->display.disable_fbc)
2378 dev_priv->display.disable_fbc(dev);
2379
2380 /* Disable display plane */
2381 reg = DSPCNTR(plane);
2382 temp = I915_READ(reg);
2383 if (temp & DISPLAY_PLANE_ENABLE) {
2384 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2385 /* Flush the plane changes */
2386 intel_flush_display_plane(dev, plane);
2387
2388 /* Wait for vblank for the disable to take effect */
2389 if (!IS_I9XX(dev))
2390 intel_wait_for_vblank_off(dev, pipe);
2391 }
2392
2393 /* Don't disable pipe A or pipe A PLLs if needed */
2394 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2395 goto done;
2396
2397 /* Next, disable display pipes */
2398 reg = PIPECONF(pipe);
2399 temp = I915_READ(reg);
2400 if (temp & PIPECONF_ENABLE) {
2401 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2402
2403 /* Wait for vblank for the disable to take effect. */
2404 POSTING_READ(reg);
2405 intel_wait_for_vblank_off(dev, pipe);
2406 }
2407
2408 reg = DPLL(pipe);
2409 temp = I915_READ(reg);
2410 if (temp & DPLL_VCO_ENABLE) {
2411 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2412
2413 /* Wait for the clocks to turn off. */
2414 POSTING_READ(reg);
2415 udelay(150);
2416 }
2417
2418 done:
2419 intel_crtc->active = false;
2420 intel_update_fbc(dev);
2421 intel_update_watermarks(dev);
2422 intel_clear_scanline_wait(dev);
2423 }
2424
2425 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2426 {
2427 /* XXX: When our outputs are all unaware of DPMS modes other than off
2428 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2429 */
2430 switch (mode) {
2431 case DRM_MODE_DPMS_ON:
2432 case DRM_MODE_DPMS_STANDBY:
2433 case DRM_MODE_DPMS_SUSPEND:
2434 i9xx_crtc_enable(crtc);
2435 break;
2436 case DRM_MODE_DPMS_OFF:
2437 i9xx_crtc_disable(crtc);
2438 break;
2439 }
2440 }
2441
2442 /**
2443 * Sets the power management mode of the pipe and plane.
2444 */
2445 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2446 {
2447 struct drm_device *dev = crtc->dev;
2448 struct drm_i915_private *dev_priv = dev->dev_private;
2449 struct drm_i915_master_private *master_priv;
2450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451 int pipe = intel_crtc->pipe;
2452 bool enabled;
2453
2454 if (intel_crtc->dpms_mode == mode)
2455 return;
2456
2457 intel_crtc->dpms_mode = mode;
2458
2459 dev_priv->display.dpms(crtc, mode);
2460
2461 if (!dev->primary->master)
2462 return;
2463
2464 master_priv = dev->primary->master->driver_priv;
2465 if (!master_priv->sarea_priv)
2466 return;
2467
2468 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2469
2470 switch (pipe) {
2471 case 0:
2472 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2473 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2474 break;
2475 case 1:
2476 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2477 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2478 break;
2479 default:
2480 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2481 break;
2482 }
2483 }
2484
2485 /* Prepare for a mode set.
2486 *
2487 * Note we could be a lot smarter here. We need to figure out which outputs
2488 * will be enabled, which disabled (in short, how the config will changes)
2489 * and perform the minimum necessary steps to accomplish that, e.g. updating
2490 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2491 * panel fitting is in the proper state, etc.
2492 */
2493 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2494 {
2495 i9xx_crtc_disable(crtc);
2496 }
2497
2498 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2499 {
2500 i9xx_crtc_enable(crtc);
2501 }
2502
2503 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2504 {
2505 ironlake_crtc_disable(crtc);
2506 }
2507
2508 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2509 {
2510 ironlake_crtc_enable(crtc);
2511 }
2512
2513 void intel_encoder_prepare (struct drm_encoder *encoder)
2514 {
2515 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2516 /* lvds has its own version of prepare see intel_lvds_prepare */
2517 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2518 }
2519
2520 void intel_encoder_commit (struct drm_encoder *encoder)
2521 {
2522 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2523 /* lvds has its own version of commit see intel_lvds_commit */
2524 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2525 }
2526
2527 void intel_encoder_destroy(struct drm_encoder *encoder)
2528 {
2529 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2530
2531 if (intel_encoder->ddc_bus)
2532 intel_i2c_destroy(intel_encoder->ddc_bus);
2533
2534 if (intel_encoder->i2c_bus)
2535 intel_i2c_destroy(intel_encoder->i2c_bus);
2536
2537 drm_encoder_cleanup(encoder);
2538 kfree(intel_encoder);
2539 }
2540
2541 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2542 struct drm_display_mode *mode,
2543 struct drm_display_mode *adjusted_mode)
2544 {
2545 struct drm_device *dev = crtc->dev;
2546 if (HAS_PCH_SPLIT(dev)) {
2547 /* FDI link clock is fixed at 2.7G */
2548 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2549 return false;
2550 }
2551 return true;
2552 }
2553
2554 static int i945_get_display_clock_speed(struct drm_device *dev)
2555 {
2556 return 400000;
2557 }
2558
2559 static int i915_get_display_clock_speed(struct drm_device *dev)
2560 {
2561 return 333000;
2562 }
2563
2564 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2565 {
2566 return 200000;
2567 }
2568
2569 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2570 {
2571 u16 gcfgc = 0;
2572
2573 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2574
2575 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2576 return 133000;
2577 else {
2578 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2579 case GC_DISPLAY_CLOCK_333_MHZ:
2580 return 333000;
2581 default:
2582 case GC_DISPLAY_CLOCK_190_200_MHZ:
2583 return 190000;
2584 }
2585 }
2586 }
2587
2588 static int i865_get_display_clock_speed(struct drm_device *dev)
2589 {
2590 return 266000;
2591 }
2592
2593 static int i855_get_display_clock_speed(struct drm_device *dev)
2594 {
2595 u16 hpllcc = 0;
2596 /* Assume that the hardware is in the high speed state. This
2597 * should be the default.
2598 */
2599 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2600 case GC_CLOCK_133_200:
2601 case GC_CLOCK_100_200:
2602 return 200000;
2603 case GC_CLOCK_166_250:
2604 return 250000;
2605 case GC_CLOCK_100_133:
2606 return 133000;
2607 }
2608
2609 /* Shouldn't happen */
2610 return 0;
2611 }
2612
2613 static int i830_get_display_clock_speed(struct drm_device *dev)
2614 {
2615 return 133000;
2616 }
2617
2618 struct fdi_m_n {
2619 u32 tu;
2620 u32 gmch_m;
2621 u32 gmch_n;
2622 u32 link_m;
2623 u32 link_n;
2624 };
2625
2626 static void
2627 fdi_reduce_ratio(u32 *num, u32 *den)
2628 {
2629 while (*num > 0xffffff || *den > 0xffffff) {
2630 *num >>= 1;
2631 *den >>= 1;
2632 }
2633 }
2634
2635 #define DATA_N 0x800000
2636 #define LINK_N 0x80000
2637
2638 static void
2639 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2640 int link_clock, struct fdi_m_n *m_n)
2641 {
2642 u64 temp;
2643
2644 m_n->tu = 64; /* default size */
2645
2646 temp = (u64) DATA_N * pixel_clock;
2647 temp = div_u64(temp, link_clock);
2648 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2649 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2650 m_n->gmch_n = DATA_N;
2651 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2652
2653 temp = (u64) LINK_N * pixel_clock;
2654 m_n->link_m = div_u64(temp, link_clock);
2655 m_n->link_n = LINK_N;
2656 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2657 }
2658
2659
2660 struct intel_watermark_params {
2661 unsigned long fifo_size;
2662 unsigned long max_wm;
2663 unsigned long default_wm;
2664 unsigned long guard_size;
2665 unsigned long cacheline_size;
2666 };
2667
2668 /* Pineview has different values for various configs */
2669 static struct intel_watermark_params pineview_display_wm = {
2670 PINEVIEW_DISPLAY_FIFO,
2671 PINEVIEW_MAX_WM,
2672 PINEVIEW_DFT_WM,
2673 PINEVIEW_GUARD_WM,
2674 PINEVIEW_FIFO_LINE_SIZE
2675 };
2676 static struct intel_watermark_params pineview_display_hplloff_wm = {
2677 PINEVIEW_DISPLAY_FIFO,
2678 PINEVIEW_MAX_WM,
2679 PINEVIEW_DFT_HPLLOFF_WM,
2680 PINEVIEW_GUARD_WM,
2681 PINEVIEW_FIFO_LINE_SIZE
2682 };
2683 static struct intel_watermark_params pineview_cursor_wm = {
2684 PINEVIEW_CURSOR_FIFO,
2685 PINEVIEW_CURSOR_MAX_WM,
2686 PINEVIEW_CURSOR_DFT_WM,
2687 PINEVIEW_CURSOR_GUARD_WM,
2688 PINEVIEW_FIFO_LINE_SIZE,
2689 };
2690 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2691 PINEVIEW_CURSOR_FIFO,
2692 PINEVIEW_CURSOR_MAX_WM,
2693 PINEVIEW_CURSOR_DFT_WM,
2694 PINEVIEW_CURSOR_GUARD_WM,
2695 PINEVIEW_FIFO_LINE_SIZE
2696 };
2697 static struct intel_watermark_params g4x_wm_info = {
2698 G4X_FIFO_SIZE,
2699 G4X_MAX_WM,
2700 G4X_MAX_WM,
2701 2,
2702 G4X_FIFO_LINE_SIZE,
2703 };
2704 static struct intel_watermark_params g4x_cursor_wm_info = {
2705 I965_CURSOR_FIFO,
2706 I965_CURSOR_MAX_WM,
2707 I965_CURSOR_DFT_WM,
2708 2,
2709 G4X_FIFO_LINE_SIZE,
2710 };
2711 static struct intel_watermark_params i965_cursor_wm_info = {
2712 I965_CURSOR_FIFO,
2713 I965_CURSOR_MAX_WM,
2714 I965_CURSOR_DFT_WM,
2715 2,
2716 I915_FIFO_LINE_SIZE,
2717 };
2718 static struct intel_watermark_params i945_wm_info = {
2719 I945_FIFO_SIZE,
2720 I915_MAX_WM,
2721 1,
2722 2,
2723 I915_FIFO_LINE_SIZE
2724 };
2725 static struct intel_watermark_params i915_wm_info = {
2726 I915_FIFO_SIZE,
2727 I915_MAX_WM,
2728 1,
2729 2,
2730 I915_FIFO_LINE_SIZE
2731 };
2732 static struct intel_watermark_params i855_wm_info = {
2733 I855GM_FIFO_SIZE,
2734 I915_MAX_WM,
2735 1,
2736 2,
2737 I830_FIFO_LINE_SIZE
2738 };
2739 static struct intel_watermark_params i830_wm_info = {
2740 I830_FIFO_SIZE,
2741 I915_MAX_WM,
2742 1,
2743 2,
2744 I830_FIFO_LINE_SIZE
2745 };
2746
2747 static struct intel_watermark_params ironlake_display_wm_info = {
2748 ILK_DISPLAY_FIFO,
2749 ILK_DISPLAY_MAXWM,
2750 ILK_DISPLAY_DFTWM,
2751 2,
2752 ILK_FIFO_LINE_SIZE
2753 };
2754
2755 static struct intel_watermark_params ironlake_cursor_wm_info = {
2756 ILK_CURSOR_FIFO,
2757 ILK_CURSOR_MAXWM,
2758 ILK_CURSOR_DFTWM,
2759 2,
2760 ILK_FIFO_LINE_SIZE
2761 };
2762
2763 static struct intel_watermark_params ironlake_display_srwm_info = {
2764 ILK_DISPLAY_SR_FIFO,
2765 ILK_DISPLAY_MAX_SRWM,
2766 ILK_DISPLAY_DFT_SRWM,
2767 2,
2768 ILK_FIFO_LINE_SIZE
2769 };
2770
2771 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2772 ILK_CURSOR_SR_FIFO,
2773 ILK_CURSOR_MAX_SRWM,
2774 ILK_CURSOR_DFT_SRWM,
2775 2,
2776 ILK_FIFO_LINE_SIZE
2777 };
2778
2779 /**
2780 * intel_calculate_wm - calculate watermark level
2781 * @clock_in_khz: pixel clock
2782 * @wm: chip FIFO params
2783 * @pixel_size: display pixel size
2784 * @latency_ns: memory latency for the platform
2785 *
2786 * Calculate the watermark level (the level at which the display plane will
2787 * start fetching from memory again). Each chip has a different display
2788 * FIFO size and allocation, so the caller needs to figure that out and pass
2789 * in the correct intel_watermark_params structure.
2790 *
2791 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2792 * on the pixel size. When it reaches the watermark level, it'll start
2793 * fetching FIFO line sized based chunks from memory until the FIFO fills
2794 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2795 * will occur, and a display engine hang could result.
2796 */
2797 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2798 struct intel_watermark_params *wm,
2799 int pixel_size,
2800 unsigned long latency_ns)
2801 {
2802 long entries_required, wm_size;
2803
2804 /*
2805 * Note: we need to make sure we don't overflow for various clock &
2806 * latency values.
2807 * clocks go from a few thousand to several hundred thousand.
2808 * latency is usually a few thousand
2809 */
2810 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2811 1000;
2812 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2813
2814 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2815
2816 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2817
2818 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2819
2820 /* Don't promote wm_size to unsigned... */
2821 if (wm_size > (long)wm->max_wm)
2822 wm_size = wm->max_wm;
2823 if (wm_size <= 0)
2824 wm_size = wm->default_wm;
2825 return wm_size;
2826 }
2827
2828 struct cxsr_latency {
2829 int is_desktop;
2830 int is_ddr3;
2831 unsigned long fsb_freq;
2832 unsigned long mem_freq;
2833 unsigned long display_sr;
2834 unsigned long display_hpll_disable;
2835 unsigned long cursor_sr;
2836 unsigned long cursor_hpll_disable;
2837 };
2838
2839 static const struct cxsr_latency cxsr_latency_table[] = {
2840 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2841 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2842 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2843 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2844 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2845
2846 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2847 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2848 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2849 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2850 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2851
2852 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2853 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2854 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2855 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2856 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2857
2858 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2859 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2860 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2861 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2862 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2863
2864 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2865 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2866 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2867 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2868 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2869
2870 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2871 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2872 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2873 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2874 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2875 };
2876
2877 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2878 int is_ddr3,
2879 int fsb,
2880 int mem)
2881 {
2882 const struct cxsr_latency *latency;
2883 int i;
2884
2885 if (fsb == 0 || mem == 0)
2886 return NULL;
2887
2888 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2889 latency = &cxsr_latency_table[i];
2890 if (is_desktop == latency->is_desktop &&
2891 is_ddr3 == latency->is_ddr3 &&
2892 fsb == latency->fsb_freq && mem == latency->mem_freq)
2893 return latency;
2894 }
2895
2896 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2897
2898 return NULL;
2899 }
2900
2901 static void pineview_disable_cxsr(struct drm_device *dev)
2902 {
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904
2905 /* deactivate cxsr */
2906 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2907 }
2908
2909 /*
2910 * Latency for FIFO fetches is dependent on several factors:
2911 * - memory configuration (speed, channels)
2912 * - chipset
2913 * - current MCH state
2914 * It can be fairly high in some situations, so here we assume a fairly
2915 * pessimal value. It's a tradeoff between extra memory fetches (if we
2916 * set this value too high, the FIFO will fetch frequently to stay full)
2917 * and power consumption (set it too low to save power and we might see
2918 * FIFO underruns and display "flicker").
2919 *
2920 * A value of 5us seems to be a good balance; safe for very low end
2921 * platforms but not overly aggressive on lower latency configs.
2922 */
2923 static const int latency_ns = 5000;
2924
2925 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2926 {
2927 struct drm_i915_private *dev_priv = dev->dev_private;
2928 uint32_t dsparb = I915_READ(DSPARB);
2929 int size;
2930
2931 size = dsparb & 0x7f;
2932 if (plane)
2933 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2934
2935 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2936 plane ? "B" : "A", size);
2937
2938 return size;
2939 }
2940
2941 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2942 {
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 uint32_t dsparb = I915_READ(DSPARB);
2945 int size;
2946
2947 size = dsparb & 0x1ff;
2948 if (plane)
2949 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2950 size >>= 1; /* Convert to cachelines */
2951
2952 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2953 plane ? "B" : "A", size);
2954
2955 return size;
2956 }
2957
2958 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2959 {
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 uint32_t dsparb = I915_READ(DSPARB);
2962 int size;
2963
2964 size = dsparb & 0x7f;
2965 size >>= 2; /* Convert to cachelines */
2966
2967 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2968 plane ? "B" : "A",
2969 size);
2970
2971 return size;
2972 }
2973
2974 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2975 {
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 uint32_t dsparb = I915_READ(DSPARB);
2978 int size;
2979
2980 size = dsparb & 0x7f;
2981 size >>= 1; /* Convert to cachelines */
2982
2983 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2984 plane ? "B" : "A", size);
2985
2986 return size;
2987 }
2988
2989 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2990 int planeb_clock, int sr_hdisplay, int unused,
2991 int pixel_size)
2992 {
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 const struct cxsr_latency *latency;
2995 u32 reg;
2996 unsigned long wm;
2997 int sr_clock;
2998
2999 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3000 dev_priv->fsb_freq, dev_priv->mem_freq);
3001 if (!latency) {
3002 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3003 pineview_disable_cxsr(dev);
3004 return;
3005 }
3006
3007 if (!planea_clock || !planeb_clock) {
3008 sr_clock = planea_clock ? planea_clock : planeb_clock;
3009
3010 /* Display SR */
3011 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3012 pixel_size, latency->display_sr);
3013 reg = I915_READ(DSPFW1);
3014 reg &= ~DSPFW_SR_MASK;
3015 reg |= wm << DSPFW_SR_SHIFT;
3016 I915_WRITE(DSPFW1, reg);
3017 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3018
3019 /* cursor SR */
3020 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3021 pixel_size, latency->cursor_sr);
3022 reg = I915_READ(DSPFW3);
3023 reg &= ~DSPFW_CURSOR_SR_MASK;
3024 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3025 I915_WRITE(DSPFW3, reg);
3026
3027 /* Display HPLL off SR */
3028 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3029 pixel_size, latency->display_hpll_disable);
3030 reg = I915_READ(DSPFW3);
3031 reg &= ~DSPFW_HPLL_SR_MASK;
3032 reg |= wm & DSPFW_HPLL_SR_MASK;
3033 I915_WRITE(DSPFW3, reg);
3034
3035 /* cursor HPLL off SR */
3036 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3037 pixel_size, latency->cursor_hpll_disable);
3038 reg = I915_READ(DSPFW3);
3039 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3040 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3041 I915_WRITE(DSPFW3, reg);
3042 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3043
3044 /* activate cxsr */
3045 I915_WRITE(DSPFW3,
3046 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3047 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3048 } else {
3049 pineview_disable_cxsr(dev);
3050 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3051 }
3052 }
3053
3054 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3055 int planeb_clock, int sr_hdisplay, int sr_htotal,
3056 int pixel_size)
3057 {
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 int total_size, cacheline_size;
3060 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3061 struct intel_watermark_params planea_params, planeb_params;
3062 unsigned long line_time_us;
3063 int sr_clock, sr_entries = 0, entries_required;
3064
3065 /* Create copies of the base settings for each pipe */
3066 planea_params = planeb_params = g4x_wm_info;
3067
3068 /* Grab a couple of global values before we overwrite them */
3069 total_size = planea_params.fifo_size;
3070 cacheline_size = planea_params.cacheline_size;
3071
3072 /*
3073 * Note: we need to make sure we don't overflow for various clock &
3074 * latency values.
3075 * clocks go from a few thousand to several hundred thousand.
3076 * latency is usually a few thousand
3077 */
3078 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3079 1000;
3080 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3081 planea_wm = entries_required + planea_params.guard_size;
3082
3083 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3084 1000;
3085 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3086 planeb_wm = entries_required + planeb_params.guard_size;
3087
3088 cursora_wm = cursorb_wm = 16;
3089 cursor_sr = 32;
3090
3091 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3092
3093 /* Calc sr entries for one plane configs */
3094 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3095 /* self-refresh has much higher latency */
3096 static const int sr_latency_ns = 12000;
3097
3098 sr_clock = planea_clock ? planea_clock : planeb_clock;
3099 line_time_us = ((sr_htotal * 1000) / sr_clock);
3100
3101 /* Use ns/us then divide to preserve precision */
3102 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3103 pixel_size * sr_hdisplay;
3104 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3105
3106 entries_required = (((sr_latency_ns / line_time_us) +
3107 1000) / 1000) * pixel_size * 64;
3108 entries_required = DIV_ROUND_UP(entries_required,
3109 g4x_cursor_wm_info.cacheline_size);
3110 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3111
3112 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3113 cursor_sr = g4x_cursor_wm_info.max_wm;
3114 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3115 "cursor %d\n", sr_entries, cursor_sr);
3116
3117 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3118 } else {
3119 /* Turn off self refresh if both pipes are enabled */
3120 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3121 & ~FW_BLC_SELF_EN);
3122 }
3123
3124 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3125 planea_wm, planeb_wm, sr_entries);
3126
3127 planea_wm &= 0x3f;
3128 planeb_wm &= 0x3f;
3129
3130 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3131 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3132 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3133 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3134 (cursora_wm << DSPFW_CURSORA_SHIFT));
3135 /* HPLL off in SR has some issues on G4x... disable it */
3136 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3137 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3138 }
3139
3140 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3141 int planeb_clock, int sr_hdisplay, int sr_htotal,
3142 int pixel_size)
3143 {
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 unsigned long line_time_us;
3146 int sr_clock, sr_entries, srwm = 1;
3147 int cursor_sr = 16;
3148
3149 /* Calc sr entries for one plane configs */
3150 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3151 /* self-refresh has much higher latency */
3152 static const int sr_latency_ns = 12000;
3153
3154 sr_clock = planea_clock ? planea_clock : planeb_clock;
3155 line_time_us = ((sr_htotal * 1000) / sr_clock);
3156
3157 /* Use ns/us then divide to preserve precision */
3158 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3159 pixel_size * sr_hdisplay;
3160 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3161 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3162 srwm = I965_FIFO_SIZE - sr_entries;
3163 if (srwm < 0)
3164 srwm = 1;
3165 srwm &= 0x1ff;
3166
3167 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3168 pixel_size * 64;
3169 sr_entries = DIV_ROUND_UP(sr_entries,
3170 i965_cursor_wm_info.cacheline_size);
3171 cursor_sr = i965_cursor_wm_info.fifo_size -
3172 (sr_entries + i965_cursor_wm_info.guard_size);
3173
3174 if (cursor_sr > i965_cursor_wm_info.max_wm)
3175 cursor_sr = i965_cursor_wm_info.max_wm;
3176
3177 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3178 "cursor %d\n", srwm, cursor_sr);
3179
3180 if (IS_I965GM(dev))
3181 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3182 } else {
3183 /* Turn off self refresh if both pipes are enabled */
3184 if (IS_I965GM(dev))
3185 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3186 & ~FW_BLC_SELF_EN);
3187 }
3188
3189 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3190 srwm);
3191
3192 /* 965 has limitations... */
3193 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3194 (8 << 0));
3195 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3196 /* update cursor SR watermark */
3197 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3198 }
3199
3200 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3201 int planeb_clock, int sr_hdisplay, int sr_htotal,
3202 int pixel_size)
3203 {
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 uint32_t fwater_lo;
3206 uint32_t fwater_hi;
3207 int total_size, cacheline_size, cwm, srwm = 1;
3208 int planea_wm, planeb_wm;
3209 struct intel_watermark_params planea_params, planeb_params;
3210 unsigned long line_time_us;
3211 int sr_clock, sr_entries = 0;
3212
3213 /* Create copies of the base settings for each pipe */
3214 if (IS_I965GM(dev) || IS_I945GM(dev))
3215 planea_params = planeb_params = i945_wm_info;
3216 else if (IS_I9XX(dev))
3217 planea_params = planeb_params = i915_wm_info;
3218 else
3219 planea_params = planeb_params = i855_wm_info;
3220
3221 /* Grab a couple of global values before we overwrite them */
3222 total_size = planea_params.fifo_size;
3223 cacheline_size = planea_params.cacheline_size;
3224
3225 /* Update per-plane FIFO sizes */
3226 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3227 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3228
3229 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3230 pixel_size, latency_ns);
3231 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3232 pixel_size, latency_ns);
3233 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3234
3235 /*
3236 * Overlay gets an aggressive default since video jitter is bad.
3237 */
3238 cwm = 2;
3239
3240 /* Calc sr entries for one plane configs */
3241 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3242 (!planea_clock || !planeb_clock)) {
3243 /* self-refresh has much higher latency */
3244 static const int sr_latency_ns = 6000;
3245
3246 sr_clock = planea_clock ? planea_clock : planeb_clock;
3247 line_time_us = ((sr_htotal * 1000) / sr_clock);
3248
3249 /* Use ns/us then divide to preserve precision */
3250 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3251 pixel_size * sr_hdisplay;
3252 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3253 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3254 srwm = total_size - sr_entries;
3255 if (srwm < 0)
3256 srwm = 1;
3257
3258 if (IS_I945G(dev) || IS_I945GM(dev))
3259 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3260 else if (IS_I915GM(dev)) {
3261 /* 915M has a smaller SRWM field */
3262 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3263 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3264 }
3265 } else {
3266 /* Turn off self refresh if both pipes are enabled */
3267 if (IS_I945G(dev) || IS_I945GM(dev)) {
3268 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3269 & ~FW_BLC_SELF_EN);
3270 } else if (IS_I915GM(dev)) {
3271 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3272 }
3273 }
3274
3275 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3276 planea_wm, planeb_wm, cwm, srwm);
3277
3278 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3279 fwater_hi = (cwm & 0x1f);
3280
3281 /* Set request length to 8 cachelines per fetch */
3282 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3283 fwater_hi = fwater_hi | (1 << 8);
3284
3285 I915_WRITE(FW_BLC, fwater_lo);
3286 I915_WRITE(FW_BLC2, fwater_hi);
3287 }
3288
3289 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3290 int unused2, int unused3, int pixel_size)
3291 {
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3294 int planea_wm;
3295
3296 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3297
3298 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3299 pixel_size, latency_ns);
3300 fwater_lo |= (3<<8) | planea_wm;
3301
3302 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3303
3304 I915_WRITE(FW_BLC, fwater_lo);
3305 }
3306
3307 #define ILK_LP0_PLANE_LATENCY 700
3308 #define ILK_LP0_CURSOR_LATENCY 1300
3309
3310 static bool ironlake_compute_wm0(struct drm_device *dev,
3311 int pipe,
3312 int *plane_wm,
3313 int *cursor_wm)
3314 {
3315 struct drm_crtc *crtc;
3316 int htotal, hdisplay, clock, pixel_size = 0;
3317 int line_time_us, line_count, entries;
3318
3319 crtc = intel_get_crtc_for_pipe(dev, pipe);
3320 if (crtc->fb == NULL || !crtc->enabled)
3321 return false;
3322
3323 htotal = crtc->mode.htotal;
3324 hdisplay = crtc->mode.hdisplay;
3325 clock = crtc->mode.clock;
3326 pixel_size = crtc->fb->bits_per_pixel / 8;
3327
3328 /* Use the small buffer method to calculate plane watermark */
3329 entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3330 entries = DIV_ROUND_UP(entries,
3331 ironlake_display_wm_info.cacheline_size);
3332 *plane_wm = entries + ironlake_display_wm_info.guard_size;
3333 if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3334 *plane_wm = ironlake_display_wm_info.max_wm;
3335
3336 /* Use the large buffer method to calculate cursor watermark */
3337 line_time_us = ((htotal * 1000) / clock);
3338 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3339 entries = line_count * 64 * pixel_size;
3340 entries = DIV_ROUND_UP(entries,
3341 ironlake_cursor_wm_info.cacheline_size);
3342 *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3343 if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3344 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3345
3346 return true;
3347 }
3348
3349 static void ironlake_update_wm(struct drm_device *dev,
3350 int planea_clock, int planeb_clock,
3351 int sr_hdisplay, int sr_htotal,
3352 int pixel_size)
3353 {
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 int plane_wm, cursor_wm, enabled;
3356 int tmp;
3357
3358 enabled = 0;
3359 if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3360 I915_WRITE(WM0_PIPEA_ILK,
3361 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3362 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3363 " plane %d, " "cursor: %d\n",
3364 plane_wm, cursor_wm);
3365 enabled++;
3366 }
3367
3368 if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3369 I915_WRITE(WM0_PIPEB_ILK,
3370 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3371 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3372 " plane %d, cursor: %d\n",
3373 plane_wm, cursor_wm);
3374 enabled++;
3375 }
3376
3377 /*
3378 * Calculate and update the self-refresh watermark only when one
3379 * display plane is used.
3380 */
3381 tmp = 0;
3382 if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3383 unsigned long line_time_us;
3384 int small, large, plane_fbc;
3385 int sr_clock, entries;
3386 int line_count, line_size;
3387 /* Read the self-refresh latency. The unit is 0.5us */
3388 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3389
3390 sr_clock = planea_clock ? planea_clock : planeb_clock;
3391 line_time_us = (sr_htotal * 1000) / sr_clock;
3392
3393 /* Use ns/us then divide to preserve precision */
3394 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3395 / 1000;
3396 line_size = sr_hdisplay * pixel_size;
3397
3398 /* Use the minimum of the small and large buffer method for primary */
3399 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3400 large = line_count * line_size;
3401
3402 entries = DIV_ROUND_UP(min(small, large),
3403 ironlake_display_srwm_info.cacheline_size);
3404
3405 plane_fbc = entries * 64;
3406 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3407
3408 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3409 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3410 plane_wm = ironlake_display_srwm_info.max_wm;
3411
3412 /* calculate the self-refresh watermark for display cursor */
3413 entries = line_count * pixel_size * 64;
3414 entries = DIV_ROUND_UP(entries,
3415 ironlake_cursor_srwm_info.cacheline_size);
3416
3417 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3418 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3419 cursor_wm = ironlake_cursor_srwm_info.max_wm;
3420
3421 /* configure watermark and enable self-refresh */
3422 tmp = (WM1_LP_SR_EN |
3423 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3424 (plane_fbc << WM1_LP_FBC_SHIFT) |
3425 (plane_wm << WM1_LP_SR_SHIFT) |
3426 cursor_wm);
3427 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3428 " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3429 }
3430 I915_WRITE(WM1_LP_ILK, tmp);
3431 /* XXX setup WM2 and WM3 */
3432 }
3433
3434 /**
3435 * intel_update_watermarks - update FIFO watermark values based on current modes
3436 *
3437 * Calculate watermark values for the various WM regs based on current mode
3438 * and plane configuration.
3439 *
3440 * There are several cases to deal with here:
3441 * - normal (i.e. non-self-refresh)
3442 * - self-refresh (SR) mode
3443 * - lines are large relative to FIFO size (buffer can hold up to 2)
3444 * - lines are small relative to FIFO size (buffer can hold more than 2
3445 * lines), so need to account for TLB latency
3446 *
3447 * The normal calculation is:
3448 * watermark = dotclock * bytes per pixel * latency
3449 * where latency is platform & configuration dependent (we assume pessimal
3450 * values here).
3451 *
3452 * The SR calculation is:
3453 * watermark = (trunc(latency/line time)+1) * surface width *
3454 * bytes per pixel
3455 * where
3456 * line time = htotal / dotclock
3457 * surface width = hdisplay for normal plane and 64 for cursor
3458 * and latency is assumed to be high, as above.
3459 *
3460 * The final value programmed to the register should always be rounded up,
3461 * and include an extra 2 entries to account for clock crossings.
3462 *
3463 * We don't use the sprite, so we can ignore that. And on Crestline we have
3464 * to set the non-SR watermarks to 8.
3465 */
3466 static void intel_update_watermarks(struct drm_device *dev)
3467 {
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469 struct drm_crtc *crtc;
3470 int sr_hdisplay = 0;
3471 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3472 int enabled = 0, pixel_size = 0;
3473 int sr_htotal = 0;
3474
3475 if (!dev_priv->display.update_wm)
3476 return;
3477
3478 /* Get the clock config from both planes */
3479 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3481 if (intel_crtc->active) {
3482 enabled++;
3483 if (intel_crtc->plane == 0) {
3484 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3485 intel_crtc->pipe, crtc->mode.clock);
3486 planea_clock = crtc->mode.clock;
3487 } else {
3488 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3489 intel_crtc->pipe, crtc->mode.clock);
3490 planeb_clock = crtc->mode.clock;
3491 }
3492 sr_hdisplay = crtc->mode.hdisplay;
3493 sr_clock = crtc->mode.clock;
3494 sr_htotal = crtc->mode.htotal;
3495 if (crtc->fb)
3496 pixel_size = crtc->fb->bits_per_pixel / 8;
3497 else
3498 pixel_size = 4; /* by default */
3499 }
3500 }
3501
3502 if (enabled <= 0)
3503 return;
3504
3505 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3506 sr_hdisplay, sr_htotal, pixel_size);
3507 }
3508
3509 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3510 struct drm_display_mode *mode,
3511 struct drm_display_mode *adjusted_mode,
3512 int x, int y,
3513 struct drm_framebuffer *old_fb)
3514 {
3515 struct drm_device *dev = crtc->dev;
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3518 int pipe = intel_crtc->pipe;
3519 int plane = intel_crtc->plane;
3520 u32 fp_reg, dpll_reg;
3521 int refclk, num_connectors = 0;
3522 intel_clock_t clock, reduced_clock;
3523 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3524 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3525 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3526 struct intel_encoder *has_edp_encoder = NULL;
3527 struct drm_mode_config *mode_config = &dev->mode_config;
3528 struct intel_encoder *encoder;
3529 const intel_limit_t *limit;
3530 int ret;
3531 struct fdi_m_n m_n = {0};
3532 u32 reg, temp;
3533 int target_clock;
3534
3535 drm_vblank_pre_modeset(dev, pipe);
3536
3537 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3538 if (encoder->base.crtc != crtc)
3539 continue;
3540
3541 switch (encoder->type) {
3542 case INTEL_OUTPUT_LVDS:
3543 is_lvds = true;
3544 break;
3545 case INTEL_OUTPUT_SDVO:
3546 case INTEL_OUTPUT_HDMI:
3547 is_sdvo = true;
3548 if (encoder->needs_tv_clock)
3549 is_tv = true;
3550 break;
3551 case INTEL_OUTPUT_DVO:
3552 is_dvo = true;
3553 break;
3554 case INTEL_OUTPUT_TVOUT:
3555 is_tv = true;
3556 break;
3557 case INTEL_OUTPUT_ANALOG:
3558 is_crt = true;
3559 break;
3560 case INTEL_OUTPUT_DISPLAYPORT:
3561 is_dp = true;
3562 break;
3563 case INTEL_OUTPUT_EDP:
3564 has_edp_encoder = encoder;
3565 break;
3566 }
3567
3568 num_connectors++;
3569 }
3570
3571 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3572 refclk = dev_priv->lvds_ssc_freq * 1000;
3573 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3574 refclk / 1000);
3575 } else if (IS_I9XX(dev)) {
3576 refclk = 96000;
3577 if (HAS_PCH_SPLIT(dev))
3578 refclk = 120000; /* 120Mhz refclk */
3579 } else {
3580 refclk = 48000;
3581 }
3582
3583 /*
3584 * Returns a set of divisors for the desired target clock with the given
3585 * refclk, or FALSE. The returned values represent the clock equation:
3586 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3587 */
3588 limit = intel_limit(crtc);
3589 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3590 if (!ok) {
3591 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3592 drm_vblank_post_modeset(dev, pipe);
3593 return -EINVAL;
3594 }
3595
3596 /* Ensure that the cursor is valid for the new mode before changing... */
3597 intel_crtc_update_cursor(crtc, true);
3598
3599 if (is_lvds && dev_priv->lvds_downclock_avail) {
3600 has_reduced_clock = limit->find_pll(limit, crtc,
3601 dev_priv->lvds_downclock,
3602 refclk,
3603 &reduced_clock);
3604 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3605 /*
3606 * If the different P is found, it means that we can't
3607 * switch the display clock by using the FP0/FP1.
3608 * In such case we will disable the LVDS downclock
3609 * feature.
3610 */
3611 DRM_DEBUG_KMS("Different P is found for "
3612 "LVDS clock/downclock\n");
3613 has_reduced_clock = 0;
3614 }
3615 }
3616 /* SDVO TV has fixed PLL values depend on its clock range,
3617 this mirrors vbios setting. */
3618 if (is_sdvo && is_tv) {
3619 if (adjusted_mode->clock >= 100000
3620 && adjusted_mode->clock < 140500) {
3621 clock.p1 = 2;
3622 clock.p2 = 10;
3623 clock.n = 3;
3624 clock.m1 = 16;
3625 clock.m2 = 8;
3626 } else if (adjusted_mode->clock >= 140500
3627 && adjusted_mode->clock <= 200000) {
3628 clock.p1 = 1;
3629 clock.p2 = 10;
3630 clock.n = 6;
3631 clock.m1 = 12;
3632 clock.m2 = 8;
3633 }
3634 }
3635
3636 /* FDI link */
3637 if (HAS_PCH_SPLIT(dev)) {
3638 int lane = 0, link_bw, bpp;
3639 /* eDP doesn't require FDI link, so just set DP M/N
3640 according to current link config */
3641 if (has_edp_encoder) {
3642 target_clock = mode->clock;
3643 intel_edp_link_config(has_edp_encoder,
3644 &lane, &link_bw);
3645 } else {
3646 /* DP over FDI requires target mode clock
3647 instead of link clock */
3648 if (is_dp)
3649 target_clock = mode->clock;
3650 else
3651 target_clock = adjusted_mode->clock;
3652
3653 /* FDI is a binary signal running at ~2.7GHz, encoding
3654 * each output octet as 10 bits. The actual frequency
3655 * is stored as a divider into a 100MHz clock, and the
3656 * mode pixel clock is stored in units of 1KHz.
3657 * Hence the bw of each lane in terms of the mode signal
3658 * is:
3659 */
3660 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3661 }
3662
3663 /* determine panel color depth */
3664 temp = I915_READ(PIPECONF(pipe));
3665 temp &= ~PIPE_BPC_MASK;
3666 if (is_lvds) {
3667 /* the BPC will be 6 if it is 18-bit LVDS panel */
3668 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3669 temp |= PIPE_8BPC;
3670 else
3671 temp |= PIPE_6BPC;
3672 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3673 switch (dev_priv->edp_bpp/3) {
3674 case 8:
3675 temp |= PIPE_8BPC;
3676 break;
3677 case 10:
3678 temp |= PIPE_10BPC;
3679 break;
3680 case 6:
3681 temp |= PIPE_6BPC;
3682 break;
3683 case 12:
3684 temp |= PIPE_12BPC;
3685 break;
3686 }
3687 } else
3688 temp |= PIPE_8BPC;
3689 I915_WRITE(PIPECONF(pipe), temp);
3690
3691 switch (temp & PIPE_BPC_MASK) {
3692 case PIPE_8BPC:
3693 bpp = 24;
3694 break;
3695 case PIPE_10BPC:
3696 bpp = 30;
3697 break;
3698 case PIPE_6BPC:
3699 bpp = 18;
3700 break;
3701 case PIPE_12BPC:
3702 bpp = 36;
3703 break;
3704 default:
3705 DRM_ERROR("unknown pipe bpc value\n");
3706 bpp = 24;
3707 }
3708
3709 if (!lane) {
3710 /*
3711 * Account for spread spectrum to avoid
3712 * oversubscribing the link. Max center spread
3713 * is 2.5%; use 5% for safety's sake.
3714 */
3715 u32 bps = target_clock * bpp * 21 / 20;
3716 lane = bps / (link_bw * 8) + 1;
3717 }
3718
3719 intel_crtc->fdi_lanes = lane;
3720
3721 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3722 }
3723
3724 /* Ironlake: try to setup display ref clock before DPLL
3725 * enabling. This is only under driver's control after
3726 * PCH B stepping, previous chipset stepping should be
3727 * ignoring this setting.
3728 */
3729 if (HAS_PCH_SPLIT(dev)) {
3730 temp = I915_READ(PCH_DREF_CONTROL);
3731 /* Always enable nonspread source */
3732 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3733 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3734 temp &= ~DREF_SSC_SOURCE_MASK;
3735 temp |= DREF_SSC_SOURCE_ENABLE;
3736 I915_WRITE(PCH_DREF_CONTROL, temp);
3737
3738 POSTING_READ(PCH_DREF_CONTROL);
3739 udelay(200);
3740
3741 if (has_edp_encoder) {
3742 if (dev_priv->lvds_use_ssc) {
3743 temp |= DREF_SSC1_ENABLE;
3744 I915_WRITE(PCH_DREF_CONTROL, temp);
3745
3746 POSTING_READ(PCH_DREF_CONTROL);
3747 udelay(200);
3748
3749 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3750 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3751 } else {
3752 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3753 }
3754 I915_WRITE(PCH_DREF_CONTROL, temp);
3755 }
3756 }
3757
3758 if (IS_PINEVIEW(dev)) {
3759 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3760 if (has_reduced_clock)
3761 fp2 = (1 << reduced_clock.n) << 16 |
3762 reduced_clock.m1 << 8 | reduced_clock.m2;
3763 } else {
3764 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3765 if (has_reduced_clock)
3766 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3767 reduced_clock.m2;
3768 }
3769
3770 dpll = 0;
3771 if (!HAS_PCH_SPLIT(dev))
3772 dpll = DPLL_VGA_MODE_DIS;
3773
3774 if (IS_I9XX(dev)) {
3775 if (is_lvds)
3776 dpll |= DPLLB_MODE_LVDS;
3777 else
3778 dpll |= DPLLB_MODE_DAC_SERIAL;
3779 if (is_sdvo) {
3780 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3781 if (pixel_multiplier > 1) {
3782 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3783 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3784 else if (HAS_PCH_SPLIT(dev))
3785 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3786 }
3787 dpll |= DPLL_DVO_HIGH_SPEED;
3788 }
3789 if (is_dp)
3790 dpll |= DPLL_DVO_HIGH_SPEED;
3791
3792 /* compute bitmask from p1 value */
3793 if (IS_PINEVIEW(dev))
3794 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3795 else {
3796 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3797 /* also FPA1 */
3798 if (HAS_PCH_SPLIT(dev))
3799 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3800 if (IS_G4X(dev) && has_reduced_clock)
3801 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3802 }
3803 switch (clock.p2) {
3804 case 5:
3805 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3806 break;
3807 case 7:
3808 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3809 break;
3810 case 10:
3811 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3812 break;
3813 case 14:
3814 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3815 break;
3816 }
3817 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3818 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3819 } else {
3820 if (is_lvds) {
3821 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3822 } else {
3823 if (clock.p1 == 2)
3824 dpll |= PLL_P1_DIVIDE_BY_TWO;
3825 else
3826 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3827 if (clock.p2 == 4)
3828 dpll |= PLL_P2_DIVIDE_BY_4;
3829 }
3830 }
3831
3832 if (is_sdvo && is_tv)
3833 dpll |= PLL_REF_INPUT_TVCLKINBC;
3834 else if (is_tv)
3835 /* XXX: just matching BIOS for now */
3836 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3837 dpll |= 3;
3838 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3839 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3840 else
3841 dpll |= PLL_REF_INPUT_DREFCLK;
3842
3843 /* setup pipeconf */
3844 pipeconf = I915_READ(PIPECONF(pipe));
3845
3846 /* Set up the display plane register */
3847 dspcntr = DISPPLANE_GAMMA_ENABLE;
3848
3849 /* Ironlake's plane is forced to pipe, bit 24 is to
3850 enable color space conversion */
3851 if (!HAS_PCH_SPLIT(dev)) {
3852 if (pipe == 0)
3853 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3854 else
3855 dspcntr |= DISPPLANE_SEL_PIPE_B;
3856 }
3857
3858 if (pipe == 0 && !IS_I965G(dev)) {
3859 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3860 * core speed.
3861 *
3862 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3863 * pipe == 0 check?
3864 */
3865 if (mode->clock >
3866 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3867 pipeconf |= PIPECONF_DOUBLE_WIDE;
3868 else
3869 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3870 }
3871
3872 dspcntr |= DISPLAY_PLANE_ENABLE;
3873 pipeconf |= PIPECONF_ENABLE;
3874 dpll |= DPLL_VCO_ENABLE;
3875
3876 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3877 drm_mode_debug_printmodeline(mode);
3878
3879 /* assign to Ironlake registers */
3880 if (HAS_PCH_SPLIT(dev)) {
3881 fp_reg = PCH_FP0(pipe);
3882 dpll_reg = PCH_DPLL(pipe);
3883 } else {
3884 fp_reg = FP0(pipe);
3885 dpll_reg = DPLL(pipe);
3886 }
3887
3888 if (!has_edp_encoder) {
3889 I915_WRITE(fp_reg, fp);
3890 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3891
3892 POSTING_READ(dpll_reg);
3893 udelay(150);
3894 }
3895
3896 /* enable transcoder DPLL */
3897 if (HAS_PCH_CPT(dev)) {
3898 temp = I915_READ(PCH_DPLL_SEL);
3899 if (pipe == 0)
3900 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3901 else
3902 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3903 I915_WRITE(PCH_DPLL_SEL, temp);
3904
3905 POSTING_READ(PCH_DPLL_SEL);
3906 udelay(150);
3907 }
3908
3909 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3910 * This is an exception to the general rule that mode_set doesn't turn
3911 * things on.
3912 */
3913 if (is_lvds) {
3914 reg = LVDS;
3915 if (HAS_PCH_SPLIT(dev))
3916 reg = PCH_LVDS;
3917
3918 temp = I915_READ(reg);
3919 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3920 if (pipe == 1) {
3921 if (HAS_PCH_CPT(dev))
3922 temp |= PORT_TRANS_B_SEL_CPT;
3923 else
3924 temp |= LVDS_PIPEB_SELECT;
3925 } else {
3926 if (HAS_PCH_CPT(dev))
3927 temp &= ~PORT_TRANS_SEL_MASK;
3928 else
3929 temp &= ~LVDS_PIPEB_SELECT;
3930 }
3931 /* set the corresponsding LVDS_BORDER bit */
3932 temp |= dev_priv->lvds_border_bits;
3933 /* Set the B0-B3 data pairs corresponding to whether we're going to
3934 * set the DPLLs for dual-channel mode or not.
3935 */
3936 if (clock.p2 == 7)
3937 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3938 else
3939 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3940
3941 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3942 * appropriately here, but we need to look more thoroughly into how
3943 * panels behave in the two modes.
3944 */
3945 /* set the dithering flag on non-PCH LVDS as needed */
3946 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3947 if (dev_priv->lvds_dither)
3948 temp |= LVDS_ENABLE_DITHER;
3949 else
3950 temp &= ~LVDS_ENABLE_DITHER;
3951 }
3952 I915_WRITE(reg, temp);
3953 }
3954
3955 /* set the dithering flag and clear for anything other than a panel. */
3956 if (HAS_PCH_SPLIT(dev)) {
3957 pipeconf &= ~PIPECONF_DITHER_EN;
3958 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
3959 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
3960 pipeconf |= PIPECONF_DITHER_EN;
3961 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
3962 }
3963 }
3964
3965 if (is_dp)
3966 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3967 else if (HAS_PCH_SPLIT(dev)) {
3968 /* For non-DP output, clear any trans DP clock recovery setting.*/
3969 if (pipe == 0) {
3970 I915_WRITE(TRANSA_DATA_M1, 0);
3971 I915_WRITE(TRANSA_DATA_N1, 0);
3972 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3973 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3974 } else {
3975 I915_WRITE(TRANSB_DATA_M1, 0);
3976 I915_WRITE(TRANSB_DATA_N1, 0);
3977 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3978 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3979 }
3980 }
3981
3982 if (!has_edp_encoder) {
3983 I915_WRITE(fp_reg, fp);
3984 I915_WRITE(dpll_reg, dpll);
3985
3986 /* Wait for the clocks to stabilize. */
3987 POSTING_READ(dpll_reg);
3988 udelay(150);
3989
3990 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3991 temp = 0;
3992 if (is_sdvo) {
3993 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3994 if (temp > 1)
3995 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3996 else
3997 temp = 0;
3998 }
3999 I915_WRITE(DPLL_MD(pipe), temp);
4000 } else {
4001 /* write it again -- the BIOS does, after all */
4002 I915_WRITE(dpll_reg, dpll);
4003 }
4004
4005 /* Wait for the clocks to stabilize. */
4006 POSTING_READ(dpll_reg);
4007 udelay(150);
4008 }
4009
4010 intel_crtc->lowfreq_avail = false;
4011 if (is_lvds && has_reduced_clock && i915_powersave) {
4012 I915_WRITE(fp_reg + 4, fp2);
4013 intel_crtc->lowfreq_avail = true;
4014 if (HAS_PIPE_CXSR(dev)) {
4015 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4016 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4017 }
4018 } else {
4019 I915_WRITE(fp_reg + 4, fp);
4020 if (HAS_PIPE_CXSR(dev)) {
4021 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4022 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4023 }
4024 }
4025
4026 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4027 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4028 /* the chip adds 2 halflines automatically */
4029 adjusted_mode->crtc_vdisplay -= 1;
4030 adjusted_mode->crtc_vtotal -= 1;
4031 adjusted_mode->crtc_vblank_start -= 1;
4032 adjusted_mode->crtc_vblank_end -= 1;
4033 adjusted_mode->crtc_vsync_end -= 1;
4034 adjusted_mode->crtc_vsync_start -= 1;
4035 } else
4036 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4037
4038 I915_WRITE(HTOTAL(pipe),
4039 (adjusted_mode->crtc_hdisplay - 1) |
4040 ((adjusted_mode->crtc_htotal - 1) << 16));
4041 I915_WRITE(HBLANK(pipe),
4042 (adjusted_mode->crtc_hblank_start - 1) |
4043 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4044 I915_WRITE(HSYNC(pipe),
4045 (adjusted_mode->crtc_hsync_start - 1) |
4046 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4047
4048 I915_WRITE(VTOTAL(pipe),
4049 (adjusted_mode->crtc_vdisplay - 1) |
4050 ((adjusted_mode->crtc_vtotal - 1) << 16));
4051 I915_WRITE(VBLANK(pipe),
4052 (adjusted_mode->crtc_vblank_start - 1) |
4053 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4054 I915_WRITE(VSYNC(pipe),
4055 (adjusted_mode->crtc_vsync_start - 1) |
4056 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4057
4058 /* pipesrc and dspsize control the size that is scaled from,
4059 * which should always be the user's requested size.
4060 */
4061 if (!HAS_PCH_SPLIT(dev)) {
4062 I915_WRITE(DSPSIZE(plane),
4063 ((mode->vdisplay - 1) << 16) |
4064 (mode->hdisplay - 1));
4065 I915_WRITE(DSPPOS(plane), 0);
4066 }
4067 I915_WRITE(PIPESRC(pipe),
4068 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4069
4070 if (HAS_PCH_SPLIT(dev)) {
4071 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4072 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4073 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4074 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4075
4076 if (has_edp_encoder) {
4077 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4078 } else {
4079 /* enable FDI RX PLL too */
4080 reg = FDI_RX_CTL(pipe);
4081 temp = I915_READ(reg);
4082 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4083
4084 POSTING_READ(reg);
4085 udelay(200);
4086
4087 /* enable FDI TX PLL too */
4088 reg = FDI_TX_CTL(pipe);
4089 temp = I915_READ(reg);
4090 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4091
4092 /* enable FDI RX PCDCLK */
4093 reg = FDI_RX_CTL(pipe);
4094 temp = I915_READ(reg);
4095 I915_WRITE(reg, temp | FDI_PCDCLK);
4096
4097 POSTING_READ(reg);
4098 udelay(200);
4099 }
4100 }
4101
4102 I915_WRITE(PIPECONF(pipe), pipeconf);
4103 POSTING_READ(PIPECONF(pipe));
4104
4105 intel_wait_for_vblank(dev, pipe);
4106
4107 if (IS_IRONLAKE(dev)) {
4108 /* enable address swizzle for tiling buffer */
4109 temp = I915_READ(DISP_ARB_CTL);
4110 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4111 }
4112
4113 I915_WRITE(DSPCNTR(plane), dspcntr);
4114
4115 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4116
4117 intel_update_watermarks(dev);
4118
4119 drm_vblank_post_modeset(dev, pipe);
4120
4121 return ret;
4122 }
4123
4124 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4125 void intel_crtc_load_lut(struct drm_crtc *crtc)
4126 {
4127 struct drm_device *dev = crtc->dev;
4128 struct drm_i915_private *dev_priv = dev->dev_private;
4129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4130 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4131 int i;
4132
4133 /* The clocks have to be on to load the palette. */
4134 if (!crtc->enabled)
4135 return;
4136
4137 /* use legacy palette for Ironlake */
4138 if (HAS_PCH_SPLIT(dev))
4139 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4140 LGC_PALETTE_B;
4141
4142 for (i = 0; i < 256; i++) {
4143 I915_WRITE(palreg + 4 * i,
4144 (intel_crtc->lut_r[i] << 16) |
4145 (intel_crtc->lut_g[i] << 8) |
4146 intel_crtc->lut_b[i]);
4147 }
4148 }
4149
4150 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4151 {
4152 struct drm_device *dev = crtc->dev;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4155 bool visible = base != 0;
4156 u32 cntl;
4157
4158 if (intel_crtc->cursor_visible == visible)
4159 return;
4160
4161 cntl = I915_READ(CURACNTR);
4162 if (visible) {
4163 /* On these chipsets we can only modify the base whilst
4164 * the cursor is disabled.
4165 */
4166 I915_WRITE(CURABASE, base);
4167
4168 cntl &= ~(CURSOR_FORMAT_MASK);
4169 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4170 cntl |= CURSOR_ENABLE |
4171 CURSOR_GAMMA_ENABLE |
4172 CURSOR_FORMAT_ARGB;
4173 } else
4174 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4175 I915_WRITE(CURACNTR, cntl);
4176
4177 intel_crtc->cursor_visible = visible;
4178 }
4179
4180 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4181 {
4182 struct drm_device *dev = crtc->dev;
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4185 int pipe = intel_crtc->pipe;
4186 bool visible = base != 0;
4187
4188 if (intel_crtc->cursor_visible != visible) {
4189 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4190 if (base) {
4191 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4192 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4193 cntl |= pipe << 28; /* Connect to correct pipe */
4194 } else {
4195 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4196 cntl |= CURSOR_MODE_DISABLE;
4197 }
4198 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4199
4200 intel_crtc->cursor_visible = visible;
4201 }
4202 /* and commit changes on next vblank */
4203 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4204 }
4205
4206 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4207 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4208 bool on)
4209 {
4210 struct drm_device *dev = crtc->dev;
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4213 int pipe = intel_crtc->pipe;
4214 int x = intel_crtc->cursor_x;
4215 int y = intel_crtc->cursor_y;
4216 u32 base, pos;
4217 bool visible;
4218
4219 pos = 0;
4220
4221 if (on && crtc->enabled && crtc->fb) {
4222 base = intel_crtc->cursor_addr;
4223 if (x > (int) crtc->fb->width)
4224 base = 0;
4225
4226 if (y > (int) crtc->fb->height)
4227 base = 0;
4228 } else
4229 base = 0;
4230
4231 if (x < 0) {
4232 if (x + intel_crtc->cursor_width < 0)
4233 base = 0;
4234
4235 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4236 x = -x;
4237 }
4238 pos |= x << CURSOR_X_SHIFT;
4239
4240 if (y < 0) {
4241 if (y + intel_crtc->cursor_height < 0)
4242 base = 0;
4243
4244 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4245 y = -y;
4246 }
4247 pos |= y << CURSOR_Y_SHIFT;
4248
4249 visible = base != 0;
4250 if (!visible && !intel_crtc->cursor_visible)
4251 return;
4252
4253 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4254 if (IS_845G(dev) || IS_I865G(dev))
4255 i845_update_cursor(crtc, base);
4256 else
4257 i9xx_update_cursor(crtc, base);
4258
4259 if (visible)
4260 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4261 }
4262
4263 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4264 struct drm_file *file_priv,
4265 uint32_t handle,
4266 uint32_t width, uint32_t height)
4267 {
4268 struct drm_device *dev = crtc->dev;
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4271 struct drm_gem_object *bo;
4272 struct drm_i915_gem_object *obj_priv;
4273 uint32_t addr;
4274 int ret;
4275
4276 DRM_DEBUG_KMS("\n");
4277
4278 /* if we want to turn off the cursor ignore width and height */
4279 if (!handle) {
4280 DRM_DEBUG_KMS("cursor off\n");
4281 addr = 0;
4282 bo = NULL;
4283 mutex_lock(&dev->struct_mutex);
4284 goto finish;
4285 }
4286
4287 /* Currently we only support 64x64 cursors */
4288 if (width != 64 || height != 64) {
4289 DRM_ERROR("we currently only support 64x64 cursors\n");
4290 return -EINVAL;
4291 }
4292
4293 bo = drm_gem_object_lookup(dev, file_priv, handle);
4294 if (!bo)
4295 return -ENOENT;
4296
4297 obj_priv = to_intel_bo(bo);
4298
4299 if (bo->size < width * height * 4) {
4300 DRM_ERROR("buffer is to small\n");
4301 ret = -ENOMEM;
4302 goto fail;
4303 }
4304
4305 /* we only need to pin inside GTT if cursor is non-phy */
4306 mutex_lock(&dev->struct_mutex);
4307 if (!dev_priv->info->cursor_needs_physical) {
4308 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4309 if (ret) {
4310 DRM_ERROR("failed to pin cursor bo\n");
4311 goto fail_locked;
4312 }
4313
4314 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4315 if (ret) {
4316 DRM_ERROR("failed to move cursor bo into the GTT\n");
4317 goto fail_unpin;
4318 }
4319
4320 addr = obj_priv->gtt_offset;
4321 } else {
4322 int align = IS_I830(dev) ? 16 * 1024 : 256;
4323 ret = i915_gem_attach_phys_object(dev, bo,
4324 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4325 align);
4326 if (ret) {
4327 DRM_ERROR("failed to attach phys object\n");
4328 goto fail_locked;
4329 }
4330 addr = obj_priv->phys_obj->handle->busaddr;
4331 }
4332
4333 if (!IS_I9XX(dev))
4334 I915_WRITE(CURSIZE, (height << 12) | width);
4335
4336 finish:
4337 if (intel_crtc->cursor_bo) {
4338 if (dev_priv->info->cursor_needs_physical) {
4339 if (intel_crtc->cursor_bo != bo)
4340 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4341 } else
4342 i915_gem_object_unpin(intel_crtc->cursor_bo);
4343 drm_gem_object_unreference(intel_crtc->cursor_bo);
4344 }
4345
4346 mutex_unlock(&dev->struct_mutex);
4347
4348 intel_crtc->cursor_addr = addr;
4349 intel_crtc->cursor_bo = bo;
4350 intel_crtc->cursor_width = width;
4351 intel_crtc->cursor_height = height;
4352
4353 intel_crtc_update_cursor(crtc, true);
4354
4355 return 0;
4356 fail_unpin:
4357 i915_gem_object_unpin(bo);
4358 fail_locked:
4359 mutex_unlock(&dev->struct_mutex);
4360 fail:
4361 drm_gem_object_unreference_unlocked(bo);
4362 return ret;
4363 }
4364
4365 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4366 {
4367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4368
4369 intel_crtc->cursor_x = x;
4370 intel_crtc->cursor_y = y;
4371
4372 intel_crtc_update_cursor(crtc, true);
4373
4374 return 0;
4375 }
4376
4377 /** Sets the color ramps on behalf of RandR */
4378 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4379 u16 blue, int regno)
4380 {
4381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4382
4383 intel_crtc->lut_r[regno] = red >> 8;
4384 intel_crtc->lut_g[regno] = green >> 8;
4385 intel_crtc->lut_b[regno] = blue >> 8;
4386 }
4387
4388 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4389 u16 *blue, int regno)
4390 {
4391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4392
4393 *red = intel_crtc->lut_r[regno] << 8;
4394 *green = intel_crtc->lut_g[regno] << 8;
4395 *blue = intel_crtc->lut_b[regno] << 8;
4396 }
4397
4398 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4399 u16 *blue, uint32_t start, uint32_t size)
4400 {
4401 int end = (start + size > 256) ? 256 : start + size, i;
4402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4403
4404 for (i = start; i < end; i++) {
4405 intel_crtc->lut_r[i] = red[i] >> 8;
4406 intel_crtc->lut_g[i] = green[i] >> 8;
4407 intel_crtc->lut_b[i] = blue[i] >> 8;
4408 }
4409
4410 intel_crtc_load_lut(crtc);
4411 }
4412
4413 /**
4414 * Get a pipe with a simple mode set on it for doing load-based monitor
4415 * detection.
4416 *
4417 * It will be up to the load-detect code to adjust the pipe as appropriate for
4418 * its requirements. The pipe will be connected to no other encoders.
4419 *
4420 * Currently this code will only succeed if there is a pipe with no encoders
4421 * configured for it. In the future, it could choose to temporarily disable
4422 * some outputs to free up a pipe for its use.
4423 *
4424 * \return crtc, or NULL if no pipes are available.
4425 */
4426
4427 /* VESA 640x480x72Hz mode to set on the pipe */
4428 static struct drm_display_mode load_detect_mode = {
4429 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4430 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4431 };
4432
4433 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4434 struct drm_connector *connector,
4435 struct drm_display_mode *mode,
4436 int *dpms_mode)
4437 {
4438 struct intel_crtc *intel_crtc;
4439 struct drm_crtc *possible_crtc;
4440 struct drm_crtc *supported_crtc =NULL;
4441 struct drm_encoder *encoder = &intel_encoder->base;
4442 struct drm_crtc *crtc = NULL;
4443 struct drm_device *dev = encoder->dev;
4444 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4445 struct drm_crtc_helper_funcs *crtc_funcs;
4446 int i = -1;
4447
4448 /*
4449 * Algorithm gets a little messy:
4450 * - if the connector already has an assigned crtc, use it (but make
4451 * sure it's on first)
4452 * - try to find the first unused crtc that can drive this connector,
4453 * and use that if we find one
4454 * - if there are no unused crtcs available, try to use the first
4455 * one we found that supports the connector
4456 */
4457
4458 /* See if we already have a CRTC for this connector */
4459 if (encoder->crtc) {
4460 crtc = encoder->crtc;
4461 /* Make sure the crtc and connector are running */
4462 intel_crtc = to_intel_crtc(crtc);
4463 *dpms_mode = intel_crtc->dpms_mode;
4464 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4465 crtc_funcs = crtc->helper_private;
4466 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4467 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4468 }
4469 return crtc;
4470 }
4471
4472 /* Find an unused one (if possible) */
4473 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4474 i++;
4475 if (!(encoder->possible_crtcs & (1 << i)))
4476 continue;
4477 if (!possible_crtc->enabled) {
4478 crtc = possible_crtc;
4479 break;
4480 }
4481 if (!supported_crtc)
4482 supported_crtc = possible_crtc;
4483 }
4484
4485 /*
4486 * If we didn't find an unused CRTC, don't use any.
4487 */
4488 if (!crtc) {
4489 return NULL;
4490 }
4491
4492 encoder->crtc = crtc;
4493 connector->encoder = encoder;
4494 intel_encoder->load_detect_temp = true;
4495
4496 intel_crtc = to_intel_crtc(crtc);
4497 *dpms_mode = intel_crtc->dpms_mode;
4498
4499 if (!crtc->enabled) {
4500 if (!mode)
4501 mode = &load_detect_mode;
4502 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4503 } else {
4504 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4505 crtc_funcs = crtc->helper_private;
4506 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4507 }
4508
4509 /* Add this connector to the crtc */
4510 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4511 encoder_funcs->commit(encoder);
4512 }
4513 /* let the connector get through one full cycle before testing */
4514 intel_wait_for_vblank(dev, intel_crtc->pipe);
4515
4516 return crtc;
4517 }
4518
4519 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4520 struct drm_connector *connector, int dpms_mode)
4521 {
4522 struct drm_encoder *encoder = &intel_encoder->base;
4523 struct drm_device *dev = encoder->dev;
4524 struct drm_crtc *crtc = encoder->crtc;
4525 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4526 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4527
4528 if (intel_encoder->load_detect_temp) {
4529 encoder->crtc = NULL;
4530 connector->encoder = NULL;
4531 intel_encoder->load_detect_temp = false;
4532 crtc->enabled = drm_helper_crtc_in_use(crtc);
4533 drm_helper_disable_unused_functions(dev);
4534 }
4535
4536 /* Switch crtc and encoder back off if necessary */
4537 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4538 if (encoder->crtc == crtc)
4539 encoder_funcs->dpms(encoder, dpms_mode);
4540 crtc_funcs->dpms(crtc, dpms_mode);
4541 }
4542 }
4543
4544 /* Returns the clock of the currently programmed mode of the given pipe. */
4545 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4546 {
4547 struct drm_i915_private *dev_priv = dev->dev_private;
4548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4549 int pipe = intel_crtc->pipe;
4550 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4551 u32 fp;
4552 intel_clock_t clock;
4553
4554 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4555 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4556 else
4557 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4558
4559 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4560 if (IS_PINEVIEW(dev)) {
4561 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4562 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4563 } else {
4564 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4565 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4566 }
4567
4568 if (IS_I9XX(dev)) {
4569 if (IS_PINEVIEW(dev))
4570 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4571 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4572 else
4573 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4574 DPLL_FPA01_P1_POST_DIV_SHIFT);
4575
4576 switch (dpll & DPLL_MODE_MASK) {
4577 case DPLLB_MODE_DAC_SERIAL:
4578 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4579 5 : 10;
4580 break;
4581 case DPLLB_MODE_LVDS:
4582 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4583 7 : 14;
4584 break;
4585 default:
4586 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4587 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4588 return 0;
4589 }
4590
4591 /* XXX: Handle the 100Mhz refclk */
4592 intel_clock(dev, 96000, &clock);
4593 } else {
4594 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4595
4596 if (is_lvds) {
4597 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4598 DPLL_FPA01_P1_POST_DIV_SHIFT);
4599 clock.p2 = 14;
4600
4601 if ((dpll & PLL_REF_INPUT_MASK) ==
4602 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4603 /* XXX: might not be 66MHz */
4604 intel_clock(dev, 66000, &clock);
4605 } else
4606 intel_clock(dev, 48000, &clock);
4607 } else {
4608 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4609 clock.p1 = 2;
4610 else {
4611 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4612 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4613 }
4614 if (dpll & PLL_P2_DIVIDE_BY_4)
4615 clock.p2 = 4;
4616 else
4617 clock.p2 = 2;
4618
4619 intel_clock(dev, 48000, &clock);
4620 }
4621 }
4622
4623 /* XXX: It would be nice to validate the clocks, but we can't reuse
4624 * i830PllIsValid() because it relies on the xf86_config connector
4625 * configuration being accurate, which it isn't necessarily.
4626 */
4627
4628 return clock.dot;
4629 }
4630
4631 /** Returns the currently programmed mode of the given pipe. */
4632 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4633 struct drm_crtc *crtc)
4634 {
4635 struct drm_i915_private *dev_priv = dev->dev_private;
4636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4637 int pipe = intel_crtc->pipe;
4638 struct drm_display_mode *mode;
4639 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4640 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4641 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4642 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4643
4644 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4645 if (!mode)
4646 return NULL;
4647
4648 mode->clock = intel_crtc_clock_get(dev, crtc);
4649 mode->hdisplay = (htot & 0xffff) + 1;
4650 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4651 mode->hsync_start = (hsync & 0xffff) + 1;
4652 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4653 mode->vdisplay = (vtot & 0xffff) + 1;
4654 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4655 mode->vsync_start = (vsync & 0xffff) + 1;
4656 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4657
4658 drm_mode_set_name(mode);
4659 drm_mode_set_crtcinfo(mode, 0);
4660
4661 return mode;
4662 }
4663
4664 #define GPU_IDLE_TIMEOUT 500 /* ms */
4665
4666 /* When this timer fires, we've been idle for awhile */
4667 static void intel_gpu_idle_timer(unsigned long arg)
4668 {
4669 struct drm_device *dev = (struct drm_device *)arg;
4670 drm_i915_private_t *dev_priv = dev->dev_private;
4671
4672 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4673
4674 dev_priv->busy = false;
4675
4676 queue_work(dev_priv->wq, &dev_priv->idle_work);
4677 }
4678
4679 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4680
4681 static void intel_crtc_idle_timer(unsigned long arg)
4682 {
4683 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4684 struct drm_crtc *crtc = &intel_crtc->base;
4685 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4686
4687 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4688
4689 intel_crtc->busy = false;
4690
4691 queue_work(dev_priv->wq, &dev_priv->idle_work);
4692 }
4693
4694 static void intel_increase_pllclock(struct drm_crtc *crtc)
4695 {
4696 struct drm_device *dev = crtc->dev;
4697 drm_i915_private_t *dev_priv = dev->dev_private;
4698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699 int pipe = intel_crtc->pipe;
4700 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4701 int dpll = I915_READ(dpll_reg);
4702
4703 if (HAS_PCH_SPLIT(dev))
4704 return;
4705
4706 if (!dev_priv->lvds_downclock_avail)
4707 return;
4708
4709 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4710 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4711
4712 /* Unlock panel regs */
4713 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4714 PANEL_UNLOCK_REGS);
4715
4716 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4717 I915_WRITE(dpll_reg, dpll);
4718 dpll = I915_READ(dpll_reg);
4719 intel_wait_for_vblank(dev, pipe);
4720 dpll = I915_READ(dpll_reg);
4721 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4722 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4723
4724 /* ...and lock them again */
4725 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4726 }
4727
4728 /* Schedule downclock */
4729 mod_timer(&intel_crtc->idle_timer, jiffies +
4730 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4731 }
4732
4733 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4734 {
4735 struct drm_device *dev = crtc->dev;
4736 drm_i915_private_t *dev_priv = dev->dev_private;
4737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4738 int pipe = intel_crtc->pipe;
4739 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4740 int dpll = I915_READ(dpll_reg);
4741
4742 if (HAS_PCH_SPLIT(dev))
4743 return;
4744
4745 if (!dev_priv->lvds_downclock_avail)
4746 return;
4747
4748 /*
4749 * Since this is called by a timer, we should never get here in
4750 * the manual case.
4751 */
4752 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4753 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4754
4755 /* Unlock panel regs */
4756 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4757 PANEL_UNLOCK_REGS);
4758
4759 dpll |= DISPLAY_RATE_SELECT_FPA1;
4760 I915_WRITE(dpll_reg, dpll);
4761 dpll = I915_READ(dpll_reg);
4762 intel_wait_for_vblank(dev, pipe);
4763 dpll = I915_READ(dpll_reg);
4764 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4765 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4766
4767 /* ...and lock them again */
4768 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4769 }
4770
4771 }
4772
4773 /**
4774 * intel_idle_update - adjust clocks for idleness
4775 * @work: work struct
4776 *
4777 * Either the GPU or display (or both) went idle. Check the busy status
4778 * here and adjust the CRTC and GPU clocks as necessary.
4779 */
4780 static void intel_idle_update(struct work_struct *work)
4781 {
4782 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4783 idle_work);
4784 struct drm_device *dev = dev_priv->dev;
4785 struct drm_crtc *crtc;
4786 struct intel_crtc *intel_crtc;
4787 int enabled = 0;
4788
4789 if (!i915_powersave)
4790 return;
4791
4792 mutex_lock(&dev->struct_mutex);
4793
4794 i915_update_gfx_val(dev_priv);
4795
4796 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4797 /* Skip inactive CRTCs */
4798 if (!crtc->fb)
4799 continue;
4800
4801 enabled++;
4802 intel_crtc = to_intel_crtc(crtc);
4803 if (!intel_crtc->busy)
4804 intel_decrease_pllclock(crtc);
4805 }
4806
4807 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4808 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4809 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4810 }
4811
4812 mutex_unlock(&dev->struct_mutex);
4813 }
4814
4815 /**
4816 * intel_mark_busy - mark the GPU and possibly the display busy
4817 * @dev: drm device
4818 * @obj: object we're operating on
4819 *
4820 * Callers can use this function to indicate that the GPU is busy processing
4821 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4822 * buffer), we'll also mark the display as busy, so we know to increase its
4823 * clock frequency.
4824 */
4825 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4826 {
4827 drm_i915_private_t *dev_priv = dev->dev_private;
4828 struct drm_crtc *crtc = NULL;
4829 struct intel_framebuffer *intel_fb;
4830 struct intel_crtc *intel_crtc;
4831
4832 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4833 return;
4834
4835 if (!dev_priv->busy) {
4836 if (IS_I945G(dev) || IS_I945GM(dev)) {
4837 u32 fw_blc_self;
4838
4839 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4840 fw_blc_self = I915_READ(FW_BLC_SELF);
4841 fw_blc_self &= ~FW_BLC_SELF_EN;
4842 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4843 }
4844 dev_priv->busy = true;
4845 } else
4846 mod_timer(&dev_priv->idle_timer, jiffies +
4847 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4848
4849 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4850 if (!crtc->fb)
4851 continue;
4852
4853 intel_crtc = to_intel_crtc(crtc);
4854 intel_fb = to_intel_framebuffer(crtc->fb);
4855 if (intel_fb->obj == obj) {
4856 if (!intel_crtc->busy) {
4857 if (IS_I945G(dev) || IS_I945GM(dev)) {
4858 u32 fw_blc_self;
4859
4860 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4861 fw_blc_self = I915_READ(FW_BLC_SELF);
4862 fw_blc_self &= ~FW_BLC_SELF_EN;
4863 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4864 }
4865 /* Non-busy -> busy, upclock */
4866 intel_increase_pllclock(crtc);
4867 intel_crtc->busy = true;
4868 } else {
4869 /* Busy -> busy, put off timer */
4870 mod_timer(&intel_crtc->idle_timer, jiffies +
4871 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4872 }
4873 }
4874 }
4875 }
4876
4877 static void intel_crtc_destroy(struct drm_crtc *crtc)
4878 {
4879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4880 struct drm_device *dev = crtc->dev;
4881 struct intel_unpin_work *work;
4882 unsigned long flags;
4883
4884 spin_lock_irqsave(&dev->event_lock, flags);
4885 work = intel_crtc->unpin_work;
4886 intel_crtc->unpin_work = NULL;
4887 spin_unlock_irqrestore(&dev->event_lock, flags);
4888
4889 if (work) {
4890 cancel_work_sync(&work->work);
4891 kfree(work);
4892 }
4893
4894 drm_crtc_cleanup(crtc);
4895
4896 kfree(intel_crtc);
4897 }
4898
4899 static void intel_unpin_work_fn(struct work_struct *__work)
4900 {
4901 struct intel_unpin_work *work =
4902 container_of(__work, struct intel_unpin_work, work);
4903
4904 mutex_lock(&work->dev->struct_mutex);
4905 i915_gem_object_unpin(work->old_fb_obj);
4906 drm_gem_object_unreference(work->pending_flip_obj);
4907 drm_gem_object_unreference(work->old_fb_obj);
4908 mutex_unlock(&work->dev->struct_mutex);
4909 kfree(work);
4910 }
4911
4912 static void do_intel_finish_page_flip(struct drm_device *dev,
4913 struct drm_crtc *crtc)
4914 {
4915 drm_i915_private_t *dev_priv = dev->dev_private;
4916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4917 struct intel_unpin_work *work;
4918 struct drm_i915_gem_object *obj_priv;
4919 struct drm_pending_vblank_event *e;
4920 struct timeval now;
4921 unsigned long flags;
4922
4923 /* Ignore early vblank irqs */
4924 if (intel_crtc == NULL)
4925 return;
4926
4927 spin_lock_irqsave(&dev->event_lock, flags);
4928 work = intel_crtc->unpin_work;
4929 if (work == NULL || !work->pending) {
4930 spin_unlock_irqrestore(&dev->event_lock, flags);
4931 return;
4932 }
4933
4934 intel_crtc->unpin_work = NULL;
4935 drm_vblank_put(dev, intel_crtc->pipe);
4936
4937 if (work->event) {
4938 e = work->event;
4939 do_gettimeofday(&now);
4940 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4941 e->event.tv_sec = now.tv_sec;
4942 e->event.tv_usec = now.tv_usec;
4943 list_add_tail(&e->base.link,
4944 &e->base.file_priv->event_list);
4945 wake_up_interruptible(&e->base.file_priv->event_wait);
4946 }
4947
4948 spin_unlock_irqrestore(&dev->event_lock, flags);
4949
4950 obj_priv = to_intel_bo(work->pending_flip_obj);
4951
4952 /* Initial scanout buffer will have a 0 pending flip count */
4953 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4954 atomic_dec_and_test(&obj_priv->pending_flip))
4955 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4956 schedule_work(&work->work);
4957
4958 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4959 }
4960
4961 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4962 {
4963 drm_i915_private_t *dev_priv = dev->dev_private;
4964 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4965
4966 do_intel_finish_page_flip(dev, crtc);
4967 }
4968
4969 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4970 {
4971 drm_i915_private_t *dev_priv = dev->dev_private;
4972 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4973
4974 do_intel_finish_page_flip(dev, crtc);
4975 }
4976
4977 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4978 {
4979 drm_i915_private_t *dev_priv = dev->dev_private;
4980 struct intel_crtc *intel_crtc =
4981 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4982 unsigned long flags;
4983
4984 spin_lock_irqsave(&dev->event_lock, flags);
4985 if (intel_crtc->unpin_work) {
4986 if ((++intel_crtc->unpin_work->pending) > 1)
4987 DRM_ERROR("Prepared flip multiple times\n");
4988 } else {
4989 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4990 }
4991 spin_unlock_irqrestore(&dev->event_lock, flags);
4992 }
4993
4994 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4995 struct drm_framebuffer *fb,
4996 struct drm_pending_vblank_event *event)
4997 {
4998 struct drm_device *dev = crtc->dev;
4999 struct drm_i915_private *dev_priv = dev->dev_private;
5000 struct intel_framebuffer *intel_fb;
5001 struct drm_i915_gem_object *obj_priv;
5002 struct drm_gem_object *obj;
5003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5004 struct intel_unpin_work *work;
5005 unsigned long flags, offset;
5006 int pipe = intel_crtc->pipe;
5007 u32 pf, pipesrc;
5008 int ret;
5009
5010 work = kzalloc(sizeof *work, GFP_KERNEL);
5011 if (work == NULL)
5012 return -ENOMEM;
5013
5014 work->event = event;
5015 work->dev = crtc->dev;
5016 intel_fb = to_intel_framebuffer(crtc->fb);
5017 work->old_fb_obj = intel_fb->obj;
5018 INIT_WORK(&work->work, intel_unpin_work_fn);
5019
5020 /* We borrow the event spin lock for protecting unpin_work */
5021 spin_lock_irqsave(&dev->event_lock, flags);
5022 if (intel_crtc->unpin_work) {
5023 spin_unlock_irqrestore(&dev->event_lock, flags);
5024 kfree(work);
5025
5026 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5027 return -EBUSY;
5028 }
5029 intel_crtc->unpin_work = work;
5030 spin_unlock_irqrestore(&dev->event_lock, flags);
5031
5032 intel_fb = to_intel_framebuffer(fb);
5033 obj = intel_fb->obj;
5034
5035 mutex_lock(&dev->struct_mutex);
5036 ret = intel_pin_and_fence_fb_obj(dev, obj);
5037 if (ret)
5038 goto cleanup_work;
5039
5040 /* Reference the objects for the scheduled work. */
5041 drm_gem_object_reference(work->old_fb_obj);
5042 drm_gem_object_reference(obj);
5043
5044 crtc->fb = fb;
5045
5046 ret = drm_vblank_get(dev, intel_crtc->pipe);
5047 if (ret)
5048 goto cleanup_objs;
5049
5050 obj_priv = to_intel_bo(obj);
5051 atomic_inc(&obj_priv->pending_flip);
5052 work->pending_flip_obj = obj;
5053
5054 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5055 u32 flip_mask;
5056
5057 if (intel_crtc->plane)
5058 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5059 else
5060 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5061
5062 BEGIN_LP_RING(2);
5063 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5064 OUT_RING(0);
5065 ADVANCE_LP_RING();
5066 }
5067
5068 work->enable_stall_check = true;
5069
5070 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5071 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5072
5073 BEGIN_LP_RING(4);
5074 switch(INTEL_INFO(dev)->gen) {
5075 case 2:
5076 OUT_RING(MI_DISPLAY_FLIP |
5077 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5078 OUT_RING(fb->pitch);
5079 OUT_RING(obj_priv->gtt_offset + offset);
5080 OUT_RING(MI_NOOP);
5081 break;
5082
5083 case 3:
5084 OUT_RING(MI_DISPLAY_FLIP_I915 |
5085 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5086 OUT_RING(fb->pitch);
5087 OUT_RING(obj_priv->gtt_offset + offset);
5088 OUT_RING(MI_NOOP);
5089 break;
5090
5091 case 4:
5092 case 5:
5093 /* i965+ uses the linear or tiled offsets from the
5094 * Display Registers (which do not change across a page-flip)
5095 * so we need only reprogram the base address.
5096 */
5097 OUT_RING(MI_DISPLAY_FLIP |
5098 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5099 OUT_RING(fb->pitch);
5100 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5101
5102 /* XXX Enabling the panel-fitter across page-flip is so far
5103 * untested on non-native modes, so ignore it for now.
5104 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5105 */
5106 pf = 0;
5107 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5108 OUT_RING(pf | pipesrc);
5109 break;
5110
5111 case 6:
5112 OUT_RING(MI_DISPLAY_FLIP |
5113 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5114 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5115 OUT_RING(obj_priv->gtt_offset);
5116
5117 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5118 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5119 OUT_RING(pf | pipesrc);
5120 break;
5121 }
5122 ADVANCE_LP_RING();
5123
5124 mutex_unlock(&dev->struct_mutex);
5125
5126 trace_i915_flip_request(intel_crtc->plane, obj);
5127
5128 return 0;
5129
5130 cleanup_objs:
5131 drm_gem_object_unreference(work->old_fb_obj);
5132 drm_gem_object_unreference(obj);
5133 cleanup_work:
5134 mutex_unlock(&dev->struct_mutex);
5135
5136 spin_lock_irqsave(&dev->event_lock, flags);
5137 intel_crtc->unpin_work = NULL;
5138 spin_unlock_irqrestore(&dev->event_lock, flags);
5139
5140 kfree(work);
5141
5142 return ret;
5143 }
5144
5145 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5146 .dpms = intel_crtc_dpms,
5147 .mode_fixup = intel_crtc_mode_fixup,
5148 .mode_set = intel_crtc_mode_set,
5149 .mode_set_base = intel_pipe_set_base,
5150 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5151 .load_lut = intel_crtc_load_lut,
5152 };
5153
5154 static const struct drm_crtc_funcs intel_crtc_funcs = {
5155 .cursor_set = intel_crtc_cursor_set,
5156 .cursor_move = intel_crtc_cursor_move,
5157 .gamma_set = intel_crtc_gamma_set,
5158 .set_config = drm_crtc_helper_set_config,
5159 .destroy = intel_crtc_destroy,
5160 .page_flip = intel_crtc_page_flip,
5161 };
5162
5163
5164 static void intel_crtc_init(struct drm_device *dev, int pipe)
5165 {
5166 drm_i915_private_t *dev_priv = dev->dev_private;
5167 struct intel_crtc *intel_crtc;
5168 int i;
5169
5170 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5171 if (intel_crtc == NULL)
5172 return;
5173
5174 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5175
5176 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5177 for (i = 0; i < 256; i++) {
5178 intel_crtc->lut_r[i] = i;
5179 intel_crtc->lut_g[i] = i;
5180 intel_crtc->lut_b[i] = i;
5181 }
5182
5183 /* Swap pipes & planes for FBC on pre-965 */
5184 intel_crtc->pipe = pipe;
5185 intel_crtc->plane = pipe;
5186 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5187 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5188 intel_crtc->plane = !pipe;
5189 }
5190
5191 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5193 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5194 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5195
5196 intel_crtc->cursor_addr = 0;
5197 intel_crtc->dpms_mode = -1;
5198 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5199
5200 if (HAS_PCH_SPLIT(dev)) {
5201 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5202 intel_helper_funcs.commit = ironlake_crtc_commit;
5203 } else {
5204 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5205 intel_helper_funcs.commit = i9xx_crtc_commit;
5206 }
5207
5208 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5209
5210 intel_crtc->busy = false;
5211
5212 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5213 (unsigned long)intel_crtc);
5214 }
5215
5216 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5217 struct drm_file *file_priv)
5218 {
5219 drm_i915_private_t *dev_priv = dev->dev_private;
5220 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5221 struct drm_mode_object *drmmode_obj;
5222 struct intel_crtc *crtc;
5223
5224 if (!dev_priv) {
5225 DRM_ERROR("called with no initialization\n");
5226 return -EINVAL;
5227 }
5228
5229 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5230 DRM_MODE_OBJECT_CRTC);
5231
5232 if (!drmmode_obj) {
5233 DRM_ERROR("no such CRTC id\n");
5234 return -EINVAL;
5235 }
5236
5237 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5238 pipe_from_crtc_id->pipe = crtc->pipe;
5239
5240 return 0;
5241 }
5242
5243 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5244 {
5245 struct intel_encoder *encoder;
5246 int index_mask = 0;
5247 int entry = 0;
5248
5249 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5250 if (type_mask & encoder->clone_mask)
5251 index_mask |= (1 << entry);
5252 entry++;
5253 }
5254
5255 return index_mask;
5256 }
5257
5258 static void intel_setup_outputs(struct drm_device *dev)
5259 {
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 struct intel_encoder *encoder;
5262 bool dpd_is_edp = false;
5263
5264 if (IS_MOBILE(dev) && !IS_I830(dev))
5265 intel_lvds_init(dev);
5266
5267 if (HAS_PCH_SPLIT(dev)) {
5268 dpd_is_edp = intel_dpd_is_edp(dev);
5269
5270 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5271 intel_dp_init(dev, DP_A);
5272
5273 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5274 intel_dp_init(dev, PCH_DP_D);
5275 }
5276
5277 intel_crt_init(dev);
5278
5279 if (HAS_PCH_SPLIT(dev)) {
5280 int found;
5281
5282 if (I915_READ(HDMIB) & PORT_DETECTED) {
5283 /* PCH SDVOB multiplex with HDMIB */
5284 found = intel_sdvo_init(dev, PCH_SDVOB);
5285 if (!found)
5286 intel_hdmi_init(dev, HDMIB);
5287 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5288 intel_dp_init(dev, PCH_DP_B);
5289 }
5290
5291 if (I915_READ(HDMIC) & PORT_DETECTED)
5292 intel_hdmi_init(dev, HDMIC);
5293
5294 if (I915_READ(HDMID) & PORT_DETECTED)
5295 intel_hdmi_init(dev, HDMID);
5296
5297 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5298 intel_dp_init(dev, PCH_DP_C);
5299
5300 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5301 intel_dp_init(dev, PCH_DP_D);
5302
5303 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5304 bool found = false;
5305
5306 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5307 DRM_DEBUG_KMS("probing SDVOB\n");
5308 found = intel_sdvo_init(dev, SDVOB);
5309 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5310 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5311 intel_hdmi_init(dev, SDVOB);
5312 }
5313
5314 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5315 DRM_DEBUG_KMS("probing DP_B\n");
5316 intel_dp_init(dev, DP_B);
5317 }
5318 }
5319
5320 /* Before G4X SDVOC doesn't have its own detect register */
5321
5322 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5323 DRM_DEBUG_KMS("probing SDVOC\n");
5324 found = intel_sdvo_init(dev, SDVOC);
5325 }
5326
5327 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5328
5329 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5330 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5331 intel_hdmi_init(dev, SDVOC);
5332 }
5333 if (SUPPORTS_INTEGRATED_DP(dev)) {
5334 DRM_DEBUG_KMS("probing DP_C\n");
5335 intel_dp_init(dev, DP_C);
5336 }
5337 }
5338
5339 if (SUPPORTS_INTEGRATED_DP(dev) &&
5340 (I915_READ(DP_D) & DP_DETECTED)) {
5341 DRM_DEBUG_KMS("probing DP_D\n");
5342 intel_dp_init(dev, DP_D);
5343 }
5344 } else if (IS_GEN2(dev))
5345 intel_dvo_init(dev);
5346
5347 if (SUPPORTS_TV(dev))
5348 intel_tv_init(dev);
5349
5350 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5351 encoder->base.possible_crtcs = encoder->crtc_mask;
5352 encoder->base.possible_clones =
5353 intel_encoder_clones(dev, encoder->clone_mask);
5354 }
5355 }
5356
5357 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5358 {
5359 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5360
5361 drm_framebuffer_cleanup(fb);
5362 drm_gem_object_unreference_unlocked(intel_fb->obj);
5363
5364 kfree(intel_fb);
5365 }
5366
5367 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5368 struct drm_file *file_priv,
5369 unsigned int *handle)
5370 {
5371 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5372 struct drm_gem_object *object = intel_fb->obj;
5373
5374 return drm_gem_handle_create(file_priv, object, handle);
5375 }
5376
5377 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5378 .destroy = intel_user_framebuffer_destroy,
5379 .create_handle = intel_user_framebuffer_create_handle,
5380 };
5381
5382 int intel_framebuffer_init(struct drm_device *dev,
5383 struct intel_framebuffer *intel_fb,
5384 struct drm_mode_fb_cmd *mode_cmd,
5385 struct drm_gem_object *obj)
5386 {
5387 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5388 int ret;
5389
5390 if (obj_priv->tiling_mode == I915_TILING_Y)
5391 return -EINVAL;
5392
5393 if (mode_cmd->pitch & 63)
5394 return -EINVAL;
5395
5396 switch (mode_cmd->bpp) {
5397 case 8:
5398 case 16:
5399 case 24:
5400 case 32:
5401 break;
5402 default:
5403 return -EINVAL;
5404 }
5405
5406 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5407 if (ret) {
5408 DRM_ERROR("framebuffer init failed %d\n", ret);
5409 return ret;
5410 }
5411
5412 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5413 intel_fb->obj = obj;
5414 return 0;
5415 }
5416
5417 static struct drm_framebuffer *
5418 intel_user_framebuffer_create(struct drm_device *dev,
5419 struct drm_file *filp,
5420 struct drm_mode_fb_cmd *mode_cmd)
5421 {
5422 struct drm_gem_object *obj;
5423 struct intel_framebuffer *intel_fb;
5424 int ret;
5425
5426 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5427 if (!obj)
5428 return ERR_PTR(-ENOENT);
5429
5430 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5431 if (!intel_fb)
5432 return ERR_PTR(-ENOMEM);
5433
5434 ret = intel_framebuffer_init(dev, intel_fb,
5435 mode_cmd, obj);
5436 if (ret) {
5437 drm_gem_object_unreference_unlocked(obj);
5438 kfree(intel_fb);
5439 return ERR_PTR(ret);
5440 }
5441
5442 return &intel_fb->base;
5443 }
5444
5445 static const struct drm_mode_config_funcs intel_mode_funcs = {
5446 .fb_create = intel_user_framebuffer_create,
5447 .output_poll_changed = intel_fb_output_poll_changed,
5448 };
5449
5450 static struct drm_gem_object *
5451 intel_alloc_context_page(struct drm_device *dev)
5452 {
5453 struct drm_gem_object *ctx;
5454 int ret;
5455
5456 ctx = i915_gem_alloc_object(dev, 4096);
5457 if (!ctx) {
5458 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5459 return NULL;
5460 }
5461
5462 mutex_lock(&dev->struct_mutex);
5463 ret = i915_gem_object_pin(ctx, 4096);
5464 if (ret) {
5465 DRM_ERROR("failed to pin power context: %d\n", ret);
5466 goto err_unref;
5467 }
5468
5469 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5470 if (ret) {
5471 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5472 goto err_unpin;
5473 }
5474 mutex_unlock(&dev->struct_mutex);
5475
5476 return ctx;
5477
5478 err_unpin:
5479 i915_gem_object_unpin(ctx);
5480 err_unref:
5481 drm_gem_object_unreference(ctx);
5482 mutex_unlock(&dev->struct_mutex);
5483 return NULL;
5484 }
5485
5486 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5487 {
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 u16 rgvswctl;
5490
5491 rgvswctl = I915_READ16(MEMSWCTL);
5492 if (rgvswctl & MEMCTL_CMD_STS) {
5493 DRM_DEBUG("gpu busy, RCS change rejected\n");
5494 return false; /* still busy with another command */
5495 }
5496
5497 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5498 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5499 I915_WRITE16(MEMSWCTL, rgvswctl);
5500 POSTING_READ16(MEMSWCTL);
5501
5502 rgvswctl |= MEMCTL_CMD_STS;
5503 I915_WRITE16(MEMSWCTL, rgvswctl);
5504
5505 return true;
5506 }
5507
5508 void ironlake_enable_drps(struct drm_device *dev)
5509 {
5510 struct drm_i915_private *dev_priv = dev->dev_private;
5511 u32 rgvmodectl = I915_READ(MEMMODECTL);
5512 u8 fmax, fmin, fstart, vstart;
5513
5514 /* Enable temp reporting */
5515 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5516 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5517
5518 /* 100ms RC evaluation intervals */
5519 I915_WRITE(RCUPEI, 100000);
5520 I915_WRITE(RCDNEI, 100000);
5521
5522 /* Set max/min thresholds to 90ms and 80ms respectively */
5523 I915_WRITE(RCBMAXAVG, 90000);
5524 I915_WRITE(RCBMINAVG, 80000);
5525
5526 I915_WRITE(MEMIHYST, 1);
5527
5528 /* Set up min, max, and cur for interrupt handling */
5529 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5530 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5531 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5532 MEMMODE_FSTART_SHIFT;
5533 fstart = fmax;
5534
5535 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5536 PXVFREQ_PX_SHIFT;
5537
5538 dev_priv->fmax = fstart; /* IPS callback will increase this */
5539 dev_priv->fstart = fstart;
5540
5541 dev_priv->max_delay = fmax;
5542 dev_priv->min_delay = fmin;
5543 dev_priv->cur_delay = fstart;
5544
5545 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5546 fstart);
5547
5548 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5549
5550 /*
5551 * Interrupts will be enabled in ironlake_irq_postinstall
5552 */
5553
5554 I915_WRITE(VIDSTART, vstart);
5555 POSTING_READ(VIDSTART);
5556
5557 rgvmodectl |= MEMMODE_SWMODE_EN;
5558 I915_WRITE(MEMMODECTL, rgvmodectl);
5559
5560 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5561 DRM_ERROR("stuck trying to change perf mode\n");
5562 msleep(1);
5563
5564 ironlake_set_drps(dev, fstart);
5565
5566 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5567 I915_READ(0x112e0);
5568 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5569 dev_priv->last_count2 = I915_READ(0x112f4);
5570 getrawmonotonic(&dev_priv->last_time2);
5571 }
5572
5573 void ironlake_disable_drps(struct drm_device *dev)
5574 {
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576 u16 rgvswctl = I915_READ16(MEMSWCTL);
5577
5578 /* Ack interrupts, disable EFC interrupt */
5579 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5580 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5581 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5582 I915_WRITE(DEIIR, DE_PCU_EVENT);
5583 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5584
5585 /* Go back to the starting frequency */
5586 ironlake_set_drps(dev, dev_priv->fstart);
5587 msleep(1);
5588 rgvswctl |= MEMCTL_CMD_STS;
5589 I915_WRITE(MEMSWCTL, rgvswctl);
5590 msleep(1);
5591
5592 }
5593
5594 static unsigned long intel_pxfreq(u32 vidfreq)
5595 {
5596 unsigned long freq;
5597 int div = (vidfreq & 0x3f0000) >> 16;
5598 int post = (vidfreq & 0x3000) >> 12;
5599 int pre = (vidfreq & 0x7);
5600
5601 if (!pre)
5602 return 0;
5603
5604 freq = ((div * 133333) / ((1<<post) * pre));
5605
5606 return freq;
5607 }
5608
5609 void intel_init_emon(struct drm_device *dev)
5610 {
5611 struct drm_i915_private *dev_priv = dev->dev_private;
5612 u32 lcfuse;
5613 u8 pxw[16];
5614 int i;
5615
5616 /* Disable to program */
5617 I915_WRITE(ECR, 0);
5618 POSTING_READ(ECR);
5619
5620 /* Program energy weights for various events */
5621 I915_WRITE(SDEW, 0x15040d00);
5622 I915_WRITE(CSIEW0, 0x007f0000);
5623 I915_WRITE(CSIEW1, 0x1e220004);
5624 I915_WRITE(CSIEW2, 0x04000004);
5625
5626 for (i = 0; i < 5; i++)
5627 I915_WRITE(PEW + (i * 4), 0);
5628 for (i = 0; i < 3; i++)
5629 I915_WRITE(DEW + (i * 4), 0);
5630
5631 /* Program P-state weights to account for frequency power adjustment */
5632 for (i = 0; i < 16; i++) {
5633 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5634 unsigned long freq = intel_pxfreq(pxvidfreq);
5635 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5636 PXVFREQ_PX_SHIFT;
5637 unsigned long val;
5638
5639 val = vid * vid;
5640 val *= (freq / 1000);
5641 val *= 255;
5642 val /= (127*127*900);
5643 if (val > 0xff)
5644 DRM_ERROR("bad pxval: %ld\n", val);
5645 pxw[i] = val;
5646 }
5647 /* Render standby states get 0 weight */
5648 pxw[14] = 0;
5649 pxw[15] = 0;
5650
5651 for (i = 0; i < 4; i++) {
5652 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5653 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5654 I915_WRITE(PXW + (i * 4), val);
5655 }
5656
5657 /* Adjust magic regs to magic values (more experimental results) */
5658 I915_WRITE(OGW0, 0);
5659 I915_WRITE(OGW1, 0);
5660 I915_WRITE(EG0, 0x00007f00);
5661 I915_WRITE(EG1, 0x0000000e);
5662 I915_WRITE(EG2, 0x000e0000);
5663 I915_WRITE(EG3, 0x68000300);
5664 I915_WRITE(EG4, 0x42000000);
5665 I915_WRITE(EG5, 0x00140031);
5666 I915_WRITE(EG6, 0);
5667 I915_WRITE(EG7, 0);
5668
5669 for (i = 0; i < 8; i++)
5670 I915_WRITE(PXWL + (i * 4), 0);
5671
5672 /* Enable PMON + select events */
5673 I915_WRITE(ECR, 0x80000019);
5674
5675 lcfuse = I915_READ(LCFUSE02);
5676
5677 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5678 }
5679
5680 void intel_init_clock_gating(struct drm_device *dev)
5681 {
5682 struct drm_i915_private *dev_priv = dev->dev_private;
5683
5684 /*
5685 * Disable clock gating reported to work incorrectly according to the
5686 * specs, but enable as much else as we can.
5687 */
5688 if (HAS_PCH_SPLIT(dev)) {
5689 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5690
5691 if (IS_IRONLAKE(dev)) {
5692 /* Required for FBC */
5693 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5694 /* Required for CxSR */
5695 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5696
5697 I915_WRITE(PCH_3DCGDIS0,
5698 MARIUNIT_CLOCK_GATE_DISABLE |
5699 SVSMUNIT_CLOCK_GATE_DISABLE);
5700 }
5701
5702 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5703
5704 /*
5705 * According to the spec the following bits should be set in
5706 * order to enable memory self-refresh
5707 * The bit 22/21 of 0x42004
5708 * The bit 5 of 0x42020
5709 * The bit 15 of 0x45000
5710 */
5711 if (IS_IRONLAKE(dev)) {
5712 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5713 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5714 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5715 I915_WRITE(ILK_DSPCLK_GATE,
5716 (I915_READ(ILK_DSPCLK_GATE) |
5717 ILK_DPARB_CLK_GATE));
5718 I915_WRITE(DISP_ARB_CTL,
5719 (I915_READ(DISP_ARB_CTL) |
5720 DISP_FBC_WM_DIS));
5721 I915_WRITE(WM3_LP_ILK, 0);
5722 I915_WRITE(WM2_LP_ILK, 0);
5723 I915_WRITE(WM1_LP_ILK, 0);
5724 }
5725 /*
5726 * Based on the document from hardware guys the following bits
5727 * should be set unconditionally in order to enable FBC.
5728 * The bit 22 of 0x42000
5729 * The bit 22 of 0x42004
5730 * The bit 7,8,9 of 0x42020.
5731 */
5732 if (IS_IRONLAKE_M(dev)) {
5733 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5734 I915_READ(ILK_DISPLAY_CHICKEN1) |
5735 ILK_FBCQ_DIS);
5736 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5737 I915_READ(ILK_DISPLAY_CHICKEN2) |
5738 ILK_DPARB_GATE);
5739 I915_WRITE(ILK_DSPCLK_GATE,
5740 I915_READ(ILK_DSPCLK_GATE) |
5741 ILK_DPFC_DIS1 |
5742 ILK_DPFC_DIS2 |
5743 ILK_CLK_FBC);
5744 }
5745 return;
5746 } else if (IS_G4X(dev)) {
5747 uint32_t dspclk_gate;
5748 I915_WRITE(RENCLK_GATE_D1, 0);
5749 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5750 GS_UNIT_CLOCK_GATE_DISABLE |
5751 CL_UNIT_CLOCK_GATE_DISABLE);
5752 I915_WRITE(RAMCLK_GATE_D, 0);
5753 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5754 OVRUNIT_CLOCK_GATE_DISABLE |
5755 OVCUNIT_CLOCK_GATE_DISABLE;
5756 if (IS_GM45(dev))
5757 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5758 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5759 } else if (IS_I965GM(dev)) {
5760 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5761 I915_WRITE(RENCLK_GATE_D2, 0);
5762 I915_WRITE(DSPCLK_GATE_D, 0);
5763 I915_WRITE(RAMCLK_GATE_D, 0);
5764 I915_WRITE16(DEUC, 0);
5765 } else if (IS_I965G(dev)) {
5766 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5767 I965_RCC_CLOCK_GATE_DISABLE |
5768 I965_RCPB_CLOCK_GATE_DISABLE |
5769 I965_ISC_CLOCK_GATE_DISABLE |
5770 I965_FBC_CLOCK_GATE_DISABLE);
5771 I915_WRITE(RENCLK_GATE_D2, 0);
5772 } else if (IS_I9XX(dev)) {
5773 u32 dstate = I915_READ(D_STATE);
5774
5775 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5776 DSTATE_DOT_CLOCK_GATING;
5777 I915_WRITE(D_STATE, dstate);
5778 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5779 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5780 } else if (IS_I830(dev)) {
5781 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5782 }
5783
5784 /*
5785 * GPU can automatically power down the render unit if given a page
5786 * to save state.
5787 */
5788 if (IS_IRONLAKE_M(dev)) {
5789 if (dev_priv->renderctx == NULL)
5790 dev_priv->renderctx = intel_alloc_context_page(dev);
5791 if (dev_priv->renderctx) {
5792 struct drm_i915_gem_object *obj_priv;
5793 obj_priv = to_intel_bo(dev_priv->renderctx);
5794 if (obj_priv) {
5795 BEGIN_LP_RING(4);
5796 OUT_RING(MI_SET_CONTEXT);
5797 OUT_RING(obj_priv->gtt_offset |
5798 MI_MM_SPACE_GTT |
5799 MI_SAVE_EXT_STATE_EN |
5800 MI_RESTORE_EXT_STATE_EN |
5801 MI_RESTORE_INHIBIT);
5802 OUT_RING(MI_NOOP);
5803 OUT_RING(MI_FLUSH);
5804 ADVANCE_LP_RING();
5805 }
5806 } else
5807 DRM_DEBUG_KMS("Failed to allocate render context."
5808 "Disable RC6\n");
5809 }
5810
5811 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5812 struct drm_i915_gem_object *obj_priv = NULL;
5813
5814 if (dev_priv->pwrctx) {
5815 obj_priv = to_intel_bo(dev_priv->pwrctx);
5816 } else {
5817 struct drm_gem_object *pwrctx;
5818
5819 pwrctx = intel_alloc_context_page(dev);
5820 if (pwrctx) {
5821 dev_priv->pwrctx = pwrctx;
5822 obj_priv = to_intel_bo(pwrctx);
5823 }
5824 }
5825
5826 if (obj_priv) {
5827 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5828 I915_WRITE(MCHBAR_RENDER_STANDBY,
5829 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5830 }
5831 }
5832 }
5833
5834 /* Set up chip specific display functions */
5835 static void intel_init_display(struct drm_device *dev)
5836 {
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838
5839 /* We always want a DPMS function */
5840 if (HAS_PCH_SPLIT(dev))
5841 dev_priv->display.dpms = ironlake_crtc_dpms;
5842 else
5843 dev_priv->display.dpms = i9xx_crtc_dpms;
5844
5845 if (I915_HAS_FBC(dev)) {
5846 if (IS_IRONLAKE_M(dev)) {
5847 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5848 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5849 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5850 } else if (IS_GM45(dev)) {
5851 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5852 dev_priv->display.enable_fbc = g4x_enable_fbc;
5853 dev_priv->display.disable_fbc = g4x_disable_fbc;
5854 } else if (IS_I965GM(dev)) {
5855 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5856 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5857 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5858 }
5859 /* 855GM needs testing */
5860 }
5861
5862 /* Returns the core display clock speed */
5863 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5864 dev_priv->display.get_display_clock_speed =
5865 i945_get_display_clock_speed;
5866 else if (IS_I915G(dev))
5867 dev_priv->display.get_display_clock_speed =
5868 i915_get_display_clock_speed;
5869 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5870 dev_priv->display.get_display_clock_speed =
5871 i9xx_misc_get_display_clock_speed;
5872 else if (IS_I915GM(dev))
5873 dev_priv->display.get_display_clock_speed =
5874 i915gm_get_display_clock_speed;
5875 else if (IS_I865G(dev))
5876 dev_priv->display.get_display_clock_speed =
5877 i865_get_display_clock_speed;
5878 else if (IS_I85X(dev))
5879 dev_priv->display.get_display_clock_speed =
5880 i855_get_display_clock_speed;
5881 else /* 852, 830 */
5882 dev_priv->display.get_display_clock_speed =
5883 i830_get_display_clock_speed;
5884
5885 /* For FIFO watermark updates */
5886 if (HAS_PCH_SPLIT(dev)) {
5887 if (IS_IRONLAKE(dev)) {
5888 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5889 dev_priv->display.update_wm = ironlake_update_wm;
5890 else {
5891 DRM_DEBUG_KMS("Failed to get proper latency. "
5892 "Disable CxSR\n");
5893 dev_priv->display.update_wm = NULL;
5894 }
5895 } else
5896 dev_priv->display.update_wm = NULL;
5897 } else if (IS_PINEVIEW(dev)) {
5898 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5899 dev_priv->is_ddr3,
5900 dev_priv->fsb_freq,
5901 dev_priv->mem_freq)) {
5902 DRM_INFO("failed to find known CxSR latency "
5903 "(found ddr%s fsb freq %d, mem freq %d), "
5904 "disabling CxSR\n",
5905 (dev_priv->is_ddr3 == 1) ? "3": "2",
5906 dev_priv->fsb_freq, dev_priv->mem_freq);
5907 /* Disable CxSR and never update its watermark again */
5908 pineview_disable_cxsr(dev);
5909 dev_priv->display.update_wm = NULL;
5910 } else
5911 dev_priv->display.update_wm = pineview_update_wm;
5912 } else if (IS_G4X(dev))
5913 dev_priv->display.update_wm = g4x_update_wm;
5914 else if (IS_I965G(dev))
5915 dev_priv->display.update_wm = i965_update_wm;
5916 else if (IS_I9XX(dev)) {
5917 dev_priv->display.update_wm = i9xx_update_wm;
5918 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5919 } else if (IS_I85X(dev)) {
5920 dev_priv->display.update_wm = i9xx_update_wm;
5921 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5922 } else {
5923 dev_priv->display.update_wm = i830_update_wm;
5924 if (IS_845G(dev))
5925 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5926 else
5927 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5928 }
5929 }
5930
5931 /*
5932 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5933 * resume, or other times. This quirk makes sure that's the case for
5934 * affected systems.
5935 */
5936 static void quirk_pipea_force (struct drm_device *dev)
5937 {
5938 struct drm_i915_private *dev_priv = dev->dev_private;
5939
5940 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5941 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5942 }
5943
5944 struct intel_quirk {
5945 int device;
5946 int subsystem_vendor;
5947 int subsystem_device;
5948 void (*hook)(struct drm_device *dev);
5949 };
5950
5951 struct intel_quirk intel_quirks[] = {
5952 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5953 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5954 /* HP Mini needs pipe A force quirk (LP: #322104) */
5955 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5956
5957 /* Thinkpad R31 needs pipe A force quirk */
5958 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5959 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5960 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5961
5962 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5963 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5964 /* ThinkPad X40 needs pipe A force quirk */
5965
5966 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5967 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5968
5969 /* 855 & before need to leave pipe A & dpll A up */
5970 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5971 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5972 };
5973
5974 static void intel_init_quirks(struct drm_device *dev)
5975 {
5976 struct pci_dev *d = dev->pdev;
5977 int i;
5978
5979 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5980 struct intel_quirk *q = &intel_quirks[i];
5981
5982 if (d->device == q->device &&
5983 (d->subsystem_vendor == q->subsystem_vendor ||
5984 q->subsystem_vendor == PCI_ANY_ID) &&
5985 (d->subsystem_device == q->subsystem_device ||
5986 q->subsystem_device == PCI_ANY_ID))
5987 q->hook(dev);
5988 }
5989 }
5990
5991 /* Disable the VGA plane that we never use */
5992 static void i915_disable_vga(struct drm_device *dev)
5993 {
5994 struct drm_i915_private *dev_priv = dev->dev_private;
5995 u8 sr1;
5996 u32 vga_reg;
5997
5998 if (HAS_PCH_SPLIT(dev))
5999 vga_reg = CPU_VGACNTRL;
6000 else
6001 vga_reg = VGACNTRL;
6002
6003 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6004 outb(1, VGA_SR_INDEX);
6005 sr1 = inb(VGA_SR_DATA);
6006 outb(sr1 | 1<<5, VGA_SR_DATA);
6007 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6008 udelay(300);
6009
6010 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6011 POSTING_READ(vga_reg);
6012 }
6013
6014 void intel_modeset_init(struct drm_device *dev)
6015 {
6016 struct drm_i915_private *dev_priv = dev->dev_private;
6017 int i;
6018
6019 drm_mode_config_init(dev);
6020
6021 dev->mode_config.min_width = 0;
6022 dev->mode_config.min_height = 0;
6023
6024 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6025
6026 intel_init_quirks(dev);
6027
6028 intel_init_display(dev);
6029
6030 if (IS_I965G(dev)) {
6031 dev->mode_config.max_width = 8192;
6032 dev->mode_config.max_height = 8192;
6033 } else if (IS_I9XX(dev)) {
6034 dev->mode_config.max_width = 4096;
6035 dev->mode_config.max_height = 4096;
6036 } else {
6037 dev->mode_config.max_width = 2048;
6038 dev->mode_config.max_height = 2048;
6039 }
6040
6041 /* set memory base */
6042 if (IS_I9XX(dev))
6043 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6044 else
6045 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6046
6047 if (IS_MOBILE(dev) || IS_I9XX(dev))
6048 dev_priv->num_pipe = 2;
6049 else
6050 dev_priv->num_pipe = 1;
6051 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6052 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6053
6054 for (i = 0; i < dev_priv->num_pipe; i++) {
6055 intel_crtc_init(dev, i);
6056 }
6057
6058 intel_setup_outputs(dev);
6059
6060 intel_init_clock_gating(dev);
6061
6062 /* Just disable it once at startup */
6063 i915_disable_vga(dev);
6064
6065 if (IS_IRONLAKE_M(dev)) {
6066 ironlake_enable_drps(dev);
6067 intel_init_emon(dev);
6068 }
6069
6070 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6071 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6072 (unsigned long)dev);
6073
6074 intel_setup_overlay(dev);
6075 }
6076
6077 void intel_modeset_cleanup(struct drm_device *dev)
6078 {
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080 struct drm_crtc *crtc;
6081 struct intel_crtc *intel_crtc;
6082
6083 mutex_lock(&dev->struct_mutex);
6084
6085 drm_kms_helper_poll_fini(dev);
6086 intel_fbdev_fini(dev);
6087
6088 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6089 /* Skip inactive CRTCs */
6090 if (!crtc->fb)
6091 continue;
6092
6093 intel_crtc = to_intel_crtc(crtc);
6094 intel_increase_pllclock(crtc);
6095 }
6096
6097 if (dev_priv->display.disable_fbc)
6098 dev_priv->display.disable_fbc(dev);
6099
6100 if (dev_priv->renderctx) {
6101 struct drm_i915_gem_object *obj_priv;
6102
6103 obj_priv = to_intel_bo(dev_priv->renderctx);
6104 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6105 I915_READ(CCID);
6106 i915_gem_object_unpin(dev_priv->renderctx);
6107 drm_gem_object_unreference(dev_priv->renderctx);
6108 }
6109
6110 if (dev_priv->pwrctx) {
6111 struct drm_i915_gem_object *obj_priv;
6112
6113 obj_priv = to_intel_bo(dev_priv->pwrctx);
6114 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6115 I915_READ(PWRCTXA);
6116 i915_gem_object_unpin(dev_priv->pwrctx);
6117 drm_gem_object_unreference(dev_priv->pwrctx);
6118 }
6119
6120 if (IS_IRONLAKE_M(dev))
6121 ironlake_disable_drps(dev);
6122
6123 mutex_unlock(&dev->struct_mutex);
6124
6125 /* Disable the irq before mode object teardown, for the irq might
6126 * enqueue unpin/hotplug work. */
6127 drm_irq_uninstall(dev);
6128 cancel_work_sync(&dev_priv->hotplug_work);
6129
6130 /* Shut off idle work before the crtcs get freed. */
6131 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6132 intel_crtc = to_intel_crtc(crtc);
6133 del_timer_sync(&intel_crtc->idle_timer);
6134 }
6135 del_timer_sync(&dev_priv->idle_timer);
6136 cancel_work_sync(&dev_priv->idle_work);
6137
6138 drm_mode_config_cleanup(dev);
6139 }
6140
6141 /*
6142 * Return which encoder is currently attached for connector.
6143 */
6144 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6145 {
6146 return &intel_attached_encoder(connector)->base;
6147 }
6148
6149 void intel_connector_attach_encoder(struct intel_connector *connector,
6150 struct intel_encoder *encoder)
6151 {
6152 connector->encoder = encoder;
6153 drm_mode_connector_attach_encoder(&connector->base,
6154 &encoder->base);
6155 }
6156
6157 /*
6158 * set vga decode state - true == enable VGA decode
6159 */
6160 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6161 {
6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163 u16 gmch_ctrl;
6164
6165 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6166 if (state)
6167 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6168 else
6169 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6170 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6171 return 0;
6172 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree