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drm: expand gamma_set
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob6bb5ffc76ced351406882420856b0ec1ff1564d3
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "drm_dp_helper.h"
38
39 #include "drm_crtc_helper.h"
40
41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42
43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
44 static void intel_update_watermarks(struct drm_device *dev);
45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *);
76 };
77
78 #define I8XX_DOT_MIN 25000
79 #define I8XX_DOT_MAX 350000
80 #define I8XX_VCO_MIN 930000
81 #define I8XX_VCO_MAX 1400000
82 #define I8XX_N_MIN 3
83 #define I8XX_N_MAX 16
84 #define I8XX_M_MIN 96
85 #define I8XX_M_MAX 140
86 #define I8XX_M1_MIN 18
87 #define I8XX_M1_MAX 26
88 #define I8XX_M2_MIN 6
89 #define I8XX_M2_MAX 16
90 #define I8XX_P_MIN 4
91 #define I8XX_P_MAX 128
92 #define I8XX_P1_MIN 2
93 #define I8XX_P1_MAX 33
94 #define I8XX_P1_LVDS_MIN 1
95 #define I8XX_P1_LVDS_MAX 6
96 #define I8XX_P2_SLOW 4
97 #define I8XX_P2_FAST 2
98 #define I8XX_P2_LVDS_SLOW 14
99 #define I8XX_P2_LVDS_FAST 7
100 #define I8XX_P2_SLOW_LIMIT 165000
101
102 #define I9XX_DOT_MIN 20000
103 #define I9XX_DOT_MAX 400000
104 #define I9XX_VCO_MIN 1400000
105 #define I9XX_VCO_MAX 2800000
106 #define PINEVIEW_VCO_MIN 1700000
107 #define PINEVIEW_VCO_MAX 3500000
108 #define I9XX_N_MIN 1
109 #define I9XX_N_MAX 6
110 /* Pineview's Ncounter is a ring counter */
111 #define PINEVIEW_N_MIN 3
112 #define PINEVIEW_N_MAX 6
113 #define I9XX_M_MIN 70
114 #define I9XX_M_MAX 120
115 #define PINEVIEW_M_MIN 2
116 #define PINEVIEW_M_MAX 256
117 #define I9XX_M1_MIN 10
118 #define I9XX_M1_MAX 22
119 #define I9XX_M2_MIN 5
120 #define I9XX_M2_MAX 9
121 /* Pineview M1 is reserved, and must be 0 */
122 #define PINEVIEW_M1_MIN 0
123 #define PINEVIEW_M1_MAX 0
124 #define PINEVIEW_M2_MIN 0
125 #define PINEVIEW_M2_MAX 254
126 #define I9XX_P_SDVO_DAC_MIN 5
127 #define I9XX_P_SDVO_DAC_MAX 80
128 #define I9XX_P_LVDS_MIN 7
129 #define I9XX_P_LVDS_MAX 98
130 #define PINEVIEW_P_LVDS_MIN 7
131 #define PINEVIEW_P_LVDS_MAX 112
132 #define I9XX_P1_MIN 1
133 #define I9XX_P1_MAX 8
134 #define I9XX_P2_SDVO_DAC_SLOW 10
135 #define I9XX_P2_SDVO_DAC_FAST 5
136 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
137 #define I9XX_P2_LVDS_SLOW 14
138 #define I9XX_P2_LVDS_FAST 7
139 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
140
141 /*The parameter is for SDVO on G4x platform*/
142 #define G4X_DOT_SDVO_MIN 25000
143 #define G4X_DOT_SDVO_MAX 270000
144 #define G4X_VCO_MIN 1750000
145 #define G4X_VCO_MAX 3500000
146 #define G4X_N_SDVO_MIN 1
147 #define G4X_N_SDVO_MAX 4
148 #define G4X_M_SDVO_MIN 104
149 #define G4X_M_SDVO_MAX 138
150 #define G4X_M1_SDVO_MIN 17
151 #define G4X_M1_SDVO_MAX 23
152 #define G4X_M2_SDVO_MIN 5
153 #define G4X_M2_SDVO_MAX 11
154 #define G4X_P_SDVO_MIN 10
155 #define G4X_P_SDVO_MAX 30
156 #define G4X_P1_SDVO_MIN 1
157 #define G4X_P1_SDVO_MAX 3
158 #define G4X_P2_SDVO_SLOW 10
159 #define G4X_P2_SDVO_FAST 10
160 #define G4X_P2_SDVO_LIMIT 270000
161
162 /*The parameter is for HDMI_DAC on G4x platform*/
163 #define G4X_DOT_HDMI_DAC_MIN 22000
164 #define G4X_DOT_HDMI_DAC_MAX 400000
165 #define G4X_N_HDMI_DAC_MIN 1
166 #define G4X_N_HDMI_DAC_MAX 4
167 #define G4X_M_HDMI_DAC_MIN 104
168 #define G4X_M_HDMI_DAC_MAX 138
169 #define G4X_M1_HDMI_DAC_MIN 16
170 #define G4X_M1_HDMI_DAC_MAX 23
171 #define G4X_M2_HDMI_DAC_MIN 5
172 #define G4X_M2_HDMI_DAC_MAX 11
173 #define G4X_P_HDMI_DAC_MIN 5
174 #define G4X_P_HDMI_DAC_MAX 80
175 #define G4X_P1_HDMI_DAC_MIN 1
176 #define G4X_P1_HDMI_DAC_MAX 8
177 #define G4X_P2_HDMI_DAC_SLOW 10
178 #define G4X_P2_HDMI_DAC_FAST 5
179 #define G4X_P2_HDMI_DAC_LIMIT 165000
180
181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
199
200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
218
219 /*The parameter is for DISPLAY PORT on G4x platform*/
220 #define G4X_DOT_DISPLAY_PORT_MIN 161670
221 #define G4X_DOT_DISPLAY_PORT_MAX 227000
222 #define G4X_N_DISPLAY_PORT_MIN 1
223 #define G4X_N_DISPLAY_PORT_MAX 2
224 #define G4X_M_DISPLAY_PORT_MIN 97
225 #define G4X_M_DISPLAY_PORT_MAX 108
226 #define G4X_M1_DISPLAY_PORT_MIN 0x10
227 #define G4X_M1_DISPLAY_PORT_MAX 0x12
228 #define G4X_M2_DISPLAY_PORT_MIN 0x05
229 #define G4X_M2_DISPLAY_PORT_MAX 0x06
230 #define G4X_P_DISPLAY_PORT_MIN 10
231 #define G4X_P_DISPLAY_PORT_MAX 20
232 #define G4X_P1_DISPLAY_PORT_MIN 1
233 #define G4X_P1_DISPLAY_PORT_MAX 2
234 #define G4X_P2_DISPLAY_PORT_SLOW 10
235 #define G4X_P2_DISPLAY_PORT_FAST 10
236 #define G4X_P2_DISPLAY_PORT_LIMIT 0
237
238 /* Ironlake / Sandybridge */
239 /* as we calculate clock using (register_value + 2) for
240 N/M1/M2, so here the range value for them is (actual_value-2).
241 */
242 #define IRONLAKE_DOT_MIN 25000
243 #define IRONLAKE_DOT_MAX 350000
244 #define IRONLAKE_VCO_MIN 1760000
245 #define IRONLAKE_VCO_MAX 3510000
246 #define IRONLAKE_M1_MIN 12
247 #define IRONLAKE_M1_MAX 22
248 #define IRONLAKE_M2_MIN 5
249 #define IRONLAKE_M2_MAX 9
250 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
251
252 /* We have parameter ranges for different type of outputs. */
253
254 /* DAC & HDMI Refclk 120Mhz */
255 #define IRONLAKE_DAC_N_MIN 1
256 #define IRONLAKE_DAC_N_MAX 5
257 #define IRONLAKE_DAC_M_MIN 79
258 #define IRONLAKE_DAC_M_MAX 127
259 #define IRONLAKE_DAC_P_MIN 5
260 #define IRONLAKE_DAC_P_MAX 80
261 #define IRONLAKE_DAC_P1_MIN 1
262 #define IRONLAKE_DAC_P1_MAX 8
263 #define IRONLAKE_DAC_P2_SLOW 10
264 #define IRONLAKE_DAC_P2_FAST 5
265
266 /* LVDS single-channel 120Mhz refclk */
267 #define IRONLAKE_LVDS_S_N_MIN 1
268 #define IRONLAKE_LVDS_S_N_MAX 3
269 #define IRONLAKE_LVDS_S_M_MIN 79
270 #define IRONLAKE_LVDS_S_M_MAX 118
271 #define IRONLAKE_LVDS_S_P_MIN 28
272 #define IRONLAKE_LVDS_S_P_MAX 112
273 #define IRONLAKE_LVDS_S_P1_MIN 2
274 #define IRONLAKE_LVDS_S_P1_MAX 8
275 #define IRONLAKE_LVDS_S_P2_SLOW 14
276 #define IRONLAKE_LVDS_S_P2_FAST 14
277
278 /* LVDS dual-channel 120Mhz refclk */
279 #define IRONLAKE_LVDS_D_N_MIN 1
280 #define IRONLAKE_LVDS_D_N_MAX 3
281 #define IRONLAKE_LVDS_D_M_MIN 79
282 #define IRONLAKE_LVDS_D_M_MAX 127
283 #define IRONLAKE_LVDS_D_P_MIN 14
284 #define IRONLAKE_LVDS_D_P_MAX 56
285 #define IRONLAKE_LVDS_D_P1_MIN 2
286 #define IRONLAKE_LVDS_D_P1_MAX 8
287 #define IRONLAKE_LVDS_D_P2_SLOW 7
288 #define IRONLAKE_LVDS_D_P2_FAST 7
289
290 /* LVDS single-channel 100Mhz refclk */
291 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
292 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
293 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
294 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
295 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
296 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
297 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
298 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
299 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
300 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
301
302 /* LVDS dual-channel 100Mhz refclk */
303 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
304 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
305 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
306 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
307 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
308 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
309 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
310 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
311 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
312 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
313
314 /* DisplayPort */
315 #define IRONLAKE_DP_N_MIN 1
316 #define IRONLAKE_DP_N_MAX 2
317 #define IRONLAKE_DP_M_MIN 81
318 #define IRONLAKE_DP_M_MAX 90
319 #define IRONLAKE_DP_P_MIN 10
320 #define IRONLAKE_DP_P_MAX 20
321 #define IRONLAKE_DP_P2_FAST 10
322 #define IRONLAKE_DP_P2_SLOW 10
323 #define IRONLAKE_DP_P2_LIMIT 0
324 #define IRONLAKE_DP_P1_MIN 1
325 #define IRONLAKE_DP_P1_MAX 2
326
327 /* FDI */
328 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
329
330 static bool
331 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
332 int target, int refclk, intel_clock_t *best_clock);
333 static bool
334 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
335 int target, int refclk, intel_clock_t *best_clock);
336
337 static bool
338 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
339 int target, int refclk, intel_clock_t *best_clock);
340 static bool
341 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
342 int target, int refclk, intel_clock_t *best_clock);
343
344 static const intel_limit_t intel_limits_i8xx_dvo = {
345 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
346 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
347 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
348 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
349 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
350 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
351 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
352 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
353 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
354 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
355 .find_pll = intel_find_best_PLL,
356 };
357
358 static const intel_limit_t intel_limits_i8xx_lvds = {
359 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
360 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
361 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
362 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
363 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
364 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
365 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
366 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
367 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
368 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
369 .find_pll = intel_find_best_PLL,
370 };
371
372 static const intel_limit_t intel_limits_i9xx_sdvo = {
373 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
374 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
375 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
376 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
377 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
378 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
379 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
380 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
381 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
382 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
383 .find_pll = intel_find_best_PLL,
384 };
385
386 static const intel_limit_t intel_limits_i9xx_lvds = {
387 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
388 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
389 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
390 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
391 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
392 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
393 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
394 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
395 /* The single-channel range is 25-112Mhz, and dual-channel
396 * is 80-224Mhz. Prefer single channel as much as possible.
397 */
398 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
399 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
400 .find_pll = intel_find_best_PLL,
401 };
402
403 /* below parameter and function is for G4X Chipset Family*/
404 static const intel_limit_t intel_limits_g4x_sdvo = {
405 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
406 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
407 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
408 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
409 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
410 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
411 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
412 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
413 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
414 .p2_slow = G4X_P2_SDVO_SLOW,
415 .p2_fast = G4X_P2_SDVO_FAST
416 },
417 .find_pll = intel_g4x_find_best_PLL,
418 };
419
420 static const intel_limit_t intel_limits_g4x_hdmi = {
421 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
422 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
423 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
424 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
425 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
426 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
427 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
428 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
429 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
430 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
431 .p2_fast = G4X_P2_HDMI_DAC_FAST
432 },
433 .find_pll = intel_g4x_find_best_PLL,
434 };
435
436 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
437 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
438 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
439 .vco = { .min = G4X_VCO_MIN,
440 .max = G4X_VCO_MAX },
441 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
442 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
443 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
444 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
445 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
447 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
448 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
449 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
450 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
451 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
452 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
453 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
454 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
455 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
456 },
457 .find_pll = intel_g4x_find_best_PLL,
458 };
459
460 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
461 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
462 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
463 .vco = { .min = G4X_VCO_MIN,
464 .max = G4X_VCO_MAX },
465 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
466 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
467 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
468 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
469 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
471 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
472 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
473 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
474 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
475 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
476 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
477 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
478 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
479 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
480 },
481 .find_pll = intel_g4x_find_best_PLL,
482 };
483
484 static const intel_limit_t intel_limits_g4x_display_port = {
485 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
486 .max = G4X_DOT_DISPLAY_PORT_MAX },
487 .vco = { .min = G4X_VCO_MIN,
488 .max = G4X_VCO_MAX},
489 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
490 .max = G4X_N_DISPLAY_PORT_MAX },
491 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
492 .max = G4X_M_DISPLAY_PORT_MAX },
493 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
494 .max = G4X_M1_DISPLAY_PORT_MAX },
495 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
496 .max = G4X_M2_DISPLAY_PORT_MAX },
497 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
498 .max = G4X_P_DISPLAY_PORT_MAX },
499 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
500 .max = G4X_P1_DISPLAY_PORT_MAX},
501 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
502 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
503 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
504 .find_pll = intel_find_pll_g4x_dp,
505 };
506
507 static const intel_limit_t intel_limits_pineview_sdvo = {
508 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
509 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
510 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
511 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
512 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
513 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
514 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
515 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
516 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
517 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
518 .find_pll = intel_find_best_PLL,
519 };
520
521 static const intel_limit_t intel_limits_pineview_lvds = {
522 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
523 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
524 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
525 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
526 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
527 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
528 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
529 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
530 /* Pineview only supports single-channel mode. */
531 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
532 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
533 .find_pll = intel_find_best_PLL,
534 };
535
536 static const intel_limit_t intel_limits_ironlake_dac = {
537 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
538 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
539 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
540 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
541 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
542 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
543 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
544 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
545 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
546 .p2_slow = IRONLAKE_DAC_P2_SLOW,
547 .p2_fast = IRONLAKE_DAC_P2_FAST },
548 .find_pll = intel_g4x_find_best_PLL,
549 };
550
551 static const intel_limit_t intel_limits_ironlake_single_lvds = {
552 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
553 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
554 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
555 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
556 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
557 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
558 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
559 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
560 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
561 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
562 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
563 .find_pll = intel_g4x_find_best_PLL,
564 };
565
566 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
567 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
568 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
569 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
570 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
571 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
572 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
573 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
574 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
575 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
576 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
577 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
578 .find_pll = intel_g4x_find_best_PLL,
579 };
580
581 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
582 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
583 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
584 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
585 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
586 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
587 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
588 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
589 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
590 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
591 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
592 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
593 .find_pll = intel_g4x_find_best_PLL,
594 };
595
596 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
597 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
598 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
599 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
600 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
601 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
602 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
603 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
604 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
605 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
606 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
607 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
608 .find_pll = intel_g4x_find_best_PLL,
609 };
610
611 static const intel_limit_t intel_limits_ironlake_display_port = {
612 .dot = { .min = IRONLAKE_DOT_MIN,
613 .max = IRONLAKE_DOT_MAX },
614 .vco = { .min = IRONLAKE_VCO_MIN,
615 .max = IRONLAKE_VCO_MAX},
616 .n = { .min = IRONLAKE_DP_N_MIN,
617 .max = IRONLAKE_DP_N_MAX },
618 .m = { .min = IRONLAKE_DP_M_MIN,
619 .max = IRONLAKE_DP_M_MAX },
620 .m1 = { .min = IRONLAKE_M1_MIN,
621 .max = IRONLAKE_M1_MAX },
622 .m2 = { .min = IRONLAKE_M2_MIN,
623 .max = IRONLAKE_M2_MAX },
624 .p = { .min = IRONLAKE_DP_P_MIN,
625 .max = IRONLAKE_DP_P_MAX },
626 .p1 = { .min = IRONLAKE_DP_P1_MIN,
627 .max = IRONLAKE_DP_P1_MAX},
628 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
629 .p2_slow = IRONLAKE_DP_P2_SLOW,
630 .p2_fast = IRONLAKE_DP_P2_FAST },
631 .find_pll = intel_find_pll_ironlake_dp,
632 };
633
634 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
635 {
636 struct drm_device *dev = crtc->dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 const intel_limit_t *limit;
639 int refclk = 120;
640
641 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
642 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
643 refclk = 100;
644
645 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
646 LVDS_CLKB_POWER_UP) {
647 /* LVDS dual channel */
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_dual_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_dual_lvds;
652 } else {
653 if (refclk == 100)
654 limit = &intel_limits_ironlake_single_lvds_100m;
655 else
656 limit = &intel_limits_ironlake_single_lvds;
657 }
658 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
659 HAS_eDP)
660 limit = &intel_limits_ironlake_display_port;
661 else
662 limit = &intel_limits_ironlake_dac;
663
664 return limit;
665 }
666
667 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
668 {
669 struct drm_device *dev = crtc->dev;
670 struct drm_i915_private *dev_priv = dev->dev_private;
671 const intel_limit_t *limit;
672
673 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
674 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
675 LVDS_CLKB_POWER_UP)
676 /* LVDS with dual channel */
677 limit = &intel_limits_g4x_dual_channel_lvds;
678 else
679 /* LVDS with dual channel */
680 limit = &intel_limits_g4x_single_channel_lvds;
681 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
682 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
683 limit = &intel_limits_g4x_hdmi;
684 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
685 limit = &intel_limits_g4x_sdvo;
686 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
687 limit = &intel_limits_g4x_display_port;
688 } else /* The option is for other outputs */
689 limit = &intel_limits_i9xx_sdvo;
690
691 return limit;
692 }
693
694 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
695 {
696 struct drm_device *dev = crtc->dev;
697 const intel_limit_t *limit;
698
699 if (HAS_PCH_SPLIT(dev))
700 limit = intel_ironlake_limit(crtc);
701 else if (IS_G4X(dev)) {
702 limit = intel_g4x_limit(crtc);
703 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705 limit = &intel_limits_i9xx_lvds;
706 else
707 limit = &intel_limits_i9xx_sdvo;
708 } else if (IS_PINEVIEW(dev)) {
709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710 limit = &intel_limits_pineview_lvds;
711 else
712 limit = &intel_limits_pineview_sdvo;
713 } else {
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
715 limit = &intel_limits_i8xx_lvds;
716 else
717 limit = &intel_limits_i8xx_dvo;
718 }
719 return limit;
720 }
721
722 /* m1 is reserved as 0 in Pineview, n is a ring counter */
723 static void pineview_clock(int refclk, intel_clock_t *clock)
724 {
725 clock->m = clock->m2 + 2;
726 clock->p = clock->p1 * clock->p2;
727 clock->vco = refclk * clock->m / clock->n;
728 clock->dot = clock->vco / clock->p;
729 }
730
731 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
732 {
733 if (IS_PINEVIEW(dev)) {
734 pineview_clock(refclk, clock);
735 return;
736 }
737 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
738 clock->p = clock->p1 * clock->p2;
739 clock->vco = refclk * clock->m / (clock->n + 2);
740 clock->dot = clock->vco / clock->p;
741 }
742
743 /**
744 * Returns whether any output on the specified pipe is of the specified type
745 */
746 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
747 {
748 struct drm_device *dev = crtc->dev;
749 struct drm_mode_config *mode_config = &dev->mode_config;
750 struct drm_encoder *l_entry;
751
752 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
753 if (l_entry && l_entry->crtc == crtc) {
754 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
755 if (intel_encoder->type == type)
756 return true;
757 }
758 }
759 return false;
760 }
761
762 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
763 /**
764 * Returns whether the given set of divisors are valid for a given refclk with
765 * the given connectors.
766 */
767
768 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
769 {
770 const intel_limit_t *limit = intel_limit (crtc);
771 struct drm_device *dev = crtc->dev;
772
773 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
774 INTELPllInvalid ("p1 out of range\n");
775 if (clock->p < limit->p.min || limit->p.max < clock->p)
776 INTELPllInvalid ("p out of range\n");
777 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
778 INTELPllInvalid ("m2 out of range\n");
779 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
780 INTELPllInvalid ("m1 out of range\n");
781 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
782 INTELPllInvalid ("m1 <= m2\n");
783 if (clock->m < limit->m.min || limit->m.max < clock->m)
784 INTELPllInvalid ("m out of range\n");
785 if (clock->n < limit->n.min || limit->n.max < clock->n)
786 INTELPllInvalid ("n out of range\n");
787 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
788 INTELPllInvalid ("vco out of range\n");
789 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
790 * connector, etc., rather than just a single range.
791 */
792 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
793 INTELPllInvalid ("dot out of range\n");
794
795 return true;
796 }
797
798 static bool
799 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
800 int target, int refclk, intel_clock_t *best_clock)
801
802 {
803 struct drm_device *dev = crtc->dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 intel_clock_t clock;
806 int err = target;
807
808 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
809 (I915_READ(LVDS)) != 0) {
810 /*
811 * For LVDS, if the panel is on, just rely on its current
812 * settings for dual-channel. We haven't figured out how to
813 * reliably set up different single/dual channel state, if we
814 * even can.
815 */
816 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
817 LVDS_CLKB_POWER_UP)
818 clock.p2 = limit->p2.p2_fast;
819 else
820 clock.p2 = limit->p2.p2_slow;
821 } else {
822 if (target < limit->p2.dot_limit)
823 clock.p2 = limit->p2.p2_slow;
824 else
825 clock.p2 = limit->p2.p2_fast;
826 }
827
828 memset (best_clock, 0, sizeof (*best_clock));
829
830 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
831 clock.m1++) {
832 for (clock.m2 = limit->m2.min;
833 clock.m2 <= limit->m2.max; clock.m2++) {
834 /* m1 is always 0 in Pineview */
835 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
836 break;
837 for (clock.n = limit->n.min;
838 clock.n <= limit->n.max; clock.n++) {
839 for (clock.p1 = limit->p1.min;
840 clock.p1 <= limit->p1.max; clock.p1++) {
841 int this_err;
842
843 intel_clock(dev, refclk, &clock);
844
845 if (!intel_PLL_is_valid(crtc, &clock))
846 continue;
847
848 this_err = abs(clock.dot - target);
849 if (this_err < err) {
850 *best_clock = clock;
851 err = this_err;
852 }
853 }
854 }
855 }
856 }
857
858 return (err != target);
859 }
860
861 static bool
862 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *best_clock)
864 {
865 struct drm_device *dev = crtc->dev;
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 intel_clock_t clock;
868 int max_n;
869 bool found;
870 /* approximately equals target * 0.00585 */
871 int err_most = (target >> 8) + (target >> 9);
872 found = false;
873
874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
875 int lvds_reg;
876
877 if (HAS_PCH_SPLIT(dev))
878 lvds_reg = PCH_LVDS;
879 else
880 lvds_reg = LVDS;
881 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
882 LVDS_CLKB_POWER_UP)
883 clock.p2 = limit->p2.p2_fast;
884 else
885 clock.p2 = limit->p2.p2_slow;
886 } else {
887 if (target < limit->p2.dot_limit)
888 clock.p2 = limit->p2.p2_slow;
889 else
890 clock.p2 = limit->p2.p2_fast;
891 }
892
893 memset(best_clock, 0, sizeof(*best_clock));
894 max_n = limit->n.max;
895 /* based on hardware requirement, prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
897 /* based on hardware requirement, prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) {
900 for (clock.m2 = limit->m2.max;
901 clock.m2 >= limit->m2.min; clock.m2--) {
902 for (clock.p1 = limit->p1.max;
903 clock.p1 >= limit->p1.min; clock.p1--) {
904 int this_err;
905
906 intel_clock(dev, refclk, &clock);
907 if (!intel_PLL_is_valid(crtc, &clock))
908 continue;
909 this_err = abs(clock.dot - target) ;
910 if (this_err < err_most) {
911 *best_clock = clock;
912 err_most = this_err;
913 max_n = clock.n;
914 found = true;
915 }
916 }
917 }
918 }
919 }
920 return found;
921 }
922
923 static bool
924 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
925 int target, int refclk, intel_clock_t *best_clock)
926 {
927 struct drm_device *dev = crtc->dev;
928 intel_clock_t clock;
929
930 /* return directly when it is eDP */
931 if (HAS_eDP)
932 return true;
933
934 if (target < 200000) {
935 clock.n = 1;
936 clock.p1 = 2;
937 clock.p2 = 10;
938 clock.m1 = 12;
939 clock.m2 = 9;
940 } else {
941 clock.n = 2;
942 clock.p1 = 1;
943 clock.p2 = 10;
944 clock.m1 = 14;
945 clock.m2 = 8;
946 }
947 intel_clock(dev, refclk, &clock);
948 memcpy(best_clock, &clock, sizeof(intel_clock_t));
949 return true;
950 }
951
952 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
953 static bool
954 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
955 int target, int refclk, intel_clock_t *best_clock)
956 {
957 intel_clock_t clock;
958 if (target < 200000) {
959 clock.p1 = 2;
960 clock.p2 = 10;
961 clock.n = 2;
962 clock.m1 = 23;
963 clock.m2 = 8;
964 } else {
965 clock.p1 = 1;
966 clock.p2 = 10;
967 clock.n = 1;
968 clock.m1 = 14;
969 clock.m2 = 2;
970 }
971 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
972 clock.p = (clock.p1 * clock.p2);
973 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
974 clock.vco = 0;
975 memcpy(best_clock, &clock, sizeof(intel_clock_t));
976 return true;
977 }
978
979 void
980 intel_wait_for_vblank(struct drm_device *dev)
981 {
982 /* Wait for 20ms, i.e. one cycle at 50hz. */
983 msleep(20);
984 }
985
986 /* Parameters have changed, update FBC info */
987 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
988 {
989 struct drm_device *dev = crtc->dev;
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 struct drm_framebuffer *fb = crtc->fb;
992 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
993 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
995 int plane, i;
996 u32 fbc_ctl, fbc_ctl2;
997
998 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
999
1000 if (fb->pitch < dev_priv->cfb_pitch)
1001 dev_priv->cfb_pitch = fb->pitch;
1002
1003 /* FBC_CTL wants 64B units */
1004 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1005 dev_priv->cfb_fence = obj_priv->fence_reg;
1006 dev_priv->cfb_plane = intel_crtc->plane;
1007 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1008
1009 /* Clear old tags */
1010 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1011 I915_WRITE(FBC_TAG + (i * 4), 0);
1012
1013 /* Set it up... */
1014 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1015 if (obj_priv->tiling_mode != I915_TILING_NONE)
1016 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1017 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1018 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1019
1020 /* enable it... */
1021 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1022 if (IS_I945GM(dev))
1023 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1024 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1025 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1026 if (obj_priv->tiling_mode != I915_TILING_NONE)
1027 fbc_ctl |= dev_priv->cfb_fence;
1028 I915_WRITE(FBC_CONTROL, fbc_ctl);
1029
1030 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1031 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1032 }
1033
1034 void i8xx_disable_fbc(struct drm_device *dev)
1035 {
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1038 u32 fbc_ctl;
1039
1040 if (!I915_HAS_FBC(dev))
1041 return;
1042
1043 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1044 return; /* Already off, just return */
1045
1046 /* Disable compression */
1047 fbc_ctl = I915_READ(FBC_CONTROL);
1048 fbc_ctl &= ~FBC_CTL_EN;
1049 I915_WRITE(FBC_CONTROL, fbc_ctl);
1050
1051 /* Wait for compressing bit to clear */
1052 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1053 if (time_after(jiffies, timeout)) {
1054 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1055 break;
1056 }
1057 ; /* do nothing */
1058 }
1059
1060 intel_wait_for_vblank(dev);
1061
1062 DRM_DEBUG_KMS("disabled FBC\n");
1063 }
1064
1065 static bool i8xx_fbc_enabled(struct drm_device *dev)
1066 {
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1068
1069 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1070 }
1071
1072 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1073 {
1074 struct drm_device *dev = crtc->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 struct drm_framebuffer *fb = crtc->fb;
1077 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1078 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1080 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1081 DPFC_CTL_PLANEB);
1082 unsigned long stall_watermark = 200;
1083 u32 dpfc_ctl;
1084
1085 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1086 dev_priv->cfb_fence = obj_priv->fence_reg;
1087 dev_priv->cfb_plane = intel_crtc->plane;
1088
1089 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1090 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1091 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1092 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1093 } else {
1094 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1095 }
1096
1097 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1098 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1099 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1100 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1101 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1102
1103 /* enable it... */
1104 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1105
1106 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1107 }
1108
1109 void g4x_disable_fbc(struct drm_device *dev)
1110 {
1111 struct drm_i915_private *dev_priv = dev->dev_private;
1112 u32 dpfc_ctl;
1113
1114 /* Disable compression */
1115 dpfc_ctl = I915_READ(DPFC_CONTROL);
1116 dpfc_ctl &= ~DPFC_CTL_EN;
1117 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1118 intel_wait_for_vblank(dev);
1119
1120 DRM_DEBUG_KMS("disabled FBC\n");
1121 }
1122
1123 static bool g4x_fbc_enabled(struct drm_device *dev)
1124 {
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126
1127 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1128 }
1129
1130 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1131 {
1132 struct drm_device *dev = crtc->dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 struct drm_framebuffer *fb = crtc->fb;
1135 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1136 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1138 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1139 DPFC_CTL_PLANEB;
1140 unsigned long stall_watermark = 200;
1141 u32 dpfc_ctl;
1142
1143 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1144 dev_priv->cfb_fence = obj_priv->fence_reg;
1145 dev_priv->cfb_plane = intel_crtc->plane;
1146
1147 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1148 dpfc_ctl &= DPFC_RESERVED;
1149 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1150 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1151 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1152 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1153 } else {
1154 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1155 }
1156
1157 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1158 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1159 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1160 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1161 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1162 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1163 /* enable it... */
1164 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1165 DPFC_CTL_EN);
1166
1167 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1168 }
1169
1170 void ironlake_disable_fbc(struct drm_device *dev)
1171 {
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 dpfc_ctl;
1174
1175 /* Disable compression */
1176 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1177 dpfc_ctl &= ~DPFC_CTL_EN;
1178 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1179 intel_wait_for_vblank(dev);
1180
1181 DRM_DEBUG_KMS("disabled FBC\n");
1182 }
1183
1184 static bool ironlake_fbc_enabled(struct drm_device *dev)
1185 {
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187
1188 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1189 }
1190
1191 bool intel_fbc_enabled(struct drm_device *dev)
1192 {
1193 struct drm_i915_private *dev_priv = dev->dev_private;
1194
1195 if (!dev_priv->display.fbc_enabled)
1196 return false;
1197
1198 return dev_priv->display.fbc_enabled(dev);
1199 }
1200
1201 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1202 {
1203 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1204
1205 if (!dev_priv->display.enable_fbc)
1206 return;
1207
1208 dev_priv->display.enable_fbc(crtc, interval);
1209 }
1210
1211 void intel_disable_fbc(struct drm_device *dev)
1212 {
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215 if (!dev_priv->display.disable_fbc)
1216 return;
1217
1218 dev_priv->display.disable_fbc(dev);
1219 }
1220
1221 /**
1222 * intel_update_fbc - enable/disable FBC as needed
1223 * @crtc: CRTC to point the compressor at
1224 * @mode: mode in use
1225 *
1226 * Set up the framebuffer compression hardware at mode set time. We
1227 * enable it if possible:
1228 * - plane A only (on pre-965)
1229 * - no pixel mulitply/line duplication
1230 * - no alpha buffer discard
1231 * - no dual wide
1232 * - framebuffer <= 2048 in width, 1536 in height
1233 *
1234 * We can't assume that any compression will take place (worst case),
1235 * so the compressed buffer has to be the same size as the uncompressed
1236 * one. It also must reside (along with the line length buffer) in
1237 * stolen memory.
1238 *
1239 * We need to enable/disable FBC on a global basis.
1240 */
1241 static void intel_update_fbc(struct drm_crtc *crtc,
1242 struct drm_display_mode *mode)
1243 {
1244 struct drm_device *dev = crtc->dev;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 struct drm_framebuffer *fb = crtc->fb;
1247 struct intel_framebuffer *intel_fb;
1248 struct drm_i915_gem_object *obj_priv;
1249 struct drm_crtc *tmp_crtc;
1250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1251 int plane = intel_crtc->plane;
1252 int crtcs_enabled = 0;
1253
1254 DRM_DEBUG_KMS("\n");
1255
1256 if (!i915_powersave)
1257 return;
1258
1259 if (!I915_HAS_FBC(dev))
1260 return;
1261
1262 if (!crtc->fb)
1263 return;
1264
1265 intel_fb = to_intel_framebuffer(fb);
1266 obj_priv = to_intel_bo(intel_fb->obj);
1267
1268 /*
1269 * If FBC is already on, we just have to verify that we can
1270 * keep it that way...
1271 * Need to disable if:
1272 * - more than one pipe is active
1273 * - changing FBC params (stride, fence, mode)
1274 * - new fb is too large to fit in compressed buffer
1275 * - going to an unsupported config (interlace, pixel multiply, etc.)
1276 */
1277 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1278 if (tmp_crtc->enabled)
1279 crtcs_enabled++;
1280 }
1281 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1282 if (crtcs_enabled > 1) {
1283 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1284 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1285 goto out_disable;
1286 }
1287 if (intel_fb->obj->size > dev_priv->cfb_size) {
1288 DRM_DEBUG_KMS("framebuffer too large, disabling "
1289 "compression\n");
1290 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1291 goto out_disable;
1292 }
1293 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1294 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1295 DRM_DEBUG_KMS("mode incompatible with compression, "
1296 "disabling\n");
1297 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1298 goto out_disable;
1299 }
1300 if ((mode->hdisplay > 2048) ||
1301 (mode->vdisplay > 1536)) {
1302 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1303 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1304 goto out_disable;
1305 }
1306 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1307 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1308 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1309 goto out_disable;
1310 }
1311 if (obj_priv->tiling_mode != I915_TILING_X) {
1312 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1313 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1314 goto out_disable;
1315 }
1316
1317 if (intel_fbc_enabled(dev)) {
1318 /* We can re-enable it in this case, but need to update pitch */
1319 if ((fb->pitch > dev_priv->cfb_pitch) ||
1320 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1321 (plane != dev_priv->cfb_plane))
1322 intel_disable_fbc(dev);
1323 }
1324
1325 /* Now try to turn it back on if possible */
1326 if (!intel_fbc_enabled(dev))
1327 intel_enable_fbc(crtc, 500);
1328
1329 return;
1330
1331 out_disable:
1332 /* Multiple disables should be harmless */
1333 if (intel_fbc_enabled(dev)) {
1334 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1335 intel_disable_fbc(dev);
1336 }
1337 }
1338
1339 int
1340 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1341 {
1342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1343 u32 alignment;
1344 int ret;
1345
1346 switch (obj_priv->tiling_mode) {
1347 case I915_TILING_NONE:
1348 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1349 alignment = 128 * 1024;
1350 else if (IS_I965G(dev))
1351 alignment = 4 * 1024;
1352 else
1353 alignment = 64 * 1024;
1354 break;
1355 case I915_TILING_X:
1356 /* pin() will align the object as required by fence */
1357 alignment = 0;
1358 break;
1359 case I915_TILING_Y:
1360 /* FIXME: Is this true? */
1361 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1362 return -EINVAL;
1363 default:
1364 BUG();
1365 }
1366
1367 ret = i915_gem_object_pin(obj, alignment);
1368 if (ret != 0)
1369 return ret;
1370
1371 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1372 * fence, whereas 965+ only requires a fence if using
1373 * framebuffer compression. For simplicity, we always install
1374 * a fence as the cost is not that onerous.
1375 */
1376 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1377 obj_priv->tiling_mode != I915_TILING_NONE) {
1378 ret = i915_gem_object_get_fence_reg(obj);
1379 if (ret != 0) {
1380 i915_gem_object_unpin(obj);
1381 return ret;
1382 }
1383 }
1384
1385 return 0;
1386 }
1387
1388 static int
1389 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1390 struct drm_framebuffer *old_fb)
1391 {
1392 struct drm_device *dev = crtc->dev;
1393 struct drm_i915_private *dev_priv = dev->dev_private;
1394 struct drm_i915_master_private *master_priv;
1395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1396 struct intel_framebuffer *intel_fb;
1397 struct drm_i915_gem_object *obj_priv;
1398 struct drm_gem_object *obj;
1399 int pipe = intel_crtc->pipe;
1400 int plane = intel_crtc->plane;
1401 unsigned long Start, Offset;
1402 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1403 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1404 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1405 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1406 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1407 u32 dspcntr;
1408 int ret;
1409
1410 /* no fb bound */
1411 if (!crtc->fb) {
1412 DRM_DEBUG_KMS("No FB bound\n");
1413 return 0;
1414 }
1415
1416 switch (plane) {
1417 case 0:
1418 case 1:
1419 break;
1420 default:
1421 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1422 return -EINVAL;
1423 }
1424
1425 intel_fb = to_intel_framebuffer(crtc->fb);
1426 obj = intel_fb->obj;
1427 obj_priv = to_intel_bo(obj);
1428
1429 mutex_lock(&dev->struct_mutex);
1430 ret = intel_pin_and_fence_fb_obj(dev, obj);
1431 if (ret != 0) {
1432 mutex_unlock(&dev->struct_mutex);
1433 return ret;
1434 }
1435
1436 ret = i915_gem_object_set_to_display_plane(obj);
1437 if (ret != 0) {
1438 i915_gem_object_unpin(obj);
1439 mutex_unlock(&dev->struct_mutex);
1440 return ret;
1441 }
1442
1443 dspcntr = I915_READ(dspcntr_reg);
1444 /* Mask out pixel format bits in case we change it */
1445 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1446 switch (crtc->fb->bits_per_pixel) {
1447 case 8:
1448 dspcntr |= DISPPLANE_8BPP;
1449 break;
1450 case 16:
1451 if (crtc->fb->depth == 15)
1452 dspcntr |= DISPPLANE_15_16BPP;
1453 else
1454 dspcntr |= DISPPLANE_16BPP;
1455 break;
1456 case 24:
1457 case 32:
1458 if (crtc->fb->depth == 30)
1459 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1460 else
1461 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1462 break;
1463 default:
1464 DRM_ERROR("Unknown color depth\n");
1465 i915_gem_object_unpin(obj);
1466 mutex_unlock(&dev->struct_mutex);
1467 return -EINVAL;
1468 }
1469 if (IS_I965G(dev)) {
1470 if (obj_priv->tiling_mode != I915_TILING_NONE)
1471 dspcntr |= DISPPLANE_TILED;
1472 else
1473 dspcntr &= ~DISPPLANE_TILED;
1474 }
1475
1476 if (HAS_PCH_SPLIT(dev))
1477 /* must disable */
1478 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1479
1480 I915_WRITE(dspcntr_reg, dspcntr);
1481
1482 Start = obj_priv->gtt_offset;
1483 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1484
1485 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1486 Start, Offset, x, y, crtc->fb->pitch);
1487 I915_WRITE(dspstride, crtc->fb->pitch);
1488 if (IS_I965G(dev)) {
1489 I915_WRITE(dspbase, Offset);
1490 I915_READ(dspbase);
1491 I915_WRITE(dspsurf, Start);
1492 I915_READ(dspsurf);
1493 I915_WRITE(dsptileoff, (y << 16) | x);
1494 } else {
1495 I915_WRITE(dspbase, Start + Offset);
1496 I915_READ(dspbase);
1497 }
1498
1499 if ((IS_I965G(dev) || plane == 0))
1500 intel_update_fbc(crtc, &crtc->mode);
1501
1502 intel_wait_for_vblank(dev);
1503
1504 if (old_fb) {
1505 intel_fb = to_intel_framebuffer(old_fb);
1506 obj_priv = to_intel_bo(intel_fb->obj);
1507 i915_gem_object_unpin(intel_fb->obj);
1508 }
1509 intel_increase_pllclock(crtc, true);
1510
1511 mutex_unlock(&dev->struct_mutex);
1512
1513 if (!dev->primary->master)
1514 return 0;
1515
1516 master_priv = dev->primary->master->driver_priv;
1517 if (!master_priv->sarea_priv)
1518 return 0;
1519
1520 if (pipe) {
1521 master_priv->sarea_priv->pipeB_x = x;
1522 master_priv->sarea_priv->pipeB_y = y;
1523 } else {
1524 master_priv->sarea_priv->pipeA_x = x;
1525 master_priv->sarea_priv->pipeA_y = y;
1526 }
1527
1528 return 0;
1529 }
1530
1531 /* Disable the VGA plane that we never use */
1532 static void i915_disable_vga (struct drm_device *dev)
1533 {
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 u8 sr1;
1536 u32 vga_reg;
1537
1538 if (HAS_PCH_SPLIT(dev))
1539 vga_reg = CPU_VGACNTRL;
1540 else
1541 vga_reg = VGACNTRL;
1542
1543 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1544 return;
1545
1546 I915_WRITE8(VGA_SR_INDEX, 1);
1547 sr1 = I915_READ8(VGA_SR_DATA);
1548 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1549 udelay(100);
1550
1551 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1552 }
1553
1554 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1555 {
1556 struct drm_device *dev = crtc->dev;
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 u32 dpa_ctl;
1559
1560 DRM_DEBUG_KMS("\n");
1561 dpa_ctl = I915_READ(DP_A);
1562 dpa_ctl &= ~DP_PLL_ENABLE;
1563 I915_WRITE(DP_A, dpa_ctl);
1564 }
1565
1566 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1567 {
1568 struct drm_device *dev = crtc->dev;
1569 struct drm_i915_private *dev_priv = dev->dev_private;
1570 u32 dpa_ctl;
1571
1572 dpa_ctl = I915_READ(DP_A);
1573 dpa_ctl |= DP_PLL_ENABLE;
1574 I915_WRITE(DP_A, dpa_ctl);
1575 udelay(200);
1576 }
1577
1578
1579 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1580 {
1581 struct drm_device *dev = crtc->dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 u32 dpa_ctl;
1584
1585 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1586 dpa_ctl = I915_READ(DP_A);
1587 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1588
1589 if (clock < 200000) {
1590 u32 temp;
1591 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1592 /* workaround for 160Mhz:
1593 1) program 0x4600c bits 15:0 = 0x8124
1594 2) program 0x46010 bit 0 = 1
1595 3) program 0x46034 bit 24 = 1
1596 4) program 0x64000 bit 14 = 1
1597 */
1598 temp = I915_READ(0x4600c);
1599 temp &= 0xffff0000;
1600 I915_WRITE(0x4600c, temp | 0x8124);
1601
1602 temp = I915_READ(0x46010);
1603 I915_WRITE(0x46010, temp | 1);
1604
1605 temp = I915_READ(0x46034);
1606 I915_WRITE(0x46034, temp | (1 << 24));
1607 } else {
1608 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1609 }
1610 I915_WRITE(DP_A, dpa_ctl);
1611
1612 udelay(500);
1613 }
1614
1615 /* The FDI link training functions for ILK/Ibexpeak. */
1616 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1617 {
1618 struct drm_device *dev = crtc->dev;
1619 struct drm_i915_private *dev_priv = dev->dev_private;
1620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1621 int pipe = intel_crtc->pipe;
1622 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1623 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1624 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1625 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1626 u32 temp, tries = 0;
1627
1628 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1629 for train result */
1630 temp = I915_READ(fdi_rx_imr_reg);
1631 temp &= ~FDI_RX_SYMBOL_LOCK;
1632 temp &= ~FDI_RX_BIT_LOCK;
1633 I915_WRITE(fdi_rx_imr_reg, temp);
1634 I915_READ(fdi_rx_imr_reg);
1635 udelay(150);
1636
1637 /* enable CPU FDI TX and PCH FDI RX */
1638 temp = I915_READ(fdi_tx_reg);
1639 temp |= FDI_TX_ENABLE;
1640 temp &= ~(7 << 19);
1641 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1642 temp &= ~FDI_LINK_TRAIN_NONE;
1643 temp |= FDI_LINK_TRAIN_PATTERN_1;
1644 I915_WRITE(fdi_tx_reg, temp);
1645 I915_READ(fdi_tx_reg);
1646
1647 temp = I915_READ(fdi_rx_reg);
1648 temp &= ~FDI_LINK_TRAIN_NONE;
1649 temp |= FDI_LINK_TRAIN_PATTERN_1;
1650 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1651 I915_READ(fdi_rx_reg);
1652 udelay(150);
1653
1654 for (tries = 0; tries < 5; tries++) {
1655 temp = I915_READ(fdi_rx_iir_reg);
1656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1657
1658 if ((temp & FDI_RX_BIT_LOCK)) {
1659 DRM_DEBUG_KMS("FDI train 1 done.\n");
1660 I915_WRITE(fdi_rx_iir_reg,
1661 temp | FDI_RX_BIT_LOCK);
1662 break;
1663 }
1664 }
1665 if (tries == 5)
1666 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1667
1668 /* Train 2 */
1669 temp = I915_READ(fdi_tx_reg);
1670 temp &= ~FDI_LINK_TRAIN_NONE;
1671 temp |= FDI_LINK_TRAIN_PATTERN_2;
1672 I915_WRITE(fdi_tx_reg, temp);
1673
1674 temp = I915_READ(fdi_rx_reg);
1675 temp &= ~FDI_LINK_TRAIN_NONE;
1676 temp |= FDI_LINK_TRAIN_PATTERN_2;
1677 I915_WRITE(fdi_rx_reg, temp);
1678 udelay(150);
1679
1680 tries = 0;
1681
1682 for (tries = 0; tries < 5; tries++) {
1683 temp = I915_READ(fdi_rx_iir_reg);
1684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1685
1686 if (temp & FDI_RX_SYMBOL_LOCK) {
1687 I915_WRITE(fdi_rx_iir_reg,
1688 temp | FDI_RX_SYMBOL_LOCK);
1689 DRM_DEBUG_KMS("FDI train 2 done.\n");
1690 break;
1691 }
1692 }
1693 if (tries == 5)
1694 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1695
1696 DRM_DEBUG_KMS("FDI train done\n");
1697 }
1698
1699 static int snb_b_fdi_train_param [] = {
1700 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1701 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1702 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1703 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1704 };
1705
1706 /* The FDI link training functions for SNB/Cougarpoint. */
1707 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1708 {
1709 struct drm_device *dev = crtc->dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1712 int pipe = intel_crtc->pipe;
1713 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1714 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1715 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1716 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1717 u32 temp, i;
1718
1719 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1720 for train result */
1721 temp = I915_READ(fdi_rx_imr_reg);
1722 temp &= ~FDI_RX_SYMBOL_LOCK;
1723 temp &= ~FDI_RX_BIT_LOCK;
1724 I915_WRITE(fdi_rx_imr_reg, temp);
1725 I915_READ(fdi_rx_imr_reg);
1726 udelay(150);
1727
1728 /* enable CPU FDI TX and PCH FDI RX */
1729 temp = I915_READ(fdi_tx_reg);
1730 temp |= FDI_TX_ENABLE;
1731 temp &= ~(7 << 19);
1732 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1733 temp &= ~FDI_LINK_TRAIN_NONE;
1734 temp |= FDI_LINK_TRAIN_PATTERN_1;
1735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1736 /* SNB-B */
1737 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1738 I915_WRITE(fdi_tx_reg, temp);
1739 I915_READ(fdi_tx_reg);
1740
1741 temp = I915_READ(fdi_rx_reg);
1742 if (HAS_PCH_CPT(dev)) {
1743 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1744 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1745 } else {
1746 temp &= ~FDI_LINK_TRAIN_NONE;
1747 temp |= FDI_LINK_TRAIN_PATTERN_1;
1748 }
1749 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1750 I915_READ(fdi_rx_reg);
1751 udelay(150);
1752
1753 for (i = 0; i < 4; i++ ) {
1754 temp = I915_READ(fdi_tx_reg);
1755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1756 temp |= snb_b_fdi_train_param[i];
1757 I915_WRITE(fdi_tx_reg, temp);
1758 udelay(500);
1759
1760 temp = I915_READ(fdi_rx_iir_reg);
1761 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1762
1763 if (temp & FDI_RX_BIT_LOCK) {
1764 I915_WRITE(fdi_rx_iir_reg,
1765 temp | FDI_RX_BIT_LOCK);
1766 DRM_DEBUG_KMS("FDI train 1 done.\n");
1767 break;
1768 }
1769 }
1770 if (i == 4)
1771 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1772
1773 /* Train 2 */
1774 temp = I915_READ(fdi_tx_reg);
1775 temp &= ~FDI_LINK_TRAIN_NONE;
1776 temp |= FDI_LINK_TRAIN_PATTERN_2;
1777 if (IS_GEN6(dev)) {
1778 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1779 /* SNB-B */
1780 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1781 }
1782 I915_WRITE(fdi_tx_reg, temp);
1783
1784 temp = I915_READ(fdi_rx_reg);
1785 if (HAS_PCH_CPT(dev)) {
1786 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1787 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1788 } else {
1789 temp &= ~FDI_LINK_TRAIN_NONE;
1790 temp |= FDI_LINK_TRAIN_PATTERN_2;
1791 }
1792 I915_WRITE(fdi_rx_reg, temp);
1793 udelay(150);
1794
1795 for (i = 0; i < 4; i++ ) {
1796 temp = I915_READ(fdi_tx_reg);
1797 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1798 temp |= snb_b_fdi_train_param[i];
1799 I915_WRITE(fdi_tx_reg, temp);
1800 udelay(500);
1801
1802 temp = I915_READ(fdi_rx_iir_reg);
1803 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1804
1805 if (temp & FDI_RX_SYMBOL_LOCK) {
1806 I915_WRITE(fdi_rx_iir_reg,
1807 temp | FDI_RX_SYMBOL_LOCK);
1808 DRM_DEBUG_KMS("FDI train 2 done.\n");
1809 break;
1810 }
1811 }
1812 if (i == 4)
1813 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1814
1815 DRM_DEBUG_KMS("FDI train done.\n");
1816 }
1817
1818 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1819 {
1820 struct drm_device *dev = crtc->dev;
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823 int pipe = intel_crtc->pipe;
1824 int plane = intel_crtc->plane;
1825 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1826 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1827 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1828 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1829 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1830 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1831 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1832 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1833 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1834 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1835 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1836 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1837 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1838 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1839 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1840 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1841 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1842 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1843 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1844 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1845 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1846 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1847 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1848 u32 temp;
1849 int n;
1850 u32 pipe_bpc;
1851
1852 temp = I915_READ(pipeconf_reg);
1853 pipe_bpc = temp & PIPE_BPC_MASK;
1854
1855 /* XXX: When our outputs are all unaware of DPMS modes other than off
1856 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1857 */
1858 switch (mode) {
1859 case DRM_MODE_DPMS_ON:
1860 case DRM_MODE_DPMS_STANDBY:
1861 case DRM_MODE_DPMS_SUSPEND:
1862 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1863
1864 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1865 temp = I915_READ(PCH_LVDS);
1866 if ((temp & LVDS_PORT_EN) == 0) {
1867 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1868 POSTING_READ(PCH_LVDS);
1869 }
1870 }
1871
1872 if (HAS_eDP) {
1873 /* enable eDP PLL */
1874 ironlake_enable_pll_edp(crtc);
1875 } else {
1876
1877 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1878 temp = I915_READ(fdi_rx_reg);
1879 /*
1880 * make the BPC in FDI Rx be consistent with that in
1881 * pipeconf reg.
1882 */
1883 temp &= ~(0x7 << 16);
1884 temp |= (pipe_bpc << 11);
1885 temp &= ~(7 << 19);
1886 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1887 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1888 I915_READ(fdi_rx_reg);
1889 udelay(200);
1890
1891 /* Switch from Rawclk to PCDclk */
1892 temp = I915_READ(fdi_rx_reg);
1893 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1894 I915_READ(fdi_rx_reg);
1895 udelay(200);
1896
1897 /* Enable CPU FDI TX PLL, always on for Ironlake */
1898 temp = I915_READ(fdi_tx_reg);
1899 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1900 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1901 I915_READ(fdi_tx_reg);
1902 udelay(100);
1903 }
1904 }
1905
1906 /* Enable panel fitting for LVDS */
1907 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1908 || HAS_eDP || intel_pch_has_edp(crtc)) {
1909 temp = I915_READ(pf_ctl_reg);
1910 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1911
1912 /* currently full aspect */
1913 I915_WRITE(pf_win_pos, 0);
1914
1915 I915_WRITE(pf_win_size,
1916 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1917 (dev_priv->panel_fixed_mode->vdisplay));
1918 }
1919
1920 /* Enable CPU pipe */
1921 temp = I915_READ(pipeconf_reg);
1922 if ((temp & PIPEACONF_ENABLE) == 0) {
1923 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1924 I915_READ(pipeconf_reg);
1925 udelay(100);
1926 }
1927
1928 /* configure and enable CPU plane */
1929 temp = I915_READ(dspcntr_reg);
1930 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1931 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1932 /* Flush the plane changes */
1933 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1934 }
1935
1936 if (!HAS_eDP) {
1937 /* For PCH output, training FDI link */
1938 if (IS_GEN6(dev))
1939 gen6_fdi_link_train(crtc);
1940 else
1941 ironlake_fdi_link_train(crtc);
1942
1943 /* enable PCH DPLL */
1944 temp = I915_READ(pch_dpll_reg);
1945 if ((temp & DPLL_VCO_ENABLE) == 0) {
1946 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1947 I915_READ(pch_dpll_reg);
1948 }
1949 udelay(200);
1950
1951 if (HAS_PCH_CPT(dev)) {
1952 /* Be sure PCH DPLL SEL is set */
1953 temp = I915_READ(PCH_DPLL_SEL);
1954 if (trans_dpll_sel == 0 &&
1955 (temp & TRANSA_DPLL_ENABLE) == 0)
1956 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1957 else if (trans_dpll_sel == 1 &&
1958 (temp & TRANSB_DPLL_ENABLE) == 0)
1959 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1960 I915_WRITE(PCH_DPLL_SEL, temp);
1961 I915_READ(PCH_DPLL_SEL);
1962 }
1963
1964 /* set transcoder timing */
1965 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1966 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1967 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1968
1969 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1970 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1971 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1972
1973 /* enable normal train */
1974 temp = I915_READ(fdi_tx_reg);
1975 temp &= ~FDI_LINK_TRAIN_NONE;
1976 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1977 FDI_TX_ENHANCE_FRAME_ENABLE);
1978 I915_READ(fdi_tx_reg);
1979
1980 temp = I915_READ(fdi_rx_reg);
1981 if (HAS_PCH_CPT(dev)) {
1982 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1983 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1984 } else {
1985 temp &= ~FDI_LINK_TRAIN_NONE;
1986 temp |= FDI_LINK_TRAIN_NONE;
1987 }
1988 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1989 I915_READ(fdi_rx_reg);
1990
1991 /* wait one idle pattern time */
1992 udelay(100);
1993
1994 /* For PCH DP, enable TRANS_DP_CTL */
1995 if (HAS_PCH_CPT(dev) &&
1996 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1997 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1998 int reg;
1999
2000 reg = I915_READ(trans_dp_ctl);
2001 reg &= ~TRANS_DP_PORT_SEL_MASK;
2002 reg = TRANS_DP_OUTPUT_ENABLE |
2003 TRANS_DP_ENH_FRAMING;
2004
2005 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2006 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2007 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2008 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2009
2010 switch (intel_trans_dp_port_sel(crtc)) {
2011 case PCH_DP_B:
2012 reg |= TRANS_DP_PORT_SEL_B;
2013 break;
2014 case PCH_DP_C:
2015 reg |= TRANS_DP_PORT_SEL_C;
2016 break;
2017 case PCH_DP_D:
2018 reg |= TRANS_DP_PORT_SEL_D;
2019 break;
2020 default:
2021 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2022 reg |= TRANS_DP_PORT_SEL_B;
2023 break;
2024 }
2025
2026 I915_WRITE(trans_dp_ctl, reg);
2027 POSTING_READ(trans_dp_ctl);
2028 }
2029
2030 /* enable PCH transcoder */
2031 temp = I915_READ(transconf_reg);
2032 /*
2033 * make the BPC in transcoder be consistent with
2034 * that in pipeconf reg.
2035 */
2036 temp &= ~PIPE_BPC_MASK;
2037 temp |= pipe_bpc;
2038 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2039 I915_READ(transconf_reg);
2040
2041 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2042 ;
2043
2044 }
2045
2046 intel_crtc_load_lut(crtc);
2047
2048 intel_update_fbc(crtc, &crtc->mode);
2049
2050 break;
2051 case DRM_MODE_DPMS_OFF:
2052 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2053
2054 drm_vblank_off(dev, pipe);
2055 /* Disable display plane */
2056 temp = I915_READ(dspcntr_reg);
2057 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2058 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2059 /* Flush the plane changes */
2060 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2061 I915_READ(dspbase_reg);
2062 }
2063
2064 if (dev_priv->cfb_plane == plane &&
2065 dev_priv->display.disable_fbc)
2066 dev_priv->display.disable_fbc(dev);
2067
2068 i915_disable_vga(dev);
2069
2070 /* disable cpu pipe, disable after all planes disabled */
2071 temp = I915_READ(pipeconf_reg);
2072 if ((temp & PIPEACONF_ENABLE) != 0) {
2073 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2074 I915_READ(pipeconf_reg);
2075 n = 0;
2076 /* wait for cpu pipe off, pipe state */
2077 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2078 n++;
2079 if (n < 60) {
2080 udelay(500);
2081 continue;
2082 } else {
2083 DRM_DEBUG_KMS("pipe %d off delay\n",
2084 pipe);
2085 break;
2086 }
2087 }
2088 } else
2089 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2090
2091 udelay(100);
2092
2093 /* Disable PF */
2094 temp = I915_READ(pf_ctl_reg);
2095 if ((temp & PF_ENABLE) != 0) {
2096 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2097 I915_READ(pf_ctl_reg);
2098 }
2099 I915_WRITE(pf_win_size, 0);
2100 POSTING_READ(pf_win_size);
2101
2102
2103 /* disable CPU FDI tx and PCH FDI rx */
2104 temp = I915_READ(fdi_tx_reg);
2105 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2106 I915_READ(fdi_tx_reg);
2107
2108 temp = I915_READ(fdi_rx_reg);
2109 /* BPC in FDI rx is consistent with that in pipeconf */
2110 temp &= ~(0x07 << 16);
2111 temp |= (pipe_bpc << 11);
2112 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2113 I915_READ(fdi_rx_reg);
2114
2115 udelay(100);
2116
2117 /* still set train pattern 1 */
2118 temp = I915_READ(fdi_tx_reg);
2119 temp &= ~FDI_LINK_TRAIN_NONE;
2120 temp |= FDI_LINK_TRAIN_PATTERN_1;
2121 I915_WRITE(fdi_tx_reg, temp);
2122 POSTING_READ(fdi_tx_reg);
2123
2124 temp = I915_READ(fdi_rx_reg);
2125 if (HAS_PCH_CPT(dev)) {
2126 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2127 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2128 } else {
2129 temp &= ~FDI_LINK_TRAIN_NONE;
2130 temp |= FDI_LINK_TRAIN_PATTERN_1;
2131 }
2132 I915_WRITE(fdi_rx_reg, temp);
2133 POSTING_READ(fdi_rx_reg);
2134
2135 udelay(100);
2136
2137 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2138 temp = I915_READ(PCH_LVDS);
2139 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2140 I915_READ(PCH_LVDS);
2141 udelay(100);
2142 }
2143
2144 /* disable PCH transcoder */
2145 temp = I915_READ(transconf_reg);
2146 if ((temp & TRANS_ENABLE) != 0) {
2147 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2148 I915_READ(transconf_reg);
2149 n = 0;
2150 /* wait for PCH transcoder off, transcoder state */
2151 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2152 n++;
2153 if (n < 60) {
2154 udelay(500);
2155 continue;
2156 } else {
2157 DRM_DEBUG_KMS("transcoder %d off "
2158 "delay\n", pipe);
2159 break;
2160 }
2161 }
2162 }
2163
2164 temp = I915_READ(transconf_reg);
2165 /* BPC in transcoder is consistent with that in pipeconf */
2166 temp &= ~PIPE_BPC_MASK;
2167 temp |= pipe_bpc;
2168 I915_WRITE(transconf_reg, temp);
2169 I915_READ(transconf_reg);
2170 udelay(100);
2171
2172 if (HAS_PCH_CPT(dev)) {
2173 /* disable TRANS_DP_CTL */
2174 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2175 int reg;
2176
2177 reg = I915_READ(trans_dp_ctl);
2178 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2179 I915_WRITE(trans_dp_ctl, reg);
2180 POSTING_READ(trans_dp_ctl);
2181
2182 /* disable DPLL_SEL */
2183 temp = I915_READ(PCH_DPLL_SEL);
2184 if (trans_dpll_sel == 0)
2185 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2186 else
2187 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2188 I915_WRITE(PCH_DPLL_SEL, temp);
2189 I915_READ(PCH_DPLL_SEL);
2190
2191 }
2192
2193 /* disable PCH DPLL */
2194 temp = I915_READ(pch_dpll_reg);
2195 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2196 I915_READ(pch_dpll_reg);
2197
2198 if (HAS_eDP) {
2199 ironlake_disable_pll_edp(crtc);
2200 }
2201
2202 /* Switch from PCDclk to Rawclk */
2203 temp = I915_READ(fdi_rx_reg);
2204 temp &= ~FDI_SEL_PCDCLK;
2205 I915_WRITE(fdi_rx_reg, temp);
2206 I915_READ(fdi_rx_reg);
2207
2208 /* Disable CPU FDI TX PLL */
2209 temp = I915_READ(fdi_tx_reg);
2210 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2211 I915_READ(fdi_tx_reg);
2212 udelay(100);
2213
2214 temp = I915_READ(fdi_rx_reg);
2215 temp &= ~FDI_RX_PLL_ENABLE;
2216 I915_WRITE(fdi_rx_reg, temp);
2217 I915_READ(fdi_rx_reg);
2218
2219 /* Wait for the clocks to turn off. */
2220 udelay(100);
2221 break;
2222 }
2223 }
2224
2225 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2226 {
2227 struct intel_overlay *overlay;
2228 int ret;
2229
2230 if (!enable && intel_crtc->overlay) {
2231 overlay = intel_crtc->overlay;
2232 mutex_lock(&overlay->dev->struct_mutex);
2233 for (;;) {
2234 ret = intel_overlay_switch_off(overlay);
2235 if (ret == 0)
2236 break;
2237
2238 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2239 if (ret != 0) {
2240 /* overlay doesn't react anymore. Usually
2241 * results in a black screen and an unkillable
2242 * X server. */
2243 BUG();
2244 overlay->hw_wedged = HW_WEDGED;
2245 break;
2246 }
2247 }
2248 mutex_unlock(&overlay->dev->struct_mutex);
2249 }
2250 /* Let userspace switch the overlay on again. In most cases userspace
2251 * has to recompute where to put it anyway. */
2252
2253 return;
2254 }
2255
2256 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2257 {
2258 struct drm_device *dev = crtc->dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2261 int pipe = intel_crtc->pipe;
2262 int plane = intel_crtc->plane;
2263 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2264 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2265 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2266 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2267 u32 temp;
2268
2269 /* XXX: When our outputs are all unaware of DPMS modes other than off
2270 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2271 */
2272 switch (mode) {
2273 case DRM_MODE_DPMS_ON:
2274 case DRM_MODE_DPMS_STANDBY:
2275 case DRM_MODE_DPMS_SUSPEND:
2276 intel_update_watermarks(dev);
2277
2278 /* Enable the DPLL */
2279 temp = I915_READ(dpll_reg);
2280 if ((temp & DPLL_VCO_ENABLE) == 0) {
2281 I915_WRITE(dpll_reg, temp);
2282 I915_READ(dpll_reg);
2283 /* Wait for the clocks to stabilize. */
2284 udelay(150);
2285 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2286 I915_READ(dpll_reg);
2287 /* Wait for the clocks to stabilize. */
2288 udelay(150);
2289 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2290 I915_READ(dpll_reg);
2291 /* Wait for the clocks to stabilize. */
2292 udelay(150);
2293 }
2294
2295 /* Enable the pipe */
2296 temp = I915_READ(pipeconf_reg);
2297 if ((temp & PIPEACONF_ENABLE) == 0)
2298 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2299
2300 /* Enable the plane */
2301 temp = I915_READ(dspcntr_reg);
2302 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2303 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2304 /* Flush the plane changes */
2305 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2306 }
2307
2308 intel_crtc_load_lut(crtc);
2309
2310 if ((IS_I965G(dev) || plane == 0))
2311 intel_update_fbc(crtc, &crtc->mode);
2312
2313 /* Give the overlay scaler a chance to enable if it's on this pipe */
2314 intel_crtc_dpms_overlay(intel_crtc, true);
2315 break;
2316 case DRM_MODE_DPMS_OFF:
2317 intel_update_watermarks(dev);
2318
2319 /* Give the overlay scaler a chance to disable if it's on this pipe */
2320 intel_crtc_dpms_overlay(intel_crtc, false);
2321 drm_vblank_off(dev, pipe);
2322
2323 if (dev_priv->cfb_plane == plane &&
2324 dev_priv->display.disable_fbc)
2325 dev_priv->display.disable_fbc(dev);
2326
2327 /* Disable the VGA plane that we never use */
2328 i915_disable_vga(dev);
2329
2330 /* Disable display plane */
2331 temp = I915_READ(dspcntr_reg);
2332 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2333 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2334 /* Flush the plane changes */
2335 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2336 I915_READ(dspbase_reg);
2337 }
2338
2339 if (!IS_I9XX(dev)) {
2340 /* Wait for vblank for the disable to take effect */
2341 intel_wait_for_vblank(dev);
2342 }
2343
2344 /* Don't disable pipe A or pipe A PLLs if needed */
2345 if (pipeconf_reg == PIPEACONF &&
2346 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2347 goto skip_pipe_off;
2348
2349 /* Next, disable display pipes */
2350 temp = I915_READ(pipeconf_reg);
2351 if ((temp & PIPEACONF_ENABLE) != 0) {
2352 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2353 I915_READ(pipeconf_reg);
2354 }
2355
2356 /* Wait for vblank for the disable to take effect. */
2357 intel_wait_for_vblank(dev);
2358
2359 temp = I915_READ(dpll_reg);
2360 if ((temp & DPLL_VCO_ENABLE) != 0) {
2361 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2362 I915_READ(dpll_reg);
2363 }
2364 skip_pipe_off:
2365 /* Wait for the clocks to turn off. */
2366 udelay(150);
2367 break;
2368 }
2369 }
2370
2371 /**
2372 * Sets the power management mode of the pipe and plane.
2373 *
2374 * This code should probably grow support for turning the cursor off and back
2375 * on appropriately at the same time as we're turning the pipe off/on.
2376 */
2377 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2378 {
2379 struct drm_device *dev = crtc->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 struct drm_i915_master_private *master_priv;
2382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2383 int pipe = intel_crtc->pipe;
2384 bool enabled;
2385
2386 dev_priv->display.dpms(crtc, mode);
2387
2388 intel_crtc->dpms_mode = mode;
2389
2390 if (!dev->primary->master)
2391 return;
2392
2393 master_priv = dev->primary->master->driver_priv;
2394 if (!master_priv->sarea_priv)
2395 return;
2396
2397 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2398
2399 switch (pipe) {
2400 case 0:
2401 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2402 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2403 break;
2404 case 1:
2405 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2406 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2407 break;
2408 default:
2409 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2410 break;
2411 }
2412 }
2413
2414 static void intel_crtc_prepare (struct drm_crtc *crtc)
2415 {
2416 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2417 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2418 }
2419
2420 static void intel_crtc_commit (struct drm_crtc *crtc)
2421 {
2422 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2423 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2424 }
2425
2426 void intel_encoder_prepare (struct drm_encoder *encoder)
2427 {
2428 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2429 /* lvds has its own version of prepare see intel_lvds_prepare */
2430 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2431 }
2432
2433 void intel_encoder_commit (struct drm_encoder *encoder)
2434 {
2435 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2436 /* lvds has its own version of commit see intel_lvds_commit */
2437 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2438 }
2439
2440 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2441 struct drm_display_mode *mode,
2442 struct drm_display_mode *adjusted_mode)
2443 {
2444 struct drm_device *dev = crtc->dev;
2445 if (HAS_PCH_SPLIT(dev)) {
2446 /* FDI link clock is fixed at 2.7G */
2447 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2448 return false;
2449 }
2450 return true;
2451 }
2452
2453 static int i945_get_display_clock_speed(struct drm_device *dev)
2454 {
2455 return 400000;
2456 }
2457
2458 static int i915_get_display_clock_speed(struct drm_device *dev)
2459 {
2460 return 333000;
2461 }
2462
2463 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2464 {
2465 return 200000;
2466 }
2467
2468 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2469 {
2470 u16 gcfgc = 0;
2471
2472 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2473
2474 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2475 return 133000;
2476 else {
2477 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2478 case GC_DISPLAY_CLOCK_333_MHZ:
2479 return 333000;
2480 default:
2481 case GC_DISPLAY_CLOCK_190_200_MHZ:
2482 return 190000;
2483 }
2484 }
2485 }
2486
2487 static int i865_get_display_clock_speed(struct drm_device *dev)
2488 {
2489 return 266000;
2490 }
2491
2492 static int i855_get_display_clock_speed(struct drm_device *dev)
2493 {
2494 u16 hpllcc = 0;
2495 /* Assume that the hardware is in the high speed state. This
2496 * should be the default.
2497 */
2498 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2499 case GC_CLOCK_133_200:
2500 case GC_CLOCK_100_200:
2501 return 200000;
2502 case GC_CLOCK_166_250:
2503 return 250000;
2504 case GC_CLOCK_100_133:
2505 return 133000;
2506 }
2507
2508 /* Shouldn't happen */
2509 return 0;
2510 }
2511
2512 static int i830_get_display_clock_speed(struct drm_device *dev)
2513 {
2514 return 133000;
2515 }
2516
2517 /**
2518 * Return the pipe currently connected to the panel fitter,
2519 * or -1 if the panel fitter is not present or not in use
2520 */
2521 int intel_panel_fitter_pipe (struct drm_device *dev)
2522 {
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 u32 pfit_control;
2525
2526 /* i830 doesn't have a panel fitter */
2527 if (IS_I830(dev))
2528 return -1;
2529
2530 pfit_control = I915_READ(PFIT_CONTROL);
2531
2532 /* See if the panel fitter is in use */
2533 if ((pfit_control & PFIT_ENABLE) == 0)
2534 return -1;
2535
2536 /* 965 can place panel fitter on either pipe */
2537 if (IS_I965G(dev))
2538 return (pfit_control >> 29) & 0x3;
2539
2540 /* older chips can only use pipe 1 */
2541 return 1;
2542 }
2543
2544 struct fdi_m_n {
2545 u32 tu;
2546 u32 gmch_m;
2547 u32 gmch_n;
2548 u32 link_m;
2549 u32 link_n;
2550 };
2551
2552 static void
2553 fdi_reduce_ratio(u32 *num, u32 *den)
2554 {
2555 while (*num > 0xffffff || *den > 0xffffff) {
2556 *num >>= 1;
2557 *den >>= 1;
2558 }
2559 }
2560
2561 #define DATA_N 0x800000
2562 #define LINK_N 0x80000
2563
2564 static void
2565 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2566 int link_clock, struct fdi_m_n *m_n)
2567 {
2568 u64 temp;
2569
2570 m_n->tu = 64; /* default size */
2571
2572 temp = (u64) DATA_N * pixel_clock;
2573 temp = div_u64(temp, link_clock);
2574 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2575 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2576 m_n->gmch_n = DATA_N;
2577 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2578
2579 temp = (u64) LINK_N * pixel_clock;
2580 m_n->link_m = div_u64(temp, link_clock);
2581 m_n->link_n = LINK_N;
2582 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2583 }
2584
2585
2586 struct intel_watermark_params {
2587 unsigned long fifo_size;
2588 unsigned long max_wm;
2589 unsigned long default_wm;
2590 unsigned long guard_size;
2591 unsigned long cacheline_size;
2592 };
2593
2594 /* Pineview has different values for various configs */
2595 static struct intel_watermark_params pineview_display_wm = {
2596 PINEVIEW_DISPLAY_FIFO,
2597 PINEVIEW_MAX_WM,
2598 PINEVIEW_DFT_WM,
2599 PINEVIEW_GUARD_WM,
2600 PINEVIEW_FIFO_LINE_SIZE
2601 };
2602 static struct intel_watermark_params pineview_display_hplloff_wm = {
2603 PINEVIEW_DISPLAY_FIFO,
2604 PINEVIEW_MAX_WM,
2605 PINEVIEW_DFT_HPLLOFF_WM,
2606 PINEVIEW_GUARD_WM,
2607 PINEVIEW_FIFO_LINE_SIZE
2608 };
2609 static struct intel_watermark_params pineview_cursor_wm = {
2610 PINEVIEW_CURSOR_FIFO,
2611 PINEVIEW_CURSOR_MAX_WM,
2612 PINEVIEW_CURSOR_DFT_WM,
2613 PINEVIEW_CURSOR_GUARD_WM,
2614 PINEVIEW_FIFO_LINE_SIZE,
2615 };
2616 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2617 PINEVIEW_CURSOR_FIFO,
2618 PINEVIEW_CURSOR_MAX_WM,
2619 PINEVIEW_CURSOR_DFT_WM,
2620 PINEVIEW_CURSOR_GUARD_WM,
2621 PINEVIEW_FIFO_LINE_SIZE
2622 };
2623 static struct intel_watermark_params g4x_wm_info = {
2624 G4X_FIFO_SIZE,
2625 G4X_MAX_WM,
2626 G4X_MAX_WM,
2627 2,
2628 G4X_FIFO_LINE_SIZE,
2629 };
2630 static struct intel_watermark_params g4x_cursor_wm_info = {
2631 I965_CURSOR_FIFO,
2632 I965_CURSOR_MAX_WM,
2633 I965_CURSOR_DFT_WM,
2634 2,
2635 G4X_FIFO_LINE_SIZE,
2636 };
2637 static struct intel_watermark_params i965_cursor_wm_info = {
2638 I965_CURSOR_FIFO,
2639 I965_CURSOR_MAX_WM,
2640 I965_CURSOR_DFT_WM,
2641 2,
2642 I915_FIFO_LINE_SIZE,
2643 };
2644 static struct intel_watermark_params i945_wm_info = {
2645 I945_FIFO_SIZE,
2646 I915_MAX_WM,
2647 1,
2648 2,
2649 I915_FIFO_LINE_SIZE
2650 };
2651 static struct intel_watermark_params i915_wm_info = {
2652 I915_FIFO_SIZE,
2653 I915_MAX_WM,
2654 1,
2655 2,
2656 I915_FIFO_LINE_SIZE
2657 };
2658 static struct intel_watermark_params i855_wm_info = {
2659 I855GM_FIFO_SIZE,
2660 I915_MAX_WM,
2661 1,
2662 2,
2663 I830_FIFO_LINE_SIZE
2664 };
2665 static struct intel_watermark_params i830_wm_info = {
2666 I830_FIFO_SIZE,
2667 I915_MAX_WM,
2668 1,
2669 2,
2670 I830_FIFO_LINE_SIZE
2671 };
2672
2673 static struct intel_watermark_params ironlake_display_wm_info = {
2674 ILK_DISPLAY_FIFO,
2675 ILK_DISPLAY_MAXWM,
2676 ILK_DISPLAY_DFTWM,
2677 2,
2678 ILK_FIFO_LINE_SIZE
2679 };
2680
2681 static struct intel_watermark_params ironlake_cursor_wm_info = {
2682 ILK_CURSOR_FIFO,
2683 ILK_CURSOR_MAXWM,
2684 ILK_CURSOR_DFTWM,
2685 2,
2686 ILK_FIFO_LINE_SIZE
2687 };
2688
2689 static struct intel_watermark_params ironlake_display_srwm_info = {
2690 ILK_DISPLAY_SR_FIFO,
2691 ILK_DISPLAY_MAX_SRWM,
2692 ILK_DISPLAY_DFT_SRWM,
2693 2,
2694 ILK_FIFO_LINE_SIZE
2695 };
2696
2697 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2698 ILK_CURSOR_SR_FIFO,
2699 ILK_CURSOR_MAX_SRWM,
2700 ILK_CURSOR_DFT_SRWM,
2701 2,
2702 ILK_FIFO_LINE_SIZE
2703 };
2704
2705 /**
2706 * intel_calculate_wm - calculate watermark level
2707 * @clock_in_khz: pixel clock
2708 * @wm: chip FIFO params
2709 * @pixel_size: display pixel size
2710 * @latency_ns: memory latency for the platform
2711 *
2712 * Calculate the watermark level (the level at which the display plane will
2713 * start fetching from memory again). Each chip has a different display
2714 * FIFO size and allocation, so the caller needs to figure that out and pass
2715 * in the correct intel_watermark_params structure.
2716 *
2717 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2718 * on the pixel size. When it reaches the watermark level, it'll start
2719 * fetching FIFO line sized based chunks from memory until the FIFO fills
2720 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2721 * will occur, and a display engine hang could result.
2722 */
2723 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2724 struct intel_watermark_params *wm,
2725 int pixel_size,
2726 unsigned long latency_ns)
2727 {
2728 long entries_required, wm_size;
2729
2730 /*
2731 * Note: we need to make sure we don't overflow for various clock &
2732 * latency values.
2733 * clocks go from a few thousand to several hundred thousand.
2734 * latency is usually a few thousand
2735 */
2736 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2737 1000;
2738 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2739
2740 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2741
2742 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2743
2744 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2745
2746 /* Don't promote wm_size to unsigned... */
2747 if (wm_size > (long)wm->max_wm)
2748 wm_size = wm->max_wm;
2749 if (wm_size <= 0) {
2750 wm_size = wm->default_wm;
2751 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2752 " entries required = %ld, available = %lu.\n",
2753 entries_required + wm->guard_size,
2754 wm->fifo_size);
2755 }
2756
2757 return wm_size;
2758 }
2759
2760 struct cxsr_latency {
2761 int is_desktop;
2762 int is_ddr3;
2763 unsigned long fsb_freq;
2764 unsigned long mem_freq;
2765 unsigned long display_sr;
2766 unsigned long display_hpll_disable;
2767 unsigned long cursor_sr;
2768 unsigned long cursor_hpll_disable;
2769 };
2770
2771 static struct cxsr_latency cxsr_latency_table[] = {
2772 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2773 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2774 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2775 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2776 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2777
2778 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2779 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2780 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2781 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2782 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2783
2784 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2785 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2786 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2787 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2788 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2789
2790 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2791 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2792 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2793 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2794 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2795
2796 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2797 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2798 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2799 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2800 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2801
2802 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2803 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2804 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2805 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2806 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2807 };
2808
2809 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2810 int fsb, int mem)
2811 {
2812 int i;
2813 struct cxsr_latency *latency;
2814
2815 if (fsb == 0 || mem == 0)
2816 return NULL;
2817
2818 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2819 latency = &cxsr_latency_table[i];
2820 if (is_desktop == latency->is_desktop &&
2821 is_ddr3 == latency->is_ddr3 &&
2822 fsb == latency->fsb_freq && mem == latency->mem_freq)
2823 return latency;
2824 }
2825
2826 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2827
2828 return NULL;
2829 }
2830
2831 static void pineview_disable_cxsr(struct drm_device *dev)
2832 {
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834 u32 reg;
2835
2836 /* deactivate cxsr */
2837 reg = I915_READ(DSPFW3);
2838 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2839 I915_WRITE(DSPFW3, reg);
2840 DRM_INFO("Big FIFO is disabled\n");
2841 }
2842
2843 /*
2844 * Latency for FIFO fetches is dependent on several factors:
2845 * - memory configuration (speed, channels)
2846 * - chipset
2847 * - current MCH state
2848 * It can be fairly high in some situations, so here we assume a fairly
2849 * pessimal value. It's a tradeoff between extra memory fetches (if we
2850 * set this value too high, the FIFO will fetch frequently to stay full)
2851 * and power consumption (set it too low to save power and we might see
2852 * FIFO underruns and display "flicker").
2853 *
2854 * A value of 5us seems to be a good balance; safe for very low end
2855 * platforms but not overly aggressive on lower latency configs.
2856 */
2857 static const int latency_ns = 5000;
2858
2859 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2860 {
2861 struct drm_i915_private *dev_priv = dev->dev_private;
2862 uint32_t dsparb = I915_READ(DSPARB);
2863 int size;
2864
2865 size = dsparb & 0x7f;
2866 if (plane)
2867 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2868
2869 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2870 plane ? "B" : "A", size);
2871
2872 return size;
2873 }
2874
2875 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2876 {
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2878 uint32_t dsparb = I915_READ(DSPARB);
2879 int size;
2880
2881 size = dsparb & 0x1ff;
2882 if (plane)
2883 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2884 size >>= 1; /* Convert to cachelines */
2885
2886 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2887 plane ? "B" : "A", size);
2888
2889 return size;
2890 }
2891
2892 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2893 {
2894 struct drm_i915_private *dev_priv = dev->dev_private;
2895 uint32_t dsparb = I915_READ(DSPARB);
2896 int size;
2897
2898 size = dsparb & 0x7f;
2899 size >>= 2; /* Convert to cachelines */
2900
2901 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2902 plane ? "B" : "A",
2903 size);
2904
2905 return size;
2906 }
2907
2908 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2909 {
2910 struct drm_i915_private *dev_priv = dev->dev_private;
2911 uint32_t dsparb = I915_READ(DSPARB);
2912 int size;
2913
2914 size = dsparb & 0x7f;
2915 size >>= 1; /* Convert to cachelines */
2916
2917 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2918 plane ? "B" : "A", size);
2919
2920 return size;
2921 }
2922
2923 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2924 int planeb_clock, int sr_hdisplay, int unused,
2925 int pixel_size)
2926 {
2927 struct drm_i915_private *dev_priv = dev->dev_private;
2928 u32 reg;
2929 unsigned long wm;
2930 struct cxsr_latency *latency;
2931 int sr_clock;
2932
2933 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2934 dev_priv->fsb_freq, dev_priv->mem_freq);
2935 if (!latency) {
2936 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2937 pineview_disable_cxsr(dev);
2938 return;
2939 }
2940
2941 if (!planea_clock || !planeb_clock) {
2942 sr_clock = planea_clock ? planea_clock : planeb_clock;
2943
2944 /* Display SR */
2945 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2946 pixel_size, latency->display_sr);
2947 reg = I915_READ(DSPFW1);
2948 reg &= ~DSPFW_SR_MASK;
2949 reg |= wm << DSPFW_SR_SHIFT;
2950 I915_WRITE(DSPFW1, reg);
2951 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2952
2953 /* cursor SR */
2954 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2955 pixel_size, latency->cursor_sr);
2956 reg = I915_READ(DSPFW3);
2957 reg &= ~DSPFW_CURSOR_SR_MASK;
2958 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2959 I915_WRITE(DSPFW3, reg);
2960
2961 /* Display HPLL off SR */
2962 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2963 pixel_size, latency->display_hpll_disable);
2964 reg = I915_READ(DSPFW3);
2965 reg &= ~DSPFW_HPLL_SR_MASK;
2966 reg |= wm & DSPFW_HPLL_SR_MASK;
2967 I915_WRITE(DSPFW3, reg);
2968
2969 /* cursor HPLL off SR */
2970 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2971 pixel_size, latency->cursor_hpll_disable);
2972 reg = I915_READ(DSPFW3);
2973 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2974 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2975 I915_WRITE(DSPFW3, reg);
2976 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2977
2978 /* activate cxsr */
2979 reg = I915_READ(DSPFW3);
2980 reg |= PINEVIEW_SELF_REFRESH_EN;
2981 I915_WRITE(DSPFW3, reg);
2982 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2983 } else {
2984 pineview_disable_cxsr(dev);
2985 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2986 }
2987 }
2988
2989 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2990 int planeb_clock, int sr_hdisplay, int sr_htotal,
2991 int pixel_size)
2992 {
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 int total_size, cacheline_size;
2995 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2996 struct intel_watermark_params planea_params, planeb_params;
2997 unsigned long line_time_us;
2998 int sr_clock, sr_entries = 0, entries_required;
2999
3000 /* Create copies of the base settings for each pipe */
3001 planea_params = planeb_params = g4x_wm_info;
3002
3003 /* Grab a couple of global values before we overwrite them */
3004 total_size = planea_params.fifo_size;
3005 cacheline_size = planea_params.cacheline_size;
3006
3007 /*
3008 * Note: we need to make sure we don't overflow for various clock &
3009 * latency values.
3010 * clocks go from a few thousand to several hundred thousand.
3011 * latency is usually a few thousand
3012 */
3013 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3014 1000;
3015 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3016 planea_wm = entries_required + planea_params.guard_size;
3017
3018 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3019 1000;
3020 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3021 planeb_wm = entries_required + planeb_params.guard_size;
3022
3023 cursora_wm = cursorb_wm = 16;
3024 cursor_sr = 32;
3025
3026 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3027
3028 /* Calc sr entries for one plane configs */
3029 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3030 /* self-refresh has much higher latency */
3031 static const int sr_latency_ns = 12000;
3032
3033 sr_clock = planea_clock ? planea_clock : planeb_clock;
3034 line_time_us = ((sr_htotal * 1000) / sr_clock);
3035
3036 /* Use ns/us then divide to preserve precision */
3037 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3038 pixel_size * sr_hdisplay;
3039 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3040
3041 entries_required = (((sr_latency_ns / line_time_us) +
3042 1000) / 1000) * pixel_size * 64;
3043 entries_required = DIV_ROUND_UP(entries_required,
3044 g4x_cursor_wm_info.cacheline_size);
3045 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3046
3047 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3048 cursor_sr = g4x_cursor_wm_info.max_wm;
3049 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3050 "cursor %d\n", sr_entries, cursor_sr);
3051
3052 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3053 } else {
3054 /* Turn off self refresh if both pipes are enabled */
3055 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3056 & ~FW_BLC_SELF_EN);
3057 }
3058
3059 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3060 planea_wm, planeb_wm, sr_entries);
3061
3062 planea_wm &= 0x3f;
3063 planeb_wm &= 0x3f;
3064
3065 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3066 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3067 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3068 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3069 (cursora_wm << DSPFW_CURSORA_SHIFT));
3070 /* HPLL off in SR has some issues on G4x... disable it */
3071 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3072 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3073 }
3074
3075 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3076 int planeb_clock, int sr_hdisplay, int sr_htotal,
3077 int pixel_size)
3078 {
3079 struct drm_i915_private *dev_priv = dev->dev_private;
3080 unsigned long line_time_us;
3081 int sr_clock, sr_entries, srwm = 1;
3082 int cursor_sr = 16;
3083
3084 /* Calc sr entries for one plane configs */
3085 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3086 /* self-refresh has much higher latency */
3087 static const int sr_latency_ns = 12000;
3088
3089 sr_clock = planea_clock ? planea_clock : planeb_clock;
3090 line_time_us = ((sr_htotal * 1000) / sr_clock);
3091
3092 /* Use ns/us then divide to preserve precision */
3093 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3094 pixel_size * sr_hdisplay;
3095 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3096 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3097 srwm = I965_FIFO_SIZE - sr_entries;
3098 if (srwm < 0)
3099 srwm = 1;
3100 srwm &= 0x1ff;
3101
3102 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3103 pixel_size * 64;
3104 sr_entries = DIV_ROUND_UP(sr_entries,
3105 i965_cursor_wm_info.cacheline_size);
3106 cursor_sr = i965_cursor_wm_info.fifo_size -
3107 (sr_entries + i965_cursor_wm_info.guard_size);
3108
3109 if (cursor_sr > i965_cursor_wm_info.max_wm)
3110 cursor_sr = i965_cursor_wm_info.max_wm;
3111
3112 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3113 "cursor %d\n", srwm, cursor_sr);
3114
3115 if (IS_I965GM(dev))
3116 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3117 } else {
3118 /* Turn off self refresh if both pipes are enabled */
3119 if (IS_I965GM(dev))
3120 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3121 & ~FW_BLC_SELF_EN);
3122 }
3123
3124 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3125 srwm);
3126
3127 /* 965 has limitations... */
3128 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3129 (8 << 0));
3130 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3131 /* update cursor SR watermark */
3132 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3133 }
3134
3135 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3136 int planeb_clock, int sr_hdisplay, int sr_htotal,
3137 int pixel_size)
3138 {
3139 struct drm_i915_private *dev_priv = dev->dev_private;
3140 uint32_t fwater_lo;
3141 uint32_t fwater_hi;
3142 int total_size, cacheline_size, cwm, srwm = 1;
3143 int planea_wm, planeb_wm;
3144 struct intel_watermark_params planea_params, planeb_params;
3145 unsigned long line_time_us;
3146 int sr_clock, sr_entries = 0;
3147
3148 /* Create copies of the base settings for each pipe */
3149 if (IS_I965GM(dev) || IS_I945GM(dev))
3150 planea_params = planeb_params = i945_wm_info;
3151 else if (IS_I9XX(dev))
3152 planea_params = planeb_params = i915_wm_info;
3153 else
3154 planea_params = planeb_params = i855_wm_info;
3155
3156 /* Grab a couple of global values before we overwrite them */
3157 total_size = planea_params.fifo_size;
3158 cacheline_size = planea_params.cacheline_size;
3159
3160 /* Update per-plane FIFO sizes */
3161 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3162 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3163
3164 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3165 pixel_size, latency_ns);
3166 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3167 pixel_size, latency_ns);
3168 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3169
3170 /*
3171 * Overlay gets an aggressive default since video jitter is bad.
3172 */
3173 cwm = 2;
3174
3175 /* Calc sr entries for one plane configs */
3176 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3177 (!planea_clock || !planeb_clock)) {
3178 /* self-refresh has much higher latency */
3179 static const int sr_latency_ns = 6000;
3180
3181 sr_clock = planea_clock ? planea_clock : planeb_clock;
3182 line_time_us = ((sr_htotal * 1000) / sr_clock);
3183
3184 /* Use ns/us then divide to preserve precision */
3185 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3186 pixel_size * sr_hdisplay;
3187 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3188 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3189 srwm = total_size - sr_entries;
3190 if (srwm < 0)
3191 srwm = 1;
3192
3193 if (IS_I945G(dev) || IS_I945GM(dev))
3194 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3195 else if (IS_I915GM(dev)) {
3196 /* 915M has a smaller SRWM field */
3197 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3198 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3199 }
3200 } else {
3201 /* Turn off self refresh if both pipes are enabled */
3202 if (IS_I945G(dev) || IS_I945GM(dev)) {
3203 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3204 & ~FW_BLC_SELF_EN);
3205 } else if (IS_I915GM(dev)) {
3206 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3207 }
3208 }
3209
3210 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3211 planea_wm, planeb_wm, cwm, srwm);
3212
3213 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3214 fwater_hi = (cwm & 0x1f);
3215
3216 /* Set request length to 8 cachelines per fetch */
3217 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3218 fwater_hi = fwater_hi | (1 << 8);
3219
3220 I915_WRITE(FW_BLC, fwater_lo);
3221 I915_WRITE(FW_BLC2, fwater_hi);
3222 }
3223
3224 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3225 int unused2, int unused3, int pixel_size)
3226 {
3227 struct drm_i915_private *dev_priv = dev->dev_private;
3228 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3229 int planea_wm;
3230
3231 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3232
3233 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3234 pixel_size, latency_ns);
3235 fwater_lo |= (3<<8) | planea_wm;
3236
3237 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3238
3239 I915_WRITE(FW_BLC, fwater_lo);
3240 }
3241
3242 #define ILK_LP0_PLANE_LATENCY 700
3243 #define ILK_LP0_CURSOR_LATENCY 1300
3244
3245 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3246 int planeb_clock, int sr_hdisplay, int sr_htotal,
3247 int pixel_size)
3248 {
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3251 int sr_wm, cursor_wm;
3252 unsigned long line_time_us;
3253 int sr_clock, entries_required;
3254 u32 reg_value;
3255 int line_count;
3256 int planea_htotal = 0, planeb_htotal = 0;
3257 struct drm_crtc *crtc;
3258 struct intel_crtc *intel_crtc;
3259
3260 /* Need htotal for all active display plane */
3261 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3262 intel_crtc = to_intel_crtc(crtc);
3263 if (crtc->enabled) {
3264 if (intel_crtc->plane == 0)
3265 planea_htotal = crtc->mode.htotal;
3266 else
3267 planeb_htotal = crtc->mode.htotal;
3268 }
3269 }
3270
3271 /* Calculate and update the watermark for plane A */
3272 if (planea_clock) {
3273 entries_required = ((planea_clock / 1000) * pixel_size *
3274 ILK_LP0_PLANE_LATENCY) / 1000;
3275 entries_required = DIV_ROUND_UP(entries_required,
3276 ironlake_display_wm_info.cacheline_size);
3277 planea_wm = entries_required +
3278 ironlake_display_wm_info.guard_size;
3279
3280 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3281 planea_wm = ironlake_display_wm_info.max_wm;
3282
3283 /* Use the large buffer method to calculate cursor watermark */
3284 line_time_us = (planea_htotal * 1000) / planea_clock;
3285
3286 /* Use ns/us then divide to preserve precision */
3287 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3288
3289 /* calculate the cursor watermark for cursor A */
3290 entries_required = line_count * 64 * pixel_size;
3291 entries_required = DIV_ROUND_UP(entries_required,
3292 ironlake_cursor_wm_info.cacheline_size);
3293 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3294 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3295 cursora_wm = ironlake_cursor_wm_info.max_wm;
3296
3297 reg_value = I915_READ(WM0_PIPEA_ILK);
3298 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3299 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3300 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3301 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3302 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3303 "cursor: %d\n", planea_wm, cursora_wm);
3304 }
3305 /* Calculate and update the watermark for plane B */
3306 if (planeb_clock) {
3307 entries_required = ((planeb_clock / 1000) * pixel_size *
3308 ILK_LP0_PLANE_LATENCY) / 1000;
3309 entries_required = DIV_ROUND_UP(entries_required,
3310 ironlake_display_wm_info.cacheline_size);
3311 planeb_wm = entries_required +
3312 ironlake_display_wm_info.guard_size;
3313
3314 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3315 planeb_wm = ironlake_display_wm_info.max_wm;
3316
3317 /* Use the large buffer method to calculate cursor watermark */
3318 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3319
3320 /* Use ns/us then divide to preserve precision */
3321 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3322
3323 /* calculate the cursor watermark for cursor B */
3324 entries_required = line_count * 64 * pixel_size;
3325 entries_required = DIV_ROUND_UP(entries_required,
3326 ironlake_cursor_wm_info.cacheline_size);
3327 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3328 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3329 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3330
3331 reg_value = I915_READ(WM0_PIPEB_ILK);
3332 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3333 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3334 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3335 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3336 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3337 "cursor: %d\n", planeb_wm, cursorb_wm);
3338 }
3339
3340 /*
3341 * Calculate and update the self-refresh watermark only when one
3342 * display plane is used.
3343 */
3344 if (!planea_clock || !planeb_clock) {
3345
3346 /* Read the self-refresh latency. The unit is 0.5us */
3347 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3348
3349 sr_clock = planea_clock ? planea_clock : planeb_clock;
3350 line_time_us = ((sr_htotal * 1000) / sr_clock);
3351
3352 /* Use ns/us then divide to preserve precision */
3353 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3354 / 1000;
3355
3356 /* calculate the self-refresh watermark for display plane */
3357 entries_required = line_count * sr_hdisplay * pixel_size;
3358 entries_required = DIV_ROUND_UP(entries_required,
3359 ironlake_display_srwm_info.cacheline_size);
3360 sr_wm = entries_required +
3361 ironlake_display_srwm_info.guard_size;
3362
3363 /* calculate the self-refresh watermark for display cursor */
3364 entries_required = line_count * pixel_size * 64;
3365 entries_required = DIV_ROUND_UP(entries_required,
3366 ironlake_cursor_srwm_info.cacheline_size);
3367 cursor_wm = entries_required +
3368 ironlake_cursor_srwm_info.guard_size;
3369
3370 /* configure watermark and enable self-refresh */
3371 reg_value = I915_READ(WM1_LP_ILK);
3372 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3373 WM1_LP_CURSOR_MASK);
3374 reg_value |= WM1_LP_SR_EN |
3375 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3376 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3377
3378 I915_WRITE(WM1_LP_ILK, reg_value);
3379 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3380 "cursor %d\n", sr_wm, cursor_wm);
3381
3382 } else {
3383 /* Turn off self refresh if both pipes are enabled */
3384 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3385 }
3386 }
3387 /**
3388 * intel_update_watermarks - update FIFO watermark values based on current modes
3389 *
3390 * Calculate watermark values for the various WM regs based on current mode
3391 * and plane configuration.
3392 *
3393 * There are several cases to deal with here:
3394 * - normal (i.e. non-self-refresh)
3395 * - self-refresh (SR) mode
3396 * - lines are large relative to FIFO size (buffer can hold up to 2)
3397 * - lines are small relative to FIFO size (buffer can hold more than 2
3398 * lines), so need to account for TLB latency
3399 *
3400 * The normal calculation is:
3401 * watermark = dotclock * bytes per pixel * latency
3402 * where latency is platform & configuration dependent (we assume pessimal
3403 * values here).
3404 *
3405 * The SR calculation is:
3406 * watermark = (trunc(latency/line time)+1) * surface width *
3407 * bytes per pixel
3408 * where
3409 * line time = htotal / dotclock
3410 * surface width = hdisplay for normal plane and 64 for cursor
3411 * and latency is assumed to be high, as above.
3412 *
3413 * The final value programmed to the register should always be rounded up,
3414 * and include an extra 2 entries to account for clock crossings.
3415 *
3416 * We don't use the sprite, so we can ignore that. And on Crestline we have
3417 * to set the non-SR watermarks to 8.
3418 */
3419 static void intel_update_watermarks(struct drm_device *dev)
3420 {
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct drm_crtc *crtc;
3423 struct intel_crtc *intel_crtc;
3424 int sr_hdisplay = 0;
3425 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3426 int enabled = 0, pixel_size = 0;
3427 int sr_htotal = 0;
3428
3429 if (!dev_priv->display.update_wm)
3430 return;
3431
3432 /* Get the clock config from both planes */
3433 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3434 intel_crtc = to_intel_crtc(crtc);
3435 if (crtc->enabled) {
3436 enabled++;
3437 if (intel_crtc->plane == 0) {
3438 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3439 intel_crtc->pipe, crtc->mode.clock);
3440 planea_clock = crtc->mode.clock;
3441 } else {
3442 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3443 intel_crtc->pipe, crtc->mode.clock);
3444 planeb_clock = crtc->mode.clock;
3445 }
3446 sr_hdisplay = crtc->mode.hdisplay;
3447 sr_clock = crtc->mode.clock;
3448 sr_htotal = crtc->mode.htotal;
3449 if (crtc->fb)
3450 pixel_size = crtc->fb->bits_per_pixel / 8;
3451 else
3452 pixel_size = 4; /* by default */
3453 }
3454 }
3455
3456 if (enabled <= 0)
3457 return;
3458
3459 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3460 sr_hdisplay, sr_htotal, pixel_size);
3461 }
3462
3463 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3464 struct drm_display_mode *mode,
3465 struct drm_display_mode *adjusted_mode,
3466 int x, int y,
3467 struct drm_framebuffer *old_fb)
3468 {
3469 struct drm_device *dev = crtc->dev;
3470 struct drm_i915_private *dev_priv = dev->dev_private;
3471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3472 int pipe = intel_crtc->pipe;
3473 int plane = intel_crtc->plane;
3474 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3475 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3476 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3477 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3478 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3479 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3480 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3481 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3482 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3483 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3484 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3485 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3486 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3487 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3488 int refclk, num_connectors = 0;
3489 intel_clock_t clock, reduced_clock;
3490 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3491 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3492 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3493 bool is_edp = false;
3494 struct drm_mode_config *mode_config = &dev->mode_config;
3495 struct drm_encoder *encoder;
3496 struct intel_encoder *intel_encoder = NULL;
3497 const intel_limit_t *limit;
3498 int ret;
3499 struct fdi_m_n m_n = {0};
3500 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3501 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3502 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3503 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3504 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3505 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3506 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3507 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3508 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3509 int lvds_reg = LVDS;
3510 u32 temp;
3511 int sdvo_pixel_multiply;
3512 int target_clock;
3513
3514 drm_vblank_pre_modeset(dev, pipe);
3515
3516 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3517
3518 if (!encoder || encoder->crtc != crtc)
3519 continue;
3520
3521 intel_encoder = enc_to_intel_encoder(encoder);
3522
3523 switch (intel_encoder->type) {
3524 case INTEL_OUTPUT_LVDS:
3525 is_lvds = true;
3526 break;
3527 case INTEL_OUTPUT_SDVO:
3528 case INTEL_OUTPUT_HDMI:
3529 is_sdvo = true;
3530 if (intel_encoder->needs_tv_clock)
3531 is_tv = true;
3532 break;
3533 case INTEL_OUTPUT_DVO:
3534 is_dvo = true;
3535 break;
3536 case INTEL_OUTPUT_TVOUT:
3537 is_tv = true;
3538 break;
3539 case INTEL_OUTPUT_ANALOG:
3540 is_crt = true;
3541 break;
3542 case INTEL_OUTPUT_DISPLAYPORT:
3543 is_dp = true;
3544 break;
3545 case INTEL_OUTPUT_EDP:
3546 is_edp = true;
3547 break;
3548 }
3549
3550 num_connectors++;
3551 }
3552
3553 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3554 refclk = dev_priv->lvds_ssc_freq * 1000;
3555 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3556 refclk / 1000);
3557 } else if (IS_I9XX(dev)) {
3558 refclk = 96000;
3559 if (HAS_PCH_SPLIT(dev))
3560 refclk = 120000; /* 120Mhz refclk */
3561 } else {
3562 refclk = 48000;
3563 }
3564
3565
3566 /*
3567 * Returns a set of divisors for the desired target clock with the given
3568 * refclk, or FALSE. The returned values represent the clock equation:
3569 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3570 */
3571 limit = intel_limit(crtc);
3572 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3573 if (!ok) {
3574 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3575 drm_vblank_post_modeset(dev, pipe);
3576 return -EINVAL;
3577 }
3578
3579 /* Ensure that the cursor is valid for the new mode before changing... */
3580 intel_crtc_update_cursor(crtc);
3581
3582 if (is_lvds && dev_priv->lvds_downclock_avail) {
3583 has_reduced_clock = limit->find_pll(limit, crtc,
3584 dev_priv->lvds_downclock,
3585 refclk,
3586 &reduced_clock);
3587 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3588 /*
3589 * If the different P is found, it means that we can't
3590 * switch the display clock by using the FP0/FP1.
3591 * In such case we will disable the LVDS downclock
3592 * feature.
3593 */
3594 DRM_DEBUG_KMS("Different P is found for "
3595 "LVDS clock/downclock\n");
3596 has_reduced_clock = 0;
3597 }
3598 }
3599 /* SDVO TV has fixed PLL values depend on its clock range,
3600 this mirrors vbios setting. */
3601 if (is_sdvo && is_tv) {
3602 if (adjusted_mode->clock >= 100000
3603 && adjusted_mode->clock < 140500) {
3604 clock.p1 = 2;
3605 clock.p2 = 10;
3606 clock.n = 3;
3607 clock.m1 = 16;
3608 clock.m2 = 8;
3609 } else if (adjusted_mode->clock >= 140500
3610 && adjusted_mode->clock <= 200000) {
3611 clock.p1 = 1;
3612 clock.p2 = 10;
3613 clock.n = 6;
3614 clock.m1 = 12;
3615 clock.m2 = 8;
3616 }
3617 }
3618
3619 /* FDI link */
3620 if (HAS_PCH_SPLIT(dev)) {
3621 int lane = 0, link_bw, bpp;
3622 /* eDP doesn't require FDI link, so just set DP M/N
3623 according to current link config */
3624 if (is_edp) {
3625 target_clock = mode->clock;
3626 intel_edp_link_config(intel_encoder,
3627 &lane, &link_bw);
3628 } else {
3629 /* DP over FDI requires target mode clock
3630 instead of link clock */
3631 if (is_dp)
3632 target_clock = mode->clock;
3633 else
3634 target_clock = adjusted_mode->clock;
3635 link_bw = 270000;
3636 }
3637
3638 /* determine panel color depth */
3639 temp = I915_READ(pipeconf_reg);
3640 temp &= ~PIPE_BPC_MASK;
3641 if (is_lvds) {
3642 int lvds_reg = I915_READ(PCH_LVDS);
3643 /* the BPC will be 6 if it is 18-bit LVDS panel */
3644 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3645 temp |= PIPE_8BPC;
3646 else
3647 temp |= PIPE_6BPC;
3648 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3649 switch (dev_priv->edp_bpp/3) {
3650 case 8:
3651 temp |= PIPE_8BPC;
3652 break;
3653 case 10:
3654 temp |= PIPE_10BPC;
3655 break;
3656 case 6:
3657 temp |= PIPE_6BPC;
3658 break;
3659 case 12:
3660 temp |= PIPE_12BPC;
3661 break;
3662 }
3663 } else
3664 temp |= PIPE_8BPC;
3665 I915_WRITE(pipeconf_reg, temp);
3666 I915_READ(pipeconf_reg);
3667
3668 switch (temp & PIPE_BPC_MASK) {
3669 case PIPE_8BPC:
3670 bpp = 24;
3671 break;
3672 case PIPE_10BPC:
3673 bpp = 30;
3674 break;
3675 case PIPE_6BPC:
3676 bpp = 18;
3677 break;
3678 case PIPE_12BPC:
3679 bpp = 36;
3680 break;
3681 default:
3682 DRM_ERROR("unknown pipe bpc value\n");
3683 bpp = 24;
3684 }
3685
3686 if (!lane) {
3687 /*
3688 * Account for spread spectrum to avoid
3689 * oversubscribing the link. Max center spread
3690 * is 2.5%; use 5% for safety's sake.
3691 */
3692 u32 bps = target_clock * bpp * 21 / 20;
3693 lane = bps / (link_bw * 8) + 1;
3694 }
3695
3696 intel_crtc->fdi_lanes = lane;
3697
3698 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3699 }
3700
3701 /* Ironlake: try to setup display ref clock before DPLL
3702 * enabling. This is only under driver's control after
3703 * PCH B stepping, previous chipset stepping should be
3704 * ignoring this setting.
3705 */
3706 if (HAS_PCH_SPLIT(dev)) {
3707 temp = I915_READ(PCH_DREF_CONTROL);
3708 /* Always enable nonspread source */
3709 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3710 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3711 I915_WRITE(PCH_DREF_CONTROL, temp);
3712 POSTING_READ(PCH_DREF_CONTROL);
3713
3714 temp &= ~DREF_SSC_SOURCE_MASK;
3715 temp |= DREF_SSC_SOURCE_ENABLE;
3716 I915_WRITE(PCH_DREF_CONTROL, temp);
3717 POSTING_READ(PCH_DREF_CONTROL);
3718
3719 udelay(200);
3720
3721 if (is_edp) {
3722 if (dev_priv->lvds_use_ssc) {
3723 temp |= DREF_SSC1_ENABLE;
3724 I915_WRITE(PCH_DREF_CONTROL, temp);
3725 POSTING_READ(PCH_DREF_CONTROL);
3726
3727 udelay(200);
3728
3729 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3730 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3731 I915_WRITE(PCH_DREF_CONTROL, temp);
3732 POSTING_READ(PCH_DREF_CONTROL);
3733 } else {
3734 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3735 I915_WRITE(PCH_DREF_CONTROL, temp);
3736 POSTING_READ(PCH_DREF_CONTROL);
3737 }
3738 }
3739 }
3740
3741 if (IS_PINEVIEW(dev)) {
3742 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3743 if (has_reduced_clock)
3744 fp2 = (1 << reduced_clock.n) << 16 |
3745 reduced_clock.m1 << 8 | reduced_clock.m2;
3746 } else {
3747 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3748 if (has_reduced_clock)
3749 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3750 reduced_clock.m2;
3751 }
3752
3753 if (!HAS_PCH_SPLIT(dev))
3754 dpll = DPLL_VGA_MODE_DIS;
3755
3756 if (IS_I9XX(dev)) {
3757 if (is_lvds)
3758 dpll |= DPLLB_MODE_LVDS;
3759 else
3760 dpll |= DPLLB_MODE_DAC_SERIAL;
3761 if (is_sdvo) {
3762 dpll |= DPLL_DVO_HIGH_SPEED;
3763 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3764 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3765 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3766 else if (HAS_PCH_SPLIT(dev))
3767 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3768 }
3769 if (is_dp)
3770 dpll |= DPLL_DVO_HIGH_SPEED;
3771
3772 /* compute bitmask from p1 value */
3773 if (IS_PINEVIEW(dev))
3774 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3775 else {
3776 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3777 /* also FPA1 */
3778 if (HAS_PCH_SPLIT(dev))
3779 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3780 if (IS_G4X(dev) && has_reduced_clock)
3781 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3782 }
3783 switch (clock.p2) {
3784 case 5:
3785 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3786 break;
3787 case 7:
3788 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3789 break;
3790 case 10:
3791 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3792 break;
3793 case 14:
3794 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3795 break;
3796 }
3797 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3798 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3799 } else {
3800 if (is_lvds) {
3801 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3802 } else {
3803 if (clock.p1 == 2)
3804 dpll |= PLL_P1_DIVIDE_BY_TWO;
3805 else
3806 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3807 if (clock.p2 == 4)
3808 dpll |= PLL_P2_DIVIDE_BY_4;
3809 }
3810 }
3811
3812 if (is_sdvo && is_tv)
3813 dpll |= PLL_REF_INPUT_TVCLKINBC;
3814 else if (is_tv)
3815 /* XXX: just matching BIOS for now */
3816 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3817 dpll |= 3;
3818 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3819 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3820 else
3821 dpll |= PLL_REF_INPUT_DREFCLK;
3822
3823 /* setup pipeconf */
3824 pipeconf = I915_READ(pipeconf_reg);
3825
3826 /* Set up the display plane register */
3827 dspcntr = DISPPLANE_GAMMA_ENABLE;
3828
3829 /* Ironlake's plane is forced to pipe, bit 24 is to
3830 enable color space conversion */
3831 if (!HAS_PCH_SPLIT(dev)) {
3832 if (pipe == 0)
3833 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3834 else
3835 dspcntr |= DISPPLANE_SEL_PIPE_B;
3836 }
3837
3838 if (pipe == 0 && !IS_I965G(dev)) {
3839 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3840 * core speed.
3841 *
3842 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3843 * pipe == 0 check?
3844 */
3845 if (mode->clock >
3846 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3847 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3848 else
3849 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3850 }
3851
3852 dspcntr |= DISPLAY_PLANE_ENABLE;
3853 pipeconf |= PIPEACONF_ENABLE;
3854 dpll |= DPLL_VCO_ENABLE;
3855
3856
3857 /* Disable the panel fitter if it was on our pipe */
3858 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3859 I915_WRITE(PFIT_CONTROL, 0);
3860
3861 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3862 drm_mode_debug_printmodeline(mode);
3863
3864 /* assign to Ironlake registers */
3865 if (HAS_PCH_SPLIT(dev)) {
3866 fp_reg = pch_fp_reg;
3867 dpll_reg = pch_dpll_reg;
3868 }
3869
3870 if (is_edp) {
3871 ironlake_disable_pll_edp(crtc);
3872 } else if ((dpll & DPLL_VCO_ENABLE)) {
3873 I915_WRITE(fp_reg, fp);
3874 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3875 I915_READ(dpll_reg);
3876 udelay(150);
3877 }
3878
3879 /* enable transcoder DPLL */
3880 if (HAS_PCH_CPT(dev)) {
3881 temp = I915_READ(PCH_DPLL_SEL);
3882 if (trans_dpll_sel == 0)
3883 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3884 else
3885 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3886 I915_WRITE(PCH_DPLL_SEL, temp);
3887 I915_READ(PCH_DPLL_SEL);
3888 udelay(150);
3889 }
3890
3891 if (HAS_PCH_SPLIT(dev)) {
3892 pipeconf &= ~PIPE_ENABLE_DITHER;
3893 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3894 }
3895
3896 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3897 * This is an exception to the general rule that mode_set doesn't turn
3898 * things on.
3899 */
3900 if (is_lvds) {
3901 u32 lvds;
3902
3903 if (HAS_PCH_SPLIT(dev))
3904 lvds_reg = PCH_LVDS;
3905
3906 lvds = I915_READ(lvds_reg);
3907 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3908 if (pipe == 1) {
3909 if (HAS_PCH_CPT(dev))
3910 lvds |= PORT_TRANS_B_SEL_CPT;
3911 else
3912 lvds |= LVDS_PIPEB_SELECT;
3913 } else {
3914 if (HAS_PCH_CPT(dev))
3915 lvds &= ~PORT_TRANS_SEL_MASK;
3916 else
3917 lvds &= ~LVDS_PIPEB_SELECT;
3918 }
3919 /* set the corresponsding LVDS_BORDER bit */
3920 lvds |= dev_priv->lvds_border_bits;
3921 /* Set the B0-B3 data pairs corresponding to whether we're going to
3922 * set the DPLLs for dual-channel mode or not.
3923 */
3924 if (clock.p2 == 7)
3925 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3926 else
3927 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3928
3929 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3930 * appropriately here, but we need to look more thoroughly into how
3931 * panels behave in the two modes.
3932 */
3933 /* set the dithering flag */
3934 if (IS_I965G(dev)) {
3935 if (dev_priv->lvds_dither) {
3936 if (HAS_PCH_SPLIT(dev)) {
3937 pipeconf |= PIPE_ENABLE_DITHER;
3938 pipeconf |= PIPE_DITHER_TYPE_ST01;
3939 } else
3940 lvds |= LVDS_ENABLE_DITHER;
3941 } else {
3942 if (!HAS_PCH_SPLIT(dev)) {
3943 lvds &= ~LVDS_ENABLE_DITHER;
3944 }
3945 }
3946 }
3947 I915_WRITE(lvds_reg, lvds);
3948 I915_READ(lvds_reg);
3949 }
3950 if (is_dp)
3951 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3952 else if (HAS_PCH_SPLIT(dev)) {
3953 /* For non-DP output, clear any trans DP clock recovery setting.*/
3954 if (pipe == 0) {
3955 I915_WRITE(TRANSA_DATA_M1, 0);
3956 I915_WRITE(TRANSA_DATA_N1, 0);
3957 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3958 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3959 } else {
3960 I915_WRITE(TRANSB_DATA_M1, 0);
3961 I915_WRITE(TRANSB_DATA_N1, 0);
3962 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3963 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3964 }
3965 }
3966
3967 if (!is_edp) {
3968 I915_WRITE(fp_reg, fp);
3969 I915_WRITE(dpll_reg, dpll);
3970 I915_READ(dpll_reg);
3971 /* Wait for the clocks to stabilize. */
3972 udelay(150);
3973
3974 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3975 if (is_sdvo) {
3976 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3977 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3978 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3979 } else
3980 I915_WRITE(dpll_md_reg, 0);
3981 } else {
3982 /* write it again -- the BIOS does, after all */
3983 I915_WRITE(dpll_reg, dpll);
3984 }
3985 I915_READ(dpll_reg);
3986 /* Wait for the clocks to stabilize. */
3987 udelay(150);
3988 }
3989
3990 if (is_lvds && has_reduced_clock && i915_powersave) {
3991 I915_WRITE(fp_reg + 4, fp2);
3992 intel_crtc->lowfreq_avail = true;
3993 if (HAS_PIPE_CXSR(dev)) {
3994 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3995 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3996 }
3997 } else {
3998 I915_WRITE(fp_reg + 4, fp);
3999 intel_crtc->lowfreq_avail = false;
4000 if (HAS_PIPE_CXSR(dev)) {
4001 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4002 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4003 }
4004 }
4005
4006 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4007 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4008 /* the chip adds 2 halflines automatically */
4009 adjusted_mode->crtc_vdisplay -= 1;
4010 adjusted_mode->crtc_vtotal -= 1;
4011 adjusted_mode->crtc_vblank_start -= 1;
4012 adjusted_mode->crtc_vblank_end -= 1;
4013 adjusted_mode->crtc_vsync_end -= 1;
4014 adjusted_mode->crtc_vsync_start -= 1;
4015 } else
4016 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4017
4018 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4019 ((adjusted_mode->crtc_htotal - 1) << 16));
4020 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4021 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4022 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4023 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4024 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4025 ((adjusted_mode->crtc_vtotal - 1) << 16));
4026 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4027 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4028 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4029 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4030 /* pipesrc and dspsize control the size that is scaled from, which should
4031 * always be the user's requested size.
4032 */
4033 if (!HAS_PCH_SPLIT(dev)) {
4034 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4035 (mode->hdisplay - 1));
4036 I915_WRITE(dsppos_reg, 0);
4037 }
4038 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4039
4040 if (HAS_PCH_SPLIT(dev)) {
4041 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4042 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4043 I915_WRITE(link_m1_reg, m_n.link_m);
4044 I915_WRITE(link_n1_reg, m_n.link_n);
4045
4046 if (is_edp) {
4047 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4048 } else {
4049 /* enable FDI RX PLL too */
4050 temp = I915_READ(fdi_rx_reg);
4051 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4052 I915_READ(fdi_rx_reg);
4053 udelay(200);
4054
4055 /* enable FDI TX PLL too */
4056 temp = I915_READ(fdi_tx_reg);
4057 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4058 I915_READ(fdi_tx_reg);
4059
4060 /* enable FDI RX PCDCLK */
4061 temp = I915_READ(fdi_rx_reg);
4062 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4063 I915_READ(fdi_rx_reg);
4064 udelay(200);
4065 }
4066 }
4067
4068 I915_WRITE(pipeconf_reg, pipeconf);
4069 I915_READ(pipeconf_reg);
4070
4071 intel_wait_for_vblank(dev);
4072
4073 if (IS_IRONLAKE(dev)) {
4074 /* enable address swizzle for tiling buffer */
4075 temp = I915_READ(DISP_ARB_CTL);
4076 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4077 }
4078
4079 I915_WRITE(dspcntr_reg, dspcntr);
4080
4081 /* Flush the plane changes */
4082 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4083
4084 if ((IS_I965G(dev) || plane == 0))
4085 intel_update_fbc(crtc, &crtc->mode);
4086
4087 intel_update_watermarks(dev);
4088
4089 drm_vblank_post_modeset(dev, pipe);
4090
4091 return ret;
4092 }
4093
4094 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4095 void intel_crtc_load_lut(struct drm_crtc *crtc)
4096 {
4097 struct drm_device *dev = crtc->dev;
4098 struct drm_i915_private *dev_priv = dev->dev_private;
4099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4100 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4101 int i;
4102
4103 /* The clocks have to be on to load the palette. */
4104 if (!crtc->enabled)
4105 return;
4106
4107 /* use legacy palette for Ironlake */
4108 if (HAS_PCH_SPLIT(dev))
4109 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4110 LGC_PALETTE_B;
4111
4112 for (i = 0; i < 256; i++) {
4113 I915_WRITE(palreg + 4 * i,
4114 (intel_crtc->lut_r[i] << 16) |
4115 (intel_crtc->lut_g[i] << 8) |
4116 intel_crtc->lut_b[i]);
4117 }
4118 }
4119
4120 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4121 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4122 {
4123 struct drm_device *dev = crtc->dev;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4126 int pipe = intel_crtc->pipe;
4127 int x = intel_crtc->cursor_x;
4128 int y = intel_crtc->cursor_y;
4129 uint32_t base, pos;
4130 bool visible;
4131
4132 pos = 0;
4133
4134 if (crtc->fb) {
4135 base = intel_crtc->cursor_addr;
4136 if (x > (int) crtc->fb->width)
4137 base = 0;
4138
4139 if (y > (int) crtc->fb->height)
4140 base = 0;
4141 } else
4142 base = 0;
4143
4144 if (x < 0) {
4145 if (x + intel_crtc->cursor_width < 0)
4146 base = 0;
4147
4148 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4149 x = -x;
4150 }
4151 pos |= x << CURSOR_X_SHIFT;
4152
4153 if (y < 0) {
4154 if (y + intel_crtc->cursor_height < 0)
4155 base = 0;
4156
4157 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4158 y = -y;
4159 }
4160 pos |= y << CURSOR_Y_SHIFT;
4161
4162 visible = base != 0;
4163 if (!visible && !intel_crtc->cursor_visble)
4164 return;
4165
4166 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4167 if (intel_crtc->cursor_visble != visible) {
4168 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4169 if (base) {
4170 /* Hooray for CUR*CNTR differences */
4171 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4172 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4173 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4174 cntl |= pipe << 28; /* Connect to correct pipe */
4175 } else {
4176 cntl &= ~(CURSOR_FORMAT_MASK);
4177 cntl |= CURSOR_ENABLE;
4178 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4179 }
4180 } else {
4181 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4182 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4183 cntl |= CURSOR_MODE_DISABLE;
4184 } else {
4185 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4186 }
4187 }
4188 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4189
4190 intel_crtc->cursor_visble = visible;
4191 }
4192 /* and commit changes on next vblank */
4193 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4194
4195 if (visible)
4196 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4197 }
4198
4199 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4200 struct drm_file *file_priv,
4201 uint32_t handle,
4202 uint32_t width, uint32_t height)
4203 {
4204 struct drm_device *dev = crtc->dev;
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4207 struct drm_gem_object *bo;
4208 struct drm_i915_gem_object *obj_priv;
4209 uint32_t addr;
4210 int ret;
4211
4212 DRM_DEBUG_KMS("\n");
4213
4214 /* if we want to turn off the cursor ignore width and height */
4215 if (!handle) {
4216 DRM_DEBUG_KMS("cursor off\n");
4217 addr = 0;
4218 bo = NULL;
4219 mutex_lock(&dev->struct_mutex);
4220 goto finish;
4221 }
4222
4223 /* Currently we only support 64x64 cursors */
4224 if (width != 64 || height != 64) {
4225 DRM_ERROR("we currently only support 64x64 cursors\n");
4226 return -EINVAL;
4227 }
4228
4229 bo = drm_gem_object_lookup(dev, file_priv, handle);
4230 if (!bo)
4231 return -ENOENT;
4232
4233 obj_priv = to_intel_bo(bo);
4234
4235 if (bo->size < width * height * 4) {
4236 DRM_ERROR("buffer is to small\n");
4237 ret = -ENOMEM;
4238 goto fail;
4239 }
4240
4241 /* we only need to pin inside GTT if cursor is non-phy */
4242 mutex_lock(&dev->struct_mutex);
4243 if (!dev_priv->info->cursor_needs_physical) {
4244 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4245 if (ret) {
4246 DRM_ERROR("failed to pin cursor bo\n");
4247 goto fail_locked;
4248 }
4249
4250 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4251 if (ret) {
4252 DRM_ERROR("failed to move cursor bo into the GTT\n");
4253 goto fail_unpin;
4254 }
4255
4256 addr = obj_priv->gtt_offset;
4257 } else {
4258 ret = i915_gem_attach_phys_object(dev, bo,
4259 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4260 if (ret) {
4261 DRM_ERROR("failed to attach phys object\n");
4262 goto fail_locked;
4263 }
4264 addr = obj_priv->phys_obj->handle->busaddr;
4265 }
4266
4267 if (!IS_I9XX(dev))
4268 I915_WRITE(CURSIZE, (height << 12) | width);
4269
4270 finish:
4271 if (intel_crtc->cursor_bo) {
4272 if (dev_priv->info->cursor_needs_physical) {
4273 if (intel_crtc->cursor_bo != bo)
4274 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4275 } else
4276 i915_gem_object_unpin(intel_crtc->cursor_bo);
4277 drm_gem_object_unreference(intel_crtc->cursor_bo);
4278 }
4279
4280 mutex_unlock(&dev->struct_mutex);
4281
4282 intel_crtc->cursor_addr = addr;
4283 intel_crtc->cursor_bo = bo;
4284 intel_crtc->cursor_width = width;
4285 intel_crtc->cursor_height = height;
4286
4287 intel_crtc_update_cursor(crtc);
4288
4289 return 0;
4290 fail_unpin:
4291 i915_gem_object_unpin(bo);
4292 fail_locked:
4293 mutex_unlock(&dev->struct_mutex);
4294 fail:
4295 drm_gem_object_unreference_unlocked(bo);
4296 return ret;
4297 }
4298
4299 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4300 {
4301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4302
4303 intel_crtc->cursor_x = x;
4304 intel_crtc->cursor_y = y;
4305
4306 intel_crtc_update_cursor(crtc);
4307
4308 return 0;
4309 }
4310
4311 /** Sets the color ramps on behalf of RandR */
4312 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4313 u16 blue, int regno)
4314 {
4315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4316
4317 intel_crtc->lut_r[regno] = red >> 8;
4318 intel_crtc->lut_g[regno] = green >> 8;
4319 intel_crtc->lut_b[regno] = blue >> 8;
4320 }
4321
4322 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4323 u16 *blue, int regno)
4324 {
4325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4326
4327 *red = intel_crtc->lut_r[regno] << 8;
4328 *green = intel_crtc->lut_g[regno] << 8;
4329 *blue = intel_crtc->lut_b[regno] << 8;
4330 }
4331
4332 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4333 u16 *blue, uint32_t start, uint32_t size)
4334 {
4335 int end = (start + size > 256) ? 256 : start + size, i;
4336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4337
4338 for (i = start; i < end; i++) {
4339 intel_crtc->lut_r[i] = red[i] >> 8;
4340 intel_crtc->lut_g[i] = green[i] >> 8;
4341 intel_crtc->lut_b[i] = blue[i] >> 8;
4342 }
4343
4344 intel_crtc_load_lut(crtc);
4345 }
4346
4347 /**
4348 * Get a pipe with a simple mode set on it for doing load-based monitor
4349 * detection.
4350 *
4351 * It will be up to the load-detect code to adjust the pipe as appropriate for
4352 * its requirements. The pipe will be connected to no other encoders.
4353 *
4354 * Currently this code will only succeed if there is a pipe with no encoders
4355 * configured for it. In the future, it could choose to temporarily disable
4356 * some outputs to free up a pipe for its use.
4357 *
4358 * \return crtc, or NULL if no pipes are available.
4359 */
4360
4361 /* VESA 640x480x72Hz mode to set on the pipe */
4362 static struct drm_display_mode load_detect_mode = {
4363 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4364 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4365 };
4366
4367 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4368 struct drm_connector *connector,
4369 struct drm_display_mode *mode,
4370 int *dpms_mode)
4371 {
4372 struct intel_crtc *intel_crtc;
4373 struct drm_crtc *possible_crtc;
4374 struct drm_crtc *supported_crtc =NULL;
4375 struct drm_encoder *encoder = &intel_encoder->enc;
4376 struct drm_crtc *crtc = NULL;
4377 struct drm_device *dev = encoder->dev;
4378 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4379 struct drm_crtc_helper_funcs *crtc_funcs;
4380 int i = -1;
4381
4382 /*
4383 * Algorithm gets a little messy:
4384 * - if the connector already has an assigned crtc, use it (but make
4385 * sure it's on first)
4386 * - try to find the first unused crtc that can drive this connector,
4387 * and use that if we find one
4388 * - if there are no unused crtcs available, try to use the first
4389 * one we found that supports the connector
4390 */
4391
4392 /* See if we already have a CRTC for this connector */
4393 if (encoder->crtc) {
4394 crtc = encoder->crtc;
4395 /* Make sure the crtc and connector are running */
4396 intel_crtc = to_intel_crtc(crtc);
4397 *dpms_mode = intel_crtc->dpms_mode;
4398 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4399 crtc_funcs = crtc->helper_private;
4400 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4401 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4402 }
4403 return crtc;
4404 }
4405
4406 /* Find an unused one (if possible) */
4407 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4408 i++;
4409 if (!(encoder->possible_crtcs & (1 << i)))
4410 continue;
4411 if (!possible_crtc->enabled) {
4412 crtc = possible_crtc;
4413 break;
4414 }
4415 if (!supported_crtc)
4416 supported_crtc = possible_crtc;
4417 }
4418
4419 /*
4420 * If we didn't find an unused CRTC, don't use any.
4421 */
4422 if (!crtc) {
4423 return NULL;
4424 }
4425
4426 encoder->crtc = crtc;
4427 connector->encoder = encoder;
4428 intel_encoder->load_detect_temp = true;
4429
4430 intel_crtc = to_intel_crtc(crtc);
4431 *dpms_mode = intel_crtc->dpms_mode;
4432
4433 if (!crtc->enabled) {
4434 if (!mode)
4435 mode = &load_detect_mode;
4436 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4437 } else {
4438 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4439 crtc_funcs = crtc->helper_private;
4440 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4441 }
4442
4443 /* Add this connector to the crtc */
4444 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4445 encoder_funcs->commit(encoder);
4446 }
4447 /* let the connector get through one full cycle before testing */
4448 intel_wait_for_vblank(dev);
4449
4450 return crtc;
4451 }
4452
4453 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4454 struct drm_connector *connector, int dpms_mode)
4455 {
4456 struct drm_encoder *encoder = &intel_encoder->enc;
4457 struct drm_device *dev = encoder->dev;
4458 struct drm_crtc *crtc = encoder->crtc;
4459 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4460 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4461
4462 if (intel_encoder->load_detect_temp) {
4463 encoder->crtc = NULL;
4464 connector->encoder = NULL;
4465 intel_encoder->load_detect_temp = false;
4466 crtc->enabled = drm_helper_crtc_in_use(crtc);
4467 drm_helper_disable_unused_functions(dev);
4468 }
4469
4470 /* Switch crtc and encoder back off if necessary */
4471 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4472 if (encoder->crtc == crtc)
4473 encoder_funcs->dpms(encoder, dpms_mode);
4474 crtc_funcs->dpms(crtc, dpms_mode);
4475 }
4476 }
4477
4478 /* Returns the clock of the currently programmed mode of the given pipe. */
4479 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4480 {
4481 struct drm_i915_private *dev_priv = dev->dev_private;
4482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4483 int pipe = intel_crtc->pipe;
4484 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4485 u32 fp;
4486 intel_clock_t clock;
4487
4488 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4489 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4490 else
4491 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4492
4493 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4494 if (IS_PINEVIEW(dev)) {
4495 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4496 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4497 } else {
4498 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4499 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4500 }
4501
4502 if (IS_I9XX(dev)) {
4503 if (IS_PINEVIEW(dev))
4504 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4505 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4506 else
4507 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4508 DPLL_FPA01_P1_POST_DIV_SHIFT);
4509
4510 switch (dpll & DPLL_MODE_MASK) {
4511 case DPLLB_MODE_DAC_SERIAL:
4512 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4513 5 : 10;
4514 break;
4515 case DPLLB_MODE_LVDS:
4516 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4517 7 : 14;
4518 break;
4519 default:
4520 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4521 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4522 return 0;
4523 }
4524
4525 /* XXX: Handle the 100Mhz refclk */
4526 intel_clock(dev, 96000, &clock);
4527 } else {
4528 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4529
4530 if (is_lvds) {
4531 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4532 DPLL_FPA01_P1_POST_DIV_SHIFT);
4533 clock.p2 = 14;
4534
4535 if ((dpll & PLL_REF_INPUT_MASK) ==
4536 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4537 /* XXX: might not be 66MHz */
4538 intel_clock(dev, 66000, &clock);
4539 } else
4540 intel_clock(dev, 48000, &clock);
4541 } else {
4542 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4543 clock.p1 = 2;
4544 else {
4545 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4546 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4547 }
4548 if (dpll & PLL_P2_DIVIDE_BY_4)
4549 clock.p2 = 4;
4550 else
4551 clock.p2 = 2;
4552
4553 intel_clock(dev, 48000, &clock);
4554 }
4555 }
4556
4557 /* XXX: It would be nice to validate the clocks, but we can't reuse
4558 * i830PllIsValid() because it relies on the xf86_config connector
4559 * configuration being accurate, which it isn't necessarily.
4560 */
4561
4562 return clock.dot;
4563 }
4564
4565 /** Returns the currently programmed mode of the given pipe. */
4566 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4567 struct drm_crtc *crtc)
4568 {
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4571 int pipe = intel_crtc->pipe;
4572 struct drm_display_mode *mode;
4573 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4574 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4575 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4576 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4577
4578 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4579 if (!mode)
4580 return NULL;
4581
4582 mode->clock = intel_crtc_clock_get(dev, crtc);
4583 mode->hdisplay = (htot & 0xffff) + 1;
4584 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4585 mode->hsync_start = (hsync & 0xffff) + 1;
4586 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4587 mode->vdisplay = (vtot & 0xffff) + 1;
4588 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4589 mode->vsync_start = (vsync & 0xffff) + 1;
4590 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4591
4592 drm_mode_set_name(mode);
4593 drm_mode_set_crtcinfo(mode, 0);
4594
4595 return mode;
4596 }
4597
4598 #define GPU_IDLE_TIMEOUT 500 /* ms */
4599
4600 /* When this timer fires, we've been idle for awhile */
4601 static void intel_gpu_idle_timer(unsigned long arg)
4602 {
4603 struct drm_device *dev = (struct drm_device *)arg;
4604 drm_i915_private_t *dev_priv = dev->dev_private;
4605
4606 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4607
4608 dev_priv->busy = false;
4609
4610 queue_work(dev_priv->wq, &dev_priv->idle_work);
4611 }
4612
4613 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4614
4615 static void intel_crtc_idle_timer(unsigned long arg)
4616 {
4617 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4618 struct drm_crtc *crtc = &intel_crtc->base;
4619 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4620
4621 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4622
4623 intel_crtc->busy = false;
4624
4625 queue_work(dev_priv->wq, &dev_priv->idle_work);
4626 }
4627
4628 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4629 {
4630 struct drm_device *dev = crtc->dev;
4631 drm_i915_private_t *dev_priv = dev->dev_private;
4632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4633 int pipe = intel_crtc->pipe;
4634 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4635 int dpll = I915_READ(dpll_reg);
4636
4637 if (HAS_PCH_SPLIT(dev))
4638 return;
4639
4640 if (!dev_priv->lvds_downclock_avail)
4641 return;
4642
4643 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4644 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4645
4646 /* Unlock panel regs */
4647 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4648 PANEL_UNLOCK_REGS);
4649
4650 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4651 I915_WRITE(dpll_reg, dpll);
4652 dpll = I915_READ(dpll_reg);
4653 intel_wait_for_vblank(dev);
4654 dpll = I915_READ(dpll_reg);
4655 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4656 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4657
4658 /* ...and lock them again */
4659 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4660 }
4661
4662 /* Schedule downclock */
4663 if (schedule)
4664 mod_timer(&intel_crtc->idle_timer, jiffies +
4665 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4666 }
4667
4668 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4669 {
4670 struct drm_device *dev = crtc->dev;
4671 drm_i915_private_t *dev_priv = dev->dev_private;
4672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4673 int pipe = intel_crtc->pipe;
4674 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4675 int dpll = I915_READ(dpll_reg);
4676
4677 if (HAS_PCH_SPLIT(dev))
4678 return;
4679
4680 if (!dev_priv->lvds_downclock_avail)
4681 return;
4682
4683 /*
4684 * Since this is called by a timer, we should never get here in
4685 * the manual case.
4686 */
4687 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4688 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4689
4690 /* Unlock panel regs */
4691 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4692 PANEL_UNLOCK_REGS);
4693
4694 dpll |= DISPLAY_RATE_SELECT_FPA1;
4695 I915_WRITE(dpll_reg, dpll);
4696 dpll = I915_READ(dpll_reg);
4697 intel_wait_for_vblank(dev);
4698 dpll = I915_READ(dpll_reg);
4699 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4700 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4701
4702 /* ...and lock them again */
4703 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4704 }
4705
4706 }
4707
4708 /**
4709 * intel_idle_update - adjust clocks for idleness
4710 * @work: work struct
4711 *
4712 * Either the GPU or display (or both) went idle. Check the busy status
4713 * here and adjust the CRTC and GPU clocks as necessary.
4714 */
4715 static void intel_idle_update(struct work_struct *work)
4716 {
4717 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4718 idle_work);
4719 struct drm_device *dev = dev_priv->dev;
4720 struct drm_crtc *crtc;
4721 struct intel_crtc *intel_crtc;
4722 int enabled = 0;
4723
4724 if (!i915_powersave)
4725 return;
4726
4727 mutex_lock(&dev->struct_mutex);
4728
4729 i915_update_gfx_val(dev_priv);
4730
4731 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4732 /* Skip inactive CRTCs */
4733 if (!crtc->fb)
4734 continue;
4735
4736 enabled++;
4737 intel_crtc = to_intel_crtc(crtc);
4738 if (!intel_crtc->busy)
4739 intel_decrease_pllclock(crtc);
4740 }
4741
4742 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4743 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4744 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4745 }
4746
4747 mutex_unlock(&dev->struct_mutex);
4748 }
4749
4750 /**
4751 * intel_mark_busy - mark the GPU and possibly the display busy
4752 * @dev: drm device
4753 * @obj: object we're operating on
4754 *
4755 * Callers can use this function to indicate that the GPU is busy processing
4756 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4757 * buffer), we'll also mark the display as busy, so we know to increase its
4758 * clock frequency.
4759 */
4760 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4761 {
4762 drm_i915_private_t *dev_priv = dev->dev_private;
4763 struct drm_crtc *crtc = NULL;
4764 struct intel_framebuffer *intel_fb;
4765 struct intel_crtc *intel_crtc;
4766
4767 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4768 return;
4769
4770 if (!dev_priv->busy) {
4771 if (IS_I945G(dev) || IS_I945GM(dev)) {
4772 u32 fw_blc_self;
4773
4774 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4775 fw_blc_self = I915_READ(FW_BLC_SELF);
4776 fw_blc_self &= ~FW_BLC_SELF_EN;
4777 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4778 }
4779 dev_priv->busy = true;
4780 } else
4781 mod_timer(&dev_priv->idle_timer, jiffies +
4782 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4783
4784 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4785 if (!crtc->fb)
4786 continue;
4787
4788 intel_crtc = to_intel_crtc(crtc);
4789 intel_fb = to_intel_framebuffer(crtc->fb);
4790 if (intel_fb->obj == obj) {
4791 if (!intel_crtc->busy) {
4792 if (IS_I945G(dev) || IS_I945GM(dev)) {
4793 u32 fw_blc_self;
4794
4795 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4796 fw_blc_self = I915_READ(FW_BLC_SELF);
4797 fw_blc_self &= ~FW_BLC_SELF_EN;
4798 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4799 }
4800 /* Non-busy -> busy, upclock */
4801 intel_increase_pllclock(crtc, true);
4802 intel_crtc->busy = true;
4803 } else {
4804 /* Busy -> busy, put off timer */
4805 mod_timer(&intel_crtc->idle_timer, jiffies +
4806 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4807 }
4808 }
4809 }
4810 }
4811
4812 static void intel_crtc_destroy(struct drm_crtc *crtc)
4813 {
4814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4815
4816 drm_crtc_cleanup(crtc);
4817 kfree(intel_crtc);
4818 }
4819
4820 struct intel_unpin_work {
4821 struct work_struct work;
4822 struct drm_device *dev;
4823 struct drm_gem_object *old_fb_obj;
4824 struct drm_gem_object *pending_flip_obj;
4825 struct drm_pending_vblank_event *event;
4826 int pending;
4827 };
4828
4829 static void intel_unpin_work_fn(struct work_struct *__work)
4830 {
4831 struct intel_unpin_work *work =
4832 container_of(__work, struct intel_unpin_work, work);
4833
4834 mutex_lock(&work->dev->struct_mutex);
4835 i915_gem_object_unpin(work->old_fb_obj);
4836 drm_gem_object_unreference(work->pending_flip_obj);
4837 drm_gem_object_unreference(work->old_fb_obj);
4838 mutex_unlock(&work->dev->struct_mutex);
4839 kfree(work);
4840 }
4841
4842 static void do_intel_finish_page_flip(struct drm_device *dev,
4843 struct drm_crtc *crtc)
4844 {
4845 drm_i915_private_t *dev_priv = dev->dev_private;
4846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4847 struct intel_unpin_work *work;
4848 struct drm_i915_gem_object *obj_priv;
4849 struct drm_pending_vblank_event *e;
4850 struct timeval now;
4851 unsigned long flags;
4852
4853 /* Ignore early vblank irqs */
4854 if (intel_crtc == NULL)
4855 return;
4856
4857 spin_lock_irqsave(&dev->event_lock, flags);
4858 work = intel_crtc->unpin_work;
4859 if (work == NULL || !work->pending) {
4860 spin_unlock_irqrestore(&dev->event_lock, flags);
4861 return;
4862 }
4863
4864 intel_crtc->unpin_work = NULL;
4865 drm_vblank_put(dev, intel_crtc->pipe);
4866
4867 if (work->event) {
4868 e = work->event;
4869 do_gettimeofday(&now);
4870 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4871 e->event.tv_sec = now.tv_sec;
4872 e->event.tv_usec = now.tv_usec;
4873 list_add_tail(&e->base.link,
4874 &e->base.file_priv->event_list);
4875 wake_up_interruptible(&e->base.file_priv->event_wait);
4876 }
4877
4878 spin_unlock_irqrestore(&dev->event_lock, flags);
4879
4880 obj_priv = to_intel_bo(work->pending_flip_obj);
4881
4882 /* Initial scanout buffer will have a 0 pending flip count */
4883 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4884 atomic_dec_and_test(&obj_priv->pending_flip))
4885 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4886 schedule_work(&work->work);
4887
4888 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4889 }
4890
4891 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4892 {
4893 drm_i915_private_t *dev_priv = dev->dev_private;
4894 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4895
4896 do_intel_finish_page_flip(dev, crtc);
4897 }
4898
4899 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4900 {
4901 drm_i915_private_t *dev_priv = dev->dev_private;
4902 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4903
4904 do_intel_finish_page_flip(dev, crtc);
4905 }
4906
4907 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4908 {
4909 drm_i915_private_t *dev_priv = dev->dev_private;
4910 struct intel_crtc *intel_crtc =
4911 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4912 unsigned long flags;
4913
4914 spin_lock_irqsave(&dev->event_lock, flags);
4915 if (intel_crtc->unpin_work) {
4916 intel_crtc->unpin_work->pending = 1;
4917 } else {
4918 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4919 }
4920 spin_unlock_irqrestore(&dev->event_lock, flags);
4921 }
4922
4923 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4924 struct drm_framebuffer *fb,
4925 struct drm_pending_vblank_event *event)
4926 {
4927 struct drm_device *dev = crtc->dev;
4928 struct drm_i915_private *dev_priv = dev->dev_private;
4929 struct intel_framebuffer *intel_fb;
4930 struct drm_i915_gem_object *obj_priv;
4931 struct drm_gem_object *obj;
4932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4933 struct intel_unpin_work *work;
4934 unsigned long flags, offset;
4935 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4936 int ret, pipesrc;
4937 u32 flip_mask;
4938
4939 work = kzalloc(sizeof *work, GFP_KERNEL);
4940 if (work == NULL)
4941 return -ENOMEM;
4942
4943 work->event = event;
4944 work->dev = crtc->dev;
4945 intel_fb = to_intel_framebuffer(crtc->fb);
4946 work->old_fb_obj = intel_fb->obj;
4947 INIT_WORK(&work->work, intel_unpin_work_fn);
4948
4949 /* We borrow the event spin lock for protecting unpin_work */
4950 spin_lock_irqsave(&dev->event_lock, flags);
4951 if (intel_crtc->unpin_work) {
4952 spin_unlock_irqrestore(&dev->event_lock, flags);
4953 kfree(work);
4954
4955 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4956 return -EBUSY;
4957 }
4958 intel_crtc->unpin_work = work;
4959 spin_unlock_irqrestore(&dev->event_lock, flags);
4960
4961 intel_fb = to_intel_framebuffer(fb);
4962 obj = intel_fb->obj;
4963
4964 mutex_lock(&dev->struct_mutex);
4965 ret = intel_pin_and_fence_fb_obj(dev, obj);
4966 if (ret)
4967 goto cleanup_work;
4968
4969 /* Reference the objects for the scheduled work. */
4970 drm_gem_object_reference(work->old_fb_obj);
4971 drm_gem_object_reference(obj);
4972
4973 crtc->fb = fb;
4974 ret = i915_gem_object_flush_write_domain(obj);
4975 if (ret)
4976 goto cleanup_objs;
4977
4978 ret = drm_vblank_get(dev, intel_crtc->pipe);
4979 if (ret)
4980 goto cleanup_objs;
4981
4982 obj_priv = to_intel_bo(obj);
4983 atomic_inc(&obj_priv->pending_flip);
4984 work->pending_flip_obj = obj;
4985
4986 if (intel_crtc->plane)
4987 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4988 else
4989 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4990
4991 /* Wait for any previous flip to finish */
4992 if (IS_GEN3(dev))
4993 while (I915_READ(ISR) & flip_mask)
4994 ;
4995
4996 /* Offset into the new buffer for cases of shared fbs between CRTCs */
4997 offset = obj_priv->gtt_offset;
4998 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
4999
5000 BEGIN_LP_RING(4);
5001 if (IS_I965G(dev)) {
5002 OUT_RING(MI_DISPLAY_FLIP |
5003 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5004 OUT_RING(fb->pitch);
5005 OUT_RING(offset | obj_priv->tiling_mode);
5006 pipesrc = I915_READ(pipesrc_reg);
5007 OUT_RING(pipesrc & 0x0fff0fff);
5008 } else {
5009 OUT_RING(MI_DISPLAY_FLIP_I915 |
5010 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5011 OUT_RING(fb->pitch);
5012 OUT_RING(offset);
5013 OUT_RING(MI_NOOP);
5014 }
5015 ADVANCE_LP_RING();
5016
5017 mutex_unlock(&dev->struct_mutex);
5018
5019 trace_i915_flip_request(intel_crtc->plane, obj);
5020
5021 return 0;
5022
5023 cleanup_objs:
5024 drm_gem_object_unreference(work->old_fb_obj);
5025 drm_gem_object_unreference(obj);
5026 cleanup_work:
5027 mutex_unlock(&dev->struct_mutex);
5028
5029 spin_lock_irqsave(&dev->event_lock, flags);
5030 intel_crtc->unpin_work = NULL;
5031 spin_unlock_irqrestore(&dev->event_lock, flags);
5032
5033 kfree(work);
5034
5035 return ret;
5036 }
5037
5038 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5039 .dpms = intel_crtc_dpms,
5040 .mode_fixup = intel_crtc_mode_fixup,
5041 .mode_set = intel_crtc_mode_set,
5042 .mode_set_base = intel_pipe_set_base,
5043 .prepare = intel_crtc_prepare,
5044 .commit = intel_crtc_commit,
5045 .load_lut = intel_crtc_load_lut,
5046 };
5047
5048 static const struct drm_crtc_funcs intel_crtc_funcs = {
5049 .cursor_set = intel_crtc_cursor_set,
5050 .cursor_move = intel_crtc_cursor_move,
5051 .gamma_set = intel_crtc_gamma_set,
5052 .set_config = drm_crtc_helper_set_config,
5053 .destroy = intel_crtc_destroy,
5054 .page_flip = intel_crtc_page_flip,
5055 };
5056
5057
5058 static void intel_crtc_init(struct drm_device *dev, int pipe)
5059 {
5060 drm_i915_private_t *dev_priv = dev->dev_private;
5061 struct intel_crtc *intel_crtc;
5062 int i;
5063
5064 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5065 if (intel_crtc == NULL)
5066 return;
5067
5068 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5069
5070 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5071 intel_crtc->pipe = pipe;
5072 intel_crtc->plane = pipe;
5073 for (i = 0; i < 256; i++) {
5074 intel_crtc->lut_r[i] = i;
5075 intel_crtc->lut_g[i] = i;
5076 intel_crtc->lut_b[i] = i;
5077 }
5078
5079 /* Swap pipes & planes for FBC on pre-965 */
5080 intel_crtc->pipe = pipe;
5081 intel_crtc->plane = pipe;
5082 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5083 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5084 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5085 }
5086
5087 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5088 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5089 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5090 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5091
5092 intel_crtc->cursor_addr = 0;
5093 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5094 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5095
5096 intel_crtc->busy = false;
5097
5098 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5099 (unsigned long)intel_crtc);
5100 }
5101
5102 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5103 struct drm_file *file_priv)
5104 {
5105 drm_i915_private_t *dev_priv = dev->dev_private;
5106 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5107 struct drm_mode_object *drmmode_obj;
5108 struct intel_crtc *crtc;
5109
5110 if (!dev_priv) {
5111 DRM_ERROR("called with no initialization\n");
5112 return -EINVAL;
5113 }
5114
5115 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5116 DRM_MODE_OBJECT_CRTC);
5117
5118 if (!drmmode_obj) {
5119 DRM_ERROR("no such CRTC id\n");
5120 return -EINVAL;
5121 }
5122
5123 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5124 pipe_from_crtc_id->pipe = crtc->pipe;
5125
5126 return 0;
5127 }
5128
5129 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5130 {
5131 struct drm_crtc *crtc = NULL;
5132
5133 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5135 if (intel_crtc->pipe == pipe)
5136 break;
5137 }
5138 return crtc;
5139 }
5140
5141 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5142 {
5143 int index_mask = 0;
5144 struct drm_encoder *encoder;
5145 int entry = 0;
5146
5147 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5148 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5149 if (type_mask & intel_encoder->clone_mask)
5150 index_mask |= (1 << entry);
5151 entry++;
5152 }
5153 return index_mask;
5154 }
5155
5156
5157 static void intel_setup_outputs(struct drm_device *dev)
5158 {
5159 struct drm_i915_private *dev_priv = dev->dev_private;
5160 struct drm_encoder *encoder;
5161 bool dpd_is_edp = false;
5162
5163 if (IS_MOBILE(dev) && !IS_I830(dev))
5164 intel_lvds_init(dev);
5165
5166 if (HAS_PCH_SPLIT(dev)) {
5167 dpd_is_edp = intel_dpd_is_edp(dev);
5168
5169 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5170 intel_dp_init(dev, DP_A);
5171
5172 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5173 intel_dp_init(dev, PCH_DP_D);
5174 }
5175
5176 intel_crt_init(dev);
5177
5178 if (HAS_PCH_SPLIT(dev)) {
5179 int found;
5180
5181 if (I915_READ(HDMIB) & PORT_DETECTED) {
5182 /* PCH SDVOB multiplex with HDMIB */
5183 found = intel_sdvo_init(dev, PCH_SDVOB);
5184 if (!found)
5185 intel_hdmi_init(dev, HDMIB);
5186 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5187 intel_dp_init(dev, PCH_DP_B);
5188 }
5189
5190 if (I915_READ(HDMIC) & PORT_DETECTED)
5191 intel_hdmi_init(dev, HDMIC);
5192
5193 if (I915_READ(HDMID) & PORT_DETECTED)
5194 intel_hdmi_init(dev, HDMID);
5195
5196 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5197 intel_dp_init(dev, PCH_DP_C);
5198
5199 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5200 intel_dp_init(dev, PCH_DP_D);
5201
5202 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5203 bool found = false;
5204
5205 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5206 DRM_DEBUG_KMS("probing SDVOB\n");
5207 found = intel_sdvo_init(dev, SDVOB);
5208 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5209 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5210 intel_hdmi_init(dev, SDVOB);
5211 }
5212
5213 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5214 DRM_DEBUG_KMS("probing DP_B\n");
5215 intel_dp_init(dev, DP_B);
5216 }
5217 }
5218
5219 /* Before G4X SDVOC doesn't have its own detect register */
5220
5221 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5222 DRM_DEBUG_KMS("probing SDVOC\n");
5223 found = intel_sdvo_init(dev, SDVOC);
5224 }
5225
5226 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5227
5228 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5229 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5230 intel_hdmi_init(dev, SDVOC);
5231 }
5232 if (SUPPORTS_INTEGRATED_DP(dev)) {
5233 DRM_DEBUG_KMS("probing DP_C\n");
5234 intel_dp_init(dev, DP_C);
5235 }
5236 }
5237
5238 if (SUPPORTS_INTEGRATED_DP(dev) &&
5239 (I915_READ(DP_D) & DP_DETECTED)) {
5240 DRM_DEBUG_KMS("probing DP_D\n");
5241 intel_dp_init(dev, DP_D);
5242 }
5243 } else if (IS_GEN2(dev))
5244 intel_dvo_init(dev);
5245
5246 if (SUPPORTS_TV(dev))
5247 intel_tv_init(dev);
5248
5249 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5250 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5251
5252 encoder->possible_crtcs = intel_encoder->crtc_mask;
5253 encoder->possible_clones = intel_encoder_clones(dev,
5254 intel_encoder->clone_mask);
5255 }
5256 }
5257
5258 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5259 {
5260 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5261
5262 drm_framebuffer_cleanup(fb);
5263 drm_gem_object_unreference_unlocked(intel_fb->obj);
5264
5265 kfree(intel_fb);
5266 }
5267
5268 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5269 struct drm_file *file_priv,
5270 unsigned int *handle)
5271 {
5272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5273 struct drm_gem_object *object = intel_fb->obj;
5274
5275 return drm_gem_handle_create(file_priv, object, handle);
5276 }
5277
5278 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5279 .destroy = intel_user_framebuffer_destroy,
5280 .create_handle = intel_user_framebuffer_create_handle,
5281 };
5282
5283 int intel_framebuffer_init(struct drm_device *dev,
5284 struct intel_framebuffer *intel_fb,
5285 struct drm_mode_fb_cmd *mode_cmd,
5286 struct drm_gem_object *obj)
5287 {
5288 int ret;
5289
5290 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5291 if (ret) {
5292 DRM_ERROR("framebuffer init failed %d\n", ret);
5293 return ret;
5294 }
5295
5296 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5297 intel_fb->obj = obj;
5298 return 0;
5299 }
5300
5301 static struct drm_framebuffer *
5302 intel_user_framebuffer_create(struct drm_device *dev,
5303 struct drm_file *filp,
5304 struct drm_mode_fb_cmd *mode_cmd)
5305 {
5306 struct drm_gem_object *obj;
5307 struct intel_framebuffer *intel_fb;
5308 int ret;
5309
5310 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5311 if (!obj)
5312 return ERR_PTR(-ENOENT);
5313
5314 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5315 if (!intel_fb)
5316 return ERR_PTR(-ENOMEM);
5317
5318 ret = intel_framebuffer_init(dev, intel_fb,
5319 mode_cmd, obj);
5320 if (ret) {
5321 drm_gem_object_unreference_unlocked(obj);
5322 kfree(intel_fb);
5323 return ERR_PTR(ret);
5324 }
5325
5326 return &intel_fb->base;
5327 }
5328
5329 static const struct drm_mode_config_funcs intel_mode_funcs = {
5330 .fb_create = intel_user_framebuffer_create,
5331 .output_poll_changed = intel_fb_output_poll_changed,
5332 };
5333
5334 static struct drm_gem_object *
5335 intel_alloc_power_context(struct drm_device *dev)
5336 {
5337 struct drm_gem_object *pwrctx;
5338 int ret;
5339
5340 pwrctx = i915_gem_alloc_object(dev, 4096);
5341 if (!pwrctx) {
5342 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5343 return NULL;
5344 }
5345
5346 mutex_lock(&dev->struct_mutex);
5347 ret = i915_gem_object_pin(pwrctx, 4096);
5348 if (ret) {
5349 DRM_ERROR("failed to pin power context: %d\n", ret);
5350 goto err_unref;
5351 }
5352
5353 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5354 if (ret) {
5355 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5356 goto err_unpin;
5357 }
5358 mutex_unlock(&dev->struct_mutex);
5359
5360 return pwrctx;
5361
5362 err_unpin:
5363 i915_gem_object_unpin(pwrctx);
5364 err_unref:
5365 drm_gem_object_unreference(pwrctx);
5366 mutex_unlock(&dev->struct_mutex);
5367 return NULL;
5368 }
5369
5370 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5371 {
5372 struct drm_i915_private *dev_priv = dev->dev_private;
5373 u16 rgvswctl;
5374
5375 rgvswctl = I915_READ16(MEMSWCTL);
5376 if (rgvswctl & MEMCTL_CMD_STS) {
5377 DRM_DEBUG("gpu busy, RCS change rejected\n");
5378 return false; /* still busy with another command */
5379 }
5380
5381 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5382 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5383 I915_WRITE16(MEMSWCTL, rgvswctl);
5384 POSTING_READ16(MEMSWCTL);
5385
5386 rgvswctl |= MEMCTL_CMD_STS;
5387 I915_WRITE16(MEMSWCTL, rgvswctl);
5388
5389 return true;
5390 }
5391
5392 void ironlake_enable_drps(struct drm_device *dev)
5393 {
5394 struct drm_i915_private *dev_priv = dev->dev_private;
5395 u32 rgvmodectl = I915_READ(MEMMODECTL);
5396 u8 fmax, fmin, fstart, vstart;
5397 int i = 0;
5398
5399 /* 100ms RC evaluation intervals */
5400 I915_WRITE(RCUPEI, 100000);
5401 I915_WRITE(RCDNEI, 100000);
5402
5403 /* Set max/min thresholds to 90ms and 80ms respectively */
5404 I915_WRITE(RCBMAXAVG, 90000);
5405 I915_WRITE(RCBMINAVG, 80000);
5406
5407 I915_WRITE(MEMIHYST, 1);
5408
5409 /* Set up min, max, and cur for interrupt handling */
5410 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5411 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5412 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5413 MEMMODE_FSTART_SHIFT;
5414 fstart = fmax;
5415
5416 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5417 PXVFREQ_PX_SHIFT;
5418
5419 dev_priv->fmax = fstart; /* IPS callback will increase this */
5420 dev_priv->fstart = fstart;
5421
5422 dev_priv->max_delay = fmax;
5423 dev_priv->min_delay = fmin;
5424 dev_priv->cur_delay = fstart;
5425
5426 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5427 fstart);
5428
5429 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5430
5431 /*
5432 * Interrupts will be enabled in ironlake_irq_postinstall
5433 */
5434
5435 I915_WRITE(VIDSTART, vstart);
5436 POSTING_READ(VIDSTART);
5437
5438 rgvmodectl |= MEMMODE_SWMODE_EN;
5439 I915_WRITE(MEMMODECTL, rgvmodectl);
5440
5441 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5442 if (i++ > 100) {
5443 DRM_ERROR("stuck trying to change perf mode\n");
5444 break;
5445 }
5446 msleep(1);
5447 }
5448 msleep(1);
5449
5450 ironlake_set_drps(dev, fstart);
5451
5452 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5453 I915_READ(0x112e0);
5454 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5455 dev_priv->last_count2 = I915_READ(0x112f4);
5456 getrawmonotonic(&dev_priv->last_time2);
5457 }
5458
5459 void ironlake_disable_drps(struct drm_device *dev)
5460 {
5461 struct drm_i915_private *dev_priv = dev->dev_private;
5462 u16 rgvswctl = I915_READ16(MEMSWCTL);
5463
5464 /* Ack interrupts, disable EFC interrupt */
5465 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5466 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5467 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5468 I915_WRITE(DEIIR, DE_PCU_EVENT);
5469 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5470
5471 /* Go back to the starting frequency */
5472 ironlake_set_drps(dev, dev_priv->fstart);
5473 msleep(1);
5474 rgvswctl |= MEMCTL_CMD_STS;
5475 I915_WRITE(MEMSWCTL, rgvswctl);
5476 msleep(1);
5477
5478 }
5479
5480 static unsigned long intel_pxfreq(u32 vidfreq)
5481 {
5482 unsigned long freq;
5483 int div = (vidfreq & 0x3f0000) >> 16;
5484 int post = (vidfreq & 0x3000) >> 12;
5485 int pre = (vidfreq & 0x7);
5486
5487 if (!pre)
5488 return 0;
5489
5490 freq = ((div * 133333) / ((1<<post) * pre));
5491
5492 return freq;
5493 }
5494
5495 void intel_init_emon(struct drm_device *dev)
5496 {
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 u32 lcfuse;
5499 u8 pxw[16];
5500 int i;
5501
5502 /* Disable to program */
5503 I915_WRITE(ECR, 0);
5504 POSTING_READ(ECR);
5505
5506 /* Program energy weights for various events */
5507 I915_WRITE(SDEW, 0x15040d00);
5508 I915_WRITE(CSIEW0, 0x007f0000);
5509 I915_WRITE(CSIEW1, 0x1e220004);
5510 I915_WRITE(CSIEW2, 0x04000004);
5511
5512 for (i = 0; i < 5; i++)
5513 I915_WRITE(PEW + (i * 4), 0);
5514 for (i = 0; i < 3; i++)
5515 I915_WRITE(DEW + (i * 4), 0);
5516
5517 /* Program P-state weights to account for frequency power adjustment */
5518 for (i = 0; i < 16; i++) {
5519 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5520 unsigned long freq = intel_pxfreq(pxvidfreq);
5521 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5522 PXVFREQ_PX_SHIFT;
5523 unsigned long val;
5524
5525 val = vid * vid;
5526 val *= (freq / 1000);
5527 val *= 255;
5528 val /= (127*127*900);
5529 if (val > 0xff)
5530 DRM_ERROR("bad pxval: %ld\n", val);
5531 pxw[i] = val;
5532 }
5533 /* Render standby states get 0 weight */
5534 pxw[14] = 0;
5535 pxw[15] = 0;
5536
5537 for (i = 0; i < 4; i++) {
5538 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5539 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5540 I915_WRITE(PXW + (i * 4), val);
5541 }
5542
5543 /* Adjust magic regs to magic values (more experimental results) */
5544 I915_WRITE(OGW0, 0);
5545 I915_WRITE(OGW1, 0);
5546 I915_WRITE(EG0, 0x00007f00);
5547 I915_WRITE(EG1, 0x0000000e);
5548 I915_WRITE(EG2, 0x000e0000);
5549 I915_WRITE(EG3, 0x68000300);
5550 I915_WRITE(EG4, 0x42000000);
5551 I915_WRITE(EG5, 0x00140031);
5552 I915_WRITE(EG6, 0);
5553 I915_WRITE(EG7, 0);
5554
5555 for (i = 0; i < 8; i++)
5556 I915_WRITE(PXWL + (i * 4), 0);
5557
5558 /* Enable PMON + select events */
5559 I915_WRITE(ECR, 0x80000019);
5560
5561 lcfuse = I915_READ(LCFUSE02);
5562
5563 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5564 }
5565
5566 void intel_init_clock_gating(struct drm_device *dev)
5567 {
5568 struct drm_i915_private *dev_priv = dev->dev_private;
5569
5570 /*
5571 * Disable clock gating reported to work incorrectly according to the
5572 * specs, but enable as much else as we can.
5573 */
5574 if (HAS_PCH_SPLIT(dev)) {
5575 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5576
5577 if (IS_IRONLAKE(dev)) {
5578 /* Required for FBC */
5579 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5580 /* Required for CxSR */
5581 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5582
5583 I915_WRITE(PCH_3DCGDIS0,
5584 MARIUNIT_CLOCK_GATE_DISABLE |
5585 SVSMUNIT_CLOCK_GATE_DISABLE);
5586 }
5587
5588 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5589
5590 /*
5591 * According to the spec the following bits should be set in
5592 * order to enable memory self-refresh
5593 * The bit 22/21 of 0x42004
5594 * The bit 5 of 0x42020
5595 * The bit 15 of 0x45000
5596 */
5597 if (IS_IRONLAKE(dev)) {
5598 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5599 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5600 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5601 I915_WRITE(ILK_DSPCLK_GATE,
5602 (I915_READ(ILK_DSPCLK_GATE) |
5603 ILK_DPARB_CLK_GATE));
5604 I915_WRITE(DISP_ARB_CTL,
5605 (I915_READ(DISP_ARB_CTL) |
5606 DISP_FBC_WM_DIS));
5607 }
5608 /*
5609 * Based on the document from hardware guys the following bits
5610 * should be set unconditionally in order to enable FBC.
5611 * The bit 22 of 0x42000
5612 * The bit 22 of 0x42004
5613 * The bit 7,8,9 of 0x42020.
5614 */
5615 if (IS_IRONLAKE_M(dev)) {
5616 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5617 I915_READ(ILK_DISPLAY_CHICKEN1) |
5618 ILK_FBCQ_DIS);
5619 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5620 I915_READ(ILK_DISPLAY_CHICKEN2) |
5621 ILK_DPARB_GATE);
5622 I915_WRITE(ILK_DSPCLK_GATE,
5623 I915_READ(ILK_DSPCLK_GATE) |
5624 ILK_DPFC_DIS1 |
5625 ILK_DPFC_DIS2 |
5626 ILK_CLK_FBC);
5627 }
5628 return;
5629 } else if (IS_G4X(dev)) {
5630 uint32_t dspclk_gate;
5631 I915_WRITE(RENCLK_GATE_D1, 0);
5632 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5633 GS_UNIT_CLOCK_GATE_DISABLE |
5634 CL_UNIT_CLOCK_GATE_DISABLE);
5635 I915_WRITE(RAMCLK_GATE_D, 0);
5636 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5637 OVRUNIT_CLOCK_GATE_DISABLE |
5638 OVCUNIT_CLOCK_GATE_DISABLE;
5639 if (IS_GM45(dev))
5640 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5641 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5642 } else if (IS_I965GM(dev)) {
5643 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5644 I915_WRITE(RENCLK_GATE_D2, 0);
5645 I915_WRITE(DSPCLK_GATE_D, 0);
5646 I915_WRITE(RAMCLK_GATE_D, 0);
5647 I915_WRITE16(DEUC, 0);
5648 } else if (IS_I965G(dev)) {
5649 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5650 I965_RCC_CLOCK_GATE_DISABLE |
5651 I965_RCPB_CLOCK_GATE_DISABLE |
5652 I965_ISC_CLOCK_GATE_DISABLE |
5653 I965_FBC_CLOCK_GATE_DISABLE);
5654 I915_WRITE(RENCLK_GATE_D2, 0);
5655 } else if (IS_I9XX(dev)) {
5656 u32 dstate = I915_READ(D_STATE);
5657
5658 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5659 DSTATE_DOT_CLOCK_GATING;
5660 I915_WRITE(D_STATE, dstate);
5661 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5662 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5663 } else if (IS_I830(dev)) {
5664 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5665 }
5666
5667 /*
5668 * GPU can automatically power down the render unit if given a page
5669 * to save state.
5670 */
5671 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5672 struct drm_i915_gem_object *obj_priv = NULL;
5673
5674 if (dev_priv->pwrctx) {
5675 obj_priv = to_intel_bo(dev_priv->pwrctx);
5676 } else {
5677 struct drm_gem_object *pwrctx;
5678
5679 pwrctx = intel_alloc_power_context(dev);
5680 if (pwrctx) {
5681 dev_priv->pwrctx = pwrctx;
5682 obj_priv = to_intel_bo(pwrctx);
5683 }
5684 }
5685
5686 if (obj_priv) {
5687 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5688 I915_WRITE(MCHBAR_RENDER_STANDBY,
5689 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5690 }
5691 }
5692 }
5693
5694 /* Set up chip specific display functions */
5695 static void intel_init_display(struct drm_device *dev)
5696 {
5697 struct drm_i915_private *dev_priv = dev->dev_private;
5698
5699 /* We always want a DPMS function */
5700 if (HAS_PCH_SPLIT(dev))
5701 dev_priv->display.dpms = ironlake_crtc_dpms;
5702 else
5703 dev_priv->display.dpms = i9xx_crtc_dpms;
5704
5705 if (I915_HAS_FBC(dev)) {
5706 if (IS_IRONLAKE_M(dev)) {
5707 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5708 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5709 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5710 } else if (IS_GM45(dev)) {
5711 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5712 dev_priv->display.enable_fbc = g4x_enable_fbc;
5713 dev_priv->display.disable_fbc = g4x_disable_fbc;
5714 } else if (IS_I965GM(dev)) {
5715 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5716 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5717 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5718 }
5719 /* 855GM needs testing */
5720 }
5721
5722 /* Returns the core display clock speed */
5723 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5724 dev_priv->display.get_display_clock_speed =
5725 i945_get_display_clock_speed;
5726 else if (IS_I915G(dev))
5727 dev_priv->display.get_display_clock_speed =
5728 i915_get_display_clock_speed;
5729 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5730 dev_priv->display.get_display_clock_speed =
5731 i9xx_misc_get_display_clock_speed;
5732 else if (IS_I915GM(dev))
5733 dev_priv->display.get_display_clock_speed =
5734 i915gm_get_display_clock_speed;
5735 else if (IS_I865G(dev))
5736 dev_priv->display.get_display_clock_speed =
5737 i865_get_display_clock_speed;
5738 else if (IS_I85X(dev))
5739 dev_priv->display.get_display_clock_speed =
5740 i855_get_display_clock_speed;
5741 else /* 852, 830 */
5742 dev_priv->display.get_display_clock_speed =
5743 i830_get_display_clock_speed;
5744
5745 /* For FIFO watermark updates */
5746 if (HAS_PCH_SPLIT(dev)) {
5747 if (IS_IRONLAKE(dev)) {
5748 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5749 dev_priv->display.update_wm = ironlake_update_wm;
5750 else {
5751 DRM_DEBUG_KMS("Failed to get proper latency. "
5752 "Disable CxSR\n");
5753 dev_priv->display.update_wm = NULL;
5754 }
5755 } else
5756 dev_priv->display.update_wm = NULL;
5757 } else if (IS_PINEVIEW(dev)) {
5758 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5759 dev_priv->is_ddr3,
5760 dev_priv->fsb_freq,
5761 dev_priv->mem_freq)) {
5762 DRM_INFO("failed to find known CxSR latency "
5763 "(found ddr%s fsb freq %d, mem freq %d), "
5764 "disabling CxSR\n",
5765 (dev_priv->is_ddr3 == 1) ? "3": "2",
5766 dev_priv->fsb_freq, dev_priv->mem_freq);
5767 /* Disable CxSR and never update its watermark again */
5768 pineview_disable_cxsr(dev);
5769 dev_priv->display.update_wm = NULL;
5770 } else
5771 dev_priv->display.update_wm = pineview_update_wm;
5772 } else if (IS_G4X(dev))
5773 dev_priv->display.update_wm = g4x_update_wm;
5774 else if (IS_I965G(dev))
5775 dev_priv->display.update_wm = i965_update_wm;
5776 else if (IS_I9XX(dev)) {
5777 dev_priv->display.update_wm = i9xx_update_wm;
5778 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5779 } else if (IS_I85X(dev)) {
5780 dev_priv->display.update_wm = i9xx_update_wm;
5781 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5782 } else {
5783 dev_priv->display.update_wm = i830_update_wm;
5784 if (IS_845G(dev))
5785 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5786 else
5787 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5788 }
5789 }
5790
5791 /*
5792 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5793 * resume, or other times. This quirk makes sure that's the case for
5794 * affected systems.
5795 */
5796 static void quirk_pipea_force (struct drm_device *dev)
5797 {
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799
5800 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5801 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5802 }
5803
5804 struct intel_quirk {
5805 int device;
5806 int subsystem_vendor;
5807 int subsystem_device;
5808 void (*hook)(struct drm_device *dev);
5809 };
5810
5811 struct intel_quirk intel_quirks[] = {
5812 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5813 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5814 /* HP Mini needs pipe A force quirk (LP: #322104) */
5815 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5816
5817 /* Thinkpad R31 needs pipe A force quirk */
5818 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5819 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5820 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5821
5822 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5823 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5824 /* ThinkPad X40 needs pipe A force quirk */
5825
5826 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5827 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5828
5829 /* 855 & before need to leave pipe A & dpll A up */
5830 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5831 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5832 };
5833
5834 static void intel_init_quirks(struct drm_device *dev)
5835 {
5836 struct pci_dev *d = dev->pdev;
5837 int i;
5838
5839 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5840 struct intel_quirk *q = &intel_quirks[i];
5841
5842 if (d->device == q->device &&
5843 (d->subsystem_vendor == q->subsystem_vendor ||
5844 q->subsystem_vendor == PCI_ANY_ID) &&
5845 (d->subsystem_device == q->subsystem_device ||
5846 q->subsystem_device == PCI_ANY_ID))
5847 q->hook(dev);
5848 }
5849 }
5850
5851 void intel_modeset_init(struct drm_device *dev)
5852 {
5853 struct drm_i915_private *dev_priv = dev->dev_private;
5854 int i;
5855
5856 drm_mode_config_init(dev);
5857
5858 dev->mode_config.min_width = 0;
5859 dev->mode_config.min_height = 0;
5860
5861 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5862
5863 intel_init_quirks(dev);
5864
5865 intel_init_display(dev);
5866
5867 if (IS_I965G(dev)) {
5868 dev->mode_config.max_width = 8192;
5869 dev->mode_config.max_height = 8192;
5870 } else if (IS_I9XX(dev)) {
5871 dev->mode_config.max_width = 4096;
5872 dev->mode_config.max_height = 4096;
5873 } else {
5874 dev->mode_config.max_width = 2048;
5875 dev->mode_config.max_height = 2048;
5876 }
5877
5878 /* set memory base */
5879 if (IS_I9XX(dev))
5880 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5881 else
5882 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5883
5884 if (IS_MOBILE(dev) || IS_I9XX(dev))
5885 dev_priv->num_pipe = 2;
5886 else
5887 dev_priv->num_pipe = 1;
5888 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5889 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5890
5891 for (i = 0; i < dev_priv->num_pipe; i++) {
5892 intel_crtc_init(dev, i);
5893 }
5894
5895 intel_setup_outputs(dev);
5896
5897 intel_init_clock_gating(dev);
5898
5899 if (IS_IRONLAKE_M(dev)) {
5900 ironlake_enable_drps(dev);
5901 intel_init_emon(dev);
5902 }
5903
5904 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5905 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5906 (unsigned long)dev);
5907
5908 intel_setup_overlay(dev);
5909 }
5910
5911 void intel_modeset_cleanup(struct drm_device *dev)
5912 {
5913 struct drm_i915_private *dev_priv = dev->dev_private;
5914 struct drm_crtc *crtc;
5915 struct intel_crtc *intel_crtc;
5916
5917 mutex_lock(&dev->struct_mutex);
5918
5919 drm_kms_helper_poll_fini(dev);
5920 intel_fbdev_fini(dev);
5921
5922 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5923 /* Skip inactive CRTCs */
5924 if (!crtc->fb)
5925 continue;
5926
5927 intel_crtc = to_intel_crtc(crtc);
5928 intel_increase_pllclock(crtc, false);
5929 del_timer_sync(&intel_crtc->idle_timer);
5930 }
5931
5932 del_timer_sync(&dev_priv->idle_timer);
5933
5934 if (dev_priv->display.disable_fbc)
5935 dev_priv->display.disable_fbc(dev);
5936
5937 if (dev_priv->pwrctx) {
5938 struct drm_i915_gem_object *obj_priv;
5939
5940 obj_priv = to_intel_bo(dev_priv->pwrctx);
5941 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5942 I915_READ(PWRCTXA);
5943 i915_gem_object_unpin(dev_priv->pwrctx);
5944 drm_gem_object_unreference(dev_priv->pwrctx);
5945 }
5946
5947 if (IS_IRONLAKE_M(dev))
5948 ironlake_disable_drps(dev);
5949
5950 mutex_unlock(&dev->struct_mutex);
5951
5952 drm_mode_config_cleanup(dev);
5953 }
5954
5955
5956 /*
5957 * Return which encoder is currently attached for connector.
5958 */
5959 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5960 {
5961 struct drm_mode_object *obj;
5962 struct drm_encoder *encoder;
5963 int i;
5964
5965 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5966 if (connector->encoder_ids[i] == 0)
5967 break;
5968
5969 obj = drm_mode_object_find(connector->dev,
5970 connector->encoder_ids[i],
5971 DRM_MODE_OBJECT_ENCODER);
5972 if (!obj)
5973 continue;
5974
5975 encoder = obj_to_encoder(obj);
5976 return encoder;
5977 }
5978 return NULL;
5979 }
5980
5981 /*
5982 * set vga decode state - true == enable VGA decode
5983 */
5984 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5985 {
5986 struct drm_i915_private *dev_priv = dev->dev_private;
5987 u16 gmch_ctrl;
5988
5989 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5990 if (state)
5991 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5992 else
5993 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5994 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5995 return 0;
5996 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree