include/asm-arm/arch-s3c2410/uncompress.h

   1 /* linux/include/asm-arm/arch-s3c2410/uncompress.h
   2  *
   3  * (c) 2003 Simtec Electronics
   4  *    Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 - uncompress code
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_UNCOMPRESS_H
  14 #define __ASM_ARCH_UNCOMPRESS_H
  15
  16
  17 /* defines for UART registers */
  18 #include "asm/arch/regs-serial.h"
  19 #include "asm/arch/regs-gpio.h"
  20 #include "asm/arch/regs-watchdog.h"
  21
  22 #include <asm/arch/map.h>
  23
  24 /* working in physical space... */
  25 #undef S3C2410_GPIOREG
  26 #undef S3C2410_WDOGREG
  27
  28 #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
  29 #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
  30
  31 /* how many bytes we allow into the FIFO at a time in FIFO mode */
  32 #define FIFO_MAX         (14)
  33
  34 #define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
  35
  36 static __inline__ void
  37 uart_wr(unsigned int reg, unsigned int val)
  38 {
  39         volatile unsigned int *ptr;
  40
  41         ptr = (volatile unsigned int *)(reg + uart_base);
  42         *ptr = val;
  43 }
  44
  45 static __inline__ unsigned int
  46 uart_rd(unsigned int reg)
  47 {
  48         volatile unsigned int *ptr;
  49
  50         ptr = (volatile unsigned int *)(reg + uart_base);
  51         return *ptr;
  52 }
  53
  54
  55 /* we can deal with the case the UARTs are being run
  56  * in FIFO mode, so that we don't hold up our execution
  57  * waiting for tx to happen...
  58 */
  59
  60 static void putc(int ch)
  61 {
  62         int cpuid = S3C2410_GSTATUS1_2410;
  63
  64 #ifndef CONFIG_CPU_S3C2400
  65         cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
  66         cpuid &= S3C2410_GSTATUS1_IDMASK;
  67 #endif
  68
  69         if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
  70                 int level;
  71
  72                 while (1) {
  73                         level = uart_rd(S3C2410_UFSTAT);
  74
  75                         if (cpuid == S3C2410_GSTATUS1_2440 ||
  76                             cpuid == S3C2410_GSTATUS1_2442) {
  77                                 level &= S3C2440_UFSTAT_TXMASK;
  78                                 level >>= S3C2440_UFSTAT_TXSHIFT;
  79                         } else {
  80                                 level &= S3C2410_UFSTAT_TXMASK;
  81                                 level >>= S3C2410_UFSTAT_TXSHIFT;
  82                         }
  83
  84                         if (level < FIFO_MAX)
  85                                 break;
  86                 }
  87
  88         } else {
  89                 /* not using fifos */
  90
  91                 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
  92                         barrier();
  93         }
  94
  95         /* write byte to transmission register */
  96         uart_wr(S3C2410_UTXH, ch);
  97 }
  98
  99 static inline void flush(void)
 100 {
 101 }
 102
 103 #define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
 104
 105 /* CONFIG_S3C2410_BOOT_WATCHDOG
 106  *
 107  * Simple boot-time watchdog setup, to reboot the system if there is
 108  * any problem with the boot process
 109 */
 110
 111 #ifdef CONFIG_S3C2410_BOOT_WATCHDOG
 112
 113 #define WDOG_COUNT (0xff00)
 114
 115 static inline void arch_decomp_wdog(void)
 116 {
 117         __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
 118 }
 119
 120 static void arch_decomp_wdog_start(void)
 121 {
 122         __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
 123         __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
 124         __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
 125 }
 126
 127 #else
 128 #define arch_decomp_wdog_start()
 129 #define arch_decomp_wdog()
 130 #endif
 131
 132 #ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
 133
 134 static void arch_decomp_error(const char *x)
 135 {
 136         putstr("\n\n");
 137         putstr(x);
 138         putstr("\n\n -- System resetting\n");
 139
 140         __raw_writel(0x4000, S3C2410_WTDAT);
 141         __raw_writel(0x4000, S3C2410_WTCNT);
 142         __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
 143
 144         while(1);
 145 }
 146
 147 #define arch_error arch_decomp_error
 148 #endif
 149
 150 static void error(char *err);
 151
 152 static void
 153 arch_decomp_setup(void)
 154 {
 155         /* we may need to setup the uart(s) here if we are not running
 156          * on an BAST... the BAST will have left the uarts configured
 157          * after calling linux.
 158          */
 159
 160         arch_decomp_wdog_start();
 161 }
 162
 163
 164 #endif /* __ASM_ARCH_UNCOMPRESS_H */