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USB: remove dev->power.power_state
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / gadget / omap_udc.c
blob56277d24f0418c88a06bd8954498359abb6b51b2
1 /*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #undef DEBUG
25 #undef VERBOSE
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/ioport.h>
30 #include <linux/types.h>
31 #include <linux/errno.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/init.h>
35 #include <linux/timer.h>
36 #include <linux/list.h>
37 #include <linux/interrupt.h>
38 #include <linux/proc_fs.h>
39 #include <linux/mm.h>
40 #include <linux/moduleparam.h>
41 #include <linux/platform_device.h>
42 #include <linux/usb/ch9.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/otg.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/clk.h>
47
48 #include <asm/byteorder.h>
49 #include <asm/io.h>
50 #include <asm/irq.h>
51 #include <asm/system.h>
52 #include <asm/unaligned.h>
53 #include <asm/mach-types.h>
54
55 #include <asm/arch/dma.h>
56 #include <asm/arch/usb.h>
57
58 #include "omap_udc.h"
59
60 #undef USB_TRACE
61
62 /* bulk DMA seems to be behaving for both IN and OUT */
63 #define USE_DMA
64
65 /* ISO too */
66 #define USE_ISO
67
68 #define DRIVER_DESC "OMAP UDC driver"
69 #define DRIVER_VERSION "4 October 2004"
70
71 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
72
73 #define OMAP2_DMA_CH(ch) (((ch) - 1) << 1)
74 #define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
75
76 /*
77 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
78 * D+ pullup to allow enumeration. That's too early for the gadget
79 * framework to use from usb_endpoint_enable(), which happens after
80 * enumeration as part of activating an interface. (But if we add an
81 * optional new "UDC not yet running" state to the gadget driver model,
82 * even just during driver binding, the endpoint autoconfig logic is the
83 * natural spot to manufacture new endpoints.)
84 *
85 * So instead of using endpoint enable calls to control the hardware setup,
86 * this driver defines a "fifo mode" parameter. It's used during driver
87 * initialization to choose among a set of pre-defined endpoint configs.
88 * See omap_udc_setup() for available modes, or to add others. That code
89 * lives in an init section, so use this driver as a module if you need
90 * to change the fifo mode after the kernel boots.
91 *
92 * Gadget drivers normally ignore endpoints they don't care about, and
93 * won't include them in configuration descriptors. That means only
94 * misbehaving hosts would even notice they exist.
95 */
96 #ifdef USE_ISO
97 static unsigned fifo_mode = 3;
98 #else
99 static unsigned fifo_mode = 0;
100 #endif
101
102 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
103 * boot parameter "omap_udc:fifo_mode=42"
104 */
105 module_param (fifo_mode, uint, 0);
106 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
107
108 #ifdef USE_DMA
109 static unsigned use_dma = 1;
110
111 /* "modprobe omap_udc use_dma=y", or else as a kernel
112 * boot parameter "omap_udc:use_dma=y"
113 */
114 module_param (use_dma, bool, 0);
115 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
116 #else /* !USE_DMA */
117
118 /* save a bit of code */
119 #define use_dma 0
120 #endif /* !USE_DMA */
121
122
123 static const char driver_name [] = "omap_udc";
124 static const char driver_desc [] = DRIVER_DESC;
125
126 /*-------------------------------------------------------------------------*/
127
128 /* there's a notion of "current endpoint" for modifying endpoint
129 * state, and PIO access to its FIFO.
130 */
131
132 static void use_ep(struct omap_ep *ep, u16 select)
133 {
134 u16 num = ep->bEndpointAddress & 0x0f;
135
136 if (ep->bEndpointAddress & USB_DIR_IN)
137 num |= UDC_EP_DIR;
138 UDC_EP_NUM_REG = num | select;
139 /* when select, MUST deselect later !! */
140 }
141
142 static inline void deselect_ep(void)
143 {
144 UDC_EP_NUM_REG &= ~UDC_EP_SEL;
145 /* 6 wait states before TX will happen */
146 }
147
148 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
149
150 /*-------------------------------------------------------------------------*/
151
152 static int omap_ep_enable(struct usb_ep *_ep,
153 const struct usb_endpoint_descriptor *desc)
154 {
155 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
156 struct omap_udc *udc;
157 unsigned long flags;
158 u16 maxp;
159
160 /* catch various bogus parameters */
161 if (!_ep || !desc || ep->desc
162 || desc->bDescriptorType != USB_DT_ENDPOINT
163 || ep->bEndpointAddress != desc->bEndpointAddress
164 || ep->maxpacket < le16_to_cpu
165 (desc->wMaxPacketSize)) {
166 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
167 return -EINVAL;
168 }
169 maxp = le16_to_cpu (desc->wMaxPacketSize);
170 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
171 && maxp != ep->maxpacket)
172 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
173 || !desc->wMaxPacketSize) {
174 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
175 return -ERANGE;
176 }
177
178 #ifdef USE_ISO
179 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
180 && desc->bInterval != 1)) {
181 /* hardware wants period = 1; USB allows 2^(Interval-1) */
182 DBG("%s, unsupported ISO period %dms\n", _ep->name,
183 1 << (desc->bInterval - 1));
184 return -EDOM;
185 }
186 #else
187 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
188 DBG("%s, ISO nyet\n", _ep->name);
189 return -EDOM;
190 }
191 #endif
192
193 /* xfer types must match, except that interrupt ~= bulk */
194 if (ep->bmAttributes != desc->bmAttributes
195 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
196 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
197 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
198 return -EINVAL;
199 }
200
201 udc = ep->udc;
202 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
203 DBG("%s, bogus device state\n", __FUNCTION__);
204 return -ESHUTDOWN;
205 }
206
207 spin_lock_irqsave(&udc->lock, flags);
208
209 ep->desc = desc;
210 ep->irqs = 0;
211 ep->stopped = 0;
212 ep->ep.maxpacket = maxp;
213
214 /* set endpoint to initial state */
215 ep->dma_channel = 0;
216 ep->has_dma = 0;
217 ep->lch = -1;
218 use_ep(ep, UDC_EP_SEL);
219 UDC_CTRL_REG = udc->clr_halt;
220 ep->ackwait = 0;
221 deselect_ep();
222
223 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
224 list_add(&ep->iso, &udc->iso);
225
226 /* maybe assign a DMA channel to this endpoint */
227 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
228 /* FIXME ISO can dma, but prefers first channel */
229 dma_channel_claim(ep, 0);
230
231 /* PIO OUT may RX packets */
232 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
233 && !ep->has_dma
234 && !(ep->bEndpointAddress & USB_DIR_IN)) {
235 UDC_CTRL_REG = UDC_SET_FIFO_EN;
236 ep->ackwait = 1 + ep->double_buf;
237 }
238
239 spin_unlock_irqrestore(&udc->lock, flags);
240 VDBG("%s enabled\n", _ep->name);
241 return 0;
242 }
243
244 static void nuke(struct omap_ep *, int status);
245
246 static int omap_ep_disable(struct usb_ep *_ep)
247 {
248 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
249 unsigned long flags;
250
251 if (!_ep || !ep->desc) {
252 DBG("%s, %s not enabled\n", __FUNCTION__,
253 _ep ? ep->ep.name : NULL);
254 return -EINVAL;
255 }
256
257 spin_lock_irqsave(&ep->udc->lock, flags);
258 ep->desc = NULL;
259 nuke (ep, -ESHUTDOWN);
260 ep->ep.maxpacket = ep->maxpacket;
261 ep->has_dma = 0;
262 UDC_CTRL_REG = UDC_SET_HALT;
263 list_del_init(&ep->iso);
264 del_timer(&ep->timer);
265
266 spin_unlock_irqrestore(&ep->udc->lock, flags);
267
268 VDBG("%s disabled\n", _ep->name);
269 return 0;
270 }
271
272 /*-------------------------------------------------------------------------*/
273
274 static struct usb_request *
275 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
276 {
277 struct omap_req *req;
278
279 req = kzalloc(sizeof(*req), gfp_flags);
280 if (req) {
281 req->req.dma = DMA_ADDR_INVALID;
282 INIT_LIST_HEAD (&req->queue);
283 }
284 return &req->req;
285 }
286
287 static void
288 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
289 {
290 struct omap_req *req = container_of(_req, struct omap_req, req);
291
292 if (_req)
293 kfree (req);
294 }
295
296 /*-------------------------------------------------------------------------*/
297
298 static void
299 done(struct omap_ep *ep, struct omap_req *req, int status)
300 {
301 unsigned stopped = ep->stopped;
302
303 list_del_init(&req->queue);
304
305 if (req->req.status == -EINPROGRESS)
306 req->req.status = status;
307 else
308 status = req->req.status;
309
310 if (use_dma && ep->has_dma) {
311 if (req->mapped) {
312 dma_unmap_single(ep->udc->gadget.dev.parent,
313 req->req.dma, req->req.length,
314 (ep->bEndpointAddress & USB_DIR_IN)
315 ? DMA_TO_DEVICE
316 : DMA_FROM_DEVICE);
317 req->req.dma = DMA_ADDR_INVALID;
318 req->mapped = 0;
319 } else
320 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
321 req->req.dma, req->req.length,
322 (ep->bEndpointAddress & USB_DIR_IN)
323 ? DMA_TO_DEVICE
324 : DMA_FROM_DEVICE);
325 }
326
327 #ifndef USB_TRACE
328 if (status && status != -ESHUTDOWN)
329 #endif
330 VDBG("complete %s req %p stat %d len %u/%u\n",
331 ep->ep.name, &req->req, status,
332 req->req.actual, req->req.length);
333
334 /* don't modify queue heads during completion callback */
335 ep->stopped = 1;
336 spin_unlock(&ep->udc->lock);
337 req->req.complete(&ep->ep, &req->req);
338 spin_lock(&ep->udc->lock);
339 ep->stopped = stopped;
340 }
341
342 /*-------------------------------------------------------------------------*/
343
344 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
345 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
346
347 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
348 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
349
350 static inline int
351 write_packet(u8 *buf, struct omap_req *req, unsigned max)
352 {
353 unsigned len;
354 u16 *wp;
355
356 len = min(req->req.length - req->req.actual, max);
357 req->req.actual += len;
358
359 max = len;
360 if (likely((((int)buf) & 1) == 0)) {
361 wp = (u16 *)buf;
362 while (max >= 2) {
363 UDC_DATA_REG = *wp++;
364 max -= 2;
365 }
366 buf = (u8 *)wp;
367 }
368 while (max--)
369 *(volatile u8 *)&UDC_DATA_REG = *buf++;
370 return len;
371 }
372
373 // FIXME change r/w fifo calling convention
374
375
376 // return: 0 = still running, 1 = completed, negative = errno
377 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
378 {
379 u8 *buf;
380 unsigned count;
381 int is_last;
382 u16 ep_stat;
383
384 buf = req->req.buf + req->req.actual;
385 prefetch(buf);
386
387 /* PIO-IN isn't double buffered except for iso */
388 ep_stat = UDC_STAT_FLG_REG;
389 if (ep_stat & UDC_FIFO_UNWRITABLE)
390 return 0;
391
392 count = ep->ep.maxpacket;
393 count = write_packet(buf, req, count);
394 UDC_CTRL_REG = UDC_SET_FIFO_EN;
395 ep->ackwait = 1;
396
397 /* last packet is often short (sometimes a zlp) */
398 if (count != ep->ep.maxpacket)
399 is_last = 1;
400 else if (req->req.length == req->req.actual
401 && !req->req.zero)
402 is_last = 1;
403 else
404 is_last = 0;
405
406 /* NOTE: requests complete when all IN data is in a
407 * FIFO (or sometimes later, if a zlp was needed).
408 * Use usb_ep_fifo_status() where needed.
409 */
410 if (is_last)
411 done(ep, req, 0);
412 return is_last;
413 }
414
415 static inline int
416 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
417 {
418 unsigned len;
419 u16 *wp;
420
421 len = min(req->req.length - req->req.actual, avail);
422 req->req.actual += len;
423 avail = len;
424
425 if (likely((((int)buf) & 1) == 0)) {
426 wp = (u16 *)buf;
427 while (avail >= 2) {
428 *wp++ = UDC_DATA_REG;
429 avail -= 2;
430 }
431 buf = (u8 *)wp;
432 }
433 while (avail--)
434 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
435 return len;
436 }
437
438 // return: 0 = still running, 1 = queue empty, negative = errno
439 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
440 {
441 u8 *buf;
442 unsigned count, avail;
443 int is_last;
444
445 buf = req->req.buf + req->req.actual;
446 prefetchw(buf);
447
448 for (;;) {
449 u16 ep_stat = UDC_STAT_FLG_REG;
450
451 is_last = 0;
452 if (ep_stat & FIFO_EMPTY) {
453 if (!ep->double_buf)
454 break;
455 ep->fnf = 1;
456 }
457 if (ep_stat & UDC_EP_HALTED)
458 break;
459
460 if (ep_stat & UDC_FIFO_FULL)
461 avail = ep->ep.maxpacket;
462 else {
463 avail = UDC_RXFSTAT_REG;
464 ep->fnf = ep->double_buf;
465 }
466 count = read_packet(buf, req, avail);
467
468 /* partial packet reads may not be errors */
469 if (count < ep->ep.maxpacket) {
470 is_last = 1;
471 /* overflowed this request? flush extra data */
472 if (count != avail) {
473 req->req.status = -EOVERFLOW;
474 avail -= count;
475 while (avail--)
476 (void) *(volatile u8 *)&UDC_DATA_REG;
477 }
478 } else if (req->req.length == req->req.actual)
479 is_last = 1;
480 else
481 is_last = 0;
482
483 if (!ep->bEndpointAddress)
484 break;
485 if (is_last)
486 done(ep, req, 0);
487 break;
488 }
489 return is_last;
490 }
491
492 /*-------------------------------------------------------------------------*/
493
494 static inline dma_addr_t dma_csac(unsigned lch)
495 {
496 dma_addr_t csac;
497
498 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
499 * read before the DMA controller finished disabling the channel.
500 */
501 csac = OMAP_DMA_CSAC_REG(lch);
502 if (csac == 0)
503 csac = OMAP_DMA_CSAC_REG(lch);
504 return csac;
505 }
506
507 static inline dma_addr_t dma_cdac(unsigned lch)
508 {
509 dma_addr_t cdac;
510
511 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
512 * read before the DMA controller finished disabling the channel.
513 */
514 cdac = OMAP_DMA_CDAC_REG(lch);
515 if (cdac == 0)
516 cdac = OMAP_DMA_CDAC_REG(lch);
517 return cdac;
518 }
519
520 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
521 {
522 dma_addr_t end;
523
524 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
525 * the last transfer's bytecount by more than a FIFO's worth.
526 */
527 if (cpu_is_omap15xx())
528 return 0;
529
530 end = dma_csac(ep->lch);
531 if (end == ep->dma_counter)
532 return 0;
533
534 end |= start & (0xffff << 16);
535 if (end < start)
536 end += 0x10000;
537 return end - start;
538 }
539
540 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
541 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
542 : dma_cdac(x))
543
544 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
545 {
546 dma_addr_t end;
547
548 end = DMA_DEST_LAST(ep->lch);
549 if (end == ep->dma_counter)
550 return 0;
551
552 end |= start & (0xffff << 16);
553 if (cpu_is_omap15xx())
554 end++;
555 if (end < start)
556 end += 0x10000;
557 return end - start;
558 }
559
560
561 /* Each USB transfer request using DMA maps to one or more DMA transfers.
562 * When DMA completion isn't request completion, the UDC continues with
563 * the next DMA transfer for that USB transfer.
564 */
565
566 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
567 {
568 u16 txdma_ctrl;
569 unsigned length = req->req.length - req->req.actual;
570 const int sync_mode = cpu_is_omap15xx()
571 ? OMAP_DMA_SYNC_FRAME
572 : OMAP_DMA_SYNC_ELEMENT;
573 int dma_trigger = 0;
574
575 if (cpu_is_omap24xx())
576 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
577
578 /* measure length in either bytes or packets */
579 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
580 || (cpu_is_omap24xx() && length < ep->maxpacket)
581 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
582 txdma_ctrl = UDC_TXN_EOT | length;
583 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
584 length, 1, sync_mode, dma_trigger, 0);
585 } else {
586 length = min(length / ep->maxpacket,
587 (unsigned) UDC_TXN_TSC + 1);
588 txdma_ctrl = length;
589 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
590 ep->ep.maxpacket >> 1, length, sync_mode,
591 dma_trigger, 0);
592 length *= ep->maxpacket;
593 }
594 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
595 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
596 0, 0);
597
598 omap_start_dma(ep->lch);
599 ep->dma_counter = dma_csac(ep->lch);
600 UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
601 UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
602 req->dma_bytes = length;
603 }
604
605 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
606 {
607 if (status == 0) {
608 req->req.actual += req->dma_bytes;
609
610 /* return if this request needs to send data or zlp */
611 if (req->req.actual < req->req.length)
612 return;
613 if (req->req.zero
614 && req->dma_bytes != 0
615 && (req->req.actual % ep->maxpacket) == 0)
616 return;
617 } else
618 req->req.actual += dma_src_len(ep, req->req.dma
619 + req->req.actual);
620
621 /* tx completion */
622 omap_stop_dma(ep->lch);
623 UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
624 done(ep, req, status);
625 }
626
627 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
628 {
629 unsigned packets = req->req.length - req->req.actual;
630 int dma_trigger = 0;
631
632 if (cpu_is_omap24xx())
633 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
634
635 /* NOTE: we filtered out "short reads" before, so we know
636 * the buffer has only whole numbers of packets.
637 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
638 */
639 if (cpu_is_omap24xx() && packets < ep->maxpacket) {
640 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
641 packets, 1, OMAP_DMA_SYNC_ELEMENT,
642 dma_trigger, 0);
643 req->dma_bytes = packets;
644 } else {
645 /* set up this DMA transfer, enable the fifo, start */
646 packets /= ep->ep.maxpacket;
647 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
648 req->dma_bytes = packets * ep->ep.maxpacket;
649 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
650 ep->ep.maxpacket >> 1, packets,
651 OMAP_DMA_SYNC_ELEMENT,
652 dma_trigger, 0);
653 }
654 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
655 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
656 0, 0);
657 ep->dma_counter = DMA_DEST_LAST(ep->lch);
658
659 UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
660 UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
661 UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
662 UDC_CTRL_REG = UDC_SET_FIFO_EN;
663
664 omap_start_dma(ep->lch);
665 }
666
667 static void
668 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
669 {
670 u16 count;
671
672 if (status == 0)
673 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
674 count = dma_dest_len(ep, req->req.dma + req->req.actual);
675 count += req->req.actual;
676 if (one)
677 count--;
678 if (count <= req->req.length)
679 req->req.actual = count;
680
681 if (count != req->dma_bytes || status)
682 omap_stop_dma(ep->lch);
683
684 /* if this wasn't short, request may need another transfer */
685 else if (req->req.actual < req->req.length)
686 return;
687
688 /* rx completion */
689 UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
690 done(ep, req, status);
691 }
692
693 static void dma_irq(struct omap_udc *udc, u16 irq_src)
694 {
695 u16 dman_stat = UDC_DMAN_STAT_REG;
696 struct omap_ep *ep;
697 struct omap_req *req;
698
699 /* IN dma: tx to host */
700 if (irq_src & UDC_TXN_DONE) {
701 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
702 ep->irqs++;
703 /* can see TXN_DONE after dma abort */
704 if (!list_empty(&ep->queue)) {
705 req = container_of(ep->queue.next,
706 struct omap_req, queue);
707 finish_in_dma(ep, req, 0);
708 }
709 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
710
711 if (!list_empty (&ep->queue)) {
712 req = container_of(ep->queue.next,
713 struct omap_req, queue);
714 next_in_dma(ep, req);
715 }
716 }
717
718 /* OUT dma: rx from host */
719 if (irq_src & UDC_RXN_EOT) {
720 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
721 ep->irqs++;
722 /* can see RXN_EOT after dma abort */
723 if (!list_empty(&ep->queue)) {
724 req = container_of(ep->queue.next,
725 struct omap_req, queue);
726 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
727 }
728 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
729
730 if (!list_empty (&ep->queue)) {
731 req = container_of(ep->queue.next,
732 struct omap_req, queue);
733 next_out_dma(ep, req);
734 }
735 }
736
737 if (irq_src & UDC_RXN_CNT) {
738 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
739 ep->irqs++;
740 /* omap15xx does this unasked... */
741 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
742 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
743 }
744 }
745
746 static void dma_error(int lch, u16 ch_status, void *data)
747 {
748 struct omap_ep *ep = data;
749
750 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
751 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
752 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
753
754 /* complete current transfer ... */
755 }
756
757 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
758 {
759 u16 reg;
760 int status, restart, is_in;
761 int dma_channel;
762
763 is_in = ep->bEndpointAddress & USB_DIR_IN;
764 if (is_in)
765 reg = UDC_TXDMA_CFG_REG;
766 else
767 reg = UDC_RXDMA_CFG_REG;
768 reg |= UDC_DMA_REQ; /* "pulse" activated */
769
770 ep->dma_channel = 0;
771 ep->lch = -1;
772 if (channel == 0 || channel > 3) {
773 if ((reg & 0x0f00) == 0)
774 channel = 3;
775 else if ((reg & 0x00f0) == 0)
776 channel = 2;
777 else if ((reg & 0x000f) == 0) /* preferred for ISO */
778 channel = 1;
779 else {
780 status = -EMLINK;
781 goto just_restart;
782 }
783 }
784 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
785 ep->dma_channel = channel;
786
787 if (is_in) {
788 if (cpu_is_omap24xx())
789 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
790 else
791 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
792 status = omap_request_dma(dma_channel,
793 ep->ep.name, dma_error, ep, &ep->lch);
794 if (status == 0) {
795 UDC_TXDMA_CFG_REG = reg;
796 /* EMIFF or SDRC */
797 omap_set_dma_src_burst_mode(ep->lch,
798 OMAP_DMA_DATA_BURST_4);
799 omap_set_dma_src_data_pack(ep->lch, 1);
800 /* TIPB */
801 omap_set_dma_dest_params(ep->lch,
802 OMAP_DMA_PORT_TIPB,
803 OMAP_DMA_AMODE_CONSTANT,
804 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
805 0, 0);
806 }
807 } else {
808 if (cpu_is_omap24xx())
809 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
810 else
811 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
812
813 status = omap_request_dma(dma_channel,
814 ep->ep.name, dma_error, ep, &ep->lch);
815 if (status == 0) {
816 UDC_RXDMA_CFG_REG = reg;
817 /* TIPB */
818 omap_set_dma_src_params(ep->lch,
819 OMAP_DMA_PORT_TIPB,
820 OMAP_DMA_AMODE_CONSTANT,
821 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
822 0, 0);
823 /* EMIFF or SDRC */
824 omap_set_dma_dest_burst_mode(ep->lch,
825 OMAP_DMA_DATA_BURST_4);
826 omap_set_dma_dest_data_pack(ep->lch, 1);
827 }
828 }
829 if (status)
830 ep->dma_channel = 0;
831 else {
832 ep->has_dma = 1;
833 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
834
835 /* channel type P: hw synch (fifo) */
836 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
837 OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
838 }
839
840 just_restart:
841 /* restart any queue, even if the claim failed */
842 restart = !ep->stopped && !list_empty(&ep->queue);
843
844 if (status)
845 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
846 restart ? " (restart)" : "");
847 else
848 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
849 is_in ? 't' : 'r',
850 ep->dma_channel - 1, ep->lch,
851 restart ? " (restart)" : "");
852
853 if (restart) {
854 struct omap_req *req;
855 req = container_of(ep->queue.next, struct omap_req, queue);
856 if (ep->has_dma)
857 (is_in ? next_in_dma : next_out_dma)(ep, req);
858 else {
859 use_ep(ep, UDC_EP_SEL);
860 (is_in ? write_fifo : read_fifo)(ep, req);
861 deselect_ep();
862 if (!is_in) {
863 UDC_CTRL_REG = UDC_SET_FIFO_EN;
864 ep->ackwait = 1 + ep->double_buf;
865 }
866 /* IN: 6 wait states before it'll tx */
867 }
868 }
869 }
870
871 static void dma_channel_release(struct omap_ep *ep)
872 {
873 int shift = 4 * (ep->dma_channel - 1);
874 u16 mask = 0x0f << shift;
875 struct omap_req *req;
876 int active;
877
878 /* abort any active usb transfer request */
879 if (!list_empty(&ep->queue))
880 req = container_of(ep->queue.next, struct omap_req, queue);
881 else
882 req = NULL;
883
884 active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
885
886 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
887 active ? "active" : "idle",
888 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
889 ep->dma_channel - 1, req);
890
891 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
892 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
893 */
894
895 /* wait till current packet DMA finishes, and fifo empties */
896 if (ep->bEndpointAddress & USB_DIR_IN) {
897 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
898
899 if (req) {
900 finish_in_dma(ep, req, -ECONNRESET);
901
902 /* clear FIFO; hosts probably won't empty it */
903 use_ep(ep, UDC_EP_SEL);
904 UDC_CTRL_REG = UDC_CLR_EP;
905 deselect_ep();
906 }
907 while (UDC_TXDMA_CFG_REG & mask)
908 udelay(10);
909 } else {
910 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
911
912 /* dma empties the fifo */
913 while (UDC_RXDMA_CFG_REG & mask)
914 udelay(10);
915 if (req)
916 finish_out_dma(ep, req, -ECONNRESET, 0);
917 }
918 omap_free_dma(ep->lch);
919 ep->dma_channel = 0;
920 ep->lch = -1;
921 /* has_dma still set, till endpoint is fully quiesced */
922 }
923
924
925 /*-------------------------------------------------------------------------*/
926
927 static int
928 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
929 {
930 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
931 struct omap_req *req = container_of(_req, struct omap_req, req);
932 struct omap_udc *udc;
933 unsigned long flags;
934 int is_iso = 0;
935
936 /* catch various bogus parameters */
937 if (!_req || !req->req.complete || !req->req.buf
938 || !list_empty(&req->queue)) {
939 DBG("%s, bad params\n", __FUNCTION__);
940 return -EINVAL;
941 }
942 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
943 DBG("%s, bad ep\n", __FUNCTION__);
944 return -EINVAL;
945 }
946 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
947 if (req->req.length > ep->ep.maxpacket)
948 return -EMSGSIZE;
949 is_iso = 1;
950 }
951
952 /* this isn't bogus, but OMAP DMA isn't the only hardware to
953 * have a hard time with partial packet reads... reject it.
954 * Except OMAP2 can handle the small packets.
955 */
956 if (use_dma
957 && ep->has_dma
958 && ep->bEndpointAddress != 0
959 && (ep->bEndpointAddress & USB_DIR_IN) == 0
960 && !cpu_class_is_omap2()
961 && (req->req.length % ep->ep.maxpacket) != 0) {
962 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
963 return -EMSGSIZE;
964 }
965
966 udc = ep->udc;
967 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
968 return -ESHUTDOWN;
969
970 if (use_dma && ep->has_dma) {
971 if (req->req.dma == DMA_ADDR_INVALID) {
972 req->req.dma = dma_map_single(
973 ep->udc->gadget.dev.parent,
974 req->req.buf,
975 req->req.length,
976 (ep->bEndpointAddress & USB_DIR_IN)
977 ? DMA_TO_DEVICE
978 : DMA_FROM_DEVICE);
979 req->mapped = 1;
980 } else {
981 dma_sync_single_for_device(
982 ep->udc->gadget.dev.parent,
983 req->req.dma, req->req.length,
984 (ep->bEndpointAddress & USB_DIR_IN)
985 ? DMA_TO_DEVICE
986 : DMA_FROM_DEVICE);
987 req->mapped = 0;
988 }
989 }
990
991 VDBG("%s queue req %p, len %d buf %p\n",
992 ep->ep.name, _req, _req->length, _req->buf);
993
994 spin_lock_irqsave(&udc->lock, flags);
995
996 req->req.status = -EINPROGRESS;
997 req->req.actual = 0;
998
999 /* maybe kickstart non-iso i/o queues */
1000 if (is_iso)
1001 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1002 else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1003 int is_in;
1004
1005 if (ep->bEndpointAddress == 0) {
1006 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1007 spin_unlock_irqrestore(&udc->lock, flags);
1008 return -EL2HLT;
1009 }
1010
1011 /* empty DATA stage? */
1012 is_in = udc->ep0_in;
1013 if (!req->req.length) {
1014
1015 /* chip became CONFIGURED or ADDRESSED
1016 * earlier; drivers may already have queued
1017 * requests to non-control endpoints
1018 */
1019 if (udc->ep0_set_config) {
1020 u16 irq_en = UDC_IRQ_EN_REG;
1021
1022 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1023 if (!udc->ep0_reset_config)
1024 irq_en |= UDC_EPN_RX_IE
1025 | UDC_EPN_TX_IE;
1026 UDC_IRQ_EN_REG = irq_en;
1027 }
1028
1029 /* STATUS for zero length DATA stages is
1030 * always an IN ... even for IN transfers,
1031 * a weird case which seem to stall OMAP.
1032 */
1033 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1034 UDC_CTRL_REG = UDC_CLR_EP;
1035 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1036 UDC_EP_NUM_REG = UDC_EP_DIR;
1037
1038 /* cleanup */
1039 udc->ep0_pending = 0;
1040 done(ep, req, 0);
1041 req = NULL;
1042
1043 /* non-empty DATA stage */
1044 } else if (is_in) {
1045 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1046 } else {
1047 if (udc->ep0_setup)
1048 goto irq_wait;
1049 UDC_EP_NUM_REG = UDC_EP_SEL;
1050 }
1051 } else {
1052 is_in = ep->bEndpointAddress & USB_DIR_IN;
1053 if (!ep->has_dma)
1054 use_ep(ep, UDC_EP_SEL);
1055 /* if ISO: SOF IRQs must be enabled/disabled! */
1056 }
1057
1058 if (ep->has_dma)
1059 (is_in ? next_in_dma : next_out_dma)(ep, req);
1060 else if (req) {
1061 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1062 req = NULL;
1063 deselect_ep();
1064 if (!is_in) {
1065 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1066 ep->ackwait = 1 + ep->double_buf;
1067 }
1068 /* IN: 6 wait states before it'll tx */
1069 }
1070 }
1071
1072 irq_wait:
1073 /* irq handler advances the queue */
1074 if (req != NULL)
1075 list_add_tail(&req->queue, &ep->queue);
1076 spin_unlock_irqrestore(&udc->lock, flags);
1077
1078 return 0;
1079 }
1080
1081 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1082 {
1083 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1084 struct omap_req *req;
1085 unsigned long flags;
1086
1087 if (!_ep || !_req)
1088 return -EINVAL;
1089
1090 spin_lock_irqsave(&ep->udc->lock, flags);
1091
1092 /* make sure it's actually queued on this endpoint */
1093 list_for_each_entry (req, &ep->queue, queue) {
1094 if (&req->req == _req)
1095 break;
1096 }
1097 if (&req->req != _req) {
1098 spin_unlock_irqrestore(&ep->udc->lock, flags);
1099 return -EINVAL;
1100 }
1101
1102 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1103 int channel = ep->dma_channel;
1104
1105 /* releasing the channel cancels the request,
1106 * reclaiming the channel restarts the queue
1107 */
1108 dma_channel_release(ep);
1109 dma_channel_claim(ep, channel);
1110 } else
1111 done(ep, req, -ECONNRESET);
1112 spin_unlock_irqrestore(&ep->udc->lock, flags);
1113 return 0;
1114 }
1115
1116 /*-------------------------------------------------------------------------*/
1117
1118 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1119 {
1120 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1121 unsigned long flags;
1122 int status = -EOPNOTSUPP;
1123
1124 spin_lock_irqsave(&ep->udc->lock, flags);
1125
1126 /* just use protocol stalls for ep0; real halts are annoying */
1127 if (ep->bEndpointAddress == 0) {
1128 if (!ep->udc->ep0_pending)
1129 status = -EINVAL;
1130 else if (value) {
1131 if (ep->udc->ep0_set_config) {
1132 WARN("error changing config?\n");
1133 UDC_SYSCON2_REG = UDC_CLR_CFG;
1134 }
1135 UDC_SYSCON2_REG = UDC_STALL_CMD;
1136 ep->udc->ep0_pending = 0;
1137 status = 0;
1138 } else /* NOP */
1139 status = 0;
1140
1141 /* otherwise, all active non-ISO endpoints can halt */
1142 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1143
1144 /* IN endpoints must already be idle */
1145 if ((ep->bEndpointAddress & USB_DIR_IN)
1146 && !list_empty(&ep->queue)) {
1147 status = -EAGAIN;
1148 goto done;
1149 }
1150
1151 if (value) {
1152 int channel;
1153
1154 if (use_dma && ep->dma_channel
1155 && !list_empty(&ep->queue)) {
1156 channel = ep->dma_channel;
1157 dma_channel_release(ep);
1158 } else
1159 channel = 0;
1160
1161 use_ep(ep, UDC_EP_SEL);
1162 if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1163 UDC_CTRL_REG = UDC_SET_HALT;
1164 status = 0;
1165 } else
1166 status = -EAGAIN;
1167 deselect_ep();
1168
1169 if (channel)
1170 dma_channel_claim(ep, channel);
1171 } else {
1172 use_ep(ep, 0);
1173 UDC_CTRL_REG = ep->udc->clr_halt;
1174 ep->ackwait = 0;
1175 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1176 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1177 ep->ackwait = 1 + ep->double_buf;
1178 }
1179 }
1180 }
1181 done:
1182 VDBG("%s %s halt stat %d\n", ep->ep.name,
1183 value ? "set" : "clear", status);
1184
1185 spin_unlock_irqrestore(&ep->udc->lock, flags);
1186 return status;
1187 }
1188
1189 static struct usb_ep_ops omap_ep_ops = {
1190 .enable = omap_ep_enable,
1191 .disable = omap_ep_disable,
1192
1193 .alloc_request = omap_alloc_request,
1194 .free_request = omap_free_request,
1195
1196 .queue = omap_ep_queue,
1197 .dequeue = omap_ep_dequeue,
1198
1199 .set_halt = omap_ep_set_halt,
1200 // fifo_status ... report bytes in fifo
1201 // fifo_flush ... flush fifo
1202 };
1203
1204 /*-------------------------------------------------------------------------*/
1205
1206 static int omap_get_frame(struct usb_gadget *gadget)
1207 {
1208 u16 sof = UDC_SOF_REG;
1209 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1210 }
1211
1212 static int omap_wakeup(struct usb_gadget *gadget)
1213 {
1214 struct omap_udc *udc;
1215 unsigned long flags;
1216 int retval = -EHOSTUNREACH;
1217
1218 udc = container_of(gadget, struct omap_udc, gadget);
1219
1220 spin_lock_irqsave(&udc->lock, flags);
1221 if (udc->devstat & UDC_SUS) {
1222 /* NOTE: OTG spec erratum says that OTG devices may
1223 * issue wakeups without host enable.
1224 */
1225 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1226 DBG("remote wakeup...\n");
1227 UDC_SYSCON2_REG = UDC_RMT_WKP;
1228 retval = 0;
1229 }
1230
1231 /* NOTE: non-OTG systems may use SRP TOO... */
1232 } else if (!(udc->devstat & UDC_ATT)) {
1233 if (udc->transceiver)
1234 retval = otg_start_srp(udc->transceiver);
1235 }
1236 spin_unlock_irqrestore(&udc->lock, flags);
1237
1238 return retval;
1239 }
1240
1241 static int
1242 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1243 {
1244 struct omap_udc *udc;
1245 unsigned long flags;
1246 u16 syscon1;
1247
1248 udc = container_of(gadget, struct omap_udc, gadget);
1249 spin_lock_irqsave(&udc->lock, flags);
1250 syscon1 = UDC_SYSCON1_REG;
1251 if (is_selfpowered)
1252 syscon1 |= UDC_SELF_PWR;
1253 else
1254 syscon1 &= ~UDC_SELF_PWR;
1255 UDC_SYSCON1_REG = syscon1;
1256 spin_unlock_irqrestore(&udc->lock, flags);
1257
1258 return 0;
1259 }
1260
1261 static int can_pullup(struct omap_udc *udc)
1262 {
1263 return udc->driver && udc->softconnect && udc->vbus_active;
1264 }
1265
1266 static void pullup_enable(struct omap_udc *udc)
1267 {
1268 UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1269 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1270 OTG_CTRL_REG |= OTG_BSESSVLD;
1271 UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1272 }
1273
1274 static void pullup_disable(struct omap_udc *udc)
1275 {
1276 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1277 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1278 UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1279 UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1280 }
1281
1282 static struct omap_udc *udc;
1283
1284 static void omap_udc_enable_clock(int enable)
1285 {
1286 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1287 return;
1288
1289 if (enable) {
1290 clk_enable(udc->dc_clk);
1291 clk_enable(udc->hhc_clk);
1292 udelay(100);
1293 } else {
1294 clk_disable(udc->hhc_clk);
1295 clk_disable(udc->dc_clk);
1296 }
1297 }
1298
1299 /*
1300 * Called by whatever detects VBUS sessions: external transceiver
1301 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1302 */
1303 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1304 {
1305 struct omap_udc *udc;
1306 unsigned long flags;
1307
1308 udc = container_of(gadget, struct omap_udc, gadget);
1309 spin_lock_irqsave(&udc->lock, flags);
1310 VDBG("VBUS %s\n", is_active ? "on" : "off");
1311 udc->vbus_active = (is_active != 0);
1312 if (cpu_is_omap15xx()) {
1313 /* "software" detect, ignored if !VBUS_MODE_1510 */
1314 if (is_active)
1315 FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1316 else
1317 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1318 }
1319 if (udc->dc_clk != NULL && is_active) {
1320 if (!udc->clk_requested) {
1321 omap_udc_enable_clock(1);
1322 udc->clk_requested = 1;
1323 }
1324 }
1325 if (can_pullup(udc))
1326 pullup_enable(udc);
1327 else
1328 pullup_disable(udc);
1329 if (udc->dc_clk != NULL && !is_active) {
1330 if (udc->clk_requested) {
1331 omap_udc_enable_clock(0);
1332 udc->clk_requested = 0;
1333 }
1334 }
1335 spin_unlock_irqrestore(&udc->lock, flags);
1336 return 0;
1337 }
1338
1339 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1340 {
1341 struct omap_udc *udc;
1342
1343 udc = container_of(gadget, struct omap_udc, gadget);
1344 if (udc->transceiver)
1345 return otg_set_power(udc->transceiver, mA);
1346 return -EOPNOTSUPP;
1347 }
1348
1349 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1350 {
1351 struct omap_udc *udc;
1352 unsigned long flags;
1353
1354 udc = container_of(gadget, struct omap_udc, gadget);
1355 spin_lock_irqsave(&udc->lock, flags);
1356 udc->softconnect = (is_on != 0);
1357 if (can_pullup(udc))
1358 pullup_enable(udc);
1359 else
1360 pullup_disable(udc);
1361 spin_unlock_irqrestore(&udc->lock, flags);
1362 return 0;
1363 }
1364
1365 static struct usb_gadget_ops omap_gadget_ops = {
1366 .get_frame = omap_get_frame,
1367 .wakeup = omap_wakeup,
1368 .set_selfpowered = omap_set_selfpowered,
1369 .vbus_session = omap_vbus_session,
1370 .vbus_draw = omap_vbus_draw,
1371 .pullup = omap_pullup,
1372 };
1373
1374 /*-------------------------------------------------------------------------*/
1375
1376 /* dequeue ALL requests; caller holds udc->lock */
1377 static void nuke(struct omap_ep *ep, int status)
1378 {
1379 struct omap_req *req;
1380
1381 ep->stopped = 1;
1382
1383 if (use_dma && ep->dma_channel)
1384 dma_channel_release(ep);
1385
1386 use_ep(ep, 0);
1387 UDC_CTRL_REG = UDC_CLR_EP;
1388 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1389 UDC_CTRL_REG = UDC_SET_HALT;
1390
1391 while (!list_empty(&ep->queue)) {
1392 req = list_entry(ep->queue.next, struct omap_req, queue);
1393 done(ep, req, status);
1394 }
1395 }
1396
1397 /* caller holds udc->lock */
1398 static void udc_quiesce(struct omap_udc *udc)
1399 {
1400 struct omap_ep *ep;
1401
1402 udc->gadget.speed = USB_SPEED_UNKNOWN;
1403 nuke(&udc->ep[0], -ESHUTDOWN);
1404 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1405 nuke(ep, -ESHUTDOWN);
1406 }
1407
1408 /*-------------------------------------------------------------------------*/
1409
1410 static void update_otg(struct omap_udc *udc)
1411 {
1412 u16 devstat;
1413
1414 if (!gadget_is_otg(&udc->gadget))
1415 return;
1416
1417 if (OTG_CTRL_REG & OTG_ID)
1418 devstat = UDC_DEVSTAT_REG;
1419 else
1420 devstat = 0;
1421
1422 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1423 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1424 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1425
1426 /* Enable HNP early, avoiding races on suspend irq path.
1427 * ASSUMES OTG state machine B_BUS_REQ input is true.
1428 */
1429 if (udc->gadget.b_hnp_enable)
1430 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1431 & ~OTG_PULLUP;
1432 }
1433
1434 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1435 {
1436 struct omap_ep *ep0 = &udc->ep[0];
1437 struct omap_req *req = NULL;
1438
1439 ep0->irqs++;
1440
1441 /* Clear any pending requests and then scrub any rx/tx state
1442 * before starting to handle the SETUP request.
1443 */
1444 if (irq_src & UDC_SETUP) {
1445 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1446
1447 nuke(ep0, 0);
1448 if (ack) {
1449 UDC_IRQ_SRC_REG = ack;
1450 irq_src = UDC_SETUP;
1451 }
1452 }
1453
1454 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1455 * This driver uses only uses protocol stalls (ep0 never halts),
1456 * and if we got this far the gadget driver already had a
1457 * chance to stall. Tries to be forgiving of host oddities.
1458 *
1459 * NOTE: the last chance gadget drivers have to stall control
1460 * requests is during their request completion callback.
1461 */
1462 if (!list_empty(&ep0->queue))
1463 req = container_of(ep0->queue.next, struct omap_req, queue);
1464
1465 /* IN == TX to host */
1466 if (irq_src & UDC_EP0_TX) {
1467 int stat;
1468
1469 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1470 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1471 stat = UDC_STAT_FLG_REG;
1472 if (stat & UDC_ACK) {
1473 if (udc->ep0_in) {
1474 /* write next IN packet from response,
1475 * or set up the status stage.
1476 */
1477 if (req)
1478 stat = write_fifo(ep0, req);
1479 UDC_EP_NUM_REG = UDC_EP_DIR;
1480 if (!req && udc->ep0_pending) {
1481 UDC_EP_NUM_REG = UDC_EP_SEL;
1482 UDC_CTRL_REG = UDC_CLR_EP;
1483 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1484 UDC_EP_NUM_REG = 0;
1485 udc->ep0_pending = 0;
1486 } /* else: 6 wait states before it'll tx */
1487 } else {
1488 /* ack status stage of OUT transfer */
1489 UDC_EP_NUM_REG = UDC_EP_DIR;
1490 if (req)
1491 done(ep0, req, 0);
1492 }
1493 req = NULL;
1494 } else if (stat & UDC_STALL) {
1495 UDC_CTRL_REG = UDC_CLR_HALT;
1496 UDC_EP_NUM_REG = UDC_EP_DIR;
1497 } else {
1498 UDC_EP_NUM_REG = UDC_EP_DIR;
1499 }
1500 }
1501
1502 /* OUT == RX from host */
1503 if (irq_src & UDC_EP0_RX) {
1504 int stat;
1505
1506 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1507 UDC_EP_NUM_REG = UDC_EP_SEL;
1508 stat = UDC_STAT_FLG_REG;
1509 if (stat & UDC_ACK) {
1510 if (!udc->ep0_in) {
1511 stat = 0;
1512 /* read next OUT packet of request, maybe
1513 * reactiviting the fifo; stall on errors.
1514 */
1515 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1516 UDC_SYSCON2_REG = UDC_STALL_CMD;
1517 udc->ep0_pending = 0;
1518 stat = 0;
1519 } else if (stat == 0)
1520 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1521 UDC_EP_NUM_REG = 0;
1522
1523 /* activate status stage */
1524 if (stat == 1) {
1525 done(ep0, req, 0);
1526 /* that may have STALLed ep0... */
1527 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1528 UDC_CTRL_REG = UDC_CLR_EP;
1529 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1530 UDC_EP_NUM_REG = UDC_EP_DIR;
1531 udc->ep0_pending = 0;
1532 }
1533 } else {
1534 /* ack status stage of IN transfer */
1535 UDC_EP_NUM_REG = 0;
1536 if (req)
1537 done(ep0, req, 0);
1538 }
1539 } else if (stat & UDC_STALL) {
1540 UDC_CTRL_REG = UDC_CLR_HALT;
1541 UDC_EP_NUM_REG = 0;
1542 } else {
1543 UDC_EP_NUM_REG = 0;
1544 }
1545 }
1546
1547 /* SETUP starts all control transfers */
1548 if (irq_src & UDC_SETUP) {
1549 union u {
1550 u16 word[4];
1551 struct usb_ctrlrequest r;
1552 } u;
1553 int status = -EINVAL;
1554 struct omap_ep *ep;
1555
1556 /* read the (latest) SETUP message */
1557 do {
1558 UDC_EP_NUM_REG = UDC_SETUP_SEL;
1559 /* two bytes at a time */
1560 u.word[0] = UDC_DATA_REG;
1561 u.word[1] = UDC_DATA_REG;
1562 u.word[2] = UDC_DATA_REG;
1563 u.word[3] = UDC_DATA_REG;
1564 UDC_EP_NUM_REG = 0;
1565 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1566
1567 #define w_value le16_to_cpu(u.r.wValue)
1568 #define w_index le16_to_cpu(u.r.wIndex)
1569 #define w_length le16_to_cpu(u.r.wLength)
1570
1571 /* Delegate almost all control requests to the gadget driver,
1572 * except for a handful of ch9 status/feature requests that
1573 * hardware doesn't autodecode _and_ the gadget API hides.
1574 */
1575 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1576 udc->ep0_set_config = 0;
1577 udc->ep0_pending = 1;
1578 ep0->stopped = 0;
1579 ep0->ackwait = 0;
1580 switch (u.r.bRequest) {
1581 case USB_REQ_SET_CONFIGURATION:
1582 /* udc needs to know when ep != 0 is valid */
1583 if (u.r.bRequestType != USB_RECIP_DEVICE)
1584 goto delegate;
1585 if (w_length != 0)
1586 goto do_stall;
1587 udc->ep0_set_config = 1;
1588 udc->ep0_reset_config = (w_value == 0);
1589 VDBG("set config %d\n", w_value);
1590
1591 /* update udc NOW since gadget driver may start
1592 * queueing requests immediately; clear config
1593 * later if it fails the request.
1594 */
1595 if (udc->ep0_reset_config)
1596 UDC_SYSCON2_REG = UDC_CLR_CFG;
1597 else
1598 UDC_SYSCON2_REG = UDC_DEV_CFG;
1599 update_otg(udc);
1600 goto delegate;
1601 case USB_REQ_CLEAR_FEATURE:
1602 /* clear endpoint halt */
1603 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1604 goto delegate;
1605 if (w_value != USB_ENDPOINT_HALT
1606 || w_length != 0)
1607 goto do_stall;
1608 ep = &udc->ep[w_index & 0xf];
1609 if (ep != ep0) {
1610 if (w_index & USB_DIR_IN)
1611 ep += 16;
1612 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1613 || !ep->desc)
1614 goto do_stall;
1615 use_ep(ep, 0);
1616 UDC_CTRL_REG = udc->clr_halt;
1617 ep->ackwait = 0;
1618 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1619 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1620 ep->ackwait = 1 + ep->double_buf;
1621 }
1622 /* NOTE: assumes the host behaves sanely,
1623 * only clearing real halts. Else we may
1624 * need to kill pending transfers and then
1625 * restart the queue... very messy for DMA!
1626 */
1627 }
1628 VDBG("%s halt cleared by host\n", ep->name);
1629 goto ep0out_status_stage;
1630 case USB_REQ_SET_FEATURE:
1631 /* set endpoint halt */
1632 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1633 goto delegate;
1634 if (w_value != USB_ENDPOINT_HALT
1635 || w_length != 0)
1636 goto do_stall;
1637 ep = &udc->ep[w_index & 0xf];
1638 if (w_index & USB_DIR_IN)
1639 ep += 16;
1640 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1641 || ep == ep0 || !ep->desc)
1642 goto do_stall;
1643 if (use_dma && ep->has_dma) {
1644 /* this has rude side-effects (aborts) and
1645 * can't really work if DMA-IN is active
1646 */
1647 DBG("%s host set_halt, NYET \n", ep->name);
1648 goto do_stall;
1649 }
1650 use_ep(ep, 0);
1651 /* can't halt if fifo isn't empty... */
1652 UDC_CTRL_REG = UDC_CLR_EP;
1653 UDC_CTRL_REG = UDC_SET_HALT;
1654 VDBG("%s halted by host\n", ep->name);
1655 ep0out_status_stage:
1656 status = 0;
1657 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1658 UDC_CTRL_REG = UDC_CLR_EP;
1659 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1660 UDC_EP_NUM_REG = UDC_EP_DIR;
1661 udc->ep0_pending = 0;
1662 break;
1663 case USB_REQ_GET_STATUS:
1664 /* USB_ENDPOINT_HALT status? */
1665 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1666 goto intf_status;
1667
1668 /* ep0 never stalls */
1669 if (!(w_index & 0xf))
1670 goto zero_status;
1671
1672 /* only active endpoints count */
1673 ep = &udc->ep[w_index & 0xf];
1674 if (w_index & USB_DIR_IN)
1675 ep += 16;
1676 if (!ep->desc)
1677 goto do_stall;
1678
1679 /* iso never stalls */
1680 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1681 goto zero_status;
1682
1683 /* FIXME don't assume non-halted endpoints!! */
1684 ERR("%s status, can't report\n", ep->ep.name);
1685 goto do_stall;
1686
1687 intf_status:
1688 /* return interface status. if we were pedantic,
1689 * we'd detect non-existent interfaces, and stall.
1690 */
1691 if (u.r.bRequestType
1692 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1693 goto delegate;
1694
1695 zero_status:
1696 /* return two zero bytes */
1697 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1698 UDC_DATA_REG = 0;
1699 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1700 UDC_EP_NUM_REG = UDC_EP_DIR;
1701 status = 0;
1702 VDBG("GET_STATUS, interface %d\n", w_index);
1703 /* next, status stage */
1704 break;
1705 default:
1706 delegate:
1707 /* activate the ep0out fifo right away */
1708 if (!udc->ep0_in && w_length) {
1709 UDC_EP_NUM_REG = 0;
1710 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1711 }
1712
1713 /* gadget drivers see class/vendor specific requests,
1714 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1715 * and more
1716 */
1717 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1718 u.r.bRequestType, u.r.bRequest,
1719 w_value, w_index, w_length);
1720
1721 #undef w_value
1722 #undef w_index
1723 #undef w_length
1724
1725 /* The gadget driver may return an error here,
1726 * causing an immediate protocol stall.
1727 *
1728 * Else it must issue a response, either queueing a
1729 * response buffer for the DATA stage, or halting ep0
1730 * (causing a protocol stall, not a real halt). A
1731 * zero length buffer means no DATA stage.
1732 *
1733 * It's fine to issue that response after the setup()
1734 * call returns, and this IRQ was handled.
1735 */
1736 udc->ep0_setup = 1;
1737 spin_unlock(&udc->lock);
1738 status = udc->driver->setup (&udc->gadget, &u.r);
1739 spin_lock(&udc->lock);
1740 udc->ep0_setup = 0;
1741 }
1742
1743 if (status < 0) {
1744 do_stall:
1745 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1746 u.r.bRequestType, u.r.bRequest, status);
1747 if (udc->ep0_set_config) {
1748 if (udc->ep0_reset_config)
1749 WARN("error resetting config?\n");
1750 else
1751 UDC_SYSCON2_REG = UDC_CLR_CFG;
1752 }
1753 UDC_SYSCON2_REG = UDC_STALL_CMD;
1754 udc->ep0_pending = 0;
1755 }
1756 }
1757 }
1758
1759 /*-------------------------------------------------------------------------*/
1760
1761 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1762
1763 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1764 {
1765 u16 devstat, change;
1766
1767 devstat = UDC_DEVSTAT_REG;
1768 change = devstat ^ udc->devstat;
1769 udc->devstat = devstat;
1770
1771 if (change & (UDC_USB_RESET|UDC_ATT)) {
1772 udc_quiesce(udc);
1773
1774 if (change & UDC_ATT) {
1775 /* driver for any external transceiver will
1776 * have called omap_vbus_session() already
1777 */
1778 if (devstat & UDC_ATT) {
1779 udc->gadget.speed = USB_SPEED_FULL;
1780 VDBG("connect\n");
1781 if (!udc->transceiver)
1782 pullup_enable(udc);
1783 // if (driver->connect) call it
1784 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1785 udc->gadget.speed = USB_SPEED_UNKNOWN;
1786 if (!udc->transceiver)
1787 pullup_disable(udc);
1788 DBG("disconnect, gadget %s\n",
1789 udc->driver->driver.name);
1790 if (udc->driver->disconnect) {
1791 spin_unlock(&udc->lock);
1792 udc->driver->disconnect(&udc->gadget);
1793 spin_lock(&udc->lock);
1794 }
1795 }
1796 change &= ~UDC_ATT;
1797 }
1798
1799 if (change & UDC_USB_RESET) {
1800 if (devstat & UDC_USB_RESET) {
1801 VDBG("RESET=1\n");
1802 } else {
1803 udc->gadget.speed = USB_SPEED_FULL;
1804 INFO("USB reset done, gadget %s\n",
1805 udc->driver->driver.name);
1806 /* ep0 traffic is legal from now on */
1807 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1808 }
1809 change &= ~UDC_USB_RESET;
1810 }
1811 }
1812 if (change & UDC_SUS) {
1813 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1814 // FIXME tell isp1301 to suspend/resume (?)
1815 if (devstat & UDC_SUS) {
1816 VDBG("suspend\n");
1817 update_otg(udc);
1818 /* HNP could be under way already */
1819 if (udc->gadget.speed == USB_SPEED_FULL
1820 && udc->driver->suspend) {
1821 spin_unlock(&udc->lock);
1822 udc->driver->suspend(&udc->gadget);
1823 spin_lock(&udc->lock);
1824 }
1825 if (udc->transceiver)
1826 otg_set_suspend(udc->transceiver, 1);
1827 } else {
1828 VDBG("resume\n");
1829 if (udc->transceiver)
1830 otg_set_suspend(udc->transceiver, 0);
1831 if (udc->gadget.speed == USB_SPEED_FULL
1832 && udc->driver->resume) {
1833 spin_unlock(&udc->lock);
1834 udc->driver->resume(&udc->gadget);
1835 spin_lock(&udc->lock);
1836 }
1837 }
1838 }
1839 change &= ~UDC_SUS;
1840 }
1841 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1842 update_otg(udc);
1843 change &= ~OTG_FLAGS;
1844 }
1845
1846 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1847 if (change)
1848 VDBG("devstat %03x, ignore change %03x\n",
1849 devstat, change);
1850
1851 UDC_IRQ_SRC_REG = UDC_DS_CHG;
1852 }
1853
1854 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1855 {
1856 struct omap_udc *udc = _udc;
1857 u16 irq_src;
1858 irqreturn_t status = IRQ_NONE;
1859 unsigned long flags;
1860
1861 spin_lock_irqsave(&udc->lock, flags);
1862 irq_src = UDC_IRQ_SRC_REG;
1863
1864 /* Device state change (usb ch9 stuff) */
1865 if (irq_src & UDC_DS_CHG) {
1866 devstate_irq(_udc, irq_src);
1867 status = IRQ_HANDLED;
1868 irq_src &= ~UDC_DS_CHG;
1869 }
1870
1871 /* EP0 control transfers */
1872 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1873 ep0_irq(_udc, irq_src);
1874 status = IRQ_HANDLED;
1875 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1876 }
1877
1878 /* DMA transfer completion */
1879 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1880 dma_irq(_udc, irq_src);
1881 status = IRQ_HANDLED;
1882 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1883 }
1884
1885 irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1886 if (irq_src)
1887 DBG("udc_irq, unhandled %03x\n", irq_src);
1888 spin_unlock_irqrestore(&udc->lock, flags);
1889
1890 return status;
1891 }
1892
1893 /* workaround for seemingly-lost IRQs for RX ACKs... */
1894 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1895 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1896
1897 static void pio_out_timer(unsigned long _ep)
1898 {
1899 struct omap_ep *ep = (void *) _ep;
1900 unsigned long flags;
1901 u16 stat_flg;
1902
1903 spin_lock_irqsave(&ep->udc->lock, flags);
1904 if (!list_empty(&ep->queue) && ep->ackwait) {
1905 use_ep(ep, UDC_EP_SEL);
1906 stat_flg = UDC_STAT_FLG_REG;
1907
1908 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1909 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1910 struct omap_req *req;
1911
1912 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1913 req = container_of(ep->queue.next,
1914 struct omap_req, queue);
1915 (void) read_fifo(ep, req);
1916 UDC_EP_NUM_REG = ep->bEndpointAddress;
1917 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1918 ep->ackwait = 1 + ep->double_buf;
1919 } else
1920 deselect_ep();
1921 }
1922 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1923 spin_unlock_irqrestore(&ep->udc->lock, flags);
1924 }
1925
1926 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1927 {
1928 u16 epn_stat, irq_src;
1929 irqreturn_t status = IRQ_NONE;
1930 struct omap_ep *ep;
1931 int epnum;
1932 struct omap_udc *udc = _dev;
1933 struct omap_req *req;
1934 unsigned long flags;
1935
1936 spin_lock_irqsave(&udc->lock, flags);
1937 epn_stat = UDC_EPN_STAT_REG;
1938 irq_src = UDC_IRQ_SRC_REG;
1939
1940 /* handle OUT first, to avoid some wasteful NAKs */
1941 if (irq_src & UDC_EPN_RX) {
1942 epnum = (epn_stat >> 8) & 0x0f;
1943 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1944 status = IRQ_HANDLED;
1945 ep = &udc->ep[epnum];
1946 ep->irqs++;
1947
1948 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1949 ep->fnf = 0;
1950 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1951 ep->ackwait--;
1952 if (!list_empty(&ep->queue)) {
1953 int stat;
1954 req = container_of(ep->queue.next,
1955 struct omap_req, queue);
1956 stat = read_fifo(ep, req);
1957 if (!ep->double_buf)
1958 ep->fnf = 1;
1959 }
1960 }
1961 /* min 6 clock delay before clearing EP_SEL ... */
1962 epn_stat = UDC_EPN_STAT_REG;
1963 epn_stat = UDC_EPN_STAT_REG;
1964 UDC_EP_NUM_REG = epnum;
1965
1966 /* enabling fifo _after_ clearing ACK, contrary to docs,
1967 * reduces lossage; timer still needed though (sigh).
1968 */
1969 if (ep->fnf) {
1970 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1971 ep->ackwait = 1 + ep->double_buf;
1972 }
1973 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1974 }
1975
1976 /* then IN transfers */
1977 else if (irq_src & UDC_EPN_TX) {
1978 epnum = epn_stat & 0x0f;
1979 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1980 status = IRQ_HANDLED;
1981 ep = &udc->ep[16 + epnum];
1982 ep->irqs++;
1983
1984 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1985 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1986 ep->ackwait = 0;
1987 if (!list_empty(&ep->queue)) {
1988 req = container_of(ep->queue.next,
1989 struct omap_req, queue);
1990 (void) write_fifo(ep, req);
1991 }
1992 }
1993 /* min 6 clock delay before clearing EP_SEL ... */
1994 epn_stat = UDC_EPN_STAT_REG;
1995 epn_stat = UDC_EPN_STAT_REG;
1996 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1997 /* then 6 clocks before it'd tx */
1998 }
1999
2000 spin_unlock_irqrestore(&udc->lock, flags);
2001 return status;
2002 }
2003
2004 #ifdef USE_ISO
2005 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2006 {
2007 struct omap_udc *udc = _dev;
2008 struct omap_ep *ep;
2009 int pending = 0;
2010 unsigned long flags;
2011
2012 spin_lock_irqsave(&udc->lock, flags);
2013
2014 /* handle all non-DMA ISO transfers */
2015 list_for_each_entry (ep, &udc->iso, iso) {
2016 u16 stat;
2017 struct omap_req *req;
2018
2019 if (ep->has_dma || list_empty(&ep->queue))
2020 continue;
2021 req = list_entry(ep->queue.next, struct omap_req, queue);
2022
2023 use_ep(ep, UDC_EP_SEL);
2024 stat = UDC_STAT_FLG_REG;
2025
2026 /* NOTE: like the other controller drivers, this isn't
2027 * currently reporting lost or damaged frames.
2028 */
2029 if (ep->bEndpointAddress & USB_DIR_IN) {
2030 if (stat & UDC_MISS_IN)
2031 /* done(ep, req, -EPROTO) */;
2032 else
2033 write_fifo(ep, req);
2034 } else {
2035 int status = 0;
2036
2037 if (stat & UDC_NO_RXPACKET)
2038 status = -EREMOTEIO;
2039 else if (stat & UDC_ISO_ERR)
2040 status = -EILSEQ;
2041 else if (stat & UDC_DATA_FLUSH)
2042 status = -ENOSR;
2043
2044 if (status)
2045 /* done(ep, req, status) */;
2046 else
2047 read_fifo(ep, req);
2048 }
2049 deselect_ep();
2050 /* 6 wait states before next EP */
2051
2052 ep->irqs++;
2053 if (!list_empty(&ep->queue))
2054 pending = 1;
2055 }
2056 if (!pending)
2057 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2058 UDC_IRQ_SRC_REG = UDC_SOF;
2059
2060 spin_unlock_irqrestore(&udc->lock, flags);
2061 return IRQ_HANDLED;
2062 }
2063 #endif
2064
2065 /*-------------------------------------------------------------------------*/
2066
2067 static inline int machine_without_vbus_sense(void)
2068 {
2069 return (machine_is_omap_innovator()
2070 || machine_is_omap_osk()
2071 || machine_is_omap_apollon()
2072 #ifndef CONFIG_MACH_OMAP_H4_OTG
2073 || machine_is_omap_h4()
2074 #endif
2075 || machine_is_sx1()
2076 );
2077 }
2078
2079 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2080 {
2081 int status = -ENODEV;
2082 struct omap_ep *ep;
2083 unsigned long flags;
2084
2085 /* basic sanity tests */
2086 if (!udc)
2087 return -ENODEV;
2088 if (!driver
2089 // FIXME if otg, check: driver->is_otg
2090 || driver->speed < USB_SPEED_FULL
2091 || !driver->bind
2092 || !driver->setup)
2093 return -EINVAL;
2094
2095 spin_lock_irqsave(&udc->lock, flags);
2096 if (udc->driver) {
2097 spin_unlock_irqrestore(&udc->lock, flags);
2098 return -EBUSY;
2099 }
2100
2101 /* reset state */
2102 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2103 ep->irqs = 0;
2104 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2105 continue;
2106 use_ep(ep, 0);
2107 UDC_CTRL_REG = UDC_SET_HALT;
2108 }
2109 udc->ep0_pending = 0;
2110 udc->ep[0].irqs = 0;
2111 udc->softconnect = 1;
2112
2113 /* hook up the driver */
2114 driver->driver.bus = NULL;
2115 udc->driver = driver;
2116 udc->gadget.dev.driver = &driver->driver;
2117 spin_unlock_irqrestore(&udc->lock, flags);
2118
2119 if (udc->dc_clk != NULL)
2120 omap_udc_enable_clock(1);
2121
2122 status = driver->bind (&udc->gadget);
2123 if (status) {
2124 DBG("bind to %s --> %d\n", driver->driver.name, status);
2125 udc->gadget.dev.driver = NULL;
2126 udc->driver = NULL;
2127 goto done;
2128 }
2129 DBG("bound to driver %s\n", driver->driver.name);
2130
2131 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2132
2133 /* connect to bus through transceiver */
2134 if (udc->transceiver) {
2135 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2136 if (status < 0) {
2137 ERR("can't bind to transceiver\n");
2138 if (driver->unbind) {
2139 driver->unbind (&udc->gadget);
2140 udc->gadget.dev.driver = NULL;
2141 udc->driver = NULL;
2142 }
2143 goto done;
2144 }
2145 } else {
2146 if (can_pullup(udc))
2147 pullup_enable (udc);
2148 else
2149 pullup_disable (udc);
2150 }
2151
2152 /* boards that don't have VBUS sensing can't autogate 48MHz;
2153 * can't enter deep sleep while a gadget driver is active.
2154 */
2155 if (machine_without_vbus_sense())
2156 omap_vbus_session(&udc->gadget, 1);
2157
2158 done:
2159 if (udc->dc_clk != NULL)
2160 omap_udc_enable_clock(0);
2161 return status;
2162 }
2163 EXPORT_SYMBOL(usb_gadget_register_driver);
2164
2165 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2166 {
2167 unsigned long flags;
2168 int status = -ENODEV;
2169
2170 if (!udc)
2171 return -ENODEV;
2172 if (!driver || driver != udc->driver || !driver->unbind)
2173 return -EINVAL;
2174
2175 if (udc->dc_clk != NULL)
2176 omap_udc_enable_clock(1);
2177
2178 if (machine_without_vbus_sense())
2179 omap_vbus_session(&udc->gadget, 0);
2180
2181 if (udc->transceiver)
2182 (void) otg_set_peripheral(udc->transceiver, NULL);
2183 else
2184 pullup_disable(udc);
2185
2186 spin_lock_irqsave(&udc->lock, flags);
2187 udc_quiesce(udc);
2188 spin_unlock_irqrestore(&udc->lock, flags);
2189
2190 driver->unbind(&udc->gadget);
2191 udc->gadget.dev.driver = NULL;
2192 udc->driver = NULL;
2193
2194 if (udc->dc_clk != NULL)
2195 omap_udc_enable_clock(0);
2196 DBG("unregistered driver '%s'\n", driver->driver.name);
2197 return status;
2198 }
2199 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2200
2201
2202 /*-------------------------------------------------------------------------*/
2203
2204 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2205
2206 #include <linux/seq_file.h>
2207
2208 static const char proc_filename[] = "driver/udc";
2209
2210 #define FOURBITS "%s%s%s%s"
2211 #define EIGHTBITS FOURBITS FOURBITS
2212
2213 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2214 {
2215 u16 stat_flg;
2216 struct omap_req *req;
2217 char buf[20];
2218
2219 use_ep(ep, 0);
2220
2221 if (use_dma && ep->has_dma)
2222 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2223 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2224 ep->dma_channel - 1, ep->lch);
2225 else
2226 buf[0] = 0;
2227
2228 stat_flg = UDC_STAT_FLG_REG;
2229 seq_printf(s,
2230 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2231 ep->name, buf,
2232 ep->double_buf ? "dbuf " : "",
2233 ({char *s; switch(ep->ackwait){
2234 case 0: s = ""; break;
2235 case 1: s = "(ackw) "; break;
2236 case 2: s = "(ackw2) "; break;
2237 default: s = "(?) "; break;
2238 } s;}),
2239 ep->irqs, stat_flg,
2240 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2241 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2242 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2243 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2244 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2245 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2246 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2247 (stat_flg & UDC_STALL) ? "STALL " : "",
2248 (stat_flg & UDC_NAK) ? "NAK " : "",
2249 (stat_flg & UDC_ACK) ? "ACK " : "",
2250 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2251 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2252 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2253
2254 if (list_empty (&ep->queue))
2255 seq_printf(s, "\t(queue empty)\n");
2256 else
2257 list_for_each_entry (req, &ep->queue, queue) {
2258 unsigned length = req->req.actual;
2259
2260 if (use_dma && buf[0]) {
2261 length += ((ep->bEndpointAddress & USB_DIR_IN)
2262 ? dma_src_len : dma_dest_len)
2263 (ep, req->req.dma + length);
2264 buf[0] = 0;
2265 }
2266 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2267 &req->req, length,
2268 req->req.length, req->req.buf);
2269 }
2270 }
2271
2272 static char *trx_mode(unsigned m, int enabled)
2273 {
2274 switch (m) {
2275 case 0: return enabled ? "*6wire" : "unused";
2276 case 1: return "4wire";
2277 case 2: return "3wire";
2278 case 3: return "6wire";
2279 default: return "unknown";
2280 }
2281 }
2282
2283 static int proc_otg_show(struct seq_file *s)
2284 {
2285 u32 tmp;
2286 u32 trans;
2287 char *ctrl_name;
2288
2289 tmp = OTG_REV_REG;
2290 if (cpu_is_omap24xx()) {
2291 ctrl_name = "control_devconf";
2292 trans = CONTROL_DEVCONF_REG;
2293 } else {
2294 ctrl_name = "tranceiver_ctrl";
2295 trans = USB_TRANSCEIVER_CTRL_REG;
2296 }
2297 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2298 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2299 tmp = OTG_SYSCON_1_REG;
2300 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2301 FOURBITS "\n", tmp,
2302 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2303 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2304 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2305 ? "internal"
2306 : trx_mode(USB0_TRX_MODE(tmp), 1),
2307 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2308 (tmp & HST_IDLE_EN) ? " !host" : "",
2309 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2310 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2311 tmp = OTG_SYSCON_2_REG;
2312 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2313 " b_ase_brst=%d hmc=%d\n", tmp,
2314 (tmp & OTG_EN) ? " otg_en" : "",
2315 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2316 // much more SRP stuff
2317 (tmp & SRP_DATA) ? " srp_data" : "",
2318 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2319 (tmp & OTG_PADEN) ? " otg_paden" : "",
2320 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2321 (tmp & UHOST_EN) ? " uhost_en" : "",
2322 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2323 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2324 B_ASE_BRST(tmp),
2325 OTG_HMC(tmp));
2326 tmp = OTG_CTRL_REG;
2327 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2328 (tmp & OTG_ASESSVLD) ? " asess" : "",
2329 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2330 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2331 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2332 (tmp & OTG_ID) ? " id" : "",
2333 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2334 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2335 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2336 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2337 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2338 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2339 (tmp & OTG_PULLDOWN) ? " down" : "",
2340 (tmp & OTG_PULLUP) ? " up" : "",
2341 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2342 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2343 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2344 (tmp & OTG_PU_ID) ? " pu_id" : ""
2345 );
2346 tmp = OTG_IRQ_EN_REG;
2347 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2348 tmp = OTG_IRQ_SRC_REG;
2349 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2350 tmp = OTG_OUTCTRL_REG;
2351 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2352 tmp = OTG_TEST_REG;
2353 seq_printf(s, "otg_test %04x" "\n", tmp);
2354 return 0;
2355 }
2356
2357 static int proc_udc_show(struct seq_file *s, void *_)
2358 {
2359 u32 tmp;
2360 struct omap_ep *ep;
2361 unsigned long flags;
2362
2363 spin_lock_irqsave(&udc->lock, flags);
2364
2365 seq_printf(s, "%s, version: " DRIVER_VERSION
2366 #ifdef USE_ISO
2367 " (iso)"
2368 #endif
2369 "%s\n",
2370 driver_desc,
2371 use_dma ? " (dma)" : "");
2372
2373 tmp = UDC_REV_REG & 0xff;
2374 seq_printf(s,
2375 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2376 "hmc %d, transceiver %s\n",
2377 tmp >> 4, tmp & 0xf,
2378 fifo_mode,
2379 udc->driver ? udc->driver->driver.name : "(none)",
2380 HMC,
2381 udc->transceiver
2382 ? udc->transceiver->label
2383 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2384 ? "external" : "(none)"));
2385 if (cpu_class_is_omap1()) {
2386 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2387 __REG16(ULPD_CLOCK_CTRL),
2388 __REG16(ULPD_SOFT_REQ),
2389 __REG16(ULPD_STATUS_REQ));
2390 }
2391
2392 /* OTG controller registers */
2393 if (!cpu_is_omap15xx())
2394 proc_otg_show(s);
2395
2396 tmp = UDC_SYSCON1_REG;
2397 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2398 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2399 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2400 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2401 (tmp & UDC_NAK_EN) ? " nak" : "",
2402 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2403 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2404 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2405 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2406 // syscon2 is write-only
2407
2408 /* UDC controller registers */
2409 if (!(tmp & UDC_PULLUP_EN)) {
2410 seq_printf(s, "(suspended)\n");
2411 spin_unlock_irqrestore(&udc->lock, flags);
2412 return 0;
2413 }
2414
2415 tmp = UDC_DEVSTAT_REG;
2416 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2417 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2418 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2419 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2420 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2421 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2422 (tmp & UDC_SUS) ? " SUS" : "",
2423 (tmp & UDC_CFG) ? " CFG" : "",
2424 (tmp & UDC_ADD) ? " ADD" : "",
2425 (tmp & UDC_DEF) ? " DEF" : "",
2426 (tmp & UDC_ATT) ? " ATT" : "");
2427 seq_printf(s, "sof %04x\n", UDC_SOF_REG);
2428 tmp = UDC_IRQ_EN_REG;
2429 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2430 (tmp & UDC_SOF_IE) ? " sof" : "",
2431 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2432 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2433 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2434 (tmp & UDC_EP0_IE) ? " ep0" : "");
2435 tmp = UDC_IRQ_SRC_REG;
2436 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2437 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2438 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2439 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2440 (tmp & UDC_SOF) ? " sof" : "",
2441 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2442 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2443 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2444 (tmp & UDC_SETUP) ? " setup" : "",
2445 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2446 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2447 if (use_dma) {
2448 unsigned i;
2449
2450 tmp = UDC_DMA_IRQ_EN_REG;
2451 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2452 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2453 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2454 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2455
2456 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2457 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2458 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2459
2460 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2461 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2462 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2463
2464 tmp = UDC_RXDMA_CFG_REG;
2465 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2466 if (tmp) {
2467 for (i = 0; i < 3; i++) {
2468 if ((tmp & (0x0f << (i * 4))) == 0)
2469 continue;
2470 seq_printf(s, "rxdma[%d] %04x\n", i,
2471 UDC_RXDMA_REG(i + 1));
2472 }
2473 }
2474 tmp = UDC_TXDMA_CFG_REG;
2475 seq_printf(s, "txdma_cfg %04x\n", tmp);
2476 if (tmp) {
2477 for (i = 0; i < 3; i++) {
2478 if (!(tmp & (0x0f << (i * 4))))
2479 continue;
2480 seq_printf(s, "txdma[%d] %04x\n", i,
2481 UDC_TXDMA_REG(i + 1));
2482 }
2483 }
2484 }
2485
2486 tmp = UDC_DEVSTAT_REG;
2487 if (tmp & UDC_ATT) {
2488 proc_ep_show(s, &udc->ep[0]);
2489 if (tmp & UDC_ADD) {
2490 list_for_each_entry (ep, &udc->gadget.ep_list,
2491 ep.ep_list) {
2492 if (ep->desc)
2493 proc_ep_show(s, ep);
2494 }
2495 }
2496 }
2497 spin_unlock_irqrestore(&udc->lock, flags);
2498 return 0;
2499 }
2500
2501 static int proc_udc_open(struct inode *inode, struct file *file)
2502 {
2503 return single_open(file, proc_udc_show, NULL);
2504 }
2505
2506 static const struct file_operations proc_ops = {
2507 .open = proc_udc_open,
2508 .read = seq_read,
2509 .llseek = seq_lseek,
2510 .release = single_release,
2511 };
2512
2513 static void create_proc_file(void)
2514 {
2515 struct proc_dir_entry *pde;
2516
2517 pde = create_proc_entry (proc_filename, 0, NULL);
2518 if (pde)
2519 pde->proc_fops = &proc_ops;
2520 }
2521
2522 static void remove_proc_file(void)
2523 {
2524 remove_proc_entry(proc_filename, NULL);
2525 }
2526
2527 #else
2528
2529 static inline void create_proc_file(void) {}
2530 static inline void remove_proc_file(void) {}
2531
2532 #endif
2533
2534 /*-------------------------------------------------------------------------*/
2535
2536 /* Before this controller can enumerate, we need to pick an endpoint
2537 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2538 * buffer space among the endpoints we'll be operating.
2539 *
2540 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2541 * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that
2542 * capability yet though.
2543 */
2544 static unsigned __init
2545 omap_ep_setup(char *name, u8 addr, u8 type,
2546 unsigned buf, unsigned maxp, int dbuf)
2547 {
2548 struct omap_ep *ep;
2549 u16 epn_rxtx = 0;
2550
2551 /* OUT endpoints first, then IN */
2552 ep = &udc->ep[addr & 0xf];
2553 if (addr & USB_DIR_IN)
2554 ep += 16;
2555
2556 /* in case of ep init table bugs */
2557 BUG_ON(ep->name[0]);
2558
2559 /* chip setup ... bit values are same for IN, OUT */
2560 if (type == USB_ENDPOINT_XFER_ISOC) {
2561 switch (maxp) {
2562 case 8: epn_rxtx = 0 << 12; break;
2563 case 16: epn_rxtx = 1 << 12; break;
2564 case 32: epn_rxtx = 2 << 12; break;
2565 case 64: epn_rxtx = 3 << 12; break;
2566 case 128: epn_rxtx = 4 << 12; break;
2567 case 256: epn_rxtx = 5 << 12; break;
2568 case 512: epn_rxtx = 6 << 12; break;
2569 default: BUG();
2570 }
2571 epn_rxtx |= UDC_EPN_RX_ISO;
2572 dbuf = 1;
2573 } else {
2574 /* double-buffering "not supported" on 15xx,
2575 * and ignored for PIO-IN on newer chips
2576 * (for more reliable behavior)
2577 */
2578 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2579 dbuf = 0;
2580
2581 switch (maxp) {
2582 case 8: epn_rxtx = 0 << 12; break;
2583 case 16: epn_rxtx = 1 << 12; break;
2584 case 32: epn_rxtx = 2 << 12; break;
2585 case 64: epn_rxtx = 3 << 12; break;
2586 default: BUG();
2587 }
2588 if (dbuf && addr)
2589 epn_rxtx |= UDC_EPN_RX_DB;
2590 init_timer(&ep->timer);
2591 ep->timer.function = pio_out_timer;
2592 ep->timer.data = (unsigned long) ep;
2593 }
2594 if (addr)
2595 epn_rxtx |= UDC_EPN_RX_VALID;
2596 BUG_ON(buf & 0x07);
2597 epn_rxtx |= buf >> 3;
2598
2599 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2600 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2601
2602 if (addr & USB_DIR_IN)
2603 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2604 else
2605 UDC_EP_RX_REG(addr) = epn_rxtx;
2606
2607 /* next endpoint's buffer starts after this one's */
2608 buf += maxp;
2609 if (dbuf)
2610 buf += maxp;
2611 BUG_ON(buf > 2048);
2612
2613 /* set up driver data structures */
2614 BUG_ON(strlen(name) >= sizeof ep->name);
2615 strlcpy(ep->name, name, sizeof ep->name);
2616 INIT_LIST_HEAD(&ep->queue);
2617 INIT_LIST_HEAD(&ep->iso);
2618 ep->bEndpointAddress = addr;
2619 ep->bmAttributes = type;
2620 ep->double_buf = dbuf;
2621 ep->udc = udc;
2622
2623 ep->ep.name = ep->name;
2624 ep->ep.ops = &omap_ep_ops;
2625 ep->ep.maxpacket = ep->maxpacket = maxp;
2626 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2627
2628 return buf;
2629 }
2630
2631 static void omap_udc_release(struct device *dev)
2632 {
2633 complete(udc->done);
2634 kfree (udc);
2635 udc = NULL;
2636 }
2637
2638 static int __init
2639 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2640 {
2641 unsigned tmp, buf;
2642
2643 /* abolish any previous hardware state */
2644 UDC_SYSCON1_REG = 0;
2645 UDC_IRQ_EN_REG = 0;
2646 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2647 UDC_DMA_IRQ_EN_REG = 0;
2648 UDC_RXDMA_CFG_REG = 0;
2649 UDC_TXDMA_CFG_REG = 0;
2650
2651 /* UDC_PULLUP_EN gates the chip clock */
2652 // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2653
2654 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2655 if (!udc)
2656 return -ENOMEM;
2657
2658 spin_lock_init (&udc->lock);
2659
2660 udc->gadget.ops = &omap_gadget_ops;
2661 udc->gadget.ep0 = &udc->ep[0].ep;
2662 INIT_LIST_HEAD(&udc->gadget.ep_list);
2663 INIT_LIST_HEAD(&udc->iso);
2664 udc->gadget.speed = USB_SPEED_UNKNOWN;
2665 udc->gadget.name = driver_name;
2666
2667 device_initialize(&udc->gadget.dev);
2668 strcpy (udc->gadget.dev.bus_id, "gadget");
2669 udc->gadget.dev.release = omap_udc_release;
2670 udc->gadget.dev.parent = &odev->dev;
2671 if (use_dma)
2672 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2673
2674 udc->transceiver = xceiv;
2675
2676 /* ep0 is special; put it right after the SETUP buffer */
2677 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2678 8 /* after SETUP */, 64 /* maxpacket */, 0);
2679 list_del_init(&udc->ep[0].ep.ep_list);
2680
2681 /* initially disable all non-ep0 endpoints */
2682 for (tmp = 1; tmp < 15; tmp++) {
2683 UDC_EP_RX_REG(tmp) = 0;
2684 UDC_EP_TX_REG(tmp) = 0;
2685 }
2686
2687 #define OMAP_BULK_EP(name,addr) \
2688 buf = omap_ep_setup(name "-bulk", addr, \
2689 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2690 #define OMAP_INT_EP(name,addr, maxp) \
2691 buf = omap_ep_setup(name "-int", addr, \
2692 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2693 #define OMAP_ISO_EP(name,addr, maxp) \
2694 buf = omap_ep_setup(name "-iso", addr, \
2695 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2696
2697 switch (fifo_mode) {
2698 case 0:
2699 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2700 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2701 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2702 break;
2703 case 1:
2704 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2705 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2706 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2707
2708 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2709 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2710 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2711
2712 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2713 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2714 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2715
2716 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2717 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2718 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2719
2720 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2721 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2722 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2723 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2724
2725 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2726 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2727 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2728 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2729
2730 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2731 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2732
2733 break;
2734
2735 #ifdef USE_ISO
2736 case 2: /* mixed iso/bulk */
2737 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2738 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2739 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2740 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2741
2742 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2743
2744 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2745 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2746 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2747 break;
2748 case 3: /* mixed bulk/iso */
2749 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2750 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2751 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2752
2753 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2754 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2755 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2756
2757 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2758 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2759 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2760 break;
2761 #endif
2762
2763 /* add more modes as needed */
2764
2765 default:
2766 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2767 return -ENODEV;
2768 }
2769 UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2770 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2771 return 0;
2772 }
2773
2774 static int __init omap_udc_probe(struct platform_device *pdev)
2775 {
2776 int status = -ENODEV;
2777 int hmc;
2778 struct otg_transceiver *xceiv = NULL;
2779 const char *type = NULL;
2780 struct omap_usb_config *config = pdev->dev.platform_data;
2781 struct clk *dc_clk;
2782 struct clk *hhc_clk;
2783
2784 /* NOTE: "knows" the order of the resources! */
2785 if (!request_mem_region(pdev->resource[0].start,
2786 pdev->resource[0].end - pdev->resource[0].start + 1,
2787 driver_name)) {
2788 DBG("request_mem_region failed\n");
2789 return -EBUSY;
2790 }
2791
2792 if (cpu_is_omap16xx()) {
2793 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2794 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2795 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2796 /* can't use omap_udc_enable_clock yet */
2797 clk_enable(dc_clk);
2798 clk_enable(hhc_clk);
2799 udelay(100);
2800 }
2801
2802 if (cpu_is_omap24xx()) {
2803 dc_clk = clk_get(&pdev->dev, "usb_fck");
2804 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2805 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2806 /* can't use omap_udc_enable_clock yet */
2807 clk_enable(dc_clk);
2808 clk_enable(hhc_clk);
2809 udelay(100);
2810 }
2811
2812 INFO("OMAP UDC rev %d.%d%s\n",
2813 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2814 config->otg ? ", Mini-AB" : "");
2815
2816 /* use the mode given to us by board init code */
2817 if (cpu_is_omap15xx()) {
2818 hmc = HMC_1510;
2819 type = "(unknown)";
2820
2821 if (machine_without_vbus_sense()) {
2822 /* just set up software VBUS detect, and then
2823 * later rig it so we always report VBUS.
2824 * FIXME without really sensing VBUS, we can't
2825 * know when to turn PULLUP_EN on/off; and that
2826 * means we always "need" the 48MHz clock.
2827 */
2828 u32 tmp = FUNC_MUX_CTRL_0_REG;
2829
2830 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2831 tmp |= VBUS_MODE_1510;
2832 tmp &= ~VBUS_CTRL_1510;
2833 FUNC_MUX_CTRL_0_REG = tmp;
2834 }
2835 } else {
2836 /* The transceiver may package some GPIO logic or handle
2837 * loopback and/or transceiverless setup; if we find one,
2838 * use it. Except for OTG, we don't _need_ to talk to one;
2839 * but not having one probably means no VBUS detection.
2840 */
2841 xceiv = otg_get_transceiver();
2842 if (xceiv)
2843 type = xceiv->label;
2844 else if (config->otg) {
2845 DBG("OTG requires external transceiver!\n");
2846 goto cleanup0;
2847 }
2848
2849 hmc = HMC_1610;
2850
2851 if (cpu_is_omap24xx()) {
2852 /* this could be transceiverless in one of the
2853 * "we don't need to know" modes.
2854 */
2855 type = "external";
2856 goto known;
2857 }
2858
2859 switch (hmc) {
2860 case 0: /* POWERUP DEFAULT == 0 */
2861 case 4:
2862 case 12:
2863 case 20:
2864 if (!cpu_is_omap1710()) {
2865 type = "integrated";
2866 break;
2867 }
2868 /* FALL THROUGH */
2869 case 3:
2870 case 11:
2871 case 16:
2872 case 19:
2873 case 25:
2874 if (!xceiv) {
2875 DBG("external transceiver not registered!\n");
2876 type = "unknown";
2877 }
2878 break;
2879 case 21: /* internal loopback */
2880 type = "loopback";
2881 break;
2882 case 14: /* transceiverless */
2883 if (cpu_is_omap1710())
2884 goto bad_on_1710;
2885 /* FALL THROUGH */
2886 case 13:
2887 case 15:
2888 type = "no";
2889 break;
2890
2891 default:
2892 bad_on_1710:
2893 ERR("unrecognized UDC HMC mode %d\n", hmc);
2894 goto cleanup0;
2895 }
2896 }
2897 known:
2898 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2899
2900 /* a "gadget" abstracts/virtualizes the controller */
2901 status = omap_udc_setup(pdev, xceiv);
2902 if (status) {
2903 goto cleanup0;
2904 }
2905 xceiv = NULL;
2906 // "udc" is now valid
2907 pullup_disable(udc);
2908 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2909 udc->gadget.is_otg = (config->otg != 0);
2910 #endif
2911
2912 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2913 if (UDC_REV_REG >= 0x61)
2914 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2915 else
2916 udc->clr_halt = UDC_RESET_EP;
2917
2918 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2919 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2920 IRQF_SAMPLE_RANDOM, driver_name, udc);
2921 if (status != 0) {
2922 ERR("can't get irq %d, err %d\n",
2923 (int) pdev->resource[1].start, status);
2924 goto cleanup1;
2925 }
2926
2927 /* USB "non-iso" IRQ (PIO for all but ep0) */
2928 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2929 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2930 if (status != 0) {
2931 ERR("can't get irq %d, err %d\n",
2932 (int) pdev->resource[2].start, status);
2933 goto cleanup2;
2934 }
2935 #ifdef USE_ISO
2936 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2937 IRQF_DISABLED, "omap_udc iso", udc);
2938 if (status != 0) {
2939 ERR("can't get irq %d, err %d\n",
2940 (int) pdev->resource[3].start, status);
2941 goto cleanup3;
2942 }
2943 #endif
2944 if (cpu_is_omap16xx()) {
2945 udc->dc_clk = dc_clk;
2946 udc->hhc_clk = hhc_clk;
2947 clk_disable(hhc_clk);
2948 clk_disable(dc_clk);
2949 }
2950
2951 if (cpu_is_omap24xx()) {
2952 udc->dc_clk = dc_clk;
2953 udc->hhc_clk = hhc_clk;
2954 /* FIXME OMAP2 don't release hhc & dc clock */
2955 #if 0
2956 clk_disable(hhc_clk);
2957 clk_disable(dc_clk);
2958 #endif
2959 }
2960
2961 create_proc_file();
2962 status = device_add(&udc->gadget.dev);
2963 if (!status)
2964 return status;
2965 /* If fail, fall through */
2966 #ifdef USE_ISO
2967 cleanup3:
2968 free_irq(pdev->resource[2].start, udc);
2969 #endif
2970
2971 cleanup2:
2972 free_irq(pdev->resource[1].start, udc);
2973
2974 cleanup1:
2975 kfree (udc);
2976 udc = NULL;
2977
2978 cleanup0:
2979 if (xceiv)
2980 put_device(xceiv->dev);
2981
2982 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2983 clk_disable(hhc_clk);
2984 clk_disable(dc_clk);
2985 clk_put(hhc_clk);
2986 clk_put(dc_clk);
2987 }
2988
2989 release_mem_region(pdev->resource[0].start,
2990 pdev->resource[0].end - pdev->resource[0].start + 1);
2991
2992 return status;
2993 }
2994
2995 static int __exit omap_udc_remove(struct platform_device *pdev)
2996 {
2997 DECLARE_COMPLETION_ONSTACK(done);
2998
2999 if (!udc)
3000 return -ENODEV;
3001 if (udc->driver)
3002 return -EBUSY;
3003
3004 udc->done = &done;
3005
3006 pullup_disable(udc);
3007 if (udc->transceiver) {
3008 put_device(udc->transceiver->dev);
3009 udc->transceiver = NULL;
3010 }
3011 UDC_SYSCON1_REG = 0;
3012
3013 remove_proc_file();
3014
3015 #ifdef USE_ISO
3016 free_irq(pdev->resource[3].start, udc);
3017 #endif
3018 free_irq(pdev->resource[2].start, udc);
3019 free_irq(pdev->resource[1].start, udc);
3020
3021 if (udc->dc_clk) {
3022 if (udc->clk_requested)
3023 omap_udc_enable_clock(0);
3024 clk_put(udc->hhc_clk);
3025 clk_put(udc->dc_clk);
3026 }
3027
3028 release_mem_region(pdev->resource[0].start,
3029 pdev->resource[0].end - pdev->resource[0].start + 1);
3030
3031 device_unregister(&udc->gadget.dev);
3032 wait_for_completion(&done);
3033
3034 return 0;
3035 }
3036
3037 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3038 * system is forced into deep sleep
3039 *
3040 * REVISIT we should probably reject suspend requests when there's a host
3041 * session active, rather than disconnecting, at least on boards that can
3042 * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to
3043 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3044 * may involve talking to an external transceiver (e.g. isp1301).
3045 */
3046
3047 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3048 {
3049 u32 devstat;
3050
3051 devstat = UDC_DEVSTAT_REG;
3052
3053 /* we're requesting 48 MHz clock if the pullup is enabled
3054 * (== we're attached to the host) and we're not suspended,
3055 * which would prevent entry to deep sleep...
3056 */
3057 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3058 WARN("session active; suspend requires disconnect\n");
3059 omap_pullup(&udc->gadget, 0);
3060 }
3061
3062 return 0;
3063 }
3064
3065 static int omap_udc_resume(struct platform_device *dev)
3066 {
3067 DBG("resume + wakeup/SRP\n");
3068 omap_pullup(&udc->gadget, 1);
3069
3070 /* maybe the host would enumerate us if we nudged it */
3071 msleep(100);
3072 return omap_wakeup(&udc->gadget);
3073 }
3074
3075 /*-------------------------------------------------------------------------*/
3076
3077 static struct platform_driver udc_driver = {
3078 .probe = omap_udc_probe,
3079 .remove = __exit_p(omap_udc_remove),
3080 .suspend = omap_udc_suspend,
3081 .resume = omap_udc_resume,
3082 .driver = {
3083 .owner = THIS_MODULE,
3084 .name = (char *) driver_name,
3085 },
3086 };
3087
3088 static int __init udc_init(void)
3089 {
3090 INFO("%s, version: " DRIVER_VERSION
3091 #ifdef USE_ISO
3092 " (iso)"
3093 #endif
3094 "%s\n", driver_desc,
3095 use_dma ? " (dma)" : "");
3096 return platform_driver_register(&udc_driver);
3097 }
3098 module_init(udc_init);
3099
3100 static void __exit udc_exit(void)
3101 {
3102 platform_driver_unregister(&udc_driver);
3103 }
3104 module_exit(udc_exit);
3105
3106 MODULE_DESCRIPTION(DRIVER_DESC);
3107 MODULE_LICENSE("GPL");
3108 MODULE_ALIAS("platform:omap_udc");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree