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[PATCH] dm mirror log: sector size fix
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / i810 / i810_main.c
bloba1f7d80f0ac103928003127b7c6a2fb90c66f7b2
1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_main.c -- Intel 810 frame buffer device
3 *
4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
5 * All Rights Reserved
6 *
7 * Contributors:
8 * Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets
9 * and enabling the power-on state of
10 * external VGA connectors for
11 * secondary displays
12 *
13 * Fredrik Andersson <krueger@shell.linux.se> - alpha testing of
14 * the VESA GTF
15 *
16 * Brad Corrion <bcorrion@web-co.com> - alpha testing of customized
17 * timings support
18 *
19 * The code framework is a modification of vfb.c by Geert Uytterhoeven.
20 * DotClock and PLL calculations are partly based on i810_driver.c
21 * in xfree86 v4.0.3 by Precision Insight.
22 * Watermark calculation and tables are based on i810_wmark.c
23 * in xfre86 v4.0.3 by Precision Insight. Slight modifications
24 * only to allow for integer operations instead of floating point.
25 *
26 * This file is subject to the terms and conditions of the GNU General Public
27 * License. See the file COPYING in the main directory of this archive for
28 * more details.
29 */
30
31 #include <linux/module.h>
32 #include <linux/config.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
36 #include <linux/mm.h>
37 #include <linux/tty.h>
38 #include <linux/slab.h>
39 #include <linux/fb.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/pci_ids.h>
43 #include <linux/resource.h>
44 #include <linux/unistd.h>
45 #include <linux/console.h>
46
47 #include <asm/io.h>
48 #include <asm/div64.h>
49 #include <asm/page.h>
50
51 #include "i810_regs.h"
52 #include "i810.h"
53 #include "i810_main.h"
54
55 /*
56 * voffset - framebuffer offset in MiB from aperture start address. In order for
57 * the driver to work with X, we must try to use memory holes left untouched by X. The
58 * following table lists where X's different surfaces start at.
59 *
60 * ---------------------------------------------
61 * : : 64 MiB : 32 MiB :
62 * ----------------------------------------------
63 * : FrontBuffer : 0 : 0 :
64 * : DepthBuffer : 48 : 16 :
65 * : BackBuffer : 56 : 24 :
66 * ----------------------------------------------
67 *
68 * So for chipsets with 64 MiB Aperture sizes, 32 MiB for v_offset is okay, allowing up to
69 * 15 + 1 MiB of Framebuffer memory. For 32 MiB Aperture sizes, a v_offset of 8 MiB should
70 * work, allowing 7 + 1 MiB of Framebuffer memory.
71 * Note, the size of the hole may change depending on how much memory you allocate to X,
72 * and how the memory is split up between these surfaces.
73 *
74 * Note: Anytime the DepthBuffer or FrontBuffer is overlapped, X would still run but with
75 * DRI disabled. But if the Frontbuffer is overlapped, X will fail to load.
76 *
77 * Experiment with v_offset to find out which works best for you.
78 */
79 static u32 v_offset_default __devinitdata; /* For 32 MiB Aper size, 8 should be the default */
80 static u32 voffset __devinitdata;
81
82 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
83 static int __devinit i810fb_init_pci (struct pci_dev *dev,
84 const struct pci_device_id *entry);
85 static void __exit i810fb_remove_pci(struct pci_dev *dev);
86 static int i810fb_resume(struct pci_dev *dev);
87 static int i810fb_suspend(struct pci_dev *dev, pm_message_t state);
88
89 /* Chipset Specific Functions */
90 static int i810fb_set_par (struct fb_info *info);
91 static int i810fb_getcolreg (u8 regno, u8 *red, u8 *green, u8 *blue,
92 u8 *transp, struct fb_info *info);
93 static int i810fb_setcolreg (unsigned regno, unsigned red, unsigned green, unsigned blue,
94 unsigned transp, struct fb_info *info);
95 static int i810fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
96 static int i810fb_blank (int blank_mode, struct fb_info *info);
97
98 /* Initialization */
99 static void i810fb_release_resource (struct fb_info *info, struct i810fb_par *par);
100
101 /* PCI */
102 static const char *i810_pci_list[] __devinitdata = {
103 "Intel(R) 810 Framebuffer Device" ,
104 "Intel(R) 810-DC100 Framebuffer Device" ,
105 "Intel(R) 810E Framebuffer Device" ,
106 "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" ,
107 "Intel(R) 815 (Internal Graphics only) Framebuffer Device" ,
108 "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device"
109 };
110
111 static struct pci_device_id i810fb_pci_tbl[] = {
112 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
114 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
116 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
118 /* mvo: added i815 PCI-ID */
119 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
121 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
123 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
125 { 0 },
126 };
127
128 static struct pci_driver i810fb_driver = {
129 .name = "i810fb",
130 .id_table = i810fb_pci_tbl,
131 .probe = i810fb_init_pci,
132 .remove = __exit_p(i810fb_remove_pci),
133 .suspend = i810fb_suspend,
134 .resume = i810fb_resume,
135 };
136
137 static char *mode_option __devinitdata = NULL;
138 static int vram __devinitdata = 4;
139 static int bpp __devinitdata = 8;
140 static int mtrr __devinitdata;
141 static int accel __devinitdata;
142 static int hsync1 __devinitdata;
143 static int hsync2 __devinitdata;
144 static int vsync1 __devinitdata;
145 static int vsync2 __devinitdata;
146 static int xres __devinitdata;
147 static int yres __devinitdata;
148 static int vyres __devinitdata;
149 static int sync __devinitdata;
150 static int extvga __devinitdata;
151 static int dcolor __devinitdata;
152 static int ddc3 __devinitdata = 2;
153
154 /*------------------------------------------------------------*/
155
156 /**************************************************************
157 * Hardware Low Level Routines *
158 **************************************************************/
159
160 /**
161 * i810_screen_off - turns off/on display
162 * @mmio: address of register space
163 * @mode: on or off
164 *
165 * DESCRIPTION:
166 * Blanks/unblanks the display
167 */
168 static void i810_screen_off(u8 __iomem *mmio, u8 mode)
169 {
170 u32 count = WAIT_COUNT;
171 u8 val;
172
173 i810_writeb(SR_INDEX, mmio, SR01);
174 val = i810_readb(SR_DATA, mmio);
175 val = (mode == OFF) ? val | SCR_OFF :
176 val & ~SCR_OFF;
177
178 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
179 i810_writeb(SR_INDEX, mmio, SR01);
180 i810_writeb(SR_DATA, mmio, val);
181 }
182
183 /**
184 * i810_dram_off - turns off/on dram refresh
185 * @mmio: address of register space
186 * @mode: on or off
187 *
188 * DESCRIPTION:
189 * Turns off DRAM refresh. Must be off for only 2 vsyncs
190 * before data becomes corrupt
191 */
192 static void i810_dram_off(u8 __iomem *mmio, u8 mode)
193 {
194 u8 val;
195
196 val = i810_readb(DRAMCH, mmio);
197 val &= DRAM_OFF;
198 val = (mode == OFF) ? val : val | DRAM_ON;
199 i810_writeb(DRAMCH, mmio, val);
200 }
201
202 /**
203 * i810_protect_regs - allows rw/ro mode of certain VGA registers
204 * @mmio: address of register space
205 * @mode: protect/unprotect
206 *
207 * DESCRIPTION:
208 * The IBM VGA standard allows protection of certain VGA registers.
209 * This will protect or unprotect them.
210 */
211 static void i810_protect_regs(u8 __iomem *mmio, int mode)
212 {
213 u8 reg;
214
215 i810_writeb(CR_INDEX_CGA, mmio, CR11);
216 reg = i810_readb(CR_DATA_CGA, mmio);
217 reg = (mode == OFF) ? reg & ~0x80 :
218 reg | 0x80;
219
220 i810_writeb(CR_INDEX_CGA, mmio, CR11);
221 i810_writeb(CR_DATA_CGA, mmio, reg);
222 }
223
224 /**
225 * i810_load_pll - loads values for the hardware PLL clock
226 * @par: pointer to i810fb_par structure
227 *
228 * DESCRIPTION:
229 * Loads the P, M, and N registers.
230 */
231 static void i810_load_pll(struct i810fb_par *par)
232 {
233 u32 tmp1, tmp2;
234 u8 __iomem *mmio = par->mmio_start_virtual;
235
236 tmp1 = par->regs.M | par->regs.N << 16;
237 tmp2 = i810_readl(DCLK_2D, mmio);
238 tmp2 &= ~MN_MASK;
239 i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
240
241 tmp1 = par->regs.P;
242 tmp2 = i810_readl(DCLK_0DS, mmio);
243 tmp2 &= ~(P_OR << 16);
244 i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2);
245
246 i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1);
247
248 }
249
250 /**
251 * i810_load_vga - load standard VGA registers
252 * @par: pointer to i810fb_par structure
253 *
254 * DESCRIPTION:
255 * Load values to VGA registers
256 */
257 static void i810_load_vga(struct i810fb_par *par)
258 {
259 u8 __iomem *mmio = par->mmio_start_virtual;
260
261 /* interlace */
262 i810_writeb(CR_INDEX_CGA, mmio, CR70);
263 i810_writeb(CR_DATA_CGA, mmio, par->interlace);
264
265 i810_writeb(CR_INDEX_CGA, mmio, CR00);
266 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00);
267 i810_writeb(CR_INDEX_CGA, mmio, CR01);
268 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01);
269 i810_writeb(CR_INDEX_CGA, mmio, CR02);
270 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02);
271 i810_writeb(CR_INDEX_CGA, mmio, CR03);
272 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03);
273 i810_writeb(CR_INDEX_CGA, mmio, CR04);
274 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04);
275 i810_writeb(CR_INDEX_CGA, mmio, CR05);
276 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05);
277 i810_writeb(CR_INDEX_CGA, mmio, CR06);
278 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06);
279 i810_writeb(CR_INDEX_CGA, mmio, CR09);
280 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09);
281 i810_writeb(CR_INDEX_CGA, mmio, CR10);
282 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10);
283 i810_writeb(CR_INDEX_CGA, mmio, CR11);
284 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11);
285 i810_writeb(CR_INDEX_CGA, mmio, CR12);
286 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12);
287 i810_writeb(CR_INDEX_CGA, mmio, CR15);
288 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15);
289 i810_writeb(CR_INDEX_CGA, mmio, CR16);
290 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16);
291 }
292
293 /**
294 * i810_load_vgax - load extended VGA registers
295 * @par: pointer to i810fb_par structure
296 *
297 * DESCRIPTION:
298 * Load values to extended VGA registers
299 */
300 static void i810_load_vgax(struct i810fb_par *par)
301 {
302 u8 __iomem *mmio = par->mmio_start_virtual;
303
304 i810_writeb(CR_INDEX_CGA, mmio, CR30);
305 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30);
306 i810_writeb(CR_INDEX_CGA, mmio, CR31);
307 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31);
308 i810_writeb(CR_INDEX_CGA, mmio, CR32);
309 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32);
310 i810_writeb(CR_INDEX_CGA, mmio, CR33);
311 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33);
312 i810_writeb(CR_INDEX_CGA, mmio, CR35);
313 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35);
314 i810_writeb(CR_INDEX_CGA, mmio, CR39);
315 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39);
316 }
317
318 /**
319 * i810_load_2d - load grahics registers
320 * @par: pointer to i810fb_par structure
321 *
322 * DESCRIPTION:
323 * Load values to graphics registers
324 */
325 static void i810_load_2d(struct i810fb_par *par)
326 {
327 u32 tmp;
328 u8 tmp8;
329 u8 __iomem *mmio = par->mmio_start_virtual;
330
331 i810_writel(FW_BLC, mmio, par->watermark);
332 tmp = i810_readl(PIXCONF, mmio);
333 tmp |= 1 | 1 << 20;
334 i810_writel(PIXCONF, mmio, tmp);
335
336 i810_writel(OVRACT, mmio, par->ovract);
337
338 i810_writeb(GR_INDEX, mmio, GR10);
339 tmp8 = i810_readb(GR_DATA, mmio);
340 tmp8 |= 2;
341 i810_writeb(GR_INDEX, mmio, GR10);
342 i810_writeb(GR_DATA, mmio, tmp8);
343 }
344
345 /**
346 * i810_hires - enables high resolution mode
347 * @mmio: address of register space
348 */
349 static void i810_hires(u8 __iomem *mmio)
350 {
351 u8 val;
352
353 i810_writeb(CR_INDEX_CGA, mmio, CR80);
354 val = i810_readb(CR_DATA_CGA, mmio);
355 i810_writeb(CR_INDEX_CGA, mmio, CR80);
356 i810_writeb(CR_DATA_CGA, mmio, val | 1);
357 /* Stop LCD displays from flickering */
358 i810_writel(MEM_MODE, mmio, i810_readl(MEM_MODE, mmio) | 4);
359 }
360
361 /**
362 * i810_load_pitch - loads the characters per line of the display
363 * @par: pointer to i810fb_par structure
364 *
365 * DESCRIPTION:
366 * Loads the characters per line
367 */
368 static void i810_load_pitch(struct i810fb_par *par)
369 {
370 u32 tmp, pitch;
371 u8 val;
372 u8 __iomem *mmio = par->mmio_start_virtual;
373
374 pitch = par->pitch >> 3;
375 i810_writeb(SR_INDEX, mmio, SR01);
376 val = i810_readb(SR_DATA, mmio);
377 val &= 0xE0;
378 val |= 1 | 1 << 2;
379 i810_writeb(SR_INDEX, mmio, SR01);
380 i810_writeb(SR_DATA, mmio, val);
381
382 tmp = pitch & 0xFF;
383 i810_writeb(CR_INDEX_CGA, mmio, CR13);
384 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp);
385
386 tmp = pitch >> 8;
387 i810_writeb(CR_INDEX_CGA, mmio, CR41);
388 val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F;
389 i810_writeb(CR_INDEX_CGA, mmio, CR41);
390 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val);
391 }
392
393 /**
394 * i810_load_color - loads the color depth of the display
395 * @par: pointer to i810fb_par structure
396 *
397 * DESCRIPTION:
398 * Loads the color depth of the display and the graphics engine
399 */
400 static void i810_load_color(struct i810fb_par *par)
401 {
402 u8 __iomem *mmio = par->mmio_start_virtual;
403 u32 reg1;
404 u16 reg2;
405
406 reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27);
407 reg2 = i810_readw(BLTCNTL, mmio) & ~0x30;
408
409 reg1 |= 0x8000 | par->pixconf;
410 reg2 |= par->bltcntl;
411 i810_writel(PIXCONF, mmio, reg1);
412 i810_writew(BLTCNTL, mmio, reg2);
413 }
414
415 /**
416 * i810_load_regs - loads all registers for the mode
417 * @par: pointer to i810fb_par structure
418 *
419 * DESCRIPTION:
420 * Loads registers
421 */
422 static void i810_load_regs(struct i810fb_par *par)
423 {
424 u8 __iomem *mmio = par->mmio_start_virtual;
425
426 i810_screen_off(mmio, OFF);
427 i810_protect_regs(mmio, OFF);
428 i810_dram_off(mmio, OFF);
429 i810_load_pll(par);
430 i810_load_vga(par);
431 i810_load_vgax(par);
432 i810_dram_off(mmio, ON);
433 i810_load_2d(par);
434 i810_hires(mmio);
435 i810_screen_off(mmio, ON);
436 i810_protect_regs(mmio, ON);
437 i810_load_color(par);
438 i810_load_pitch(par);
439 }
440
441 static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue,
442 u8 __iomem *mmio)
443 {
444 i810_writeb(CLUT_INDEX_WRITE, mmio, regno);
445 i810_writeb(CLUT_DATA, mmio, red);
446 i810_writeb(CLUT_DATA, mmio, green);
447 i810_writeb(CLUT_DATA, mmio, blue);
448 }
449
450 static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue,
451 u8 __iomem *mmio)
452 {
453 i810_writeb(CLUT_INDEX_READ, mmio, regno);
454 *red = i810_readb(CLUT_DATA, mmio);
455 *green = i810_readb(CLUT_DATA, mmio);
456 *blue = i810_readb(CLUT_DATA, mmio);
457 }
458
459 /************************************************************
460 * VGA State Restore *
461 ************************************************************/
462 static void i810_restore_pll(struct i810fb_par *par)
463 {
464 u32 tmp1, tmp2;
465 u8 __iomem *mmio = par->mmio_start_virtual;
466
467 tmp1 = par->hw_state.dclk_2d;
468 tmp2 = i810_readl(DCLK_2D, mmio);
469 tmp1 &= ~MN_MASK;
470 tmp2 &= MN_MASK;
471 i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
472
473 tmp1 = par->hw_state.dclk_1d;
474 tmp2 = i810_readl(DCLK_1D, mmio);
475 tmp1 &= ~MN_MASK;
476 tmp2 &= MN_MASK;
477 i810_writel(DCLK_1D, mmio, tmp1 | tmp2);
478
479 i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds);
480 }
481
482 static void i810_restore_dac(struct i810fb_par *par)
483 {
484 u32 tmp1, tmp2;
485 u8 __iomem *mmio = par->mmio_start_virtual;
486
487 tmp1 = par->hw_state.pixconf;
488 tmp2 = i810_readl(PIXCONF, mmio);
489 tmp1 &= DAC_BIT;
490 tmp2 &= ~DAC_BIT;
491 i810_writel(PIXCONF, mmio, tmp1 | tmp2);
492 }
493
494 static void i810_restore_vgax(struct i810fb_par *par)
495 {
496 u8 i, j;
497 u8 __iomem *mmio = par->mmio_start_virtual;
498
499 for (i = 0; i < 4; i++) {
500 i810_writeb(CR_INDEX_CGA, mmio, CR30+i);
501 i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i));
502 }
503 i810_writeb(CR_INDEX_CGA, mmio, CR35);
504 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35);
505 i810_writeb(CR_INDEX_CGA, mmio, CR39);
506 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
507 i810_writeb(CR_INDEX_CGA, mmio, CR41);
508 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
509
510 /*restore interlace*/
511 i810_writeb(CR_INDEX_CGA, mmio, CR70);
512 i = par->hw_state.cr70;
513 i &= INTERLACE_BIT;
514 j = i810_readb(CR_DATA_CGA, mmio);
515 i810_writeb(CR_INDEX_CGA, mmio, CR70);
516 i810_writeb(CR_DATA_CGA, mmio, j | i);
517
518 i810_writeb(CR_INDEX_CGA, mmio, CR80);
519 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80);
520 i810_writeb(MSR_WRITE, mmio, par->hw_state.msr);
521 i810_writeb(SR_INDEX, mmio, SR01);
522 i = (par->hw_state.sr01) & ~0xE0 ;
523 j = i810_readb(SR_DATA, mmio) & 0xE0;
524 i810_writeb(SR_INDEX, mmio, SR01);
525 i810_writeb(SR_DATA, mmio, i | j);
526 }
527
528 static void i810_restore_vga(struct i810fb_par *par)
529 {
530 u8 i;
531 u8 __iomem *mmio = par->mmio_start_virtual;
532
533 for (i = 0; i < 10; i++) {
534 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
535 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i));
536 }
537 for (i = 0; i < 8; i++) {
538 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
539 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i));
540 }
541 }
542
543 static void i810_restore_addr_map(struct i810fb_par *par)
544 {
545 u8 tmp;
546 u8 __iomem *mmio = par->mmio_start_virtual;
547
548 i810_writeb(GR_INDEX, mmio, GR10);
549 tmp = i810_readb(GR_DATA, mmio);
550 tmp &= ADDR_MAP_MASK;
551 tmp |= par->hw_state.gr10;
552 i810_writeb(GR_INDEX, mmio, GR10);
553 i810_writeb(GR_DATA, mmio, tmp);
554 }
555
556 static void i810_restore_2d(struct i810fb_par *par)
557 {
558 u32 tmp_long;
559 u16 tmp_word;
560 u8 __iomem *mmio = par->mmio_start_virtual;
561
562 tmp_word = i810_readw(BLTCNTL, mmio);
563 tmp_word &= ~(3 << 4);
564 tmp_word |= par->hw_state.bltcntl;
565 i810_writew(BLTCNTL, mmio, tmp_word);
566
567 i810_dram_off(mmio, OFF);
568 i810_writel(PIXCONF, mmio, par->hw_state.pixconf);
569 i810_dram_off(mmio, ON);
570
571 tmp_word = i810_readw(HWSTAM, mmio);
572 tmp_word &= 3 << 13;
573 tmp_word |= par->hw_state.hwstam;
574 i810_writew(HWSTAM, mmio, tmp_word);
575
576 tmp_long = i810_readl(FW_BLC, mmio);
577 tmp_long &= FW_BLC_MASK;
578 tmp_long |= par->hw_state.fw_blc;
579 i810_writel(FW_BLC, mmio, tmp_long);
580
581 i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga);
582 i810_writew(IER, mmio, par->hw_state.ier);
583 i810_writew(IMR, mmio, par->hw_state.imr);
584 i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas);
585 }
586
587 static void i810_restore_vga_state(struct i810fb_par *par)
588 {
589 u8 __iomem *mmio = par->mmio_start_virtual;
590
591 i810_screen_off(mmio, OFF);
592 i810_protect_regs(mmio, OFF);
593 i810_dram_off(mmio, OFF);
594 i810_restore_pll(par);
595 i810_restore_dac(par);
596 i810_restore_vga(par);
597 i810_restore_vgax(par);
598 i810_restore_addr_map(par);
599 i810_dram_off(mmio, ON);
600 i810_restore_2d(par);
601 i810_screen_off(mmio, ON);
602 i810_protect_regs(mmio, ON);
603 }
604
605 /***********************************************************************
606 * VGA State Save *
607 ***********************************************************************/
608
609 static void i810_save_vgax(struct i810fb_par *par)
610 {
611 u8 i;
612 u8 __iomem *mmio = par->mmio_start_virtual;
613
614 for (i = 0; i < 4; i++) {
615 i810_writeb(CR_INDEX_CGA, mmio, CR30 + i);
616 *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio);
617 }
618 i810_writeb(CR_INDEX_CGA, mmio, CR35);
619 par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio);
620 i810_writeb(CR_INDEX_CGA, mmio, CR39);
621 par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio);
622 i810_writeb(CR_INDEX_CGA, mmio, CR41);
623 par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio);
624 i810_writeb(CR_INDEX_CGA, mmio, CR70);
625 par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio);
626 par->hw_state.msr = i810_readb(MSR_READ, mmio);
627 i810_writeb(CR_INDEX_CGA, mmio, CR80);
628 par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio);
629 i810_writeb(SR_INDEX, mmio, SR01);
630 par->hw_state.sr01 = i810_readb(SR_DATA, mmio);
631 }
632
633 static void i810_save_vga(struct i810fb_par *par)
634 {
635 u8 i;
636 u8 __iomem *mmio = par->mmio_start_virtual;
637
638 for (i = 0; i < 10; i++) {
639 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
640 *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio);
641 }
642 for (i = 0; i < 8; i++) {
643 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
644 *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio);
645 }
646 }
647
648 static void i810_save_2d(struct i810fb_par *par)
649 {
650 u8 __iomem *mmio = par->mmio_start_virtual;
651
652 par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio);
653 par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio);
654 par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio);
655 par->hw_state.pixconf = i810_readl(PIXCONF, mmio);
656 par->hw_state.fw_blc = i810_readl(FW_BLC, mmio);
657 par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio);
658 par->hw_state.hwstam = i810_readw(HWSTAM, mmio);
659 par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio);
660 par->hw_state.ier = i810_readw(IER, mmio);
661 par->hw_state.imr = i810_readw(IMR, mmio);
662 par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio);
663 }
664
665 static void i810_save_vga_state(struct i810fb_par *par)
666 {
667 i810_save_vga(par);
668 i810_save_vgax(par);
669 i810_save_2d(par);
670 }
671
672 /************************************************************
673 * Helpers *
674 ************************************************************/
675 /**
676 * get_line_length - calculates buffer pitch in bytes
677 * @par: pointer to i810fb_par structure
678 * @xres_virtual: virtual resolution of the frame
679 * @bpp: bits per pixel
680 *
681 * DESCRIPTION:
682 * Calculates buffer pitch in bytes.
683 */
684 static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp)
685 {
686 u32 length;
687
688 length = xres_virtual*bpp;
689 length = (length+31)&-32;
690 length >>= 3;
691 return length;
692 }
693
694 /**
695 * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value
696 * @freq: target pixelclock in picoseconds
697 * @m: where to write M register
698 * @n: where to write N register
699 * @p: where to write P register
700 *
701 * DESCRIPTION:
702 * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P)
703 * Repeatedly computes the Freq until the actual Freq is equal to
704 * the target Freq or until the loop count is zero. In the latter
705 * case, the actual frequency nearest the target will be used.
706 */
707 static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p)
708 {
709 u32 m_reg, n_reg, p_divisor, n_target_max;
710 u32 m_target, n_target, p_target, n_best, m_best, mod;
711 u32 f_out, target_freq, diff = 0, mod_min, diff_min;
712
713 diff_min = mod_min = 0xFFFFFFFF;
714 n_best = m_best = m_target = f_out = 0;
715
716 target_freq = freq;
717 n_target_max = 30;
718
719 /*
720 * find P such that target freq is 16x reference freq (Hz).
721 */
722 p_divisor = 1;
723 p_target = 0;
724 while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) &&
725 p_divisor <= 32) {
726 p_divisor <<= 1;
727 p_target++;
728 }
729
730 n_reg = m_reg = n_target = 3;
731 while (diff_min && mod_min && (n_target < n_target_max)) {
732 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg);
733 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg);
734 m_target = m_reg;
735 n_target = n_reg;
736 if (f_out <= target_freq) {
737 n_reg++;
738 diff = target_freq - f_out;
739 } else {
740 m_reg++;
741 diff = f_out - target_freq;
742 }
743
744 if (diff_min > diff) {
745 diff_min = diff;
746 n_best = n_target;
747 m_best = m_target;
748 }
749
750 if (!diff && mod_min > mod) {
751 mod_min = mod;
752 n_best = n_target;
753 m_best = m_target;
754 }
755 }
756 if (m) *m = (m_best - 2) & 0x3FF;
757 if (n) *n = (n_best - 2) & 0x3FF;
758 if (p) *p = (p_target << 4);
759 }
760
761 /*************************************************************
762 * Hardware Cursor Routines *
763 *************************************************************/
764
765 /**
766 * i810_enable_cursor - show or hide the hardware cursor
767 * @mmio: address of register space
768 * @mode: show (1) or hide (0)
769 *
770 * Description:
771 * Shows or hides the hardware cursor
772 */
773 static void i810_enable_cursor(u8 __iomem *mmio, int mode)
774 {
775 u32 temp;
776
777 temp = i810_readl(PIXCONF, mmio);
778 temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK :
779 temp & ~CURSOR_ENABLE_MASK;
780
781 i810_writel(PIXCONF, mmio, temp);
782 }
783
784 static void i810_reset_cursor_image(struct i810fb_par *par)
785 {
786 u8 __iomem *addr = par->cursor_heap.virtual;
787 int i, j;
788
789 for (i = 64; i--; ) {
790 for (j = 0; j < 8; j++) {
791 i810_writeb(j, addr, 0xff);
792 i810_writeb(j+8, addr, 0x00);
793 }
794 addr +=16;
795 }
796 }
797
798 static void i810_load_cursor_image(int width, int height, u8 *data,
799 struct i810fb_par *par)
800 {
801 u8 __iomem *addr = par->cursor_heap.virtual;
802 int i, j, w = width/8;
803 int mod = width % 8, t_mask, d_mask;
804
805 t_mask = 0xff >> mod;
806 d_mask = ~(0xff >> mod);
807 for (i = height; i--; ) {
808 for (j = 0; j < w; j++) {
809 i810_writeb(j+0, addr, 0x00);
810 i810_writeb(j+8, addr, *data++);
811 }
812 if (mod) {
813 i810_writeb(j+0, addr, t_mask);
814 i810_writeb(j+8, addr, *data++ & d_mask);
815 }
816 addr += 16;
817 }
818 }
819
820 static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info)
821 {
822 struct i810fb_par *par = info->par;
823 u8 __iomem *mmio = par->mmio_start_virtual;
824 u8 red, green, blue, trans, temp;
825
826 i810fb_getcolreg(bg, &red, &green, &blue, &trans, info);
827
828 temp = i810_readb(PIXCONF1, mmio);
829 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
830
831 i810_write_dac(4, red, green, blue, mmio);
832
833 i810_writeb(PIXCONF1, mmio, temp);
834
835 i810fb_getcolreg(fg, &red, &green, &blue, &trans, info);
836 temp = i810_readb(PIXCONF1, mmio);
837 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
838
839 i810_write_dac(5, red, green, blue, mmio);
840
841 i810_writeb(PIXCONF1, mmio, temp);
842 }
843
844 /**
845 * i810_init_cursor - initializes the cursor
846 * @par: pointer to i810fb_par structure
847 *
848 * DESCRIPTION:
849 * Initializes the cursor registers
850 */
851 static void i810_init_cursor(struct i810fb_par *par)
852 {
853 u8 __iomem *mmio = par->mmio_start_virtual;
854
855 i810_enable_cursor(mmio, OFF);
856 i810_writel(CURBASE, mmio, par->cursor_heap.physical);
857 i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR);
858 }
859
860 /*********************************************************************
861 * Framebuffer hook helpers *
862 *********************************************************************/
863 /**
864 * i810_round_off - Round off values to capability of hardware
865 * @var: pointer to fb_var_screeninfo structure
866 *
867 * DESCRIPTION:
868 * @var contains user-defined information for the mode to be set.
869 * This will try modify those values to ones nearest the
870 * capability of the hardware
871 */
872 static void i810_round_off(struct fb_var_screeninfo *var)
873 {
874 u32 xres, yres, vxres, vyres;
875
876 /*
877 * Presently supports only these configurations
878 */
879
880 xres = var->xres;
881 yres = var->yres;
882 vxres = var->xres_virtual;
883 vyres = var->yres_virtual;
884
885 var->bits_per_pixel += 7;
886 var->bits_per_pixel &= ~7;
887
888 if (var->bits_per_pixel < 8)
889 var->bits_per_pixel = 8;
890 if (var->bits_per_pixel > 32)
891 var->bits_per_pixel = 32;
892
893 round_off_xres(&xres);
894 if (xres < 40)
895 xres = 40;
896 if (xres > 2048)
897 xres = 2048;
898 xres = (xres + 7) & ~7;
899
900 if (vxres < xres)
901 vxres = xres;
902
903 round_off_yres(&xres, &yres);
904 if (yres < 1)
905 yres = 1;
906 if (yres >= 2048)
907 yres = 2048;
908
909 if (vyres < yres)
910 vyres = yres;
911
912 if (var->bits_per_pixel == 32)
913 var->accel_flags = 0;
914
915 /* round of horizontal timings to nearest 8 pixels */
916 var->left_margin = (var->left_margin + 4) & ~7;
917 var->right_margin = (var->right_margin + 4) & ~7;
918 var->hsync_len = (var->hsync_len + 4) & ~7;
919
920 if (var->vmode & FB_VMODE_INTERLACED) {
921 if (!((yres + var->upper_margin + var->vsync_len +
922 var->lower_margin) & 1))
923 var->upper_margin++;
924 }
925
926 var->xres = xres;
927 var->yres = yres;
928 var->xres_virtual = vxres;
929 var->yres_virtual = vyres;
930 }
931
932 /**
933 * set_color_bitfields - sets rgba fields
934 * @var: pointer to fb_var_screeninfo
935 *
936 * DESCRIPTION:
937 * The length, offset and ordering for each color field
938 * (red, green, blue) will be set as specified
939 * by the hardware
940 */
941 static void set_color_bitfields(struct fb_var_screeninfo *var)
942 {
943 switch (var->bits_per_pixel) {
944 case 8:
945 var->red.offset = 0;
946 var->red.length = 8;
947 var->green.offset = 0;
948 var->green.length = 8;
949 var->blue.offset = 0;
950 var->blue.length = 8;
951 var->transp.offset = 0;
952 var->transp.length = 0;
953 break;
954 case 16:
955 var->green.length = (var->green.length == 5) ? 5 : 6;
956 var->red.length = 5;
957 var->blue.length = 5;
958 var->transp.length = 6 - var->green.length;
959 var->blue.offset = 0;
960 var->green.offset = 5;
961 var->red.offset = 5 + var->green.length;
962 var->transp.offset = (5 + var->red.offset) & 15;
963 break;
964 case 24: /* RGB 888 */
965 case 32: /* RGBA 8888 */
966 var->red.offset = 16;
967 var->red.length = 8;
968 var->green.offset = 8;
969 var->green.length = 8;
970 var->blue.offset = 0;
971 var->blue.length = 8;
972 var->transp.length = var->bits_per_pixel - 24;
973 var->transp.offset = (var->transp.length) ? 24 : 0;
974 break;
975 }
976 var->red.msb_right = 0;
977 var->green.msb_right = 0;
978 var->blue.msb_right = 0;
979 var->transp.msb_right = 0;
980 }
981
982 /**
983 * i810_check_params - check if contents in var are valid
984 * @var: pointer to fb_var_screeninfo
985 * @info: pointer to fb_info
986 *
987 * DESCRIPTION:
988 * This will check if the framebuffer size is sufficient
989 * for the current mode and if the user's monitor has the
990 * required specifications to display the current mode.
991 */
992 static int i810_check_params(struct fb_var_screeninfo *var,
993 struct fb_info *info)
994 {
995 struct i810fb_par *par = info->par;
996 int line_length, vidmem, mode_valid = 0, retval = 0;
997 u32 vyres = var->yres_virtual, vxres = var->xres_virtual;
998 /*
999 * Memory limit
1000 */
1001 line_length = get_line_length(par, vxres, var->bits_per_pixel);
1002 vidmem = line_length*vyres;
1003
1004 if (vidmem > par->fb.size) {
1005 vyres = par->fb.size/line_length;
1006 if (vyres < var->yres) {
1007 vyres = yres;
1008 vxres = par->fb.size/vyres;
1009 vxres /= var->bits_per_pixel >> 3;
1010 line_length = get_line_length(par, vxres,
1011 var->bits_per_pixel);
1012 vidmem = line_length * yres;
1013 if (vxres < var->xres) {
1014 printk("i810fb: required video memory, "
1015 "%d bytes, for %dx%d-%d (virtual) "
1016 "is out of range\n",
1017 vidmem, vxres, vyres,
1018 var->bits_per_pixel);
1019 return -ENOMEM;
1020 }
1021 }
1022 }
1023
1024 var->xres_virtual = vxres;
1025 var->yres_virtual = vyres;
1026
1027 /*
1028 * Monitor limit
1029 */
1030 switch (var->bits_per_pixel) {
1031 case 8:
1032 info->monspecs.dclkmax = 234000000;
1033 break;
1034 case 16:
1035 info->monspecs.dclkmax = 229000000;
1036 break;
1037 case 24:
1038 case 32:
1039 info->monspecs.dclkmax = 204000000;
1040 break;
1041 }
1042
1043 info->monspecs.dclkmin = 15000000;
1044
1045 if (!fb_validate_mode(var, info))
1046 mode_valid = 1;
1047
1048 #ifdef CONFIG_FB_I810_I2C
1049 if (!mode_valid && info->monspecs.gtf &&
1050 !fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1051 mode_valid = 1;
1052
1053 if (!mode_valid && info->monspecs.modedb_len) {
1054 struct fb_videomode *mode;
1055
1056 mode = fb_find_best_mode(var, &info->modelist);
1057 if (mode) {
1058 fb_videomode_to_var(var, mode);
1059 mode_valid = 1;
1060 }
1061 }
1062 #endif
1063 if (!mode_valid && info->monspecs.modedb_len == 0) {
1064 if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) {
1065 int default_sync = (info->monspecs.hfmin-HFMIN)
1066 |(info->monspecs.hfmax-HFMAX)
1067 |(info->monspecs.vfmin-VFMIN)
1068 |(info->monspecs.vfmax-VFMAX);
1069 printk("i810fb: invalid video mode%s\n",
1070 default_sync ? "" : ". Specifying "
1071 "vsyncN/hsyncN parameters may help");
1072 retval = -EINVAL;
1073 }
1074 }
1075
1076 return retval;
1077 }
1078
1079 /**
1080 * encode_fix - fill up fb_fix_screeninfo structure
1081 * @fix: pointer to fb_fix_screeninfo
1082 * @info: pointer to fb_info
1083 *
1084 * DESCRIPTION:
1085 * This will set up parameters that are unmodifiable by the user.
1086 */
1087 static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
1088 {
1089 struct i810fb_par *par = info->par;
1090
1091 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1092
1093 strcpy(fix->id, "I810");
1094 fix->smem_start = par->fb.physical;
1095 fix->smem_len = par->fb.size;
1096 fix->type = FB_TYPE_PACKED_PIXELS;
1097 fix->type_aux = 0;
1098 fix->xpanstep = 8;
1099 fix->ypanstep = 1;
1100
1101 switch (info->var.bits_per_pixel) {
1102 case 8:
1103 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1104 break;
1105 case 16:
1106 case 24:
1107 case 32:
1108 if (info->var.nonstd)
1109 fix->visual = FB_VISUAL_DIRECTCOLOR;
1110 else
1111 fix->visual = FB_VISUAL_TRUECOLOR;
1112 break;
1113 default:
1114 return -EINVAL;
1115 }
1116 fix->ywrapstep = 0;
1117 fix->line_length = par->pitch;
1118 fix->mmio_start = par->mmio_start_phys;
1119 fix->mmio_len = MMIO_SIZE;
1120 fix->accel = FB_ACCEL_I810;
1121
1122 return 0;
1123 }
1124
1125 /**
1126 * decode_var - modify par according to contents of var
1127 * @var: pointer to fb_var_screeninfo
1128 * @par: pointer to i810fb_par
1129 *
1130 * DESCRIPTION:
1131 * Based on the contents of @var, @par will be dynamically filled up.
1132 * @par contains all information necessary to modify the hardware.
1133 */
1134 static void decode_var(const struct fb_var_screeninfo *var,
1135 struct i810fb_par *par)
1136 {
1137 u32 xres, yres, vxres, vyres;
1138
1139 xres = var->xres;
1140 yres = var->yres;
1141 vxres = var->xres_virtual;
1142 vyres = var->yres_virtual;
1143
1144 switch (var->bits_per_pixel) {
1145 case 8:
1146 par->pixconf = PIXCONF8;
1147 par->bltcntl = 0;
1148 par->depth = 1;
1149 par->blit_bpp = BPP8;
1150 break;
1151 case 16:
1152 if (var->green.length == 5)
1153 par->pixconf = PIXCONF15;
1154 else
1155 par->pixconf = PIXCONF16;
1156 par->bltcntl = 16;
1157 par->depth = 2;
1158 par->blit_bpp = BPP16;
1159 break;
1160 case 24:
1161 par->pixconf = PIXCONF24;
1162 par->bltcntl = 32;
1163 par->depth = 3;
1164 par->blit_bpp = BPP24;
1165 break;
1166 case 32:
1167 par->pixconf = PIXCONF32;
1168 par->bltcntl = 0;
1169 par->depth = 4;
1170 par->blit_bpp = 3 << 24;
1171 break;
1172 }
1173 if (var->nonstd && var->bits_per_pixel != 8)
1174 par->pixconf |= 1 << 27;
1175
1176 i810_calc_dclk(var->pixclock, &par->regs.M,
1177 &par->regs.N, &par->regs.P);
1178 i810fb_encode_registers(var, par, xres, yres);
1179
1180 par->watermark = i810_get_watermark(var, par);
1181 par->pitch = get_line_length(par, vxres, var->bits_per_pixel);
1182 }
1183
1184 /**
1185 * i810fb_getcolreg - gets red, green and blue values of the hardware DAC
1186 * @regno: DAC index
1187 * @red: red
1188 * @green: green
1189 * @blue: blue
1190 * @transp: transparency (alpha)
1191 * @info: pointer to fb_info
1192 *
1193 * DESCRIPTION:
1194 * Gets the red, green and blue values of the hardware DAC as pointed by @regno
1195 * and writes them to @red, @green and @blue respectively
1196 */
1197 static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue,
1198 u8 *transp, struct fb_info *info)
1199 {
1200 struct i810fb_par *par = info->par;
1201 u8 __iomem *mmio = par->mmio_start_virtual;
1202 u8 temp;
1203
1204 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1205 if ((info->var.green.length == 5 && regno > 31) ||
1206 (info->var.green.length == 6 && regno > 63))
1207 return 1;
1208 }
1209
1210 temp = i810_readb(PIXCONF1, mmio);
1211 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1212
1213 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1214 info->var.green.length == 5)
1215 i810_read_dac(regno * 8, red, green, blue, mmio);
1216
1217 else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1218 info->var.green.length == 6) {
1219 u8 tmp;
1220
1221 i810_read_dac(regno * 8, red, &tmp, blue, mmio);
1222 i810_read_dac(regno * 4, &tmp, green, &tmp, mmio);
1223 }
1224 else
1225 i810_read_dac(regno, red, green, blue, mmio);
1226
1227 *transp = 0;
1228 i810_writeb(PIXCONF1, mmio, temp);
1229
1230 return 0;
1231 }
1232
1233 /******************************************************************
1234 * Framebuffer device-specific hooks *
1235 ******************************************************************/
1236
1237 static int i810fb_open(struct fb_info *info, int user)
1238 {
1239 struct i810fb_par *par = info->par;
1240 u32 count = atomic_read(&par->use_count);
1241
1242 if (count == 0) {
1243 memset(&par->state, 0, sizeof(struct vgastate));
1244 par->state.flags = VGA_SAVE_CMAP;
1245 par->state.vgabase = par->mmio_start_virtual;
1246 save_vga(&par->state);
1247
1248 i810_save_vga_state(par);
1249 }
1250
1251 atomic_inc(&par->use_count);
1252
1253 return 0;
1254 }
1255
1256 static int i810fb_release(struct fb_info *info, int user)
1257 {
1258 struct i810fb_par *par = info->par;
1259 u32 count;
1260
1261 count = atomic_read(&par->use_count);
1262 if (count == 0)
1263 return -EINVAL;
1264
1265 if (count == 1) {
1266 i810_restore_vga_state(par);
1267 restore_vga(&par->state);
1268 }
1269
1270 atomic_dec(&par->use_count);
1271
1272 return 0;
1273 }
1274
1275
1276 static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1277 unsigned blue, unsigned transp,
1278 struct fb_info *info)
1279 {
1280 struct i810fb_par *par = info->par;
1281 u8 __iomem *mmio = par->mmio_start_virtual;
1282 u8 temp;
1283 int i;
1284
1285 if (regno > 255) return 1;
1286
1287 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1288 if ((info->var.green.length == 5 && regno > 31) ||
1289 (info->var.green.length == 6 && regno > 63))
1290 return 1;
1291 }
1292
1293 if (info->var.grayscale)
1294 red = green = blue = (19595 * red + 38470 * green +
1295 7471 * blue) >> 16;
1296
1297 temp = i810_readb(PIXCONF1, mmio);
1298 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1299
1300 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1301 info->var.green.length == 5) {
1302 for (i = 0; i < 8; i++)
1303 i810_write_dac((u8) (regno * 8) + i, (u8) red,
1304 (u8) green, (u8) blue, mmio);
1305 } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1306 info->var.green.length == 6) {
1307 u8 r, g, b;
1308
1309 if (regno < 32) {
1310 for (i = 0; i < 8; i++)
1311 i810_write_dac((u8) (regno * 8) + i,
1312 (u8) red, (u8) green,
1313 (u8) blue, mmio);
1314 }
1315 i810_read_dac((u8) (regno*4), &r, &g, &b, mmio);
1316 for (i = 0; i < 4; i++)
1317 i810_write_dac((u8) (regno*4) + i, r, (u8) green,
1318 b, mmio);
1319 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
1320 i810_write_dac((u8) regno, (u8) red, (u8) green,
1321 (u8) blue, mmio);
1322 }
1323
1324 i810_writeb(PIXCONF1, mmio, temp);
1325
1326 if (regno < 16) {
1327 switch (info->var.bits_per_pixel) {
1328 case 16:
1329 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1330 if (info->var.green.length == 5)
1331 ((u32 *)info->pseudo_palette)[regno] =
1332 (regno << 10) | (regno << 5) |
1333 regno;
1334 else
1335 ((u32 *)info->pseudo_palette)[regno] =
1336 (regno << 11) | (regno << 5) |
1337 regno;
1338 } else {
1339 if (info->var.green.length == 5) {
1340 /* RGB 555 */
1341 ((u32 *)info->pseudo_palette)[regno] =
1342 ((red & 0xf800) >> 1) |
1343 ((green & 0xf800) >> 6) |
1344 ((blue & 0xf800) >> 11);
1345 } else {
1346 /* RGB 565 */
1347 ((u32 *)info->pseudo_palette)[regno] =
1348 (red & 0xf800) |
1349 ((green & 0xf800) >> 5) |
1350 ((blue & 0xf800) >> 11);
1351 }
1352 }
1353 break;
1354 case 24: /* RGB 888 */
1355 case 32: /* RGBA 8888 */
1356 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
1357 ((u32 *)info->pseudo_palette)[regno] =
1358 (regno << 16) | (regno << 8) |
1359 regno;
1360 else
1361 ((u32 *)info->pseudo_palette)[regno] =
1362 ((red & 0xff00) << 8) |
1363 (green & 0xff00) |
1364 ((blue & 0xff00) >> 8);
1365 break;
1366 }
1367 }
1368 return 0;
1369 }
1370
1371 static int i810fb_pan_display(struct fb_var_screeninfo *var,
1372 struct fb_info *info)
1373 {
1374 struct i810fb_par *par = info->par;
1375 u32 total;
1376
1377 total = var->xoffset * par->depth +
1378 var->yoffset * info->fix.line_length;
1379 i810fb_load_front(total, info);
1380
1381 return 0;
1382 }
1383
1384 static int i810fb_blank (int blank_mode, struct fb_info *info)
1385 {
1386 struct i810fb_par *par = info->par;
1387 u8 __iomem *mmio = par->mmio_start_virtual;
1388 int mode = 0, pwr, scr_off = 0;
1389
1390 pwr = i810_readl(PWR_CLKC, mmio);
1391
1392 switch (blank_mode) {
1393 case FB_BLANK_UNBLANK:
1394 mode = POWERON;
1395 pwr |= 1;
1396 scr_off = ON;
1397 break;
1398 case FB_BLANK_NORMAL:
1399 mode = POWERON;
1400 pwr |= 1;
1401 scr_off = OFF;
1402 break;
1403 case FB_BLANK_VSYNC_SUSPEND:
1404 mode = STANDBY;
1405 pwr |= 1;
1406 scr_off = OFF;
1407 break;
1408 case FB_BLANK_HSYNC_SUSPEND:
1409 mode = SUSPEND;
1410 pwr |= 1;
1411 scr_off = OFF;
1412 break;
1413 case FB_BLANK_POWERDOWN:
1414 mode = POWERDOWN;
1415 pwr &= ~1;
1416 scr_off = OFF;
1417 break;
1418 default:
1419 return -EINVAL;
1420 }
1421
1422 i810_screen_off(mmio, scr_off);
1423 i810_writel(HVSYNC, mmio, mode);
1424 i810_writel(PWR_CLKC, mmio, pwr);
1425
1426 return 0;
1427 }
1428
1429 static int i810fb_set_par(struct fb_info *info)
1430 {
1431 struct i810fb_par *par = info->par;
1432
1433 decode_var(&info->var, par);
1434 i810_load_regs(par);
1435 i810_init_cursor(par);
1436 encode_fix(&info->fix, info);
1437
1438 if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) {
1439 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
1440 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
1441 FBINFO_HWACCEL_IMAGEBLIT;
1442 info->pixmap.scan_align = 2;
1443 } else {
1444 info->pixmap.scan_align = 1;
1445 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1446 }
1447 return 0;
1448 }
1449
1450 static int i810fb_check_var(struct fb_var_screeninfo *var,
1451 struct fb_info *info)
1452 {
1453 int err;
1454
1455 if (IS_DVT) {
1456 var->vmode &= ~FB_VMODE_MASK;
1457 var->vmode |= FB_VMODE_NONINTERLACED;
1458 }
1459 if (var->vmode & FB_VMODE_DOUBLE) {
1460 var->vmode &= ~FB_VMODE_MASK;
1461 var->vmode |= FB_VMODE_NONINTERLACED;
1462 }
1463
1464 i810_round_off(var);
1465 if ((err = i810_check_params(var, info)))
1466 return err;
1467
1468 i810fb_fill_var_timings(var);
1469 set_color_bitfields(var);
1470 return 0;
1471 }
1472
1473 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1474 {
1475 struct i810fb_par *par = info->par;
1476 u8 __iomem *mmio = par->mmio_start_virtual;
1477
1478 if (!par->dev_flags & LOCKUP)
1479 return -ENXIO;
1480
1481 if (cursor->image.width > 64 || cursor->image.height > 64)
1482 return -ENXIO;
1483
1484 if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) {
1485 i810_init_cursor(par);
1486 cursor->set |= FB_CUR_SETALL;
1487 }
1488
1489 i810_enable_cursor(mmio, OFF);
1490
1491 if (cursor->set & FB_CUR_SETPOS) {
1492 u32 tmp;
1493
1494 tmp = (cursor->image.dx - info->var.xoffset) & 0xffff;
1495 tmp |= (cursor->image.dy - info->var.yoffset) << 16;
1496 i810_writel(CURPOS, mmio, tmp);
1497 }
1498
1499 if (cursor->set & FB_CUR_SETSIZE)
1500 i810_reset_cursor_image(par);
1501
1502 if (cursor->set & FB_CUR_SETCMAP)
1503 i810_load_cursor_colors(cursor->image.fg_color,
1504 cursor->image.bg_color,
1505 info);
1506
1507 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1508 int size = ((cursor->image.width + 7) >> 3) *
1509 cursor->image.height;
1510 int i;
1511 u8 *data = kmalloc(64 * 8, GFP_ATOMIC);
1512
1513 if (data == NULL)
1514 return -ENOMEM;
1515
1516 switch (cursor->rop) {
1517 case ROP_XOR:
1518 for (i = 0; i < size; i++)
1519 data[i] = cursor->image.data[i] ^ cursor->mask[i];
1520 break;
1521 case ROP_COPY:
1522 default:
1523 for (i = 0; i < size; i++)
1524 data[i] = cursor->image.data[i] & cursor->mask[i];
1525 break;
1526 }
1527
1528 i810_load_cursor_image(cursor->image.width,
1529 cursor->image.height, data,
1530 par);
1531 kfree(data);
1532 }
1533
1534 if (cursor->enable)
1535 i810_enable_cursor(mmio, ON);
1536
1537 return 0;
1538 }
1539
1540 static struct fb_ops i810fb_ops __devinitdata = {
1541 .owner = THIS_MODULE,
1542 .fb_open = i810fb_open,
1543 .fb_release = i810fb_release,
1544 .fb_check_var = i810fb_check_var,
1545 .fb_set_par = i810fb_set_par,
1546 .fb_setcolreg = i810fb_setcolreg,
1547 .fb_blank = i810fb_blank,
1548 .fb_pan_display = i810fb_pan_display,
1549 .fb_fillrect = i810fb_fillrect,
1550 .fb_copyarea = i810fb_copyarea,
1551 .fb_imageblit = i810fb_imageblit,
1552 .fb_cursor = i810fb_cursor,
1553 .fb_sync = i810fb_sync,
1554 };
1555
1556 /***********************************************************************
1557 * Power Management *
1558 ***********************************************************************/
1559 static int i810fb_suspend(struct pci_dev *dev, pm_message_t state)
1560 {
1561 struct fb_info *info = pci_get_drvdata(dev);
1562 struct i810fb_par *par = info->par;
1563
1564 par->cur_state = state.event;
1565
1566 if (state.event == PM_EVENT_FREEZE) {
1567 dev->dev.power.power_state = state;
1568 return 0;
1569 }
1570
1571 acquire_console_sem();
1572 fb_set_suspend(info, 1);
1573
1574 if (info->fbops->fb_sync)
1575 info->fbops->fb_sync(info);
1576
1577 i810fb_blank(FB_BLANK_POWERDOWN, info);
1578 agp_unbind_memory(par->i810_gtt.i810_fb_memory);
1579 agp_unbind_memory(par->i810_gtt.i810_cursor_memory);
1580
1581 pci_save_state(dev);
1582 pci_disable_device(dev);
1583 pci_set_power_state(dev, pci_choose_state(dev, state));
1584 release_console_sem();
1585
1586 return 0;
1587 }
1588
1589 static int i810fb_resume(struct pci_dev *dev)
1590 {
1591 struct fb_info *info = pci_get_drvdata(dev);
1592 struct i810fb_par *par = info->par;
1593 int cur_state = par->cur_state;
1594
1595 par->cur_state = PM_EVENT_ON;
1596
1597 if (cur_state == PM_EVENT_FREEZE) {
1598 pci_set_power_state(dev, PCI_D0);
1599 return 0;
1600 }
1601
1602 acquire_console_sem();
1603 pci_set_power_state(dev, PCI_D0);
1604 pci_restore_state(dev);
1605 pci_enable_device(dev);
1606 pci_set_master(dev);
1607 agp_bind_memory(par->i810_gtt.i810_fb_memory,
1608 par->fb.offset);
1609 agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1610 par->cursor_heap.offset);
1611 i810fb_set_par(info);
1612 fb_set_suspend (info, 0);
1613 info->fbops->fb_blank(VESA_NO_BLANKING, info);
1614 release_console_sem();
1615 return 0;
1616 }
1617 /***********************************************************************
1618 * AGP resource allocation *
1619 ***********************************************************************/
1620
1621 static void __devinit i810_fix_pointers(struct i810fb_par *par)
1622 {
1623 par->fb.physical = par->aperture.physical+(par->fb.offset << 12);
1624 par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12);
1625 par->iring.physical = par->aperture.physical +
1626 (par->iring.offset << 12);
1627 par->iring.virtual = par->aperture.virtual +
1628 (par->iring.offset << 12);
1629 par->cursor_heap.virtual = par->aperture.virtual+
1630 (par->cursor_heap.offset << 12);
1631 }
1632
1633 static void __devinit i810_fix_offsets(struct i810fb_par *par)
1634 {
1635 if (vram + 1 > par->aperture.size >> 20)
1636 vram = (par->aperture.size >> 20) - 1;
1637 if (v_offset_default > (par->aperture.size >> 20))
1638 v_offset_default = (par->aperture.size >> 20);
1639 if (vram + v_offset_default + 1 > par->aperture.size >> 20)
1640 v_offset_default = (par->aperture.size >> 20) - (vram + 1);
1641
1642 par->fb.size = vram << 20;
1643 par->fb.offset = v_offset_default << 20;
1644 par->fb.offset >>= 12;
1645
1646 par->iring.offset = par->fb.offset + (par->fb.size >> 12);
1647 par->iring.size = RINGBUFFER_SIZE;
1648
1649 par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12);
1650 par->cursor_heap.size = 4096;
1651 }
1652
1653 static int __devinit i810_alloc_agp_mem(struct fb_info *info)
1654 {
1655 struct i810fb_par *par = info->par;
1656 int size;
1657 struct agp_bridge_data *bridge;
1658
1659 i810_fix_offsets(par);
1660 size = par->fb.size + par->iring.size;
1661
1662 if (!(bridge = agp_backend_acquire(par->dev))) {
1663 printk("i810fb_alloc_fbmem: cannot acquire agpgart\n");
1664 return -ENODEV;
1665 }
1666 if (!(par->i810_gtt.i810_fb_memory =
1667 agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) {
1668 printk("i810fb_alloc_fbmem: can't allocate framebuffer "
1669 "memory\n");
1670 agp_backend_release(bridge);
1671 return -ENOMEM;
1672 }
1673 if (agp_bind_memory(par->i810_gtt.i810_fb_memory,
1674 par->fb.offset)) {
1675 printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n");
1676 agp_backend_release(bridge);
1677 return -EBUSY;
1678 }
1679
1680 if (!(par->i810_gtt.i810_cursor_memory =
1681 agp_allocate_memory(bridge, par->cursor_heap.size >> 12,
1682 AGP_PHYSICAL_MEMORY))) {
1683 printk("i810fb_alloc_cursormem: can't allocate"
1684 "cursor memory\n");
1685 agp_backend_release(bridge);
1686 return -ENOMEM;
1687 }
1688 if (agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1689 par->cursor_heap.offset)) {
1690 printk("i810fb_alloc_cursormem: cannot bind cursor memory\n");
1691 agp_backend_release(bridge);
1692 return -EBUSY;
1693 }
1694
1695 par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical;
1696
1697 i810_fix_pointers(par);
1698
1699 agp_backend_release(bridge);
1700
1701 return 0;
1702 }
1703
1704 /***************************************************************
1705 * Initialization *
1706 ***************************************************************/
1707
1708 /**
1709 * i810_init_monspecs
1710 * @info: pointer to device specific info structure
1711 *
1712 * DESCRIPTION:
1713 * Sets the the user monitor's horizontal and vertical
1714 * frequency limits
1715 */
1716 static void __devinit i810_init_monspecs(struct fb_info *info)
1717 {
1718 if (!hsync1)
1719 hsync1 = HFMIN;
1720 if (!hsync2)
1721 hsync2 = HFMAX;
1722 if (!info->monspecs.hfmax)
1723 info->monspecs.hfmax = hsync2;
1724 if (!info->monspecs.hfmin)
1725 info->monspecs.hfmin = hsync1;
1726 if (hsync2 < hsync1)
1727 info->monspecs.hfmin = hsync2;
1728
1729 if (!vsync1)
1730 vsync1 = VFMIN;
1731 if (!vsync2)
1732 vsync2 = VFMAX;
1733 if (IS_DVT && vsync1 < 60)
1734 vsync1 = 60;
1735 if (!info->monspecs.vfmax)
1736 info->monspecs.vfmax = vsync2;
1737 if (!info->monspecs.vfmin)
1738 info->monspecs.vfmin = vsync1;
1739 if (vsync2 < vsync1)
1740 info->monspecs.vfmin = vsync2;
1741 }
1742
1743 /**
1744 * i810_init_defaults - initializes default values to use
1745 * @par: pointer to i810fb_par structure
1746 * @info: pointer to current fb_info structure
1747 */
1748 static void __devinit i810_init_defaults(struct i810fb_par *par,
1749 struct fb_info *info)
1750 {
1751 if (voffset)
1752 v_offset_default = voffset;
1753 else if (par->aperture.size > 32 * 1024 * 1024)
1754 v_offset_default = 16;
1755 else
1756 v_offset_default = 8;
1757
1758 if (!vram)
1759 vram = 1;
1760
1761 if (accel)
1762 par->dev_flags |= HAS_ACCELERATION;
1763
1764 if (sync)
1765 par->dev_flags |= ALWAYS_SYNC;
1766
1767 par->ddc_num = ddc3;
1768
1769 if (bpp < 8)
1770 bpp = 8;
1771
1772 par->i810fb_ops = i810fb_ops;
1773
1774 if (xres)
1775 info->var.xres = xres;
1776 else
1777 info->var.xres = 640;
1778
1779 if (yres)
1780 info->var.yres = yres;
1781 else
1782 info->var.yres = 480;
1783
1784 if (!vyres)
1785 vyres = (vram << 20)/(info->var.xres*bpp >> 3);
1786
1787 info->var.yres_virtual = vyres;
1788 info->var.bits_per_pixel = bpp;
1789
1790 if (dcolor)
1791 info->var.nonstd = 1;
1792
1793 if (par->dev_flags & HAS_ACCELERATION)
1794 info->var.accel_flags = 1;
1795
1796 i810_init_monspecs(info);
1797 }
1798
1799 /**
1800 * i810_init_device - initialize device
1801 * @par: pointer to i810fb_par structure
1802 */
1803 static void __devinit i810_init_device(struct i810fb_par *par)
1804 {
1805 u8 reg;
1806 u8 __iomem *mmio = par->mmio_start_virtual;
1807
1808 if (mtrr) set_mtrr(par);
1809
1810 i810_init_cursor(par);
1811
1812 /* mvo: enable external vga-connector (for laptops) */
1813 if (extvga) {
1814 i810_writel(HVSYNC, mmio, 0);
1815 i810_writel(PWR_CLKC, mmio, 3);
1816 }
1817
1818 pci_read_config_byte(par->dev, 0x50, &reg);
1819 reg &= FREQ_MASK;
1820 par->mem_freq = (reg) ? 133 : 100;
1821
1822 }
1823
1824 static int __devinit
1825 i810_allocate_pci_resource(struct i810fb_par *par,
1826 const struct pci_device_id *entry)
1827 {
1828 int err;
1829
1830 if ((err = pci_enable_device(par->dev))) {
1831 printk("i810fb_init: cannot enable device\n");
1832 return err;
1833 }
1834 par->res_flags |= PCI_DEVICE_ENABLED;
1835
1836 if (pci_resource_len(par->dev, 0) > 512 * 1024) {
1837 par->aperture.physical = pci_resource_start(par->dev, 0);
1838 par->aperture.size = pci_resource_len(par->dev, 0);
1839 par->mmio_start_phys = pci_resource_start(par->dev, 1);
1840 } else {
1841 par->aperture.physical = pci_resource_start(par->dev, 1);
1842 par->aperture.size = pci_resource_len(par->dev, 1);
1843 par->mmio_start_phys = pci_resource_start(par->dev, 0);
1844 }
1845 if (!par->aperture.size) {
1846 printk("i810fb_init: device is disabled\n");
1847 return -ENOMEM;
1848 }
1849
1850 if (!request_mem_region(par->aperture.physical,
1851 par->aperture.size,
1852 i810_pci_list[entry->driver_data])) {
1853 printk("i810fb_init: cannot request framebuffer region\n");
1854 return -ENODEV;
1855 }
1856 par->res_flags |= FRAMEBUFFER_REQ;
1857
1858 par->aperture.virtual = ioremap_nocache(par->aperture.physical,
1859 par->aperture.size);
1860 if (!par->aperture.virtual) {
1861 printk("i810fb_init: cannot remap framebuffer region\n");
1862 return -ENODEV;
1863 }
1864
1865 if (!request_mem_region(par->mmio_start_phys,
1866 MMIO_SIZE,
1867 i810_pci_list[entry->driver_data])) {
1868 printk("i810fb_init: cannot request mmio region\n");
1869 return -ENODEV;
1870 }
1871 par->res_flags |= MMIO_REQ;
1872
1873 par->mmio_start_virtual = ioremap_nocache(par->mmio_start_phys,
1874 MMIO_SIZE);
1875 if (!par->mmio_start_virtual) {
1876 printk("i810fb_init: cannot remap mmio region\n");
1877 return -ENODEV;
1878 }
1879
1880 return 0;
1881 }
1882
1883 static void __devinit i810fb_find_init_mode(struct fb_info *info)
1884 {
1885 struct fb_videomode mode;
1886 struct fb_var_screeninfo var;
1887 struct fb_monspecs *specs = &info->monspecs;
1888 int found = 0;
1889 #ifdef CONFIG_FB_I810_I2C
1890 int i;
1891 int err = 1;
1892 struct i810fb_par *par = info->par;
1893 #endif
1894
1895 INIT_LIST_HEAD(&info->modelist);
1896 memset(&mode, 0, sizeof(struct fb_videomode));
1897 var = info->var;
1898 #ifdef CONFIG_FB_I810_I2C
1899 i810_create_i2c_busses(par);
1900
1901 for (i = 0; i < par->ddc_num + 1; i++) {
1902 err = i810_probe_i2c_connector(info, &par->edid, i);
1903 if (!err)
1904 break;
1905 }
1906
1907 if (!err)
1908 printk("i810fb_init_pci: DDC probe successful\n");
1909
1910 fb_edid_to_monspecs(par->edid, specs);
1911
1912 if (specs->modedb == NULL)
1913 printk("i810fb_init_pci: Unable to get Mode Database\n");
1914
1915 fb_videomode_to_modelist(specs->modedb, specs->modedb_len,
1916 &info->modelist);
1917 if (specs->modedb != NULL) {
1918 struct fb_videomode *m;
1919
1920 if (xres && yres) {
1921 if ((m = fb_find_best_mode(&var, &info->modelist))) {
1922 mode = *m;
1923 found = 1;
1924 }
1925 }
1926
1927 if (!found) {
1928 m = fb_find_best_display(&info->monspecs, &info->modelist);
1929 mode = *m;
1930 found = 1;
1931 }
1932
1933 fb_videomode_to_var(&var, &mode);
1934 }
1935 #endif
1936 if (mode_option)
1937 fb_find_mode(&var, info, mode_option, specs->modedb,
1938 specs->modedb_len, (found) ? &mode : NULL,
1939 info->var.bits_per_pixel);
1940
1941 info->var = var;
1942 fb_destroy_modedb(specs->modedb);
1943 specs->modedb = NULL;
1944 }
1945
1946 #ifndef MODULE
1947 static int __devinit i810fb_setup(char *options)
1948 {
1949 char *this_opt, *suffix = NULL;
1950
1951 if (!options || !*options)
1952 return 0;
1953
1954 while ((this_opt = strsep(&options, ",")) != NULL) {
1955 if (!strncmp(this_opt, "mtrr", 4))
1956 mtrr = 1;
1957 else if (!strncmp(this_opt, "accel", 5))
1958 accel = 1;
1959 else if (!strncmp(this_opt, "extvga", 6))
1960 extvga = 1;
1961 else if (!strncmp(this_opt, "sync", 4))
1962 sync = 1;
1963 else if (!strncmp(this_opt, "vram:", 5))
1964 vram = (simple_strtoul(this_opt+5, NULL, 0));
1965 else if (!strncmp(this_opt, "voffset:", 8))
1966 voffset = (simple_strtoul(this_opt+8, NULL, 0));
1967 else if (!strncmp(this_opt, "xres:", 5))
1968 xres = simple_strtoul(this_opt+5, NULL, 0);
1969 else if (!strncmp(this_opt, "yres:", 5))
1970 yres = simple_strtoul(this_opt+5, NULL, 0);
1971 else if (!strncmp(this_opt, "vyres:", 6))
1972 vyres = simple_strtoul(this_opt+6, NULL, 0);
1973 else if (!strncmp(this_opt, "bpp:", 4))
1974 bpp = simple_strtoul(this_opt+4, NULL, 0);
1975 else if (!strncmp(this_opt, "hsync1:", 7)) {
1976 hsync1 = simple_strtoul(this_opt+7, &suffix, 0);
1977 if (strncmp(suffix, "H", 1))
1978 hsync1 *= 1000;
1979 } else if (!strncmp(this_opt, "hsync2:", 7)) {
1980 hsync2 = simple_strtoul(this_opt+7, &suffix, 0);
1981 if (strncmp(suffix, "H", 1))
1982 hsync2 *= 1000;
1983 } else if (!strncmp(this_opt, "vsync1:", 7))
1984 vsync1 = simple_strtoul(this_opt+7, NULL, 0);
1985 else if (!strncmp(this_opt, "vsync2:", 7))
1986 vsync2 = simple_strtoul(this_opt+7, NULL, 0);
1987 else if (!strncmp(this_opt, "dcolor", 6))
1988 dcolor = 1;
1989 else if (!strncmp(this_opt, "ddc3", 4))
1990 ddc3 = 3;
1991 else
1992 mode_option = this_opt;
1993 }
1994 return 0;
1995 }
1996 #endif
1997
1998 static int __devinit i810fb_init_pci (struct pci_dev *dev,
1999 const struct pci_device_id *entry)
2000 {
2001 struct fb_info *info;
2002 struct i810fb_par *par = NULL;
2003 struct fb_videomode mode;
2004 int i, err = -1, vfreq, hfreq, pixclock;
2005
2006 i = 0;
2007
2008 info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev);
2009 if (!info)
2010 return -ENOMEM;
2011
2012 par = info->par;
2013 par->dev = dev;
2014
2015 if (!(info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL))) {
2016 i810fb_release_resource(info, par);
2017 return -ENOMEM;
2018 }
2019 memset(info->pixmap.addr, 0, 8*1024);
2020 info->pixmap.size = 8*1024;
2021 info->pixmap.buf_align = 8;
2022 info->pixmap.access_align = 32;
2023 info->pixmap.flags = FB_PIXMAP_SYSTEM;
2024
2025 if ((err = i810_allocate_pci_resource(par, entry))) {
2026 i810fb_release_resource(info, par);
2027 return err;
2028 }
2029
2030 i810_init_defaults(par, info);
2031
2032 if ((err = i810_alloc_agp_mem(info))) {
2033 i810fb_release_resource(info, par);
2034 return err;
2035 }
2036
2037 i810_init_device(par);
2038
2039 info->screen_base = par->fb.virtual;
2040 info->fbops = &par->i810fb_ops;
2041 info->pseudo_palette = par->pseudo_palette;
2042 fb_alloc_cmap(&info->cmap, 256, 0);
2043 i810fb_find_init_mode(info);
2044
2045 if ((err = info->fbops->fb_check_var(&info->var, info))) {
2046 i810fb_release_resource(info, par);
2047 return err;
2048 }
2049
2050 fb_var_to_videomode(&mode, &info->var);
2051 fb_add_videomode(&mode, &info->modelist);
2052 encode_fix(&info->fix, info);
2053
2054 i810fb_init_ringbuffer(info);
2055 err = register_framebuffer(info);
2056
2057 if (err < 0) {
2058 i810fb_release_resource(info, par);
2059 printk("i810fb_init: cannot register framebuffer device\n");
2060 return err;
2061 }
2062
2063 pci_set_drvdata(dev, info);
2064 pixclock = 1000000000/(info->var.pixclock);
2065 pixclock *= 1000;
2066 hfreq = pixclock/(info->var.xres + info->var.left_margin +
2067 info->var.hsync_len + info->var.right_margin);
2068 vfreq = hfreq/(info->var.yres + info->var.upper_margin +
2069 info->var.vsync_len + info->var.lower_margin);
2070
2071 printk("I810FB: fb%d : %s v%d.%d.%d%s\n"
2072 "I810FB: Video RAM : %dK\n"
2073 "I810FB: Monitor : H: %d-%d KHz V: %d-%d Hz\n"
2074 "I810FB: Mode : %dx%d-%dbpp@%dHz\n",
2075 info->node,
2076 i810_pci_list[entry->driver_data],
2077 VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION,
2078 (int) par->fb.size>>10, info->monspecs.hfmin/1000,
2079 info->monspecs.hfmax/1000, info->monspecs.vfmin,
2080 info->monspecs.vfmax, info->var.xres,
2081 info->var.yres, info->var.bits_per_pixel, vfreq);
2082 return 0;
2083 }
2084
2085 /***************************************************************
2086 * De-initialization *
2087 ***************************************************************/
2088
2089 static void i810fb_release_resource(struct fb_info *info,
2090 struct i810fb_par *par)
2091 {
2092 struct gtt_data *gtt = &par->i810_gtt;
2093 unset_mtrr(par);
2094
2095 i810_delete_i2c_busses(par);
2096
2097 if (par->i810_gtt.i810_cursor_memory)
2098 agp_free_memory(gtt->i810_cursor_memory);
2099 if (par->i810_gtt.i810_fb_memory)
2100 agp_free_memory(gtt->i810_fb_memory);
2101
2102 if (par->mmio_start_virtual)
2103 iounmap(par->mmio_start_virtual);
2104 if (par->aperture.virtual)
2105 iounmap(par->aperture.virtual);
2106 kfree(par->edid);
2107 if (par->res_flags & FRAMEBUFFER_REQ)
2108 release_mem_region(par->aperture.physical,
2109 par->aperture.size);
2110 if (par->res_flags & MMIO_REQ)
2111 release_mem_region(par->mmio_start_phys, MMIO_SIZE);
2112
2113 framebuffer_release(info);
2114
2115 }
2116
2117 static void __exit i810fb_remove_pci(struct pci_dev *dev)
2118 {
2119 struct fb_info *info = pci_get_drvdata(dev);
2120 struct i810fb_par *par = info->par;
2121
2122 unregister_framebuffer(info);
2123 i810fb_release_resource(info, par);
2124 pci_set_drvdata(dev, NULL);
2125 printk("cleanup_module: unloaded i810 framebuffer device\n");
2126 }
2127
2128 #ifndef MODULE
2129 static int __devinit i810fb_init(void)
2130 {
2131 char *option = NULL;
2132
2133 if (fb_get_options("i810fb", &option))
2134 return -ENODEV;
2135 i810fb_setup(option);
2136
2137 return pci_register_driver(&i810fb_driver);
2138 }
2139 #endif
2140
2141 /*********************************************************************
2142 * Modularization *
2143 *********************************************************************/
2144
2145 #ifdef MODULE
2146
2147 static int __devinit i810fb_init(void)
2148 {
2149 hsync1 *= 1000;
2150 hsync2 *= 1000;
2151
2152 return pci_register_driver(&i810fb_driver);
2153 }
2154
2155 module_param(vram, int, 0);
2156 MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB"
2157 " (default=4)");
2158 module_param(voffset, int, 0);
2159 MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer "
2160 "memory (0 to maximum aperture size), in MiB (default = 48)");
2161 module_param(bpp, int, 0);
2162 MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel"
2163 " (default = 8)");
2164 module_param(xres, int, 0);
2165 MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)");
2166 module_param(yres, int, 0);
2167 MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)");
2168 module_param(vyres,int, 0);
2169 MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines"
2170 " (default = 480)");
2171 module_param(hsync1, int, 0);
2172 MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz"
2173 " (default = 29)");
2174 module_param(hsync2, int, 0);
2175 MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz"
2176 " (default = 30)");
2177 module_param(vsync1, int, 0);
2178 MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz"
2179 " (default = 50)");
2180 module_param(vsync2, int, 0);
2181 MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz"
2182 " (default = 60)");
2183 module_param(accel, bool, 0);
2184 MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)");
2185 module_param(mtrr, bool, 0);
2186 MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)");
2187 module_param(extvga, bool, 0);
2188 MODULE_PARM_DESC(extvga, "Enable external VGA connector (default = 0)");
2189 module_param(sync, bool, 0);
2190 MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing"
2191 " (default = 0)");
2192 module_param(dcolor, bool, 0);
2193 MODULE_PARM_DESC(dcolor, "use DirectColor visuals"
2194 " (default = 0 = TrueColor)");
2195 module_param(ddc3, bool, 0);
2196 MODULE_PARM_DESC(ddc3, "Probe DDC bus 3 (default = 0 = no)");
2197 module_param(mode_option, charp, 0);
2198 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
2199
2200 MODULE_AUTHOR("Tony A. Daplas");
2201 MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and"
2202 " compatible cards");
2203 MODULE_LICENSE("GPL");
2204
2205 static void __exit i810fb_exit(void)
2206 {
2207 pci_unregister_driver(&i810fb_driver);
2208 }
2209 module_exit(i810fb_exit);
2210
2211 #endif /* MODULE */
2212
2213 module_init(i810fb_init);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree