2 * Driver for NEC VR4100 series Real Time Clock unit.
4 * Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/err.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/rtc.h>
28 #include <linux/spinlock.h>
29 #include <linux/types.h>
31 #include <asm/div64.h>
33 #include <asm/uaccess.h>
35 MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
36 MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
37 MODULE_LICENSE("GPL");
40 #define ETIMELREG 0x00
41 #define ETIMEMREG 0x02
42 #define ETIMEHREG 0x04
48 #define RTCL1LREG 0x10
49 #define RTCL1HREG 0x12
50 #define RTCL1CNTLREG 0x14
51 #define RTCL1CNTHREG 0x16
52 #define RTCL2LREG 0x18
53 #define RTCL2HREG 0x1a
54 #define RTCL2CNTLREG 0x1c
55 #define RTCL2CNTHREG 0x1e
60 #define TCLKCNTLREG 0x04
61 #define TCLKCNTHREG 0x06
63 #define RTCINTREG 0x1e
64 #define TCLOCK_INT 0x08
65 #define RTCLONG2_INT 0x04
66 #define RTCLONG1_INT 0x02
67 #define ELAPSEDTIME_INT 0x01
69 #define RTC_FREQUENCY 32768
70 #define MAX_PERIODIC_RATE 6553
72 static void __iomem
*rtc1_base
;
73 static void __iomem
*rtc2_base
;
75 #define rtc1_read(offset) readw(rtc1_base + (offset))
76 #define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
78 #define rtc2_read(offset) readw(rtc2_base + (offset))
79 #define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
81 static unsigned long epoch
= 1970; /* Jan 1 1970 00:00:00 */
83 static DEFINE_SPINLOCK(rtc_lock
);
84 static char rtc_name
[] = "RTC";
85 static unsigned long periodic_frequency
;
86 static unsigned long periodic_count
;
87 static unsigned int alarm_enabled
;
88 static int aie_irq
= -1;
89 static int pie_irq
= -1;
91 static inline unsigned long read_elapsed_second(void)
94 unsigned long first_low
, first_mid
, first_high
;
96 unsigned long second_low
, second_mid
, second_high
;
99 first_low
= rtc1_read(ETIMELREG
);
100 first_mid
= rtc1_read(ETIMEMREG
);
101 first_high
= rtc1_read(ETIMEHREG
);
102 second_low
= rtc1_read(ETIMELREG
);
103 second_mid
= rtc1_read(ETIMEMREG
);
104 second_high
= rtc1_read(ETIMEHREG
);
105 } while (first_low
!= second_low
|| first_mid
!= second_mid
||
106 first_high
!= second_high
);
108 return (first_high
<< 17) | (first_mid
<< 1) | (first_low
>> 15);
111 static inline void write_elapsed_second(unsigned long sec
)
113 spin_lock_irq(&rtc_lock
);
115 rtc1_write(ETIMELREG
, (uint16_t)(sec
<< 15));
116 rtc1_write(ETIMEMREG
, (uint16_t)(sec
>> 1));
117 rtc1_write(ETIMEHREG
, (uint16_t)(sec
>> 17));
119 spin_unlock_irq(&rtc_lock
);
122 static void vr41xx_rtc_release(struct device
*dev
)
125 spin_lock_irq(&rtc_lock
);
127 rtc1_write(ECMPLREG
, 0);
128 rtc1_write(ECMPMREG
, 0);
129 rtc1_write(ECMPHREG
, 0);
130 rtc1_write(RTCL1LREG
, 0);
131 rtc1_write(RTCL1HREG
, 0);
133 spin_unlock_irq(&rtc_lock
);
135 disable_irq(aie_irq
);
136 disable_irq(pie_irq
);
139 static int vr41xx_rtc_read_time(struct device
*dev
, struct rtc_time
*time
)
141 unsigned long epoch_sec
, elapsed_sec
;
143 epoch_sec
= mktime(epoch
, 1, 1, 0, 0, 0);
144 elapsed_sec
= read_elapsed_second();
146 rtc_time_to_tm(epoch_sec
+ elapsed_sec
, time
);
151 static int vr41xx_rtc_set_time(struct device
*dev
, struct rtc_time
*time
)
153 unsigned long epoch_sec
, current_sec
;
155 epoch_sec
= mktime(epoch
, 1, 1, 0, 0, 0);
156 current_sec
= mktime(time
->tm_year
+ 1900, time
->tm_mon
+ 1, time
->tm_mday
,
157 time
->tm_hour
, time
->tm_min
, time
->tm_sec
);
159 write_elapsed_second(current_sec
- epoch_sec
);
164 static int vr41xx_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*wkalrm
)
166 unsigned long low
, mid
, high
;
167 struct rtc_time
*time
= &wkalrm
->time
;
169 spin_lock_irq(&rtc_lock
);
171 low
= rtc1_read(ECMPLREG
);
172 mid
= rtc1_read(ECMPMREG
);
173 high
= rtc1_read(ECMPHREG
);
174 wkalrm
->enabled
= alarm_enabled
;
176 spin_unlock_irq(&rtc_lock
);
178 rtc_time_to_tm((high
<< 17) | (mid
<< 1) | (low
>> 15), time
);
183 static int vr41xx_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*wkalrm
)
185 unsigned long alarm_sec
;
186 struct rtc_time
*time
= &wkalrm
->time
;
188 alarm_sec
= mktime(time
->tm_year
+ 1900, time
->tm_mon
+ 1, time
->tm_mday
,
189 time
->tm_hour
, time
->tm_min
, time
->tm_sec
);
191 spin_lock_irq(&rtc_lock
);
194 disable_irq(aie_irq
);
196 rtc1_write(ECMPLREG
, (uint16_t)(alarm_sec
<< 15));
197 rtc1_write(ECMPMREG
, (uint16_t)(alarm_sec
>> 1));
198 rtc1_write(ECMPHREG
, (uint16_t)(alarm_sec
>> 17));
203 alarm_enabled
= wkalrm
->enabled
;
205 spin_unlock_irq(&rtc_lock
);
210 static int vr41xx_rtc_ioctl(struct device
*dev
, unsigned int cmd
, unsigned long arg
)
216 spin_lock_irq(&rtc_lock
);
218 if (!alarm_enabled
) {
223 spin_unlock_irq(&rtc_lock
);
226 spin_lock_irq(&rtc_lock
);
229 disable_irq(aie_irq
);
233 spin_unlock_irq(&rtc_lock
);
239 disable_irq(pie_irq
);
242 return put_user(periodic_frequency
, (unsigned long __user
*)arg
);
245 if (arg
> MAX_PERIODIC_RATE
)
248 periodic_frequency
= arg
;
250 count
= RTC_FREQUENCY
;
253 periodic_count
= count
;
255 spin_lock_irq(&rtc_lock
);
257 rtc1_write(RTCL1LREG
, count
);
258 rtc1_write(RTCL1HREG
, count
>> 16);
260 spin_unlock_irq(&rtc_lock
);
263 return put_user(epoch
, (unsigned long __user
*)arg
);
265 /* Doesn't support before 1900 */
277 static irqreturn_t
elapsedtime_interrupt(int irq
, void *dev_id
)
279 struct platform_device
*pdev
= (struct platform_device
*)dev_id
;
280 struct rtc_device
*rtc
= platform_get_drvdata(pdev
);
282 rtc2_write(RTCINTREG
, ELAPSEDTIME_INT
);
284 rtc_update_irq(rtc
, 1, RTC_AF
);
289 static irqreturn_t
rtclong1_interrupt(int irq
, void *dev_id
)
291 struct platform_device
*pdev
= (struct platform_device
*)dev_id
;
292 struct rtc_device
*rtc
= platform_get_drvdata(pdev
);
293 unsigned long count
= periodic_count
;
295 rtc2_write(RTCINTREG
, RTCLONG1_INT
);
297 rtc1_write(RTCL1LREG
, count
);
298 rtc1_write(RTCL1HREG
, count
>> 16);
300 rtc_update_irq(rtc
, 1, RTC_PF
);
305 static const struct rtc_class_ops vr41xx_rtc_ops
= {
306 .release
= vr41xx_rtc_release
,
307 .ioctl
= vr41xx_rtc_ioctl
,
308 .read_time
= vr41xx_rtc_read_time
,
309 .set_time
= vr41xx_rtc_set_time
,
310 .read_alarm
= vr41xx_rtc_read_alarm
,
311 .set_alarm
= vr41xx_rtc_set_alarm
,
314 static int __devinit
rtc_probe(struct platform_device
*pdev
)
316 struct resource
*res
;
317 struct rtc_device
*rtc
;
320 if (pdev
->num_resources
!= 4)
323 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
327 rtc1_base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
331 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
334 goto err_rtc1_iounmap
;
337 rtc2_base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
340 goto err_rtc1_iounmap
;
343 rtc
= rtc_device_register(rtc_name
, &pdev
->dev
, &vr41xx_rtc_ops
, THIS_MODULE
);
345 retval
= PTR_ERR(rtc
);
346 goto err_iounmap_all
;
349 spin_lock_irq(&rtc_lock
);
351 rtc1_write(ECMPLREG
, 0);
352 rtc1_write(ECMPMREG
, 0);
353 rtc1_write(ECMPHREG
, 0);
354 rtc1_write(RTCL1LREG
, 0);
355 rtc1_write(RTCL1HREG
, 0);
357 spin_unlock_irq(&rtc_lock
);
359 aie_irq
= platform_get_irq(pdev
, 0);
360 if (aie_irq
< 0 || aie_irq
>= NR_IRQS
) {
362 goto err_device_unregister
;
365 retval
= request_irq(aie_irq
, elapsedtime_interrupt
, IRQF_DISABLED
,
366 "elapsed_time", pdev
);
368 goto err_device_unregister
;
370 pie_irq
= platform_get_irq(pdev
, 1);
371 if (pie_irq
< 0 || pie_irq
>= NR_IRQS
)
374 retval
= request_irq(pie_irq
, rtclong1_interrupt
, IRQF_DISABLED
,
379 platform_set_drvdata(pdev
, rtc
);
381 disable_irq(aie_irq
);
382 disable_irq(pie_irq
);
384 printk(KERN_INFO
"rtc: Real Time Clock of NEC VR4100 series\n");
389 free_irq(aie_irq
, pdev
);
391 err_device_unregister
:
392 rtc_device_unregister(rtc
);
405 static int __devexit
rtc_remove(struct platform_device
*pdev
)
407 struct rtc_device
*rtc
;
409 rtc
= platform_get_drvdata(pdev
);
411 rtc_device_unregister(rtc
);
413 platform_set_drvdata(pdev
, NULL
);
415 free_irq(aie_irq
, pdev
);
416 free_irq(pie_irq
, pdev
);
425 /* work with hotplug and coldplug */
426 MODULE_ALIAS("platform:RTC");
428 static struct platform_driver rtc_platform_driver
= {
430 .remove
= __devexit_p(rtc_remove
),
433 .owner
= THIS_MODULE
,
437 static int __init
vr41xx_rtc_init(void)
439 return platform_driver_register(&rtc_platform_driver
);
442 static void __exit
vr41xx_rtc_exit(void)
444 platform_driver_unregister(&rtc_platform_driver
);
447 module_init(vr41xx_rtc_init
);
448 module_exit(vr41xx_rtc_exit
);