block: fix compiler warning in genhd.c
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / pci / pci.c
blobd00f0e0d84537168c3464d476db3485753924450
1 /*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <linux/pm.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <asm/dma.h> /* isa_dma_bridge_buggy */
22 #include "pci.h"
24 unsigned int pci_pm_d3_delay = 10;
26 #ifdef CONFIG_PCI_DOMAINS
27 int pci_domains_supported = 1;
28 #endif
30 #define DEFAULT_CARDBUS_IO_SIZE (256)
31 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
32 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
33 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
34 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
36 /**
37 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
38 * @bus: pointer to PCI bus structure to search
40 * Given a PCI bus, returns the highest PCI bus number present in the set
41 * including the given PCI bus and its list of child PCI buses.
43 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
45 struct list_head *tmp;
46 unsigned char max, n;
48 max = bus->subordinate;
49 list_for_each(tmp, &bus->children) {
50 n = pci_bus_max_busnr(pci_bus_b(tmp));
51 if(n > max)
52 max = n;
54 return max;
56 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
58 #if 0
59 /**
60 * pci_max_busnr - returns maximum PCI bus number
62 * Returns the highest PCI bus number present in the system global list of
63 * PCI buses.
65 unsigned char __devinit
66 pci_max_busnr(void)
68 struct pci_bus *bus = NULL;
69 unsigned char max, n;
71 max = 0;
72 while ((bus = pci_find_next_bus(bus)) != NULL) {
73 n = pci_bus_max_busnr(bus);
74 if(n > max)
75 max = n;
77 return max;
80 #endif /* 0 */
82 #define PCI_FIND_CAP_TTL 48
84 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
85 u8 pos, int cap, int *ttl)
87 u8 id;
89 while ((*ttl)--) {
90 pci_bus_read_config_byte(bus, devfn, pos, &pos);
91 if (pos < 0x40)
92 break;
93 pos &= ~3;
94 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
95 &id);
96 if (id == 0xff)
97 break;
98 if (id == cap)
99 return pos;
100 pos += PCI_CAP_LIST_NEXT;
102 return 0;
105 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
106 u8 pos, int cap)
108 int ttl = PCI_FIND_CAP_TTL;
110 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
113 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
115 return __pci_find_next_cap(dev->bus, dev->devfn,
116 pos + PCI_CAP_LIST_NEXT, cap);
118 EXPORT_SYMBOL_GPL(pci_find_next_capability);
120 static int __pci_bus_find_cap_start(struct pci_bus *bus,
121 unsigned int devfn, u8 hdr_type)
123 u16 status;
125 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
126 if (!(status & PCI_STATUS_CAP_LIST))
127 return 0;
129 switch (hdr_type) {
130 case PCI_HEADER_TYPE_NORMAL:
131 case PCI_HEADER_TYPE_BRIDGE:
132 return PCI_CAPABILITY_LIST;
133 case PCI_HEADER_TYPE_CARDBUS:
134 return PCI_CB_CAPABILITY_LIST;
135 default:
136 return 0;
139 return 0;
143 * pci_find_capability - query for devices' capabilities
144 * @dev: PCI device to query
145 * @cap: capability code
147 * Tell if a device supports a given PCI capability.
148 * Returns the address of the requested capability structure within the
149 * device's PCI configuration space or 0 in case the device does not
150 * support it. Possible values for @cap:
152 * %PCI_CAP_ID_PM Power Management
153 * %PCI_CAP_ID_AGP Accelerated Graphics Port
154 * %PCI_CAP_ID_VPD Vital Product Data
155 * %PCI_CAP_ID_SLOTID Slot Identification
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
158 * %PCI_CAP_ID_PCIX PCI-X
159 * %PCI_CAP_ID_EXP PCI Express
161 int pci_find_capability(struct pci_dev *dev, int cap)
163 int pos;
165 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
166 if (pos)
167 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
169 return pos;
173 * pci_bus_find_capability - query for devices' capabilities
174 * @bus: the PCI bus to query
175 * @devfn: PCI device to query
176 * @cap: capability code
178 * Like pci_find_capability() but works for pci devices that do not have a
179 * pci_dev structure set up yet.
181 * Returns the address of the requested capability structure within the
182 * device's PCI configuration space or 0 in case the device does not
183 * support it.
185 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
187 int pos;
188 u8 hdr_type;
190 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
192 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
193 if (pos)
194 pos = __pci_find_next_cap(bus, devfn, pos, cap);
196 return pos;
200 * pci_find_ext_capability - Find an extended capability
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Returns the address of the requested extended capability structure
205 * within the device's PCI configuration space or 0 if the device does
206 * not support it. Possible values for @cap:
208 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
209 * %PCI_EXT_CAP_ID_VC Virtual Channel
210 * %PCI_EXT_CAP_ID_DSN Device Serial Number
211 * %PCI_EXT_CAP_ID_PWR Power Budgeting
213 int pci_find_ext_capability(struct pci_dev *dev, int cap)
215 u32 header;
216 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
217 int pos = 0x100;
219 if (dev->cfg_size <= 256)
220 return 0;
222 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
223 return 0;
226 * If we have no capabilities, this is indicated by cap ID,
227 * cap version and next pointer all being 0.
229 if (header == 0)
230 return 0;
232 while (ttl-- > 0) {
233 if (PCI_EXT_CAP_ID(header) == cap)
234 return pos;
236 pos = PCI_EXT_CAP_NEXT(header);
237 if (pos < 0x100)
238 break;
240 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
241 break;
244 return 0;
246 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
248 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
250 int rc, ttl = PCI_FIND_CAP_TTL;
251 u8 cap, mask;
253 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
254 mask = HT_3BIT_CAP_MASK;
255 else
256 mask = HT_5BIT_CAP_MASK;
258 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
259 PCI_CAP_ID_HT, &ttl);
260 while (pos) {
261 rc = pci_read_config_byte(dev, pos + 3, &cap);
262 if (rc != PCIBIOS_SUCCESSFUL)
263 return 0;
265 if ((cap & mask) == ht_cap)
266 return pos;
268 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
269 pos + PCI_CAP_LIST_NEXT,
270 PCI_CAP_ID_HT, &ttl);
273 return 0;
276 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
277 * @dev: PCI device to query
278 * @pos: Position from which to continue searching
279 * @ht_cap: Hypertransport capability code
281 * To be used in conjunction with pci_find_ht_capability() to search for
282 * all capabilities matching @ht_cap. @pos should always be a value returned
283 * from pci_find_ht_capability().
285 * NB. To be 100% safe against broken PCI devices, the caller should take
286 * steps to avoid an infinite loop.
288 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
290 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
292 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
295 * pci_find_ht_capability - query a device's Hypertransport capabilities
296 * @dev: PCI device to query
297 * @ht_cap: Hypertransport capability code
299 * Tell if a device supports a given Hypertransport capability.
300 * Returns an address within the device's PCI configuration space
301 * or 0 in case the device does not support the request capability.
302 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
303 * which has a Hypertransport capability matching @ht_cap.
305 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
307 int pos;
309 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
310 if (pos)
311 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
313 return pos;
315 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
318 * pci_find_parent_resource - return resource region of parent bus of given region
319 * @dev: PCI device structure contains resources to be searched
320 * @res: child resource record for which parent is sought
322 * For given resource region of given device, return the resource
323 * region of parent bus the given region is contained in or where
324 * it should be allocated from.
326 struct resource *
327 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
329 const struct pci_bus *bus = dev->bus;
330 int i;
331 struct resource *best = NULL;
333 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
334 struct resource *r = bus->resource[i];
335 if (!r)
336 continue;
337 if (res->start && !(res->start >= r->start && res->end <= r->end))
338 continue; /* Not contained */
339 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
340 continue; /* Wrong type */
341 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
342 return r; /* Exact match */
343 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
344 best = r; /* Approximating prefetchable by non-prefetchable */
346 return best;
350 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
351 * @dev: PCI device to have its BARs restored
353 * Restore the BAR values for a given device, so as to make it
354 * accessible by its driver.
356 static void
357 pci_restore_bars(struct pci_dev *dev)
359 int i, numres;
361 switch (dev->hdr_type) {
362 case PCI_HEADER_TYPE_NORMAL:
363 numres = 6;
364 break;
365 case PCI_HEADER_TYPE_BRIDGE:
366 numres = 2;
367 break;
368 case PCI_HEADER_TYPE_CARDBUS:
369 numres = 1;
370 break;
371 default:
372 /* Should never get here, but just in case... */
373 return;
376 for (i = 0; i < numres; i ++)
377 pci_update_resource(dev, &dev->resource[i], i);
380 static struct pci_platform_pm_ops *pci_platform_pm;
382 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
384 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
385 || !ops->sleep_wake || !ops->can_wakeup)
386 return -EINVAL;
387 pci_platform_pm = ops;
388 return 0;
391 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
393 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
396 static inline int platform_pci_set_power_state(struct pci_dev *dev,
397 pci_power_t t)
399 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
402 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
404 return pci_platform_pm ?
405 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
408 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
410 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
413 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
415 return pci_platform_pm ?
416 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
420 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
421 * given PCI device
422 * @dev: PCI device to handle.
423 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
425 * RETURN VALUE:
426 * -EINVAL if the requested state is invalid.
427 * -EIO if device does not support PCI PM or its PM capabilities register has a
428 * wrong version, or device doesn't support the requested state.
429 * 0 if device already is in the requested state.
430 * 0 if device's power state has been successfully changed.
432 static int
433 pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
435 u16 pmcsr;
436 bool need_restore = false;
438 if (!dev->pm_cap)
439 return -EIO;
441 if (state < PCI_D0 || state > PCI_D3hot)
442 return -EINVAL;
444 /* Validate current state:
445 * Can enter D0 from any state, but if we can only go deeper
446 * to sleep if we're already in a low power state
448 if (dev->current_state == state) {
449 /* we're already there */
450 return 0;
451 } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold
452 && dev->current_state > state) {
453 dev_err(&dev->dev, "invalid power transition "
454 "(from state %d to %d)\n", dev->current_state, state);
455 return -EINVAL;
458 /* check if this device supports the desired state */
459 if ((state == PCI_D1 && !dev->d1_support)
460 || (state == PCI_D2 && !dev->d2_support))
461 return -EIO;
463 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
465 /* If we're (effectively) in D3, force entire word to 0.
466 * This doesn't affect PME_Status, disables PME_En, and
467 * sets PowerState to 0.
469 switch (dev->current_state) {
470 case PCI_D0:
471 case PCI_D1:
472 case PCI_D2:
473 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
474 pmcsr |= state;
475 break;
476 case PCI_UNKNOWN: /* Boot-up */
477 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
478 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
479 need_restore = true;
480 /* Fall-through: force to D0 */
481 default:
482 pmcsr = 0;
483 break;
486 /* enter specified state */
487 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
489 /* Mandatory power management transition delays */
490 /* see PCI PM 1.1 5.6.1 table 18 */
491 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
492 msleep(pci_pm_d3_delay);
493 else if (state == PCI_D2 || dev->current_state == PCI_D2)
494 udelay(200);
496 dev->current_state = state;
498 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
499 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
500 * from D3hot to D0 _may_ perform an internal reset, thereby
501 * going to "D0 Uninitialized" rather than "D0 Initialized".
502 * For example, at least some versions of the 3c905B and the
503 * 3c556B exhibit this behaviour.
505 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
506 * devices in a D3hot state at boot. Consequently, we need to
507 * restore at least the BARs so that the device will be
508 * accessible to its driver.
510 if (need_restore)
511 pci_restore_bars(dev);
513 if (dev->bus->self)
514 pcie_aspm_pm_state_change(dev->bus->self);
516 return 0;
520 * pci_update_current_state - Read PCI power state of given device from its
521 * PCI PM registers and cache it
522 * @dev: PCI device to handle.
524 static void pci_update_current_state(struct pci_dev *dev)
526 if (dev->pm_cap) {
527 u16 pmcsr;
529 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
530 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
535 * pci_set_power_state - Set the power state of a PCI device
536 * @dev: PCI device to handle.
537 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
539 * Transition a device to a new power state, using the platform formware and/or
540 * the device's PCI PM registers.
542 * RETURN VALUE:
543 * -EINVAL if the requested state is invalid.
544 * -EIO if device does not support PCI PM or its PM capabilities register has a
545 * wrong version, or device doesn't support the requested state.
546 * 0 if device already is in the requested state.
547 * 0 if device's power state has been successfully changed.
549 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
551 int error;
553 /* bound the state we're entering */
554 if (state > PCI_D3hot)
555 state = PCI_D3hot;
556 else if (state < PCI_D0)
557 state = PCI_D0;
558 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
560 * If the device or the parent bridge do not support PCI PM,
561 * ignore the request if we're doing anything other than putting
562 * it into D0 (which would only happen on boot).
564 return 0;
566 if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
568 * Allow the platform to change the state, for example via ACPI
569 * _PR0, _PS0 and some such, but do not trust it.
571 int ret = platform_pci_set_power_state(dev, PCI_D0);
572 if (!ret)
573 pci_update_current_state(dev);
576 error = pci_raw_set_power_state(dev, state);
578 if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
579 /* Allow the platform to finalize the transition */
580 int ret = platform_pci_set_power_state(dev, state);
581 if (!ret) {
582 pci_update_current_state(dev);
583 error = 0;
587 return error;
591 * pci_choose_state - Choose the power state of a PCI device
592 * @dev: PCI device to be suspended
593 * @state: target sleep state for the whole system. This is the value
594 * that is passed to suspend() function.
596 * Returns PCI power state suitable for given device and given system
597 * message.
600 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
602 pci_power_t ret;
604 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
605 return PCI_D0;
607 ret = platform_pci_choose_state(dev);
608 if (ret != PCI_POWER_ERROR)
609 return ret;
611 switch (state.event) {
612 case PM_EVENT_ON:
613 return PCI_D0;
614 case PM_EVENT_FREEZE:
615 case PM_EVENT_PRETHAW:
616 /* REVISIT both freeze and pre-thaw "should" use D0 */
617 case PM_EVENT_SUSPEND:
618 case PM_EVENT_HIBERNATE:
619 return PCI_D3hot;
620 default:
621 dev_info(&dev->dev, "unrecognized suspend event %d\n",
622 state.event);
623 BUG();
625 return PCI_D0;
628 EXPORT_SYMBOL(pci_choose_state);
630 static int pci_save_pcie_state(struct pci_dev *dev)
632 int pos, i = 0;
633 struct pci_cap_saved_state *save_state;
634 u16 *cap;
635 int found = 0;
637 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
638 if (pos <= 0)
639 return 0;
641 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
642 if (!save_state)
643 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
644 else
645 found = 1;
646 if (!save_state) {
647 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
648 return -ENOMEM;
650 cap = (u16 *)&save_state->data[0];
652 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
653 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
654 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
655 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
656 save_state->cap_nr = PCI_CAP_ID_EXP;
657 if (!found)
658 pci_add_saved_cap(dev, save_state);
659 return 0;
662 static void pci_restore_pcie_state(struct pci_dev *dev)
664 int i = 0, pos;
665 struct pci_cap_saved_state *save_state;
666 u16 *cap;
668 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
669 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
670 if (!save_state || pos <= 0)
671 return;
672 cap = (u16 *)&save_state->data[0];
674 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
675 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
676 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
677 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
681 static int pci_save_pcix_state(struct pci_dev *dev)
683 int pos, i = 0;
684 struct pci_cap_saved_state *save_state;
685 u16 *cap;
686 int found = 0;
688 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
689 if (pos <= 0)
690 return 0;
692 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
693 if (!save_state)
694 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
695 else
696 found = 1;
697 if (!save_state) {
698 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
699 return -ENOMEM;
701 cap = (u16 *)&save_state->data[0];
703 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
704 save_state->cap_nr = PCI_CAP_ID_PCIX;
705 if (!found)
706 pci_add_saved_cap(dev, save_state);
707 return 0;
710 static void pci_restore_pcix_state(struct pci_dev *dev)
712 int i = 0, pos;
713 struct pci_cap_saved_state *save_state;
714 u16 *cap;
716 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
717 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
718 if (!save_state || pos <= 0)
719 return;
720 cap = (u16 *)&save_state->data[0];
722 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
727 * pci_save_state - save the PCI configuration space of a device before suspending
728 * @dev: - PCI device that we're dealing with
731 pci_save_state(struct pci_dev *dev)
733 int i;
734 /* XXX: 100% dword access ok here? */
735 for (i = 0; i < 16; i++)
736 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
737 if ((i = pci_save_pcie_state(dev)) != 0)
738 return i;
739 if ((i = pci_save_pcix_state(dev)) != 0)
740 return i;
741 return 0;
744 /**
745 * pci_restore_state - Restore the saved state of a PCI device
746 * @dev: - PCI device that we're dealing with
748 int
749 pci_restore_state(struct pci_dev *dev)
751 int i;
752 u32 val;
754 /* PCI Express register must be restored first */
755 pci_restore_pcie_state(dev);
758 * The Base Address register should be programmed before the command
759 * register(s)
761 for (i = 15; i >= 0; i--) {
762 pci_read_config_dword(dev, i * 4, &val);
763 if (val != dev->saved_config_space[i]) {
764 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
765 "space at offset %#x (was %#x, writing %#x)\n",
766 i, val, (int)dev->saved_config_space[i]);
767 pci_write_config_dword(dev,i * 4,
768 dev->saved_config_space[i]);
771 pci_restore_pcix_state(dev);
772 pci_restore_msi_state(dev);
774 return 0;
777 static int do_pci_enable_device(struct pci_dev *dev, int bars)
779 int err;
781 err = pci_set_power_state(dev, PCI_D0);
782 if (err < 0 && err != -EIO)
783 return err;
784 err = pcibios_enable_device(dev, bars);
785 if (err < 0)
786 return err;
787 pci_fixup_device(pci_fixup_enable, dev);
789 return 0;
793 * pci_reenable_device - Resume abandoned device
794 * @dev: PCI device to be resumed
796 * Note this function is a backend of pci_default_resume and is not supposed
797 * to be called by normal code, write proper resume handler and use it instead.
799 int pci_reenable_device(struct pci_dev *dev)
801 if (atomic_read(&dev->enable_cnt))
802 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
803 return 0;
806 static int __pci_enable_device_flags(struct pci_dev *dev,
807 resource_size_t flags)
809 int err;
810 int i, bars = 0;
812 if (atomic_add_return(1, &dev->enable_cnt) > 1)
813 return 0; /* already enabled */
815 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
816 if (dev->resource[i].flags & flags)
817 bars |= (1 << i);
819 err = do_pci_enable_device(dev, bars);
820 if (err < 0)
821 atomic_dec(&dev->enable_cnt);
822 return err;
826 * pci_enable_device_io - Initialize a device for use with IO space
827 * @dev: PCI device to be initialized
829 * Initialize device before it's used by a driver. Ask low-level code
830 * to enable I/O resources. Wake up the device if it was suspended.
831 * Beware, this function can fail.
833 int pci_enable_device_io(struct pci_dev *dev)
835 return __pci_enable_device_flags(dev, IORESOURCE_IO);
839 * pci_enable_device_mem - Initialize a device for use with Memory space
840 * @dev: PCI device to be initialized
842 * Initialize device before it's used by a driver. Ask low-level code
843 * to enable Memory resources. Wake up the device if it was suspended.
844 * Beware, this function can fail.
846 int pci_enable_device_mem(struct pci_dev *dev)
848 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
852 * pci_enable_device - Initialize device before it's used by a driver.
853 * @dev: PCI device to be initialized
855 * Initialize device before it's used by a driver. Ask low-level code
856 * to enable I/O and memory. Wake up the device if it was suspended.
857 * Beware, this function can fail.
859 * Note we don't actually enable the device many times if we call
860 * this function repeatedly (we just increment the count).
862 int pci_enable_device(struct pci_dev *dev)
864 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
868 * Managed PCI resources. This manages device on/off, intx/msi/msix
869 * on/off and BAR regions. pci_dev itself records msi/msix status, so
870 * there's no need to track it separately. pci_devres is initialized
871 * when a device is enabled using managed PCI device enable interface.
873 struct pci_devres {
874 unsigned int enabled:1;
875 unsigned int pinned:1;
876 unsigned int orig_intx:1;
877 unsigned int restore_intx:1;
878 u32 region_mask;
881 static void pcim_release(struct device *gendev, void *res)
883 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
884 struct pci_devres *this = res;
885 int i;
887 if (dev->msi_enabled)
888 pci_disable_msi(dev);
889 if (dev->msix_enabled)
890 pci_disable_msix(dev);
892 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
893 if (this->region_mask & (1 << i))
894 pci_release_region(dev, i);
896 if (this->restore_intx)
897 pci_intx(dev, this->orig_intx);
899 if (this->enabled && !this->pinned)
900 pci_disable_device(dev);
903 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
905 struct pci_devres *dr, *new_dr;
907 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
908 if (dr)
909 return dr;
911 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
912 if (!new_dr)
913 return NULL;
914 return devres_get(&pdev->dev, new_dr, NULL, NULL);
917 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
919 if (pci_is_managed(pdev))
920 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
921 return NULL;
925 * pcim_enable_device - Managed pci_enable_device()
926 * @pdev: PCI device to be initialized
928 * Managed pci_enable_device().
930 int pcim_enable_device(struct pci_dev *pdev)
932 struct pci_devres *dr;
933 int rc;
935 dr = get_pci_dr(pdev);
936 if (unlikely(!dr))
937 return -ENOMEM;
938 if (dr->enabled)
939 return 0;
941 rc = pci_enable_device(pdev);
942 if (!rc) {
943 pdev->is_managed = 1;
944 dr->enabled = 1;
946 return rc;
950 * pcim_pin_device - Pin managed PCI device
951 * @pdev: PCI device to pin
953 * Pin managed PCI device @pdev. Pinned device won't be disabled on
954 * driver detach. @pdev must have been enabled with
955 * pcim_enable_device().
957 void pcim_pin_device(struct pci_dev *pdev)
959 struct pci_devres *dr;
961 dr = find_pci_dr(pdev);
962 WARN_ON(!dr || !dr->enabled);
963 if (dr)
964 dr->pinned = 1;
968 * pcibios_disable_device - disable arch specific PCI resources for device dev
969 * @dev: the PCI device to disable
971 * Disables architecture specific PCI resources for the device. This
972 * is the default implementation. Architecture implementations can
973 * override this.
975 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
978 * pci_disable_device - Disable PCI device after use
979 * @dev: PCI device to be disabled
981 * Signal to the system that the PCI device is not in use by the system
982 * anymore. This only involves disabling PCI bus-mastering, if active.
984 * Note we don't actually disable the device until all callers of
985 * pci_device_enable() have called pci_device_disable().
987 void
988 pci_disable_device(struct pci_dev *dev)
990 struct pci_devres *dr;
991 u16 pci_command;
993 dr = find_pci_dr(dev);
994 if (dr)
995 dr->enabled = 0;
997 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
998 return;
1000 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1001 if (pci_command & PCI_COMMAND_MASTER) {
1002 pci_command &= ~PCI_COMMAND_MASTER;
1003 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1005 dev->is_busmaster = 0;
1007 pcibios_disable_device(dev);
1011 * pcibios_set_pcie_reset_state - set reset state for device dev
1012 * @dev: the PCI-E device reset
1013 * @state: Reset state to enter into
1016 * Sets the PCI-E reset state for the device. This is the default
1017 * implementation. Architecture implementations can override this.
1019 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1020 enum pcie_reset_state state)
1022 return -EINVAL;
1026 * pci_set_pcie_reset_state - set reset state for device dev
1027 * @dev: the PCI-E device reset
1028 * @state: Reset state to enter into
1031 * Sets the PCI reset state for the device.
1033 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1035 return pcibios_set_pcie_reset_state(dev, state);
1039 * pci_pme_capable - check the capability of PCI device to generate PME#
1040 * @dev: PCI device to handle.
1041 * @state: PCI state from which device will issue PME#.
1043 static bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1045 if (!dev->pm_cap)
1046 return false;
1048 return !!(dev->pme_support & (1 << state));
1052 * pci_pme_active - enable or disable PCI device's PME# function
1053 * @dev: PCI device to handle.
1054 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1056 * The caller must verify that the device is capable of generating PME# before
1057 * calling this function with @enable equal to 'true'.
1059 static void pci_pme_active(struct pci_dev *dev, bool enable)
1061 u16 pmcsr;
1063 if (!dev->pm_cap)
1064 return;
1066 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1067 /* Clear PME_Status by writing 1 to it and enable PME# */
1068 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1069 if (!enable)
1070 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1072 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1074 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1075 enable ? "enabled" : "disabled");
1079 * pci_enable_wake - enable PCI device as wakeup event source
1080 * @dev: PCI device affected
1081 * @state: PCI state from which device will issue wakeup events
1082 * @enable: True to enable event generation; false to disable
1084 * This enables the device as a wakeup event source, or disables it.
1085 * When such events involves platform-specific hooks, those hooks are
1086 * called automatically by this routine.
1088 * Devices with legacy power management (no standard PCI PM capabilities)
1089 * always require such platform hooks.
1091 * RETURN VALUE:
1092 * 0 is returned on success
1093 * -EINVAL is returned if device is not supposed to wake up the system
1094 * Error code depending on the platform is returned if both the platform and
1095 * the native mechanism fail to enable the generation of wake-up events
1097 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1099 int error = 0;
1100 bool pme_done = false;
1102 if (!device_may_wakeup(&dev->dev))
1103 return -EINVAL;
1106 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1107 * Anderson we should be doing PME# wake enable followed by ACPI wake
1108 * enable. To disable wake-up we call the platform first, for symmetry.
1111 if (!enable && platform_pci_can_wakeup(dev))
1112 error = platform_pci_sleep_wake(dev, false);
1114 if (!enable || pci_pme_capable(dev, state)) {
1115 pci_pme_active(dev, enable);
1116 pme_done = true;
1119 if (enable && platform_pci_can_wakeup(dev))
1120 error = platform_pci_sleep_wake(dev, true);
1122 return pme_done ? 0 : error;
1126 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1127 * @dev: Device to handle.
1129 * Choose the power state appropriate for the device depending on whether
1130 * it can wake up the system and/or is power manageable by the platform
1131 * (PCI_D3hot is the default) and put the device into that state.
1133 int pci_prepare_to_sleep(struct pci_dev *dev)
1135 pci_power_t target_state = PCI_D3hot;
1136 int error;
1138 if (platform_pci_power_manageable(dev)) {
1140 * Call the platform to choose the target state of the device
1141 * and enable wake-up from this state if supported.
1143 pci_power_t state = platform_pci_choose_state(dev);
1145 switch (state) {
1146 case PCI_POWER_ERROR:
1147 case PCI_UNKNOWN:
1148 break;
1149 case PCI_D1:
1150 case PCI_D2:
1151 if (pci_no_d1d2(dev))
1152 break;
1153 default:
1154 target_state = state;
1156 } else if (device_may_wakeup(&dev->dev)) {
1158 * Find the deepest state from which the device can generate
1159 * wake-up events, make it the target state and enable device
1160 * to generate PME#.
1162 if (!dev->pm_cap)
1163 return -EIO;
1165 if (dev->pme_support) {
1166 while (target_state
1167 && !(dev->pme_support & (1 << target_state)))
1168 target_state--;
1172 pci_enable_wake(dev, target_state, true);
1174 error = pci_set_power_state(dev, target_state);
1176 if (error)
1177 pci_enable_wake(dev, target_state, false);
1179 return error;
1183 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1184 * @dev: Device to handle.
1186 * Disable device's sytem wake-up capability and put it into D0.
1188 int pci_back_from_sleep(struct pci_dev *dev)
1190 pci_enable_wake(dev, PCI_D0, false);
1191 return pci_set_power_state(dev, PCI_D0);
1195 * pci_pm_init - Initialize PM functions of given PCI device
1196 * @dev: PCI device to handle.
1198 void pci_pm_init(struct pci_dev *dev)
1200 int pm;
1201 u16 pmc;
1203 dev->pm_cap = 0;
1205 /* find PCI PM capability in list */
1206 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1207 if (!pm)
1208 return;
1209 /* Check device's ability to generate PME# */
1210 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1212 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1213 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1214 pmc & PCI_PM_CAP_VER_MASK);
1215 return;
1218 dev->pm_cap = pm;
1220 dev->d1_support = false;
1221 dev->d2_support = false;
1222 if (!pci_no_d1d2(dev)) {
1223 if (pmc & PCI_PM_CAP_D1) {
1224 dev_printk(KERN_DEBUG, &dev->dev, "supports D1\n");
1225 dev->d1_support = true;
1227 if (pmc & PCI_PM_CAP_D2) {
1228 dev_printk(KERN_DEBUG, &dev->dev, "supports D2\n");
1229 dev->d2_support = true;
1233 pmc &= PCI_PM_CAP_PME_MASK;
1234 if (pmc) {
1235 dev_printk(KERN_INFO, &dev->dev,
1236 "PME# supported from%s%s%s%s%s\n",
1237 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1238 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1239 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1240 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1241 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1242 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1244 * Make device's PM flags reflect the wake-up capability, but
1245 * let the user space enable it to wake up the system as needed.
1247 device_set_wakeup_capable(&dev->dev, true);
1248 device_set_wakeup_enable(&dev->dev, false);
1249 /* Disable the PME# generation functionality */
1250 pci_pme_active(dev, false);
1251 } else {
1252 dev->pme_support = 0;
1257 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1259 u8 pin;
1261 pin = dev->pin;
1262 if (!pin)
1263 return -1;
1264 pin--;
1265 while (dev->bus->self) {
1266 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1267 dev = dev->bus->self;
1269 *bridge = dev;
1270 return pin;
1274 * pci_release_region - Release a PCI bar
1275 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1276 * @bar: BAR to release
1278 * Releases the PCI I/O and memory resources previously reserved by a
1279 * successful call to pci_request_region. Call this function only
1280 * after all use of the PCI regions has ceased.
1282 void pci_release_region(struct pci_dev *pdev, int bar)
1284 struct pci_devres *dr;
1286 if (pci_resource_len(pdev, bar) == 0)
1287 return;
1288 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1289 release_region(pci_resource_start(pdev, bar),
1290 pci_resource_len(pdev, bar));
1291 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1292 release_mem_region(pci_resource_start(pdev, bar),
1293 pci_resource_len(pdev, bar));
1295 dr = find_pci_dr(pdev);
1296 if (dr)
1297 dr->region_mask &= ~(1 << bar);
1301 * pci_request_region - Reserved PCI I/O and memory resource
1302 * @pdev: PCI device whose resources are to be reserved
1303 * @bar: BAR to be reserved
1304 * @res_name: Name to be associated with resource.
1306 * Mark the PCI region associated with PCI device @pdev BR @bar as
1307 * being reserved by owner @res_name. Do not access any
1308 * address inside the PCI regions unless this call returns
1309 * successfully.
1311 * Returns 0 on success, or %EBUSY on error. A warning
1312 * message is also printed on failure.
1314 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1316 struct pci_devres *dr;
1318 if (pci_resource_len(pdev, bar) == 0)
1319 return 0;
1321 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1322 if (!request_region(pci_resource_start(pdev, bar),
1323 pci_resource_len(pdev, bar), res_name))
1324 goto err_out;
1326 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1327 if (!request_mem_region(pci_resource_start(pdev, bar),
1328 pci_resource_len(pdev, bar), res_name))
1329 goto err_out;
1332 dr = find_pci_dr(pdev);
1333 if (dr)
1334 dr->region_mask |= 1 << bar;
1336 return 0;
1338 err_out:
1339 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n",
1340 bar,
1341 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1342 (unsigned long long)pci_resource_start(pdev, bar),
1343 (unsigned long long)pci_resource_end(pdev, bar));
1344 return -EBUSY;
1348 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1349 * @pdev: PCI device whose resources were previously reserved
1350 * @bars: Bitmask of BARs to be released
1352 * Release selected PCI I/O and memory resources previously reserved.
1353 * Call this function only after all use of the PCI regions has ceased.
1355 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1357 int i;
1359 for (i = 0; i < 6; i++)
1360 if (bars & (1 << i))
1361 pci_release_region(pdev, i);
1365 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1366 * @pdev: PCI device whose resources are to be reserved
1367 * @bars: Bitmask of BARs to be requested
1368 * @res_name: Name to be associated with resource
1370 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1371 const char *res_name)
1373 int i;
1375 for (i = 0; i < 6; i++)
1376 if (bars & (1 << i))
1377 if(pci_request_region(pdev, i, res_name))
1378 goto err_out;
1379 return 0;
1381 err_out:
1382 while(--i >= 0)
1383 if (bars & (1 << i))
1384 pci_release_region(pdev, i);
1386 return -EBUSY;
1390 * pci_release_regions - Release reserved PCI I/O and memory resources
1391 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1393 * Releases all PCI I/O and memory resources previously reserved by a
1394 * successful call to pci_request_regions. Call this function only
1395 * after all use of the PCI regions has ceased.
1398 void pci_release_regions(struct pci_dev *pdev)
1400 pci_release_selected_regions(pdev, (1 << 6) - 1);
1404 * pci_request_regions - Reserved PCI I/O and memory resources
1405 * @pdev: PCI device whose resources are to be reserved
1406 * @res_name: Name to be associated with resource.
1408 * Mark all PCI regions associated with PCI device @pdev as
1409 * being reserved by owner @res_name. Do not access any
1410 * address inside the PCI regions unless this call returns
1411 * successfully.
1413 * Returns 0 on success, or %EBUSY on error. A warning
1414 * message is also printed on failure.
1416 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1418 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1422 * pci_set_master - enables bus-mastering for device dev
1423 * @dev: the PCI device to enable
1425 * Enables bus-mastering on the device and calls pcibios_set_master()
1426 * to do the needed arch specific settings.
1428 void
1429 pci_set_master(struct pci_dev *dev)
1431 u16 cmd;
1433 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1434 if (! (cmd & PCI_COMMAND_MASTER)) {
1435 dev_dbg(&dev->dev, "enabling bus mastering\n");
1436 cmd |= PCI_COMMAND_MASTER;
1437 pci_write_config_word(dev, PCI_COMMAND, cmd);
1439 dev->is_busmaster = 1;
1440 pcibios_set_master(dev);
1443 #ifdef PCI_DISABLE_MWI
1444 int pci_set_mwi(struct pci_dev *dev)
1446 return 0;
1449 int pci_try_set_mwi(struct pci_dev *dev)
1451 return 0;
1454 void pci_clear_mwi(struct pci_dev *dev)
1458 #else
1460 #ifndef PCI_CACHE_LINE_BYTES
1461 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1462 #endif
1464 /* This can be overridden by arch code. */
1465 /* Don't forget this is measured in 32-bit words, not bytes */
1466 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1469 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1470 * @dev: the PCI device for which MWI is to be enabled
1472 * Helper function for pci_set_mwi.
1473 * Originally copied from drivers/net/acenic.c.
1474 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1476 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1478 static int
1479 pci_set_cacheline_size(struct pci_dev *dev)
1481 u8 cacheline_size;
1483 if (!pci_cache_line_size)
1484 return -EINVAL; /* The system doesn't support MWI. */
1486 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1487 equal to or multiple of the right value. */
1488 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1489 if (cacheline_size >= pci_cache_line_size &&
1490 (cacheline_size % pci_cache_line_size) == 0)
1491 return 0;
1493 /* Write the correct value. */
1494 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1495 /* Read it back. */
1496 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1497 if (cacheline_size == pci_cache_line_size)
1498 return 0;
1500 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1501 "supported\n", pci_cache_line_size << 2);
1503 return -EINVAL;
1507 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1508 * @dev: the PCI device for which MWI is enabled
1510 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1512 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1515 pci_set_mwi(struct pci_dev *dev)
1517 int rc;
1518 u16 cmd;
1520 rc = pci_set_cacheline_size(dev);
1521 if (rc)
1522 return rc;
1524 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1525 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1526 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1527 cmd |= PCI_COMMAND_INVALIDATE;
1528 pci_write_config_word(dev, PCI_COMMAND, cmd);
1531 return 0;
1535 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1536 * @dev: the PCI device for which MWI is enabled
1538 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1539 * Callers are not required to check the return value.
1541 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1543 int pci_try_set_mwi(struct pci_dev *dev)
1545 int rc = pci_set_mwi(dev);
1546 return rc;
1550 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1551 * @dev: the PCI device to disable
1553 * Disables PCI Memory-Write-Invalidate transaction on the device
1555 void
1556 pci_clear_mwi(struct pci_dev *dev)
1558 u16 cmd;
1560 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1561 if (cmd & PCI_COMMAND_INVALIDATE) {
1562 cmd &= ~PCI_COMMAND_INVALIDATE;
1563 pci_write_config_word(dev, PCI_COMMAND, cmd);
1566 #endif /* ! PCI_DISABLE_MWI */
1569 * pci_intx - enables/disables PCI INTx for device dev
1570 * @pdev: the PCI device to operate on
1571 * @enable: boolean: whether to enable or disable PCI INTx
1573 * Enables/disables PCI INTx for device dev
1575 void
1576 pci_intx(struct pci_dev *pdev, int enable)
1578 u16 pci_command, new;
1580 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1582 if (enable) {
1583 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1584 } else {
1585 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1588 if (new != pci_command) {
1589 struct pci_devres *dr;
1591 pci_write_config_word(pdev, PCI_COMMAND, new);
1593 dr = find_pci_dr(pdev);
1594 if (dr && !dr->restore_intx) {
1595 dr->restore_intx = 1;
1596 dr->orig_intx = !enable;
1602 * pci_msi_off - disables any msi or msix capabilities
1603 * @dev: the PCI device to operate on
1605 * If you want to use msi see pci_enable_msi and friends.
1606 * This is a lower level primitive that allows us to disable
1607 * msi operation at the device level.
1609 void pci_msi_off(struct pci_dev *dev)
1611 int pos;
1612 u16 control;
1614 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1615 if (pos) {
1616 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1617 control &= ~PCI_MSI_FLAGS_ENABLE;
1618 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1620 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1621 if (pos) {
1622 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1623 control &= ~PCI_MSIX_FLAGS_ENABLE;
1624 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1628 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1630 * These can be overridden by arch-specific implementations
1633 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1635 if (!pci_dma_supported(dev, mask))
1636 return -EIO;
1638 dev->dma_mask = mask;
1640 return 0;
1644 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1646 if (!pci_dma_supported(dev, mask))
1647 return -EIO;
1649 dev->dev.coherent_dma_mask = mask;
1651 return 0;
1653 #endif
1655 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1656 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1658 return dma_set_max_seg_size(&dev->dev, size);
1660 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1661 #endif
1663 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1664 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1666 return dma_set_seg_boundary(&dev->dev, mask);
1668 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1669 #endif
1672 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1673 * @dev: PCI device to query
1675 * Returns mmrbc: maximum designed memory read count in bytes
1676 * or appropriate error value.
1678 int pcix_get_max_mmrbc(struct pci_dev *dev)
1680 int err, cap;
1681 u32 stat;
1683 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1684 if (!cap)
1685 return -EINVAL;
1687 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1688 if (err)
1689 return -EINVAL;
1691 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
1693 EXPORT_SYMBOL(pcix_get_max_mmrbc);
1696 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1697 * @dev: PCI device to query
1699 * Returns mmrbc: maximum memory read count in bytes
1700 * or appropriate error value.
1702 int pcix_get_mmrbc(struct pci_dev *dev)
1704 int ret, cap;
1705 u32 cmd;
1707 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1708 if (!cap)
1709 return -EINVAL;
1711 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1712 if (!ret)
1713 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1715 return ret;
1717 EXPORT_SYMBOL(pcix_get_mmrbc);
1720 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1721 * @dev: PCI device to query
1722 * @mmrbc: maximum memory read count in bytes
1723 * valid values are 512, 1024, 2048, 4096
1725 * If possible sets maximum memory read byte count, some bridges have erratas
1726 * that prevent this.
1728 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1730 int cap, err = -EINVAL;
1731 u32 stat, cmd, v, o;
1733 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
1734 goto out;
1736 v = ffs(mmrbc) - 10;
1738 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1739 if (!cap)
1740 goto out;
1742 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1743 if (err)
1744 goto out;
1746 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1747 return -E2BIG;
1749 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1750 if (err)
1751 goto out;
1753 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1754 if (o != v) {
1755 if (v > o && dev->bus &&
1756 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1757 return -EIO;
1759 cmd &= ~PCI_X_CMD_MAX_READ;
1760 cmd |= v << 2;
1761 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1763 out:
1764 return err;
1766 EXPORT_SYMBOL(pcix_set_mmrbc);
1769 * pcie_get_readrq - get PCI Express read request size
1770 * @dev: PCI device to query
1772 * Returns maximum memory read request in bytes
1773 * or appropriate error value.
1775 int pcie_get_readrq(struct pci_dev *dev)
1777 int ret, cap;
1778 u16 ctl;
1780 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1781 if (!cap)
1782 return -EINVAL;
1784 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1785 if (!ret)
1786 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1788 return ret;
1790 EXPORT_SYMBOL(pcie_get_readrq);
1793 * pcie_set_readrq - set PCI Express maximum memory read request
1794 * @dev: PCI device to query
1795 * @rq: maximum memory read count in bytes
1796 * valid values are 128, 256, 512, 1024, 2048, 4096
1798 * If possible sets maximum read byte count
1800 int pcie_set_readrq(struct pci_dev *dev, int rq)
1802 int cap, err = -EINVAL;
1803 u16 ctl, v;
1805 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
1806 goto out;
1808 v = (ffs(rq) - 8) << 12;
1810 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1811 if (!cap)
1812 goto out;
1814 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1815 if (err)
1816 goto out;
1818 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1819 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1820 ctl |= v;
1821 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1824 out:
1825 return err;
1827 EXPORT_SYMBOL(pcie_set_readrq);
1830 * pci_select_bars - Make BAR mask from the type of resource
1831 * @dev: the PCI device for which BAR mask is made
1832 * @flags: resource type mask to be selected
1834 * This helper routine makes bar mask from the type of resource.
1836 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1838 int i, bars = 0;
1839 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1840 if (pci_resource_flags(dev, i) & flags)
1841 bars |= (1 << i);
1842 return bars;
1845 static void __devinit pci_no_domains(void)
1847 #ifdef CONFIG_PCI_DOMAINS
1848 pci_domains_supported = 0;
1849 #endif
1852 static int __devinit pci_init(void)
1854 struct pci_dev *dev = NULL;
1856 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1857 pci_fixup_device(pci_fixup_final, dev);
1859 return 0;
1862 static int __devinit pci_setup(char *str)
1864 while (str) {
1865 char *k = strchr(str, ',');
1866 if (k)
1867 *k++ = 0;
1868 if (*str && (str = pcibios_setup(str)) && *str) {
1869 if (!strcmp(str, "nomsi")) {
1870 pci_no_msi();
1871 } else if (!strcmp(str, "noaer")) {
1872 pci_no_aer();
1873 } else if (!strcmp(str, "nodomains")) {
1874 pci_no_domains();
1875 } else if (!strncmp(str, "cbiosize=", 9)) {
1876 pci_cardbus_io_size = memparse(str + 9, &str);
1877 } else if (!strncmp(str, "cbmemsize=", 10)) {
1878 pci_cardbus_mem_size = memparse(str + 10, &str);
1879 } else {
1880 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1881 str);
1884 str = k;
1886 return 0;
1888 early_param("pci", pci_setup);
1890 device_initcall(pci_init);
1892 EXPORT_SYMBOL(pci_reenable_device);
1893 EXPORT_SYMBOL(pci_enable_device_io);
1894 EXPORT_SYMBOL(pci_enable_device_mem);
1895 EXPORT_SYMBOL(pci_enable_device);
1896 EXPORT_SYMBOL(pcim_enable_device);
1897 EXPORT_SYMBOL(pcim_pin_device);
1898 EXPORT_SYMBOL(pci_disable_device);
1899 EXPORT_SYMBOL(pci_find_capability);
1900 EXPORT_SYMBOL(pci_bus_find_capability);
1901 EXPORT_SYMBOL(pci_release_regions);
1902 EXPORT_SYMBOL(pci_request_regions);
1903 EXPORT_SYMBOL(pci_release_region);
1904 EXPORT_SYMBOL(pci_request_region);
1905 EXPORT_SYMBOL(pci_release_selected_regions);
1906 EXPORT_SYMBOL(pci_request_selected_regions);
1907 EXPORT_SYMBOL(pci_set_master);
1908 EXPORT_SYMBOL(pci_set_mwi);
1909 EXPORT_SYMBOL(pci_try_set_mwi);
1910 EXPORT_SYMBOL(pci_clear_mwi);
1911 EXPORT_SYMBOL_GPL(pci_intx);
1912 EXPORT_SYMBOL(pci_set_dma_mask);
1913 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1914 EXPORT_SYMBOL(pci_assign_resource);
1915 EXPORT_SYMBOL(pci_find_parent_resource);
1916 EXPORT_SYMBOL(pci_select_bars);
1918 EXPORT_SYMBOL(pci_set_power_state);
1919 EXPORT_SYMBOL(pci_save_state);
1920 EXPORT_SYMBOL(pci_restore_state);
1921 EXPORT_SYMBOL(pci_enable_wake);
1922 EXPORT_SYMBOL(pci_prepare_to_sleep);
1923 EXPORT_SYMBOL(pci_back_from_sleep);
1924 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);