arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/string.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/module.h>
  21 #include <asm/smp.h>
  22 #include <asm/ipi.h>
  23 #include <asm/genapic.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/uv/uv_mmrs.h>
  26 #include <asm/uv/uv_hub.h>
  27 #include <asm/uv/bios.h>
  28
  29 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  30 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  31
  32 struct uv_blade_info *uv_blade_info;
  33 EXPORT_SYMBOL_GPL(uv_blade_info);
  34
  35 short *uv_node_to_blade;
  36 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  37
  38 short *uv_cpu_to_blade;
  39 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  40
  41 short uv_possible_blades;
  42 EXPORT_SYMBOL_GPL(uv_possible_blades);
  43
  44 unsigned long sn_rtc_cycles_per_second;
  45 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  46
  47 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  48
  49 static cpumask_t uv_target_cpus(void)
  50 {
  51         return cpumask_of_cpu(0);
  52 }
  53
  54 static cpumask_t uv_vector_allocation_domain(int cpu)
  55 {
  56         cpumask_t domain = CPU_MASK_NONE;
  57         cpu_set(cpu, domain);
  58         return domain;
  59 }
  60
  61 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  62 {
  63         unsigned long val;
  64         int pnode;
  65
  66         pnode = uv_apicid_to_pnode(phys_apicid);
  67         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  68             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  69             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  70             APIC_DM_INIT;
  71         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  72         mdelay(10);
  73
  74         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  75             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  76             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  77             APIC_DM_STARTUP;
  78         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  79         return 0;
  80 }
  81
  82 static void uv_send_IPI_one(int cpu, int vector)
  83 {
  84         unsigned long val, apicid, lapicid;
  85         int pnode;
  86
  87         apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
  88         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
  89         pnode = uv_apicid_to_pnode(apicid);
  90         val =
  91             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
  92                                               UVH_IPI_INT_APIC_ID_SHFT) |
  93             (vector << UVH_IPI_INT_VECTOR_SHFT);
  94         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  95 }
  96
  97 static void uv_send_IPI_mask(cpumask_t mask, int vector)
  98 {
  99         unsigned int cpu;
 100
 101         for (cpu = 0; cpu < NR_CPUS; ++cpu)
 102                 if (cpu_isset(cpu, mask))
 103                         uv_send_IPI_one(cpu, vector);
 104 }
 105
 106 static void uv_send_IPI_allbutself(int vector)
 107 {
 108         cpumask_t mask = cpu_online_map;
 109
 110         cpu_clear(smp_processor_id(), mask);
 111
 112         if (!cpus_empty(mask))
 113                 uv_send_IPI_mask(mask, vector);
 114 }
 115
 116 static void uv_send_IPI_all(int vector)
 117 {
 118         uv_send_IPI_mask(cpu_online_map, vector);
 119 }
 120
 121 static int uv_apic_id_registered(void)
 122 {
 123         return 1;
 124 }
 125
 126 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
 127 {
 128         int cpu;
 129
 130         /*
 131          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 132          * May as well be the first.
 133          */
 134         cpu = first_cpu(cpumask);
 135         if ((unsigned)cpu < NR_CPUS)
 136                 return per_cpu(x86_cpu_to_apicid, cpu);
 137         else
 138                 return BAD_APICID;
 139 }
 140
 141 static unsigned int phys_pkg_id(int index_msb)
 142 {
 143         return GET_APIC_ID(read_apic_id()) >> index_msb;
 144 }
 145
 146 #ifdef ZZZ              /* Needs x2apic patch */
 147 static void uv_send_IPI_self(int vector)
 148 {
 149         apic_write(APIC_SELF_IPI, vector);
 150 }
 151 #endif
 152
 153 struct genapic apic_x2apic_uv_x = {
 154         .name = "UV large system",
 155         .int_delivery_mode = dest_Fixed,
 156         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 157         .target_cpus = uv_target_cpus,
 158         .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
 159         .apic_id_registered = uv_apic_id_registered,
 160         .send_IPI_all = uv_send_IPI_all,
 161         .send_IPI_allbutself = uv_send_IPI_allbutself,
 162         .send_IPI_mask = uv_send_IPI_mask,
 163         /* ZZZ.send_IPI_self = uv_send_IPI_self, */
 164         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 165         .phys_pkg_id = phys_pkg_id,     /* Fixme ZZZ */
 166 };
 167
 168 static __cpuinit void set_x2apic_extra_bits(int pnode)
 169 {
 170         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 171 }
 172
 173 /*
 174  * Called on boot cpu.
 175  */
 176 static __init int boot_pnode_to_blade(int pnode)
 177 {
 178         int blade;
 179
 180         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 181                 if (pnode == uv_blade_info[blade].pnode)
 182                         return blade;
 183         BUG();
 184 }
 185
 186 struct redir_addr {
 187         unsigned long redirect;
 188         unsigned long alias;
 189 };
 190
 191 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 192
 193 static __initdata struct redir_addr redir_addrs[] = {
 194         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 195         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 196         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 197 };
 198
 199 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 200 {
 201         union uvh_si_alias0_overlay_config_u alias;
 202         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 203         int i;
 204
 205         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 206                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 207                 if (alias.s.base == 0) {
 208                         *size = (1UL << alias.s.m_alias);
 209                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 210                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 211                         return;
 212                 }
 213         }
 214         BUG();
 215 }
 216
 217 static __init void map_low_mmrs(void)
 218 {
 219         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 220         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 221 }
 222
 223 enum map_type {map_wb, map_uc};
 224
 225 static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
 226 {
 227         unsigned long bytes, paddr;
 228
 229         paddr = base << shift;
 230         bytes = (1UL << shift);
 231         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 232                                                 paddr + bytes);
 233         if (map_type == map_uc)
 234                 init_extra_mapping_uc(paddr, bytes);
 235         else
 236                 init_extra_mapping_wb(paddr, bytes);
 237
 238 }
 239 static __init void map_gru_high(int max_pnode)
 240 {
 241         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 242         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 243
 244         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 245         if (gru.s.enable)
 246                 map_high("GRU", gru.s.base, shift, map_wb);
 247 }
 248
 249 static __init void map_config_high(int max_pnode)
 250 {
 251         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 252         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 253
 254         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 255         if (cfg.s.enable)
 256                 map_high("CONFIG", cfg.s.base, shift, map_uc);
 257 }
 258
 259 static __init void map_mmr_high(int max_pnode)
 260 {
 261         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 262         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 263
 264         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 265         if (mmr.s.enable)
 266                 map_high("MMR", mmr.s.base, shift, map_uc);
 267 }
 268
 269 static __init void map_mmioh_high(int max_pnode)
 270 {
 271         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 272         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 273
 274         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 275         if (mmioh.s.enable)
 276                 map_high("MMIOH", mmioh.s.base, shift, map_uc);
 277 }
 278
 279 static __init void uv_rtc_init(void)
 280 {
 281         long status, ticks_per_sec, drift;
 282
 283         status =
 284             x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
 285                                         &drift);
 286         if (status != 0 || ticks_per_sec < 100000) {
 287                 printk(KERN_WARNING
 288                         "unable to determine platform RTC clock frequency, "
 289                         "guessing.\n");
 290                 /* BIOS gives wrong value for clock freq. so guess */
 291                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 292         } else
 293                 sn_rtc_cycles_per_second = ticks_per_sec;
 294 }
 295
 296 static __init void uv_system_init(void)
 297 {
 298         union uvh_si_addr_map_config_u m_n_config;
 299         union uvh_node_id_u node_id;
 300         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 301         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 302         int max_pnode = 0;
 303         unsigned long mmr_base, present;
 304
 305         map_low_mmrs();
 306
 307         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 308         m_val = m_n_config.s.m_skt;
 309         n_val = m_n_config.s.n_skt;
 310         mmr_base =
 311             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 312             ~UV_MMR_ENABLE;
 313         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 314
 315         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 316                 uv_possible_blades +=
 317                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 318         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 319
 320         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 321         uv_blade_info = alloc_bootmem_pages(bytes);
 322
 323         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 324
 325         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 326         uv_node_to_blade = alloc_bootmem_pages(bytes);
 327         memset(uv_node_to_blade, 255, bytes);
 328
 329         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 330         uv_cpu_to_blade = alloc_bootmem_pages(bytes);
 331         memset(uv_cpu_to_blade, 255, bytes);
 332
 333         blade = 0;
 334         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 335                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 336                 for (j = 0; j < 64; j++) {
 337                         if (!test_bit(j, &present))
 338                                 continue;
 339                         uv_blade_info[blade].pnode = (i * 64 + j);
 340                         uv_blade_info[blade].nr_possible_cpus = 0;
 341                         uv_blade_info[blade].nr_online_cpus = 0;
 342                         blade++;
 343                 }
 344         }
 345
 346         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 347         gnode_upper = (((unsigned long)node_id.s.node_id) &
 348                        ~((1 << n_val) - 1)) << m_val;
 349
 350         uv_rtc_init();
 351
 352         for_each_present_cpu(cpu) {
 353                 nid = cpu_to_node(cpu);
 354                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 355                 blade = boot_pnode_to_blade(pnode);
 356                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 357                 uv_blade_info[blade].nr_possible_cpus++;
 358
 359                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 360                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
 361                                         lowmem_redir_base + lowmem_redir_size;
 362                 uv_cpu_hub_info(cpu)->m_val = m_val;
 363                 uv_cpu_hub_info(cpu)->n_val = m_val;
 364                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 365                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 366                 uv_cpu_hub_info(cpu)->pnode = pnode;
 367                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 368                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 369                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 370                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 371                 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
 372                 uv_node_to_blade[nid] = blade;
 373                 uv_cpu_to_blade[cpu] = blade;
 374                 max_pnode = max(pnode, max_pnode);
 375
 376                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 377                         "lcpu %d, blade %d\n",
 378                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 379                         lcpu, blade);
 380         }
 381
 382         map_gru_high(max_pnode);
 383         map_mmr_high(max_pnode);
 384         map_config_high(max_pnode);
 385         map_mmioh_high(max_pnode);
 386 }
 387
 388 /*
 389  * Called on each cpu to initialize the per_cpu UV data area.
 390  *      ZZZ hotplug not supported yet
 391  */
 392 void __cpuinit uv_cpu_init(void)
 393 {
 394         if (!uv_node_to_blade)
 395                 uv_system_init();
 396
 397         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 398
 399         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 400                 set_x2apic_extra_bits(uv_hub_info->pnode);
 401 }