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ARM: 5620/1: at91/dmaengine: integration of at_hdmac driver in at91sam9rl
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
blob1c2dced8748d281e317315597be9eb2b02968855
1 /*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
11
12 #include <linux/dma-mapping.h>
13 #include <linux/platform_device.h>
14 #include <linux/i2c-gpio.h>
15
16 #include <linux/fb.h>
17 #include <video/atmel_lcdc.h>
18
19 #include <mach/board.h>
20 #include <mach/gpio.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91sam9rl_matrix.h>
23 #include <mach/at91sam9_smc.h>
24 #include <mach/at_hdmac.h>
25
26 #include "generic.h"
27
28
29 /* --------------------------------------------------------------------
30 * HDMAC - AHB DMA Controller
31 * -------------------------------------------------------------------- */
32
33 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
34 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
35
36 static struct at_dma_platform_data atdma_pdata = {
37 .nr_channels = 2,
38 };
39
40 static struct resource hdmac_resources[] = {
41 [0] = {
42 .start = AT91_BASE_SYS + AT91_DMA,
43 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [2] = {
47 .start = AT91SAM9RL_ID_DMA,
48 .end = AT91SAM9RL_ID_DMA,
49 .flags = IORESOURCE_IRQ,
50 },
51 };
52
53 static struct platform_device at_hdmac_device = {
54 .name = "at_hdmac",
55 .id = -1,
56 .dev = {
57 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &atdma_pdata,
60 },
61 .resource = hdmac_resources,
62 .num_resources = ARRAY_SIZE(hdmac_resources),
63 };
64
65 void __init at91_add_device_hdmac(void)
66 {
67 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
68 platform_device_register(&at_hdmac_device);
69 }
70 #else
71 void __init at91_add_device_hdmac(void) {}
72 #endif
73
74 /* --------------------------------------------------------------------
75 * USB HS Device (Gadget)
76 * -------------------------------------------------------------------- */
77
78 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
79
80 static struct resource usba_udc_resources[] = {
81 [0] = {
82 .start = AT91SAM9RL_UDPHS_FIFO,
83 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
84 .flags = IORESOURCE_MEM,
85 },
86 [1] = {
87 .start = AT91SAM9RL_BASE_UDPHS,
88 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
89 .flags = IORESOURCE_MEM,
90 },
91 [2] = {
92 .start = AT91SAM9RL_ID_UDPHS,
93 .end = AT91SAM9RL_ID_UDPHS,
94 .flags = IORESOURCE_IRQ,
95 },
96 };
97
98 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
99 [idx] = { \
100 .name = nam, \
101 .index = idx, \
102 .fifo_size = maxpkt, \
103 .nr_banks = maxbk, \
104 .can_dma = dma, \
105 .can_isoc = isoc, \
106 }
107
108 static struct usba_ep_data usba_udc_ep[] __initdata = {
109 EP("ep0", 0, 64, 1, 0, 0),
110 EP("ep1", 1, 1024, 2, 1, 1),
111 EP("ep2", 2, 1024, 2, 1, 1),
112 EP("ep3", 3, 1024, 3, 1, 0),
113 EP("ep4", 4, 1024, 3, 1, 0),
114 EP("ep5", 5, 1024, 3, 1, 1),
115 EP("ep6", 6, 1024, 3, 1, 1),
116 };
117
118 #undef EP
119
120 /*
121 * pdata doesn't have room for any endpoints, so we need to
122 * append room for the ones we need right after it.
123 */
124 static struct {
125 struct usba_platform_data pdata;
126 struct usba_ep_data ep[7];
127 } usba_udc_data;
128
129 static struct platform_device at91_usba_udc_device = {
130 .name = "atmel_usba_udc",
131 .id = -1,
132 .dev = {
133 .platform_data = &usba_udc_data.pdata,
134 },
135 .resource = usba_udc_resources,
136 .num_resources = ARRAY_SIZE(usba_udc_resources),
137 };
138
139 void __init at91_add_device_usba(struct usba_platform_data *data)
140 {
141 /*
142 * Invalid pins are 0 on AT91, but the usba driver is shared
143 * with AVR32, which use negative values instead. Once/if
144 * gpio_is_valid() is ported to AT91, revisit this code.
145 */
146 usba_udc_data.pdata.vbus_pin = -EINVAL;
147 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
148 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
149
150 if (data && data->vbus_pin > 0) {
151 at91_set_gpio_input(data->vbus_pin, 0);
152 at91_set_deglitch(data->vbus_pin, 1);
153 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
154 }
155
156 /* Pullup pin is handled internally by USB device peripheral */
157
158 /* Clocks */
159 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
160 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
161
162 platform_device_register(&at91_usba_udc_device);
163 }
164 #else
165 void __init at91_add_device_usba(struct usba_platform_data *data) {}
166 #endif
167
168
169 /* --------------------------------------------------------------------
170 * MMC / SD
171 * -------------------------------------------------------------------- */
172
173 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
174 static u64 mmc_dmamask = DMA_BIT_MASK(32);
175 static struct at91_mmc_data mmc_data;
176
177 static struct resource mmc_resources[] = {
178 [0] = {
179 .start = AT91SAM9RL_BASE_MCI,
180 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = AT91SAM9RL_ID_MCI,
185 .end = AT91SAM9RL_ID_MCI,
186 .flags = IORESOURCE_IRQ,
187 },
188 };
189
190 static struct platform_device at91sam9rl_mmc_device = {
191 .name = "at91_mci",
192 .id = -1,
193 .dev = {
194 .dma_mask = &mmc_dmamask,
195 .coherent_dma_mask = DMA_BIT_MASK(32),
196 .platform_data = &mmc_data,
197 },
198 .resource = mmc_resources,
199 .num_resources = ARRAY_SIZE(mmc_resources),
200 };
201
202 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
203 {
204 if (!data)
205 return;
206
207 /* input/irq */
208 if (data->det_pin) {
209 at91_set_gpio_input(data->det_pin, 1);
210 at91_set_deglitch(data->det_pin, 1);
211 }
212 if (data->wp_pin)
213 at91_set_gpio_input(data->wp_pin, 1);
214 if (data->vcc_pin)
215 at91_set_gpio_output(data->vcc_pin, 0);
216
217 /* CLK */
218 at91_set_A_periph(AT91_PIN_PA2, 0);
219
220 /* CMD */
221 at91_set_A_periph(AT91_PIN_PA1, 1);
222
223 /* DAT0, maybe DAT1..DAT3 */
224 at91_set_A_periph(AT91_PIN_PA0, 1);
225 if (data->wire4) {
226 at91_set_A_periph(AT91_PIN_PA3, 1);
227 at91_set_A_periph(AT91_PIN_PA4, 1);
228 at91_set_A_periph(AT91_PIN_PA5, 1);
229 }
230
231 mmc_data = *data;
232 platform_device_register(&at91sam9rl_mmc_device);
233 }
234 #else
235 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
236 #endif
237
238
239 /* --------------------------------------------------------------------
240 * NAND / SmartMedia
241 * -------------------------------------------------------------------- */
242
243 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
244 static struct atmel_nand_data nand_data;
245
246 #define NAND_BASE AT91_CHIPSELECT_3
247
248 static struct resource nand_resources[] = {
249 [0] = {
250 .start = NAND_BASE,
251 .end = NAND_BASE + SZ_256M - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 [1] = {
255 .start = AT91_BASE_SYS + AT91_ECC,
256 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
257 .flags = IORESOURCE_MEM,
258 }
259 };
260
261 static struct platform_device atmel_nand_device = {
262 .name = "atmel_nand",
263 .id = -1,
264 .dev = {
265 .platform_data = &nand_data,
266 },
267 .resource = nand_resources,
268 .num_resources = ARRAY_SIZE(nand_resources),
269 };
270
271 void __init at91_add_device_nand(struct atmel_nand_data *data)
272 {
273 unsigned long csa;
274
275 if (!data)
276 return;
277
278 csa = at91_sys_read(AT91_MATRIX_EBICSA);
279 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
280
281 /* enable pin */
282 if (data->enable_pin)
283 at91_set_gpio_output(data->enable_pin, 1);
284
285 /* ready/busy pin */
286 if (data->rdy_pin)
287 at91_set_gpio_input(data->rdy_pin, 1);
288
289 /* card detect pin */
290 if (data->det_pin)
291 at91_set_gpio_input(data->det_pin, 1);
292
293 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
294 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
295
296 nand_data = *data;
297 platform_device_register(&atmel_nand_device);
298 }
299
300 #else
301 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
302 #endif
303
304
305 /* --------------------------------------------------------------------
306 * TWI (i2c)
307 * -------------------------------------------------------------------- */
308
309 /*
310 * Prefer the GPIO code since the TWI controller isn't robust
311 * (gets overruns and underruns under load) and can only issue
312 * repeated STARTs in one scenario (the driver doesn't yet handle them).
313 */
314 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
315
316 static struct i2c_gpio_platform_data pdata = {
317 .sda_pin = AT91_PIN_PA23,
318 .sda_is_open_drain = 1,
319 .scl_pin = AT91_PIN_PA24,
320 .scl_is_open_drain = 1,
321 .udelay = 2, /* ~100 kHz */
322 };
323
324 static struct platform_device at91sam9rl_twi_device = {
325 .name = "i2c-gpio",
326 .id = -1,
327 .dev.platform_data = &pdata,
328 };
329
330 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
331 {
332 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
333 at91_set_multi_drive(AT91_PIN_PA23, 1);
334
335 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
336 at91_set_multi_drive(AT91_PIN_PA24, 1);
337
338 i2c_register_board_info(0, devices, nr_devices);
339 platform_device_register(&at91sam9rl_twi_device);
340 }
341
342 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
343
344 static struct resource twi_resources[] = {
345 [0] = {
346 .start = AT91SAM9RL_BASE_TWI0,
347 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AT91SAM9RL_ID_TWI0,
352 .end = AT91SAM9RL_ID_TWI0,
353 .flags = IORESOURCE_IRQ,
354 },
355 };
356
357 static struct platform_device at91sam9rl_twi_device = {
358 .name = "at91_i2c",
359 .id = -1,
360 .resource = twi_resources,
361 .num_resources = ARRAY_SIZE(twi_resources),
362 };
363
364 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
365 {
366 /* pins used for TWI interface */
367 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
368 at91_set_multi_drive(AT91_PIN_PA23, 1);
369
370 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
371 at91_set_multi_drive(AT91_PIN_PA24, 1);
372
373 i2c_register_board_info(0, devices, nr_devices);
374 platform_device_register(&at91sam9rl_twi_device);
375 }
376 #else
377 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
378 #endif
379
380
381 /* --------------------------------------------------------------------
382 * SPI
383 * -------------------------------------------------------------------- */
384
385 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
386 static u64 spi_dmamask = DMA_BIT_MASK(32);
387
388 static struct resource spi_resources[] = {
389 [0] = {
390 .start = AT91SAM9RL_BASE_SPI,
391 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
392 .flags = IORESOURCE_MEM,
393 },
394 [1] = {
395 .start = AT91SAM9RL_ID_SPI,
396 .end = AT91SAM9RL_ID_SPI,
397 .flags = IORESOURCE_IRQ,
398 },
399 };
400
401 static struct platform_device at91sam9rl_spi_device = {
402 .name = "atmel_spi",
403 .id = 0,
404 .dev = {
405 .dma_mask = &spi_dmamask,
406 .coherent_dma_mask = DMA_BIT_MASK(32),
407 },
408 .resource = spi_resources,
409 .num_resources = ARRAY_SIZE(spi_resources),
410 };
411
412 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
413
414
415 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
416 {
417 int i;
418 unsigned long cs_pin;
419
420 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
421 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
422 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
423
424 /* Enable SPI chip-selects */
425 for (i = 0; i < nr_devices; i++) {
426 if (devices[i].controller_data)
427 cs_pin = (unsigned long) devices[i].controller_data;
428 else
429 cs_pin = spi_standard_cs[devices[i].chip_select];
430
431 /* enable chip-select pin */
432 at91_set_gpio_output(cs_pin, 1);
433
434 /* pass chip-select pin to driver */
435 devices[i].controller_data = (void *) cs_pin;
436 }
437
438 spi_register_board_info(devices, nr_devices);
439 platform_device_register(&at91sam9rl_spi_device);
440 }
441 #else
442 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
443 #endif
444
445
446 /* --------------------------------------------------------------------
447 * LCD Controller
448 * -------------------------------------------------------------------- */
449
450 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
451 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
452 static struct atmel_lcdfb_info lcdc_data;
453
454 static struct resource lcdc_resources[] = {
455 [0] = {
456 .start = AT91SAM9RL_LCDC_BASE,
457 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 .start = AT91SAM9RL_ID_LCDC,
462 .end = AT91SAM9RL_ID_LCDC,
463 .flags = IORESOURCE_IRQ,
464 },
465 };
466
467 static struct platform_device at91_lcdc_device = {
468 .name = "atmel_lcdfb",
469 .id = 0,
470 .dev = {
471 .dma_mask = &lcdc_dmamask,
472 .coherent_dma_mask = DMA_BIT_MASK(32),
473 .platform_data = &lcdc_data,
474 },
475 .resource = lcdc_resources,
476 .num_resources = ARRAY_SIZE(lcdc_resources),
477 };
478
479 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
480 {
481 if (!data) {
482 return;
483 }
484
485 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
486 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
487 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
488 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
489 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
490 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
491 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
492 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
493 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
494 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
495 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
496 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
497 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
498 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
499 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
500 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
501 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
502 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
503 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
504 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
505 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
506
507 lcdc_data = *data;
508 platform_device_register(&at91_lcdc_device);
509 }
510 #else
511 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
512 #endif
513
514
515 /* --------------------------------------------------------------------
516 * Timer/Counter block
517 * -------------------------------------------------------------------- */
518
519 #ifdef CONFIG_ATMEL_TCLIB
520
521 static struct resource tcb_resources[] = {
522 [0] = {
523 .start = AT91SAM9RL_BASE_TCB0,
524 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
525 .flags = IORESOURCE_MEM,
526 },
527 [1] = {
528 .start = AT91SAM9RL_ID_TC0,
529 .end = AT91SAM9RL_ID_TC0,
530 .flags = IORESOURCE_IRQ,
531 },
532 [2] = {
533 .start = AT91SAM9RL_ID_TC1,
534 .end = AT91SAM9RL_ID_TC1,
535 .flags = IORESOURCE_IRQ,
536 },
537 [3] = {
538 .start = AT91SAM9RL_ID_TC2,
539 .end = AT91SAM9RL_ID_TC2,
540 .flags = IORESOURCE_IRQ,
541 },
542 };
543
544 static struct platform_device at91sam9rl_tcb_device = {
545 .name = "atmel_tcb",
546 .id = 0,
547 .resource = tcb_resources,
548 .num_resources = ARRAY_SIZE(tcb_resources),
549 };
550
551 static void __init at91_add_device_tc(void)
552 {
553 /* this chip has a separate clock and irq for each TC channel */
554 at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
555 at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
556 at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
557 platform_device_register(&at91sam9rl_tcb_device);
558 }
559 #else
560 static void __init at91_add_device_tc(void) { }
561 #endif
562
563
564 /* --------------------------------------------------------------------
565 * Touchscreen
566 * -------------------------------------------------------------------- */
567
568 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
569 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
570
571 static struct resource tsadcc_resources[] = {
572 [0] = {
573 .start = AT91SAM9RL_BASE_TSC,
574 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
575 .flags = IORESOURCE_MEM,
576 },
577 [1] = {
578 .start = AT91SAM9RL_ID_TSC,
579 .end = AT91SAM9RL_ID_TSC,
580 .flags = IORESOURCE_IRQ,
581 }
582 };
583
584 static struct platform_device at91sam9rl_tsadcc_device = {
585 .name = "atmel_tsadcc",
586 .id = -1,
587 .dev = {
588 .dma_mask = &tsadcc_dmamask,
589 .coherent_dma_mask = DMA_BIT_MASK(32),
590 },
591 .resource = tsadcc_resources,
592 .num_resources = ARRAY_SIZE(tsadcc_resources),
593 };
594
595 void __init at91_add_device_tsadcc(void)
596 {
597 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
598 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
599 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
600 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
601
602 platform_device_register(&at91sam9rl_tsadcc_device);
603 }
604 #else
605 void __init at91_add_device_tsadcc(void) {}
606 #endif
607
608
609 /* --------------------------------------------------------------------
610 * RTC
611 * -------------------------------------------------------------------- */
612
613 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
614 static struct platform_device at91sam9rl_rtc_device = {
615 .name = "at91_rtc",
616 .id = -1,
617 .num_resources = 0,
618 };
619
620 static void __init at91_add_device_rtc(void)
621 {
622 platform_device_register(&at91sam9rl_rtc_device);
623 }
624 #else
625 static void __init at91_add_device_rtc(void) {}
626 #endif
627
628
629 /* --------------------------------------------------------------------
630 * RTT
631 * -------------------------------------------------------------------- */
632
633 static struct resource rtt_resources[] = {
634 {
635 .start = AT91_BASE_SYS + AT91_RTT,
636 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
637 .flags = IORESOURCE_MEM,
638 }
639 };
640
641 static struct platform_device at91sam9rl_rtt_device = {
642 .name = "at91_rtt",
643 .id = 0,
644 .resource = rtt_resources,
645 .num_resources = ARRAY_SIZE(rtt_resources),
646 };
647
648 static void __init at91_add_device_rtt(void)
649 {
650 platform_device_register(&at91sam9rl_rtt_device);
651 }
652
653
654 /* --------------------------------------------------------------------
655 * Watchdog
656 * -------------------------------------------------------------------- */
657
658 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
659 static struct platform_device at91sam9rl_wdt_device = {
660 .name = "at91_wdt",
661 .id = -1,
662 .num_resources = 0,
663 };
664
665 static void __init at91_add_device_watchdog(void)
666 {
667 platform_device_register(&at91sam9rl_wdt_device);
668 }
669 #else
670 static void __init at91_add_device_watchdog(void) {}
671 #endif
672
673
674 /* --------------------------------------------------------------------
675 * PWM
676 * --------------------------------------------------------------------*/
677
678 #if defined(CONFIG_ATMEL_PWM)
679 static u32 pwm_mask;
680
681 static struct resource pwm_resources[] = {
682 [0] = {
683 .start = AT91SAM9RL_BASE_PWMC,
684 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
685 .flags = IORESOURCE_MEM,
686 },
687 [1] = {
688 .start = AT91SAM9RL_ID_PWMC,
689 .end = AT91SAM9RL_ID_PWMC,
690 .flags = IORESOURCE_IRQ,
691 },
692 };
693
694 static struct platform_device at91sam9rl_pwm0_device = {
695 .name = "atmel_pwm",
696 .id = -1,
697 .dev = {
698 .platform_data = &pwm_mask,
699 },
700 .resource = pwm_resources,
701 .num_resources = ARRAY_SIZE(pwm_resources),
702 };
703
704 void __init at91_add_device_pwm(u32 mask)
705 {
706 if (mask & (1 << AT91_PWM0))
707 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
708
709 if (mask & (1 << AT91_PWM1))
710 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
711
712 if (mask & (1 << AT91_PWM2))
713 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
714
715 if (mask & (1 << AT91_PWM3))
716 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
717
718 pwm_mask = mask;
719
720 platform_device_register(&at91sam9rl_pwm0_device);
721 }
722 #else
723 void __init at91_add_device_pwm(u32 mask) {}
724 #endif
725
726
727 /* --------------------------------------------------------------------
728 * SSC -- Synchronous Serial Controller
729 * -------------------------------------------------------------------- */
730
731 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
732 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
733
734 static struct resource ssc0_resources[] = {
735 [0] = {
736 .start = AT91SAM9RL_BASE_SSC0,
737 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
738 .flags = IORESOURCE_MEM,
739 },
740 [1] = {
741 .start = AT91SAM9RL_ID_SSC0,
742 .end = AT91SAM9RL_ID_SSC0,
743 .flags = IORESOURCE_IRQ,
744 },
745 };
746
747 static struct platform_device at91sam9rl_ssc0_device = {
748 .name = "ssc",
749 .id = 0,
750 .dev = {
751 .dma_mask = &ssc0_dmamask,
752 .coherent_dma_mask = DMA_BIT_MASK(32),
753 },
754 .resource = ssc0_resources,
755 .num_resources = ARRAY_SIZE(ssc0_resources),
756 };
757
758 static inline void configure_ssc0_pins(unsigned pins)
759 {
760 if (pins & ATMEL_SSC_TF)
761 at91_set_A_periph(AT91_PIN_PC0, 1);
762 if (pins & ATMEL_SSC_TK)
763 at91_set_A_periph(AT91_PIN_PC1, 1);
764 if (pins & ATMEL_SSC_TD)
765 at91_set_A_periph(AT91_PIN_PA15, 1);
766 if (pins & ATMEL_SSC_RD)
767 at91_set_A_periph(AT91_PIN_PA16, 1);
768 if (pins & ATMEL_SSC_RK)
769 at91_set_B_periph(AT91_PIN_PA10, 1);
770 if (pins & ATMEL_SSC_RF)
771 at91_set_B_periph(AT91_PIN_PA22, 1);
772 }
773
774 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
775
776 static struct resource ssc1_resources[] = {
777 [0] = {
778 .start = AT91SAM9RL_BASE_SSC1,
779 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
780 .flags = IORESOURCE_MEM,
781 },
782 [1] = {
783 .start = AT91SAM9RL_ID_SSC1,
784 .end = AT91SAM9RL_ID_SSC1,
785 .flags = IORESOURCE_IRQ,
786 },
787 };
788
789 static struct platform_device at91sam9rl_ssc1_device = {
790 .name = "ssc",
791 .id = 1,
792 .dev = {
793 .dma_mask = &ssc1_dmamask,
794 .coherent_dma_mask = DMA_BIT_MASK(32),
795 },
796 .resource = ssc1_resources,
797 .num_resources = ARRAY_SIZE(ssc1_resources),
798 };
799
800 static inline void configure_ssc1_pins(unsigned pins)
801 {
802 if (pins & ATMEL_SSC_TF)
803 at91_set_B_periph(AT91_PIN_PA29, 1);
804 if (pins & ATMEL_SSC_TK)
805 at91_set_B_periph(AT91_PIN_PA30, 1);
806 if (pins & ATMEL_SSC_TD)
807 at91_set_B_periph(AT91_PIN_PA13, 1);
808 if (pins & ATMEL_SSC_RD)
809 at91_set_B_periph(AT91_PIN_PA14, 1);
810 if (pins & ATMEL_SSC_RK)
811 at91_set_B_periph(AT91_PIN_PA9, 1);
812 if (pins & ATMEL_SSC_RF)
813 at91_set_B_periph(AT91_PIN_PA8, 1);
814 }
815
816 /*
817 * SSC controllers are accessed through library code, instead of any
818 * kind of all-singing/all-dancing driver. For example one could be
819 * used by a particular I2S audio codec's driver, while another one
820 * on the same system might be used by a custom data capture driver.
821 */
822 void __init at91_add_device_ssc(unsigned id, unsigned pins)
823 {
824 struct platform_device *pdev;
825
826 /*
827 * NOTE: caller is responsible for passing information matching
828 * "pins" to whatever will be using each particular controller.
829 */
830 switch (id) {
831 case AT91SAM9RL_ID_SSC0:
832 pdev = &at91sam9rl_ssc0_device;
833 configure_ssc0_pins(pins);
834 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
835 break;
836 case AT91SAM9RL_ID_SSC1:
837 pdev = &at91sam9rl_ssc1_device;
838 configure_ssc1_pins(pins);
839 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
840 break;
841 default:
842 return;
843 }
844
845 platform_device_register(pdev);
846 }
847
848 #else
849 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
850 #endif
851
852
853 /* --------------------------------------------------------------------
854 * UART
855 * -------------------------------------------------------------------- */
856
857 #if defined(CONFIG_SERIAL_ATMEL)
858 static struct resource dbgu_resources[] = {
859 [0] = {
860 .start = AT91_VA_BASE_SYS + AT91_DBGU,
861 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
862 .flags = IORESOURCE_MEM,
863 },
864 [1] = {
865 .start = AT91_ID_SYS,
866 .end = AT91_ID_SYS,
867 .flags = IORESOURCE_IRQ,
868 },
869 };
870
871 static struct atmel_uart_data dbgu_data = {
872 .use_dma_tx = 0,
873 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
874 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
875 };
876
877 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
878
879 static struct platform_device at91sam9rl_dbgu_device = {
880 .name = "atmel_usart",
881 .id = 0,
882 .dev = {
883 .dma_mask = &dbgu_dmamask,
884 .coherent_dma_mask = DMA_BIT_MASK(32),
885 .platform_data = &dbgu_data,
886 },
887 .resource = dbgu_resources,
888 .num_resources = ARRAY_SIZE(dbgu_resources),
889 };
890
891 static inline void configure_dbgu_pins(void)
892 {
893 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
894 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
895 }
896
897 static struct resource uart0_resources[] = {
898 [0] = {
899 .start = AT91SAM9RL_BASE_US0,
900 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
901 .flags = IORESOURCE_MEM,
902 },
903 [1] = {
904 .start = AT91SAM9RL_ID_US0,
905 .end = AT91SAM9RL_ID_US0,
906 .flags = IORESOURCE_IRQ,
907 },
908 };
909
910 static struct atmel_uart_data uart0_data = {
911 .use_dma_tx = 1,
912 .use_dma_rx = 1,
913 };
914
915 static u64 uart0_dmamask = DMA_BIT_MASK(32);
916
917 static struct platform_device at91sam9rl_uart0_device = {
918 .name = "atmel_usart",
919 .id = 1,
920 .dev = {
921 .dma_mask = &uart0_dmamask,
922 .coherent_dma_mask = DMA_BIT_MASK(32),
923 .platform_data = &uart0_data,
924 },
925 .resource = uart0_resources,
926 .num_resources = ARRAY_SIZE(uart0_resources),
927 };
928
929 static inline void configure_usart0_pins(unsigned pins)
930 {
931 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
932 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
933
934 if (pins & ATMEL_UART_RTS)
935 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
936 if (pins & ATMEL_UART_CTS)
937 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
938 if (pins & ATMEL_UART_DSR)
939 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
940 if (pins & ATMEL_UART_DTR)
941 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
942 if (pins & ATMEL_UART_DCD)
943 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
944 if (pins & ATMEL_UART_RI)
945 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
946 }
947
948 static struct resource uart1_resources[] = {
949 [0] = {
950 .start = AT91SAM9RL_BASE_US1,
951 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
952 .flags = IORESOURCE_MEM,
953 },
954 [1] = {
955 .start = AT91SAM9RL_ID_US1,
956 .end = AT91SAM9RL_ID_US1,
957 .flags = IORESOURCE_IRQ,
958 },
959 };
960
961 static struct atmel_uart_data uart1_data = {
962 .use_dma_tx = 1,
963 .use_dma_rx = 1,
964 };
965
966 static u64 uart1_dmamask = DMA_BIT_MASK(32);
967
968 static struct platform_device at91sam9rl_uart1_device = {
969 .name = "atmel_usart",
970 .id = 2,
971 .dev = {
972 .dma_mask = &uart1_dmamask,
973 .coherent_dma_mask = DMA_BIT_MASK(32),
974 .platform_data = &uart1_data,
975 },
976 .resource = uart1_resources,
977 .num_resources = ARRAY_SIZE(uart1_resources),
978 };
979
980 static inline void configure_usart1_pins(unsigned pins)
981 {
982 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
983 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
984
985 if (pins & ATMEL_UART_RTS)
986 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
987 if (pins & ATMEL_UART_CTS)
988 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
989 }
990
991 static struct resource uart2_resources[] = {
992 [0] = {
993 .start = AT91SAM9RL_BASE_US2,
994 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
995 .flags = IORESOURCE_MEM,
996 },
997 [1] = {
998 .start = AT91SAM9RL_ID_US2,
999 .end = AT91SAM9RL_ID_US2,
1000 .flags = IORESOURCE_IRQ,
1001 },
1002 };
1003
1004 static struct atmel_uart_data uart2_data = {
1005 .use_dma_tx = 1,
1006 .use_dma_rx = 1,
1007 };
1008
1009 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1010
1011 static struct platform_device at91sam9rl_uart2_device = {
1012 .name = "atmel_usart",
1013 .id = 3,
1014 .dev = {
1015 .dma_mask = &uart2_dmamask,
1016 .coherent_dma_mask = DMA_BIT_MASK(32),
1017 .platform_data = &uart2_data,
1018 },
1019 .resource = uart2_resources,
1020 .num_resources = ARRAY_SIZE(uart2_resources),
1021 };
1022
1023 static inline void configure_usart2_pins(unsigned pins)
1024 {
1025 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1026 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
1027
1028 if (pins & ATMEL_UART_RTS)
1029 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1030 if (pins & ATMEL_UART_CTS)
1031 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
1032 }
1033
1034 static struct resource uart3_resources[] = {
1035 [0] = {
1036 .start = AT91SAM9RL_BASE_US3,
1037 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1038 .flags = IORESOURCE_MEM,
1039 },
1040 [1] = {
1041 .start = AT91SAM9RL_ID_US3,
1042 .end = AT91SAM9RL_ID_US3,
1043 .flags = IORESOURCE_IRQ,
1044 },
1045 };
1046
1047 static struct atmel_uart_data uart3_data = {
1048 .use_dma_tx = 1,
1049 .use_dma_rx = 1,
1050 };
1051
1052 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1053
1054 static struct platform_device at91sam9rl_uart3_device = {
1055 .name = "atmel_usart",
1056 .id = 4,
1057 .dev = {
1058 .dma_mask = &uart3_dmamask,
1059 .coherent_dma_mask = DMA_BIT_MASK(32),
1060 .platform_data = &uart3_data,
1061 },
1062 .resource = uart3_resources,
1063 .num_resources = ARRAY_SIZE(uart3_resources),
1064 };
1065
1066 static inline void configure_usart3_pins(unsigned pins)
1067 {
1068 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1069 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
1070
1071 if (pins & ATMEL_UART_RTS)
1072 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1073 if (pins & ATMEL_UART_CTS)
1074 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1075 }
1076
1077 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1078 struct platform_device *atmel_default_console_device; /* the serial console device */
1079
1080 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1081 {
1082 struct platform_device *pdev;
1083
1084 switch (id) {
1085 case 0: /* DBGU */
1086 pdev = &at91sam9rl_dbgu_device;
1087 configure_dbgu_pins();
1088 at91_clock_associate("mck", &pdev->dev, "usart");
1089 break;
1090 case AT91SAM9RL_ID_US0:
1091 pdev = &at91sam9rl_uart0_device;
1092 configure_usart0_pins(pins);
1093 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1094 break;
1095 case AT91SAM9RL_ID_US1:
1096 pdev = &at91sam9rl_uart1_device;
1097 configure_usart1_pins(pins);
1098 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1099 break;
1100 case AT91SAM9RL_ID_US2:
1101 pdev = &at91sam9rl_uart2_device;
1102 configure_usart2_pins(pins);
1103 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1104 break;
1105 case AT91SAM9RL_ID_US3:
1106 pdev = &at91sam9rl_uart3_device;
1107 configure_usart3_pins(pins);
1108 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1109 break;
1110 default:
1111 return;
1112 }
1113 pdev->id = portnr; /* update to mapped ID */
1114
1115 if (portnr < ATMEL_MAX_UART)
1116 at91_uarts[portnr] = pdev;
1117 }
1118
1119 void __init at91_set_serial_console(unsigned portnr)
1120 {
1121 if (portnr < ATMEL_MAX_UART)
1122 atmel_default_console_device = at91_uarts[portnr];
1123 }
1124
1125 void __init at91_add_device_serial(void)
1126 {
1127 int i;
1128
1129 for (i = 0; i < ATMEL_MAX_UART; i++) {
1130 if (at91_uarts[i])
1131 platform_device_register(at91_uarts[i]);
1132 }
1133
1134 if (!atmel_default_console_device)
1135 printk(KERN_INFO "AT91: No default serial console defined.\n");
1136 }
1137 #else
1138 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1139 void __init at91_set_serial_console(unsigned portnr) {}
1140 void __init at91_add_device_serial(void) {}
1141 #endif
1142
1143
1144 /* -------------------------------------------------------------------- */
1145
1146 /*
1147 * These devices are always present and don't need any board-specific
1148 * setup.
1149 */
1150 static int __init at91_add_standard_devices(void)
1151 {
1152 at91_add_device_hdmac();
1153 at91_add_device_rtc();
1154 at91_add_device_rtt();
1155 at91_add_device_watchdog();
1156 at91_add_device_tc();
1157 return 0;
1158 }
1159
1160 arch_initcall(at91_add_standard_devices);
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