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spi/bfin_spi: init early
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / spi / spi_bfin5xx.c
blobd17ab37d3f6442e94372ec65e084f9f0c0c792b8
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
25
26 #include <asm/dma.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
30
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
35
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
39
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
44
45 struct master_data;
46
47 struct transfer_ops {
48 void (*write) (struct master_data *);
49 void (*read) (struct master_data *);
50 void (*duplex) (struct master_data *);
51 };
52
53 struct master_data {
54 /* Driver model hookup */
55 struct platform_device *pdev;
56
57 /* SPI framework hookup */
58 struct spi_master *master;
59
60 /* Regs base of SPI controller */
61 void __iomem *regs_base;
62
63 /* Pin request list */
64 u16 *pin_req;
65
66 /* BFIN hookup */
67 struct bfin5xx_spi_master *master_info;
68
69 /* Driver message queue */
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
72 spinlock_t lock;
73 struct list_head queue;
74 int busy;
75 bool running;
76
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers;
79
80 /* Current message transfer state info */
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
83 struct slave_data *cur_chip;
84 size_t len_in_bytes;
85 size_t len;
86 void *tx;
87 void *tx_end;
88 void *rx;
89 void *rx_end;
90
91 /* DMA stuffs */
92 int dma_channel;
93 int dma_mapped;
94 int dma_requested;
95 dma_addr_t rx_dma;
96 dma_addr_t tx_dma;
97
98 int irq_requested;
99 int spi_irq;
100
101 size_t rx_map_len;
102 size_t tx_map_len;
103 u8 n_bytes;
104 u16 ctrl_reg;
105 u16 flag_reg;
106
107 int cs_change;
108 const struct transfer_ops *ops;
109 };
110
111 struct slave_data {
112 u16 ctl_reg;
113 u16 baud;
114 u16 flag;
115
116 u8 chip_select_num;
117 u8 enable_dma;
118 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
119 u32 cs_gpio;
120 u16 idle_tx_val;
121 u8 pio_interrupt; /* use spi data irq */
122 const struct transfer_ops *ops;
123 };
124
125 #define DEFINE_SPI_REG(reg, off) \
126 static inline u16 read_##reg(struct master_data *drv_data) \
127 { return bfin_read16(drv_data->regs_base + off); } \
128 static inline void write_##reg(struct master_data *drv_data, u16 v) \
129 { bfin_write16(drv_data->regs_base + off, v); }
130
131 DEFINE_SPI_REG(CTRL, 0x00)
132 DEFINE_SPI_REG(FLAG, 0x04)
133 DEFINE_SPI_REG(STAT, 0x08)
134 DEFINE_SPI_REG(TDBR, 0x0C)
135 DEFINE_SPI_REG(RDBR, 0x10)
136 DEFINE_SPI_REG(BAUD, 0x14)
137 DEFINE_SPI_REG(SHAW, 0x18)
138
139 static void bfin_spi_enable(struct master_data *drv_data)
140 {
141 u16 cr;
142
143 cr = read_CTRL(drv_data);
144 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
145 }
146
147 static void bfin_spi_disable(struct master_data *drv_data)
148 {
149 u16 cr;
150
151 cr = read_CTRL(drv_data);
152 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
153 }
154
155 /* Caculate the SPI_BAUD register value based on input HZ */
156 static u16 hz_to_spi_baud(u32 speed_hz)
157 {
158 u_long sclk = get_sclk();
159 u16 spi_baud = (sclk / (2 * speed_hz));
160
161 if ((sclk % (2 * speed_hz)) > 0)
162 spi_baud++;
163
164 if (spi_baud < MIN_SPI_BAUD_VAL)
165 spi_baud = MIN_SPI_BAUD_VAL;
166
167 return spi_baud;
168 }
169
170 static int bfin_spi_flush(struct master_data *drv_data)
171 {
172 unsigned long limit = loops_per_jiffy << 1;
173
174 /* wait for stop and clear stat */
175 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
176 cpu_relax();
177
178 write_STAT(drv_data, BIT_STAT_CLR);
179
180 return limit;
181 }
182
183 /* Chip select operation functions for cs_change flag */
184 static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip)
185 {
186 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
187 u16 flag = read_FLAG(drv_data);
188
189 flag &= ~chip->flag;
190
191 write_FLAG(drv_data, flag);
192 } else {
193 gpio_set_value(chip->cs_gpio, 0);
194 }
195 }
196
197 static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip)
198 {
199 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
200 u16 flag = read_FLAG(drv_data);
201
202 flag |= chip->flag;
203
204 write_FLAG(drv_data, flag);
205 } else {
206 gpio_set_value(chip->cs_gpio, 1);
207 }
208
209 /* Move delay here for consistency */
210 if (chip->cs_chg_udelay)
211 udelay(chip->cs_chg_udelay);
212 }
213
214 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
215 static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip)
216 {
217 if (chip->chip_select_num < MAX_CTRL_CS) {
218 u16 flag = read_FLAG(drv_data);
219
220 flag |= (chip->flag >> 8);
221
222 write_FLAG(drv_data, flag);
223 }
224 }
225
226 static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip)
227 {
228 if (chip->chip_select_num < MAX_CTRL_CS) {
229 u16 flag = read_FLAG(drv_data);
230
231 flag &= ~(chip->flag >> 8);
232
233 write_FLAG(drv_data, flag);
234 }
235 }
236
237 /* stop controller and re-config current chip*/
238 static void bfin_spi_restore_state(struct master_data *drv_data)
239 {
240 struct slave_data *chip = drv_data->cur_chip;
241
242 /* Clear status and disable clock */
243 write_STAT(drv_data, BIT_STAT_CLR);
244 bfin_spi_disable(drv_data);
245 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
246
247 SSYNC();
248
249 /* Load the registers */
250 write_CTRL(drv_data, chip->ctl_reg);
251 write_BAUD(drv_data, chip->baud);
252
253 bfin_spi_enable(drv_data);
254 bfin_spi_cs_active(drv_data, chip);
255 }
256
257 /* used to kick off transfer in rx mode and read unwanted RX data */
258 static inline void bfin_spi_dummy_read(struct master_data *drv_data)
259 {
260 (void) read_RDBR(drv_data);
261 }
262
263 static void bfin_spi_u8_writer(struct master_data *drv_data)
264 {
265 /* clear RXS (we check for RXS inside the loop) */
266 bfin_spi_dummy_read(drv_data);
267
268 while (drv_data->tx < drv_data->tx_end) {
269 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
270 /* wait until transfer finished.
271 checking SPIF or TXS may not guarantee transfer completion */
272 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
273 cpu_relax();
274 /* discard RX data and clear RXS */
275 bfin_spi_dummy_read(drv_data);
276 }
277 }
278
279 static void bfin_spi_u8_reader(struct master_data *drv_data)
280 {
281 u16 tx_val = drv_data->cur_chip->idle_tx_val;
282
283 /* discard old RX data and clear RXS */
284 bfin_spi_dummy_read(drv_data);
285
286 while (drv_data->rx < drv_data->rx_end) {
287 write_TDBR(drv_data, tx_val);
288 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
289 cpu_relax();
290 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
291 }
292 }
293
294 static void bfin_spi_u8_duplex(struct master_data *drv_data)
295 {
296 /* discard old RX data and clear RXS */
297 bfin_spi_dummy_read(drv_data);
298
299 while (drv_data->rx < drv_data->rx_end) {
300 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
301 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
302 cpu_relax();
303 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
304 }
305 }
306
307 static const struct transfer_ops bfin_transfer_ops_u8 = {
308 .write = bfin_spi_u8_writer,
309 .read = bfin_spi_u8_reader,
310 .duplex = bfin_spi_u8_duplex,
311 };
312
313 static void bfin_spi_u16_writer(struct master_data *drv_data)
314 {
315 /* clear RXS (we check for RXS inside the loop) */
316 bfin_spi_dummy_read(drv_data);
317
318 while (drv_data->tx < drv_data->tx_end) {
319 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
320 drv_data->tx += 2;
321 /* wait until transfer finished.
322 checking SPIF or TXS may not guarantee transfer completion */
323 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
324 cpu_relax();
325 /* discard RX data and clear RXS */
326 bfin_spi_dummy_read(drv_data);
327 }
328 }
329
330 static void bfin_spi_u16_reader(struct master_data *drv_data)
331 {
332 u16 tx_val = drv_data->cur_chip->idle_tx_val;
333
334 /* discard old RX data and clear RXS */
335 bfin_spi_dummy_read(drv_data);
336
337 while (drv_data->rx < drv_data->rx_end) {
338 write_TDBR(drv_data, tx_val);
339 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
340 cpu_relax();
341 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
342 drv_data->rx += 2;
343 }
344 }
345
346 static void bfin_spi_u16_duplex(struct master_data *drv_data)
347 {
348 /* discard old RX data and clear RXS */
349 bfin_spi_dummy_read(drv_data);
350
351 while (drv_data->rx < drv_data->rx_end) {
352 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
353 drv_data->tx += 2;
354 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
355 cpu_relax();
356 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
357 drv_data->rx += 2;
358 }
359 }
360
361 static const struct transfer_ops bfin_transfer_ops_u16 = {
362 .write = bfin_spi_u16_writer,
363 .read = bfin_spi_u16_reader,
364 .duplex = bfin_spi_u16_duplex,
365 };
366
367 /* test if there is more transfer to be done */
368 static void *bfin_spi_next_transfer(struct master_data *drv_data)
369 {
370 struct spi_message *msg = drv_data->cur_msg;
371 struct spi_transfer *trans = drv_data->cur_transfer;
372
373 /* Move to next transfer */
374 if (trans->transfer_list.next != &msg->transfers) {
375 drv_data->cur_transfer =
376 list_entry(trans->transfer_list.next,
377 struct spi_transfer, transfer_list);
378 return RUNNING_STATE;
379 } else
380 return DONE_STATE;
381 }
382
383 /*
384 * caller already set message->status;
385 * dma and pio irqs are blocked give finished message back
386 */
387 static void bfin_spi_giveback(struct master_data *drv_data)
388 {
389 struct slave_data *chip = drv_data->cur_chip;
390 struct spi_transfer *last_transfer;
391 unsigned long flags;
392 struct spi_message *msg;
393
394 spin_lock_irqsave(&drv_data->lock, flags);
395 msg = drv_data->cur_msg;
396 drv_data->cur_msg = NULL;
397 drv_data->cur_transfer = NULL;
398 drv_data->cur_chip = NULL;
399 queue_work(drv_data->workqueue, &drv_data->pump_messages);
400 spin_unlock_irqrestore(&drv_data->lock, flags);
401
402 last_transfer = list_entry(msg->transfers.prev,
403 struct spi_transfer, transfer_list);
404
405 msg->state = NULL;
406
407 if (!drv_data->cs_change)
408 bfin_spi_cs_deactive(drv_data, chip);
409
410 /* Not stop spi in autobuffer mode */
411 if (drv_data->tx_dma != 0xFFFF)
412 bfin_spi_disable(drv_data);
413
414 if (msg->complete)
415 msg->complete(msg->context);
416 }
417
418 /* spi data irq handler */
419 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
420 {
421 struct master_data *drv_data = dev_id;
422 struct slave_data *chip = drv_data->cur_chip;
423 struct spi_message *msg = drv_data->cur_msg;
424 int n_bytes = drv_data->n_bytes;
425
426 /* wait until transfer finished. */
427 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
428 cpu_relax();
429
430 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
431 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
432 /* last read */
433 if (drv_data->rx) {
434 dev_dbg(&drv_data->pdev->dev, "last read\n");
435 if (n_bytes == 2)
436 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
437 else if (n_bytes == 1)
438 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
439 drv_data->rx += n_bytes;
440 }
441
442 msg->actual_length += drv_data->len_in_bytes;
443 if (drv_data->cs_change)
444 bfin_spi_cs_deactive(drv_data, chip);
445 /* Move to next transfer */
446 msg->state = bfin_spi_next_transfer(drv_data);
447
448 disable_irq_nosync(drv_data->spi_irq);
449
450 /* Schedule transfer tasklet */
451 tasklet_schedule(&drv_data->pump_transfers);
452 return IRQ_HANDLED;
453 }
454
455 if (drv_data->rx && drv_data->tx) {
456 /* duplex */
457 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
458 if (drv_data->n_bytes == 2) {
459 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
460 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
461 } else if (drv_data->n_bytes == 1) {
462 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
463 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
464 }
465 } else if (drv_data->rx) {
466 /* read */
467 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
468 if (drv_data->n_bytes == 2)
469 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
470 else if (drv_data->n_bytes == 1)
471 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
472 write_TDBR(drv_data, chip->idle_tx_val);
473 } else if (drv_data->tx) {
474 /* write */
475 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
476 bfin_spi_dummy_read(drv_data);
477 if (drv_data->n_bytes == 2)
478 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
479 else if (drv_data->n_bytes == 1)
480 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
481 }
482
483 if (drv_data->tx)
484 drv_data->tx += n_bytes;
485 if (drv_data->rx)
486 drv_data->rx += n_bytes;
487
488 return IRQ_HANDLED;
489 }
490
491 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
492 {
493 struct master_data *drv_data = dev_id;
494 struct slave_data *chip = drv_data->cur_chip;
495 struct spi_message *msg = drv_data->cur_msg;
496 unsigned long timeout;
497 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
498 u16 spistat = read_STAT(drv_data);
499
500 dev_dbg(&drv_data->pdev->dev,
501 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
502 dmastat, spistat);
503
504 clear_dma_irqstat(drv_data->dma_channel);
505
506 /*
507 * wait for the last transaction shifted out. HRM states:
508 * at this point there may still be data in the SPI DMA FIFO waiting
509 * to be transmitted ... software needs to poll TXS in the SPI_STAT
510 * register until it goes low for 2 successive reads
511 */
512 if (drv_data->tx != NULL) {
513 while ((read_STAT(drv_data) & BIT_STAT_TXS) ||
514 (read_STAT(drv_data) & BIT_STAT_TXS))
515 cpu_relax();
516 }
517
518 dev_dbg(&drv_data->pdev->dev,
519 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
520 dmastat, read_STAT(drv_data));
521
522 timeout = jiffies + HZ;
523 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
524 if (!time_before(jiffies, timeout)) {
525 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
526 break;
527 } else
528 cpu_relax();
529
530 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
531 msg->state = ERROR_STATE;
532 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
533 } else {
534 msg->actual_length += drv_data->len_in_bytes;
535
536 if (drv_data->cs_change)
537 bfin_spi_cs_deactive(drv_data, chip);
538
539 /* Move to next transfer */
540 msg->state = bfin_spi_next_transfer(drv_data);
541 }
542
543 /* Schedule transfer tasklet */
544 tasklet_schedule(&drv_data->pump_transfers);
545
546 /* free the irq handler before next transfer */
547 dev_dbg(&drv_data->pdev->dev,
548 "disable dma channel irq%d\n",
549 drv_data->dma_channel);
550 dma_disable_irq_nosync(drv_data->dma_channel);
551
552 return IRQ_HANDLED;
553 }
554
555 static void bfin_spi_pump_transfers(unsigned long data)
556 {
557 struct master_data *drv_data = (struct master_data *)data;
558 struct spi_message *message = NULL;
559 struct spi_transfer *transfer = NULL;
560 struct spi_transfer *previous = NULL;
561 struct slave_data *chip = NULL;
562 unsigned int bits_per_word;
563 u16 cr, cr_width, dma_width, dma_config;
564 u32 tranf_success = 1;
565 u8 full_duplex = 0;
566
567 /* Get current state information */
568 message = drv_data->cur_msg;
569 transfer = drv_data->cur_transfer;
570 chip = drv_data->cur_chip;
571
572 /*
573 * if msg is error or done, report it back using complete() callback
574 */
575
576 /* Handle for abort */
577 if (message->state == ERROR_STATE) {
578 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
579 message->status = -EIO;
580 bfin_spi_giveback(drv_data);
581 return;
582 }
583
584 /* Handle end of message */
585 if (message->state == DONE_STATE) {
586 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
587 message->status = 0;
588 bfin_spi_giveback(drv_data);
589 return;
590 }
591
592 /* Delay if requested at end of transfer */
593 if (message->state == RUNNING_STATE) {
594 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
595 previous = list_entry(transfer->transfer_list.prev,
596 struct spi_transfer, transfer_list);
597 if (previous->delay_usecs)
598 udelay(previous->delay_usecs);
599 }
600
601 /* Flush any existing transfers that may be sitting in the hardware */
602 if (bfin_spi_flush(drv_data) == 0) {
603 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
604 message->status = -EIO;
605 bfin_spi_giveback(drv_data);
606 return;
607 }
608
609 if (transfer->len == 0) {
610 /* Move to next transfer of this msg */
611 message->state = bfin_spi_next_transfer(drv_data);
612 /* Schedule next transfer tasklet */
613 tasklet_schedule(&drv_data->pump_transfers);
614 }
615
616 if (transfer->tx_buf != NULL) {
617 drv_data->tx = (void *)transfer->tx_buf;
618 drv_data->tx_end = drv_data->tx + transfer->len;
619 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
620 transfer->tx_buf, drv_data->tx_end);
621 } else {
622 drv_data->tx = NULL;
623 }
624
625 if (transfer->rx_buf != NULL) {
626 full_duplex = transfer->tx_buf != NULL;
627 drv_data->rx = transfer->rx_buf;
628 drv_data->rx_end = drv_data->rx + transfer->len;
629 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
630 transfer->rx_buf, drv_data->rx_end);
631 } else {
632 drv_data->rx = NULL;
633 }
634
635 drv_data->rx_dma = transfer->rx_dma;
636 drv_data->tx_dma = transfer->tx_dma;
637 drv_data->len_in_bytes = transfer->len;
638 drv_data->cs_change = transfer->cs_change;
639
640 /* Bits per word setup */
641 bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word;
642 if (bits_per_word == 8) {
643 drv_data->n_bytes = 1;
644 drv_data->len = transfer->len;
645 cr_width = 0;
646 drv_data->ops = &bfin_transfer_ops_u8;
647 } else if (bits_per_word == 16) {
648 drv_data->n_bytes = 2;
649 drv_data->len = (transfer->len) >> 1;
650 cr_width = BIT_CTL_WORDSIZE;
651 drv_data->ops = &bfin_transfer_ops_u16;
652 } else {
653 dev_err(&drv_data->pdev->dev, "transfer: unsupported bits_per_word\n");
654 message->status = -EINVAL;
655 bfin_spi_giveback(drv_data);
656 return;
657 }
658 cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
659 cr |= cr_width;
660 write_CTRL(drv_data, cr);
661
662 dev_dbg(&drv_data->pdev->dev,
663 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
664 drv_data->ops, chip->ops, &bfin_transfer_ops_u8);
665
666 message->state = RUNNING_STATE;
667 dma_config = 0;
668
669 /* Speed setup (surely valid because already checked) */
670 if (transfer->speed_hz)
671 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
672 else
673 write_BAUD(drv_data, chip->baud);
674
675 write_STAT(drv_data, BIT_STAT_CLR);
676 bfin_spi_cs_active(drv_data, chip);
677
678 dev_dbg(&drv_data->pdev->dev,
679 "now pumping a transfer: width is %d, len is %d\n",
680 cr_width, transfer->len);
681
682 /*
683 * Try to map dma buffer and do a dma transfer. If successful use,
684 * different way to r/w according to the enable_dma settings and if
685 * we are not doing a full duplex transfer (since the hardware does
686 * not support full duplex DMA transfers).
687 */
688 if (!full_duplex && drv_data->cur_chip->enable_dma
689 && drv_data->len > 6) {
690
691 unsigned long dma_start_addr, flags;
692
693 disable_dma(drv_data->dma_channel);
694 clear_dma_irqstat(drv_data->dma_channel);
695
696 /* config dma channel */
697 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
698 set_dma_x_count(drv_data->dma_channel, drv_data->len);
699 if (cr_width == BIT_CTL_WORDSIZE) {
700 set_dma_x_modify(drv_data->dma_channel, 2);
701 dma_width = WDSIZE_16;
702 } else {
703 set_dma_x_modify(drv_data->dma_channel, 1);
704 dma_width = WDSIZE_8;
705 }
706
707 /* poll for SPI completion before start */
708 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
709 cpu_relax();
710
711 /* dirty hack for autobuffer DMA mode */
712 if (drv_data->tx_dma == 0xFFFF) {
713 dev_dbg(&drv_data->pdev->dev,
714 "doing autobuffer DMA out.\n");
715
716 /* no irq in autobuffer mode */
717 dma_config =
718 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
719 set_dma_config(drv_data->dma_channel, dma_config);
720 set_dma_start_addr(drv_data->dma_channel,
721 (unsigned long)drv_data->tx);
722 enable_dma(drv_data->dma_channel);
723
724 /* start SPI transfer */
725 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
726
727 /* just return here, there can only be one transfer
728 * in this mode
729 */
730 message->status = 0;
731 bfin_spi_giveback(drv_data);
732 return;
733 }
734
735 /* In dma mode, rx or tx must be NULL in one transfer */
736 dma_config = (RESTART | dma_width | DI_EN);
737 if (drv_data->rx != NULL) {
738 /* set transfer mode, and enable SPI */
739 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
740 drv_data->rx, drv_data->len_in_bytes);
741
742 /* invalidate caches, if needed */
743 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
744 invalidate_dcache_range((unsigned long) drv_data->rx,
745 (unsigned long) (drv_data->rx +
746 drv_data->len_in_bytes));
747
748 dma_config |= WNR;
749 dma_start_addr = (unsigned long)drv_data->rx;
750 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
751
752 } else if (drv_data->tx != NULL) {
753 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
754
755 /* flush caches, if needed */
756 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
757 flush_dcache_range((unsigned long) drv_data->tx,
758 (unsigned long) (drv_data->tx +
759 drv_data->len_in_bytes));
760
761 dma_start_addr = (unsigned long)drv_data->tx;
762 cr |= BIT_CTL_TIMOD_DMA_TX;
763
764 } else
765 BUG();
766
767 /* oh man, here there be monsters ... and i dont mean the
768 * fluffy cute ones from pixar, i mean the kind that'll eat
769 * your data, kick your dog, and love it all. do *not* try
770 * and change these lines unless you (1) heavily test DMA
771 * with SPI flashes on a loaded system (e.g. ping floods),
772 * (2) know just how broken the DMA engine interaction with
773 * the SPI peripheral is, and (3) have someone else to blame
774 * when you screw it all up anyways.
775 */
776 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
777 set_dma_config(drv_data->dma_channel, dma_config);
778 local_irq_save(flags);
779 SSYNC();
780 write_CTRL(drv_data, cr);
781 enable_dma(drv_data->dma_channel);
782 dma_enable_irq(drv_data->dma_channel);
783 local_irq_restore(flags);
784
785 return;
786 }
787
788 /*
789 * We always use SPI_WRITE mode (transfer starts with TDBR write).
790 * SPI_READ mode (transfer starts with RDBR read) seems to have
791 * problems with setting up the output value in TDBR prior to the
792 * start of the transfer.
793 */
794 write_CTRL(drv_data, cr | BIT_CTL_TXMOD);
795
796 if (chip->pio_interrupt) {
797 /* SPI irq should have been disabled by now */
798
799 /* discard old RX data and clear RXS */
800 bfin_spi_dummy_read(drv_data);
801
802 /* start transfer */
803 if (drv_data->tx == NULL)
804 write_TDBR(drv_data, chip->idle_tx_val);
805 else {
806 if (bits_per_word == 8)
807 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
808 else
809 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
810 drv_data->tx += drv_data->n_bytes;
811 }
812
813 /* once TDBR is empty, interrupt is triggered */
814 enable_irq(drv_data->spi_irq);
815 return;
816 }
817
818 /* IO mode */
819 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
820
821 if (full_duplex) {
822 /* full duplex mode */
823 BUG_ON((drv_data->tx_end - drv_data->tx) !=
824 (drv_data->rx_end - drv_data->rx));
825 dev_dbg(&drv_data->pdev->dev,
826 "IO duplex: cr is 0x%x\n", cr);
827
828 drv_data->ops->duplex(drv_data);
829
830 if (drv_data->tx != drv_data->tx_end)
831 tranf_success = 0;
832 } else if (drv_data->tx != NULL) {
833 /* write only half duplex */
834 dev_dbg(&drv_data->pdev->dev,
835 "IO write: cr is 0x%x\n", cr);
836
837 drv_data->ops->write(drv_data);
838
839 if (drv_data->tx != drv_data->tx_end)
840 tranf_success = 0;
841 } else if (drv_data->rx != NULL) {
842 /* read only half duplex */
843 dev_dbg(&drv_data->pdev->dev,
844 "IO read: cr is 0x%x\n", cr);
845
846 drv_data->ops->read(drv_data);
847 if (drv_data->rx != drv_data->rx_end)
848 tranf_success = 0;
849 }
850
851 if (!tranf_success) {
852 dev_dbg(&drv_data->pdev->dev,
853 "IO write error!\n");
854 message->state = ERROR_STATE;
855 } else {
856 /* Update total byte transfered */
857 message->actual_length += drv_data->len_in_bytes;
858 /* Move to next transfer of this msg */
859 message->state = bfin_spi_next_transfer(drv_data);
860 if (drv_data->cs_change)
861 bfin_spi_cs_deactive(drv_data, chip);
862 }
863
864 /* Schedule next transfer tasklet */
865 tasklet_schedule(&drv_data->pump_transfers);
866 }
867
868 /* pop a msg from queue and kick off real transfer */
869 static void bfin_spi_pump_messages(struct work_struct *work)
870 {
871 struct master_data *drv_data;
872 unsigned long flags;
873
874 drv_data = container_of(work, struct master_data, pump_messages);
875
876 /* Lock queue and check for queue work */
877 spin_lock_irqsave(&drv_data->lock, flags);
878 if (list_empty(&drv_data->queue) || !drv_data->running) {
879 /* pumper kicked off but no work to do */
880 drv_data->busy = 0;
881 spin_unlock_irqrestore(&drv_data->lock, flags);
882 return;
883 }
884
885 /* Make sure we are not already running a message */
886 if (drv_data->cur_msg) {
887 spin_unlock_irqrestore(&drv_data->lock, flags);
888 return;
889 }
890
891 /* Extract head of queue */
892 drv_data->cur_msg = list_entry(drv_data->queue.next,
893 struct spi_message, queue);
894
895 /* Setup the SSP using the per chip configuration */
896 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
897 bfin_spi_restore_state(drv_data);
898
899 list_del_init(&drv_data->cur_msg->queue);
900
901 /* Initial message state */
902 drv_data->cur_msg->state = START_STATE;
903 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
904 struct spi_transfer, transfer_list);
905
906 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
907 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
908 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
909 drv_data->cur_chip->ctl_reg);
910
911 dev_dbg(&drv_data->pdev->dev,
912 "the first transfer len is %d\n",
913 drv_data->cur_transfer->len);
914
915 /* Mark as busy and launch transfers */
916 tasklet_schedule(&drv_data->pump_transfers);
917
918 drv_data->busy = 1;
919 spin_unlock_irqrestore(&drv_data->lock, flags);
920 }
921
922 /*
923 * got a msg to transfer, queue it in drv_data->queue.
924 * And kick off message pumper
925 */
926 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
927 {
928 struct master_data *drv_data = spi_master_get_devdata(spi->master);
929 unsigned long flags;
930
931 spin_lock_irqsave(&drv_data->lock, flags);
932
933 if (!drv_data->running) {
934 spin_unlock_irqrestore(&drv_data->lock, flags);
935 return -ESHUTDOWN;
936 }
937
938 msg->actual_length = 0;
939 msg->status = -EINPROGRESS;
940 msg->state = START_STATE;
941
942 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
943 list_add_tail(&msg->queue, &drv_data->queue);
944
945 if (drv_data->running && !drv_data->busy)
946 queue_work(drv_data->workqueue, &drv_data->pump_messages);
947
948 spin_unlock_irqrestore(&drv_data->lock, flags);
949
950 return 0;
951 }
952
953 #define MAX_SPI_SSEL 7
954
955 static u16 ssel[][MAX_SPI_SSEL] = {
956 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
957 P_SPI0_SSEL4, P_SPI0_SSEL5,
958 P_SPI0_SSEL6, P_SPI0_SSEL7},
959
960 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
961 P_SPI1_SSEL4, P_SPI1_SSEL5,
962 P_SPI1_SSEL6, P_SPI1_SSEL7},
963
964 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
965 P_SPI2_SSEL4, P_SPI2_SSEL5,
966 P_SPI2_SSEL6, P_SPI2_SSEL7},
967 };
968
969 /* setup for devices (may be called multiple times -- not just first setup) */
970 static int bfin_spi_setup(struct spi_device *spi)
971 {
972 struct bfin5xx_spi_chip *chip_info;
973 struct slave_data *chip = NULL;
974 struct master_data *drv_data = spi_master_get_devdata(spi->master);
975 u16 bfin_ctl_reg;
976 int ret = -EINVAL;
977
978 /* Only alloc (or use chip_info) on first setup */
979 chip_info = NULL;
980 chip = spi_get_ctldata(spi);
981 if (chip == NULL) {
982 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
983 if (!chip) {
984 dev_err(&spi->dev, "cannot allocate chip data\n");
985 ret = -ENOMEM;
986 goto error;
987 }
988
989 chip->enable_dma = 0;
990 chip_info = spi->controller_data;
991 }
992
993 /* Let people set non-standard bits directly */
994 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
995 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
996
997 /* chip_info isn't always needed */
998 if (chip_info) {
999 /* Make sure people stop trying to set fields via ctl_reg
1000 * when they should actually be using common SPI framework.
1001 * Currently we let through: WOM EMISO PSSE GM SZ.
1002 * Not sure if a user actually needs/uses any of these,
1003 * but let's assume (for now) they do.
1004 */
1005 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1006 dev_err(&spi->dev, "do not set bits in ctl_reg "
1007 "that the SPI framework manages\n");
1008 goto error;
1009 }
1010 chip->enable_dma = chip_info->enable_dma != 0
1011 && drv_data->master_info->enable_dma;
1012 chip->ctl_reg = chip_info->ctl_reg;
1013 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1014 chip->idle_tx_val = chip_info->idle_tx_val;
1015 chip->pio_interrupt = chip_info->pio_interrupt;
1016 spi->bits_per_word = chip_info->bits_per_word;
1017 } else {
1018 /* force a default base state */
1019 chip->ctl_reg &= bfin_ctl_reg;
1020 }
1021
1022 if (spi->bits_per_word != 8 && spi->bits_per_word != 16) {
1023 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1024 spi->bits_per_word);
1025 goto error;
1026 }
1027
1028 /* translate common spi framework into our register */
1029 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1030 dev_err(&spi->dev, "unsupported spi modes detected\n");
1031 goto error;
1032 }
1033 if (spi->mode & SPI_CPOL)
1034 chip->ctl_reg |= BIT_CTL_CPOL;
1035 if (spi->mode & SPI_CPHA)
1036 chip->ctl_reg |= BIT_CTL_CPHA;
1037 if (spi->mode & SPI_LSB_FIRST)
1038 chip->ctl_reg |= BIT_CTL_LSBF;
1039 /* we dont support running in slave mode (yet?) */
1040 chip->ctl_reg |= BIT_CTL_MASTER;
1041
1042 /*
1043 * Notice: for blackfin, the speed_hz is the value of register
1044 * SPI_BAUD, not the real baudrate
1045 */
1046 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1047 chip->chip_select_num = spi->chip_select;
1048 if (chip->chip_select_num < MAX_CTRL_CS) {
1049 if (!(spi->mode & SPI_CPHA))
1050 dev_warn(&spi->dev, "Warning: SPI CPHA not set:"
1051 " Slave Select not under software control!\n"
1052 " See Documentation/blackfin/bfin-spi-notes.txt");
1053
1054 chip->flag = (1 << spi->chip_select) << 8;
1055 } else
1056 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1057
1058 if (chip->enable_dma && chip->pio_interrupt) {
1059 dev_err(&spi->dev, "enable_dma is set, "
1060 "do not set pio_interrupt\n");
1061 goto error;
1062 }
1063 /*
1064 * if any one SPI chip is registered and wants DMA, request the
1065 * DMA channel for it
1066 */
1067 if (chip->enable_dma && !drv_data->dma_requested) {
1068 /* register dma irq handler */
1069 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1070 if (ret) {
1071 dev_err(&spi->dev,
1072 "Unable to request BlackFin SPI DMA channel\n");
1073 goto error;
1074 }
1075 drv_data->dma_requested = 1;
1076
1077 ret = set_dma_callback(drv_data->dma_channel,
1078 bfin_spi_dma_irq_handler, drv_data);
1079 if (ret) {
1080 dev_err(&spi->dev, "Unable to set dma callback\n");
1081 goto error;
1082 }
1083 dma_disable_irq(drv_data->dma_channel);
1084 }
1085
1086 if (chip->pio_interrupt && !drv_data->irq_requested) {
1087 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1088 IRQF_DISABLED, "BFIN_SPI", drv_data);
1089 if (ret) {
1090 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1091 goto error;
1092 }
1093 drv_data->irq_requested = 1;
1094 /* we use write mode, spi irq has to be disabled here */
1095 disable_irq(drv_data->spi_irq);
1096 }
1097
1098 if (chip->chip_select_num >= MAX_CTRL_CS) {
1099 ret = gpio_request(chip->cs_gpio, spi->modalias);
1100 if (ret) {
1101 dev_err(&spi->dev, "gpio_request() error\n");
1102 goto pin_error;
1103 }
1104 gpio_direction_output(chip->cs_gpio, 1);
1105 }
1106
1107 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1108 spi->modalias, spi->bits_per_word, chip->enable_dma);
1109 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1110 chip->ctl_reg, chip->flag);
1111
1112 spi_set_ctldata(spi, chip);
1113
1114 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1115 if (chip->chip_select_num < MAX_CTRL_CS) {
1116 ret = peripheral_request(ssel[spi->master->bus_num]
1117 [chip->chip_select_num-1], spi->modalias);
1118 if (ret) {
1119 dev_err(&spi->dev, "peripheral_request() error\n");
1120 goto pin_error;
1121 }
1122 }
1123
1124 bfin_spi_cs_enable(drv_data, chip);
1125 bfin_spi_cs_deactive(drv_data, chip);
1126
1127 return 0;
1128
1129 pin_error:
1130 if (chip->chip_select_num >= MAX_CTRL_CS)
1131 gpio_free(chip->cs_gpio);
1132 else
1133 peripheral_free(ssel[spi->master->bus_num]
1134 [chip->chip_select_num - 1]);
1135 error:
1136 if (chip) {
1137 if (drv_data->dma_requested)
1138 free_dma(drv_data->dma_channel);
1139 drv_data->dma_requested = 0;
1140
1141 kfree(chip);
1142 /* prevent free 'chip' twice */
1143 spi_set_ctldata(spi, NULL);
1144 }
1145
1146 return ret;
1147 }
1148
1149 /*
1150 * callback for spi framework.
1151 * clean driver specific data
1152 */
1153 static void bfin_spi_cleanup(struct spi_device *spi)
1154 {
1155 struct slave_data *chip = spi_get_ctldata(spi);
1156 struct master_data *drv_data = spi_master_get_devdata(spi->master);
1157
1158 if (!chip)
1159 return;
1160
1161 if (chip->chip_select_num < MAX_CTRL_CS) {
1162 peripheral_free(ssel[spi->master->bus_num]
1163 [chip->chip_select_num-1]);
1164 bfin_spi_cs_disable(drv_data, chip);
1165 } else
1166 gpio_free(chip->cs_gpio);
1167
1168 kfree(chip);
1169 /* prevent free 'chip' twice */
1170 spi_set_ctldata(spi, NULL);
1171 }
1172
1173 static inline int bfin_spi_init_queue(struct master_data *drv_data)
1174 {
1175 INIT_LIST_HEAD(&drv_data->queue);
1176 spin_lock_init(&drv_data->lock);
1177
1178 drv_data->running = false;
1179 drv_data->busy = 0;
1180
1181 /* init transfer tasklet */
1182 tasklet_init(&drv_data->pump_transfers,
1183 bfin_spi_pump_transfers, (unsigned long)drv_data);
1184
1185 /* init messages workqueue */
1186 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1187 drv_data->workqueue = create_singlethread_workqueue(
1188 dev_name(drv_data->master->dev.parent));
1189 if (drv_data->workqueue == NULL)
1190 return -EBUSY;
1191
1192 return 0;
1193 }
1194
1195 static inline int bfin_spi_start_queue(struct master_data *drv_data)
1196 {
1197 unsigned long flags;
1198
1199 spin_lock_irqsave(&drv_data->lock, flags);
1200
1201 if (drv_data->running || drv_data->busy) {
1202 spin_unlock_irqrestore(&drv_data->lock, flags);
1203 return -EBUSY;
1204 }
1205
1206 drv_data->running = true;
1207 drv_data->cur_msg = NULL;
1208 drv_data->cur_transfer = NULL;
1209 drv_data->cur_chip = NULL;
1210 spin_unlock_irqrestore(&drv_data->lock, flags);
1211
1212 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1213
1214 return 0;
1215 }
1216
1217 static inline int bfin_spi_stop_queue(struct master_data *drv_data)
1218 {
1219 unsigned long flags;
1220 unsigned limit = 500;
1221 int status = 0;
1222
1223 spin_lock_irqsave(&drv_data->lock, flags);
1224
1225 /*
1226 * This is a bit lame, but is optimized for the common execution path.
1227 * A wait_queue on the drv_data->busy could be used, but then the common
1228 * execution path (pump_messages) would be required to call wake_up or
1229 * friends on every SPI message. Do this instead
1230 */
1231 drv_data->running = false;
1232 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1233 spin_unlock_irqrestore(&drv_data->lock, flags);
1234 msleep(10);
1235 spin_lock_irqsave(&drv_data->lock, flags);
1236 }
1237
1238 if (!list_empty(&drv_data->queue) || drv_data->busy)
1239 status = -EBUSY;
1240
1241 spin_unlock_irqrestore(&drv_data->lock, flags);
1242
1243 return status;
1244 }
1245
1246 static inline int bfin_spi_destroy_queue(struct master_data *drv_data)
1247 {
1248 int status;
1249
1250 status = bfin_spi_stop_queue(drv_data);
1251 if (status != 0)
1252 return status;
1253
1254 destroy_workqueue(drv_data->workqueue);
1255
1256 return 0;
1257 }
1258
1259 static int __init bfin_spi_probe(struct platform_device *pdev)
1260 {
1261 struct device *dev = &pdev->dev;
1262 struct bfin5xx_spi_master *platform_info;
1263 struct spi_master *master;
1264 struct master_data *drv_data;
1265 struct resource *res;
1266 int status = 0;
1267
1268 platform_info = dev->platform_data;
1269
1270 /* Allocate master with space for drv_data */
1271 master = spi_alloc_master(dev, sizeof(*drv_data));
1272 if (!master) {
1273 dev_err(&pdev->dev, "can not alloc spi_master\n");
1274 return -ENOMEM;
1275 }
1276
1277 drv_data = spi_master_get_devdata(master);
1278 drv_data->master = master;
1279 drv_data->master_info = platform_info;
1280 drv_data->pdev = pdev;
1281 drv_data->pin_req = platform_info->pin_req;
1282
1283 /* the spi->mode bits supported by this driver: */
1284 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1285
1286 master->bus_num = pdev->id;
1287 master->num_chipselect = platform_info->num_chipselect;
1288 master->cleanup = bfin_spi_cleanup;
1289 master->setup = bfin_spi_setup;
1290 master->transfer = bfin_spi_transfer;
1291
1292 /* Find and map our resources */
1293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1294 if (res == NULL) {
1295 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1296 status = -ENOENT;
1297 goto out_error_get_res;
1298 }
1299
1300 drv_data->regs_base = ioremap(res->start, resource_size(res));
1301 if (drv_data->regs_base == NULL) {
1302 dev_err(dev, "Cannot map IO\n");
1303 status = -ENXIO;
1304 goto out_error_ioremap;
1305 }
1306
1307 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1308 if (res == NULL) {
1309 dev_err(dev, "No DMA channel specified\n");
1310 status = -ENOENT;
1311 goto out_error_free_io;
1312 }
1313 drv_data->dma_channel = res->start;
1314
1315 drv_data->spi_irq = platform_get_irq(pdev, 0);
1316 if (drv_data->spi_irq < 0) {
1317 dev_err(dev, "No spi pio irq specified\n");
1318 status = -ENOENT;
1319 goto out_error_free_io;
1320 }
1321
1322 /* Initial and start queue */
1323 status = bfin_spi_init_queue(drv_data);
1324 if (status != 0) {
1325 dev_err(dev, "problem initializing queue\n");
1326 goto out_error_queue_alloc;
1327 }
1328
1329 status = bfin_spi_start_queue(drv_data);
1330 if (status != 0) {
1331 dev_err(dev, "problem starting queue\n");
1332 goto out_error_queue_alloc;
1333 }
1334
1335 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1336 if (status != 0) {
1337 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1338 goto out_error_queue_alloc;
1339 }
1340
1341 /* Reset SPI registers. If these registers were used by the boot loader,
1342 * the sky may fall on your head if you enable the dma controller.
1343 */
1344 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1345 write_FLAG(drv_data, 0xFF00);
1346
1347 /* Register with the SPI framework */
1348 platform_set_drvdata(pdev, drv_data);
1349 status = spi_register_master(master);
1350 if (status != 0) {
1351 dev_err(dev, "problem registering spi master\n");
1352 goto out_error_queue_alloc;
1353 }
1354
1355 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1356 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1357 drv_data->dma_channel);
1358 return status;
1359
1360 out_error_queue_alloc:
1361 bfin_spi_destroy_queue(drv_data);
1362 out_error_free_io:
1363 iounmap((void *) drv_data->regs_base);
1364 out_error_ioremap:
1365 out_error_get_res:
1366 spi_master_put(master);
1367
1368 return status;
1369 }
1370
1371 /* stop hardware and remove the driver */
1372 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1373 {
1374 struct master_data *drv_data = platform_get_drvdata(pdev);
1375 int status = 0;
1376
1377 if (!drv_data)
1378 return 0;
1379
1380 /* Remove the queue */
1381 status = bfin_spi_destroy_queue(drv_data);
1382 if (status != 0)
1383 return status;
1384
1385 /* Disable the SSP at the peripheral and SOC level */
1386 bfin_spi_disable(drv_data);
1387
1388 /* Release DMA */
1389 if (drv_data->master_info->enable_dma) {
1390 if (dma_channel_active(drv_data->dma_channel))
1391 free_dma(drv_data->dma_channel);
1392 }
1393
1394 if (drv_data->irq_requested) {
1395 free_irq(drv_data->spi_irq, drv_data);
1396 drv_data->irq_requested = 0;
1397 }
1398
1399 /* Disconnect from the SPI framework */
1400 spi_unregister_master(drv_data->master);
1401
1402 peripheral_free_list(drv_data->pin_req);
1403
1404 /* Prevent double remove */
1405 platform_set_drvdata(pdev, NULL);
1406
1407 return 0;
1408 }
1409
1410 #ifdef CONFIG_PM
1411 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1412 {
1413 struct master_data *drv_data = platform_get_drvdata(pdev);
1414 int status = 0;
1415
1416 status = bfin_spi_stop_queue(drv_data);
1417 if (status != 0)
1418 return status;
1419
1420 drv_data->ctrl_reg = read_CTRL(drv_data);
1421 drv_data->flag_reg = read_FLAG(drv_data);
1422
1423 /*
1424 * reset SPI_CTL and SPI_FLG registers
1425 */
1426 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1427 write_FLAG(drv_data, 0xFF00);
1428
1429 return 0;
1430 }
1431
1432 static int bfin_spi_resume(struct platform_device *pdev)
1433 {
1434 struct master_data *drv_data = platform_get_drvdata(pdev);
1435 int status = 0;
1436
1437 write_CTRL(drv_data, drv_data->ctrl_reg);
1438 write_FLAG(drv_data, drv_data->flag_reg);
1439
1440 /* Start the queue running */
1441 status = bfin_spi_start_queue(drv_data);
1442 if (status != 0) {
1443 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1444 return status;
1445 }
1446
1447 return 0;
1448 }
1449 #else
1450 #define bfin_spi_suspend NULL
1451 #define bfin_spi_resume NULL
1452 #endif /* CONFIG_PM */
1453
1454 MODULE_ALIAS("platform:bfin-spi");
1455 static struct platform_driver bfin_spi_driver = {
1456 .driver = {
1457 .name = DRV_NAME,
1458 .owner = THIS_MODULE,
1459 },
1460 .suspend = bfin_spi_suspend,
1461 .resume = bfin_spi_resume,
1462 .remove = __devexit_p(bfin_spi_remove),
1463 };
1464
1465 static int __init bfin_spi_init(void)
1466 {
1467 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1468 }
1469 subsys_initcall(bfin_spi_init);
1470
1471 static void __exit bfin_spi_exit(void)
1472 {
1473 platform_driver_unregister(&bfin_spi_driver);
1474 }
1475 module_exit(bfin_spi_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree