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serial: core, remove uart_update_termios
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / gadget / imx_udc.h
blob7136c242b4ec515481815a0793d46843d9b00fae
1 /*
2 * Copyright (C) 2005 Mike Lee(eemike@gmail.com)
3 *
4 * This udc driver is now under testing and code is based on pxa2xx_udc.h
5 * Please use it with your own risk!
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #ifndef __LINUX_USB_GADGET_IMX_H
19 #define __LINUX_USB_GADGET_IMX_H
20
21 #include <linux/types.h>
22
23 /* Helper macros */
24 #define EP_NO(ep) ((ep->bEndpointAddress) & ~USB_DIR_IN) /* IN:1, OUT:0 */
25 #define EP_DIR(ep) ((ep->bEndpointAddress) & USB_DIR_IN ? 1 : 0)
26 #define IMX_USB_NB_EP 6
27
28 /* Driver structures */
29 struct imx_request {
30 struct usb_request req;
31 struct list_head queue;
32 unsigned int in_use;
33 };
34
35 enum ep0_state {
36 EP0_IDLE,
37 EP0_IN_DATA_PHASE,
38 EP0_OUT_DATA_PHASE,
39 EP0_CONFIG,
40 EP0_STALL,
41 };
42
43 struct imx_ep_struct {
44 struct usb_ep ep;
45 struct imx_udc_struct *imx_usb;
46 struct list_head queue;
47 unsigned char stopped;
48 unsigned char fifosize;
49 unsigned char bEndpointAddress;
50 unsigned char bmAttributes;
51 };
52
53 struct imx_udc_struct {
54 struct usb_gadget gadget;
55 struct usb_gadget_driver *driver;
56 struct device *dev;
57 struct imx_ep_struct imx_ep[IMX_USB_NB_EP];
58 struct clk *clk;
59 struct timer_list timer;
60 enum ep0_state ep0state;
61 struct resource *res;
62 void __iomem *base;
63 unsigned char set_config;
64 int cfg,
65 intf,
66 alt,
67 usbd_int[7];
68 };
69
70 /* USB registers */
71 #define USB_FRAME (0x00) /* USB frame */
72 #define USB_SPEC (0x04) /* USB Spec */
73 #define USB_STAT (0x08) /* USB Status */
74 #define USB_CTRL (0x0C) /* USB Control */
75 #define USB_DADR (0x10) /* USB Desc RAM addr */
76 #define USB_DDAT (0x14) /* USB Desc RAM/EP buffer data */
77 #define USB_INTR (0x18) /* USB interrupt */
78 #define USB_MASK (0x1C) /* USB Mask */
79 #define USB_ENAB (0x24) /* USB Enable */
80 #define USB_EP_STAT(x) (0x30 + (x*0x30)) /* USB status/control */
81 #define USB_EP_INTR(x) (0x34 + (x*0x30)) /* USB interrupt */
82 #define USB_EP_MASK(x) (0x38 + (x*0x30)) /* USB mask */
83 #define USB_EP_FDAT(x) (0x3C + (x*0x30)) /* USB FIFO data */
84 #define USB_EP_FDAT0(x) (0x3C + (x*0x30)) /* USB FIFO data */
85 #define USB_EP_FDAT1(x) (0x3D + (x*0x30)) /* USB FIFO data */
86 #define USB_EP_FDAT2(x) (0x3E + (x*0x30)) /* USB FIFO data */
87 #define USB_EP_FDAT3(x) (0x3F + (x*0x30)) /* USB FIFO data */
88 #define USB_EP_FSTAT(x) (0x40 + (x*0x30)) /* USB FIFO status */
89 #define USB_EP_FCTRL(x) (0x44 + (x*0x30)) /* USB FIFO control */
90 #define USB_EP_LRFP(x) (0x48 + (x*0x30)) /* USB last rd f. pointer */
91 #define USB_EP_LWFP(x) (0x4C + (x*0x30)) /* USB last wr f. pointer */
92 #define USB_EP_FALRM(x) (0x50 + (x*0x30)) /* USB FIFO alarm */
93 #define USB_EP_FRDP(x) (0x54 + (x*0x30)) /* USB FIFO read pointer */
94 #define USB_EP_FWRP(x) (0x58 + (x*0x30)) /* USB FIFO write pointer */
95 /* USB Control Register Bit Fields.*/
96 #define CTRL_CMDOVER (1<<6) /* UDC status */
97 #define CTRL_CMDERROR (1<<5) /* UDC status */
98 #define CTRL_FE_ENA (1<<3) /* Enable Font End logic */
99 #define CTRL_UDC_RST (1<<2) /* UDC reset */
100 #define CTRL_AFE_ENA (1<<1) /* Analog Font end enable */
101 #define CTRL_RESUME (1<<0) /* UDC resume */
102 /* USB Status Register Bit Fields.*/
103 #define STAT_RST (1<<8)
104 #define STAT_SUSP (1<<7)
105 #define STAT_CFG (3<<5)
106 #define STAT_INTF (3<<3)
107 #define STAT_ALTSET (7<<0)
108 /* USB Interrupt Status/Mask Registers Bit fields */
109 #define INTR_WAKEUP (1<<31) /* Wake up Interrupt */
110 #define INTR_MSOF (1<<7) /* Missed Start of Frame */
111 #define INTR_SOF (1<<6) /* Start of Frame */
112 #define INTR_RESET_STOP (1<<5) /* Reset Signaling stop */
113 #define INTR_RESET_START (1<<4) /* Reset Signaling start */
114 #define INTR_RESUME (1<<3) /* Suspend to resume */
115 #define INTR_SUSPEND (1<<2) /* Active to suspend */
116 #define INTR_FRAME_MATCH (1<<1) /* Frame matched */
117 #define INTR_CFG_CHG (1<<0) /* Configuration change occurred */
118 /* USB Enable Register Bit Fields.*/
119 #define ENAB_RST (1<<31) /* Reset USB modules */
120 #define ENAB_ENAB (1<<30) /* Enable USB modules*/
121 #define ENAB_SUSPEND (1<<29) /* Suspend USB modules */
122 #define ENAB_ENDIAN (1<<28) /* Endian of USB modules */
123 #define ENAB_PWRMD (1<<0) /* Power mode of USB modules */
124 /* USB Descriptor Ram Address Register bit fields */
125 #define DADR_CFG (1<<31) /* Configuration */
126 #define DADR_BSY (1<<30) /* Busy status */
127 #define DADR_DADR (0x1FF) /* Descriptor Ram Address */
128 /* USB Descriptor RAM/Endpoint Buffer Data Register bit fields */
129 #define DDAT_DDAT (0xFF) /* Descriptor Endpoint Buffer */
130 /* USB Endpoint Status Register bit fields */
131 #define EPSTAT_BCOUNT (0x7F<<16) /* Endpoint FIFO byte count */
132 #define EPSTAT_SIP (1<<8) /* Endpoint setup in progress */
133 #define EPSTAT_DIR (1<<7) /* Endpoint transfer direction */
134 #define EPSTAT_MAX (3<<5) /* Endpoint Max packet size */
135 #define EPSTAT_TYP (3<<3) /* Endpoint type */
136 #define EPSTAT_ZLPS (1<<2) /* Send zero length packet */
137 #define EPSTAT_FLUSH (1<<1) /* Endpoint FIFO Flush */
138 #define EPSTAT_STALL (1<<0) /* Force stall */
139 /* USB Endpoint FIFO Status Register bit fields */
140 #define FSTAT_FRAME_STAT (0xF<<24) /* Frame status bit [0-3] */
141 #define FSTAT_ERR (1<<22) /* FIFO error */
142 #define FSTAT_UF (1<<21) /* FIFO underflow */
143 #define FSTAT_OF (1<<20) /* FIFO overflow */
144 #define FSTAT_FR (1<<19) /* FIFO frame ready */
145 #define FSTAT_FULL (1<<18) /* FIFO full */
146 #define FSTAT_ALRM (1<<17) /* FIFO alarm */
147 #define FSTAT_EMPTY (1<<16) /* FIFO empty */
148 /* USB Endpoint FIFO Control Register bit fields */
149 #define FCTRL_WFR (1<<29) /* Write frame end */
150 /* USB Endpoint Interrupt Status Regsiter bit fields */
151 #define EPINTR_FIFO_FULL (1<<8) /* fifo full */
152 #define EPINTR_FIFO_EMPTY (1<<7) /* fifo empty */
153 #define EPINTR_FIFO_ERROR (1<<6) /* fifo error */
154 #define EPINTR_FIFO_HIGH (1<<5) /* fifo high */
155 #define EPINTR_FIFO_LOW (1<<4) /* fifo low */
156 #define EPINTR_MDEVREQ (1<<3) /* multi Device request */
157 #define EPINTR_EOT (1<<2) /* fifo end of transfer */
158 #define EPINTR_DEVREQ (1<<1) /* Device request */
159 #define EPINTR_EOF (1<<0) /* fifo end of frame */
160
161 /* Debug macros */
162 #ifdef DEBUG
163
164 /* #define DEBUG_REQ */
165 /* #define DEBUG_TRX */
166 /* #define DEBUG_INIT */
167 /* #define DEBUG_EP0 */
168 /* #define DEBUG_EPX */
169 /* #define DEBUG_IRQ */
170 /* #define DEBUG_EPIRQ */
171 /* #define DEBUG_DUMP */
172 /* #define DEBUG_ERR */
173
174 #ifdef DEBUG_REQ
175 #define D_REQ(dev, args...) dev_dbg(dev, ## args)
176 #else
177 #define D_REQ(dev, args...) do {} while (0)
178 #endif /* DEBUG_REQ */
179
180 #ifdef DEBUG_TRX
181 #define D_TRX(dev, args...) dev_dbg(dev, ## args)
182 #else
183 #define D_TRX(dev, args...) do {} while (0)
184 #endif /* DEBUG_TRX */
185
186 #ifdef DEBUG_INIT
187 #define D_INI(dev, args...) dev_dbg(dev, ## args)
188 #else
189 #define D_INI(dev, args...) do {} while (0)
190 #endif /* DEBUG_INIT */
191
192 #ifdef DEBUG_EP0
193 static const char *state_name[] = {
194 "EP0_IDLE",
195 "EP0_IN_DATA_PHASE",
196 "EP0_OUT_DATA_PHASE",
197 "EP0_CONFIG",
198 "EP0_STALL"
199 };
200 #define D_EP0(dev, args...) dev_dbg(dev, ## args)
201 #else
202 #define D_EP0(dev, args...) do {} while (0)
203 #endif /* DEBUG_EP0 */
204
205 #ifdef DEBUG_EPX
206 #define D_EPX(dev, args...) dev_dbg(dev, ## args)
207 #else
208 #define D_EPX(dev, args...) do {} while (0)
209 #endif /* DEBUG_EP0 */
210
211 #ifdef DEBUG_IRQ
212 static void dump_intr(const char *label, int irqreg, struct device *dev)
213 {
214 dev_dbg(dev, "<%s> USB_INTR=[%s%s%s%s%s%s%s%s%s]\n", label,
215 (irqreg & INTR_WAKEUP) ? " wake" : "",
216 (irqreg & INTR_MSOF) ? " msof" : "",
217 (irqreg & INTR_SOF) ? " sof" : "",
218 (irqreg & INTR_RESUME) ? " resume" : "",
219 (irqreg & INTR_SUSPEND) ? " suspend" : "",
220 (irqreg & INTR_RESET_STOP) ? " noreset" : "",
221 (irqreg & INTR_RESET_START) ? " reset" : "",
222 (irqreg & INTR_FRAME_MATCH) ? " fmatch" : "",
223 (irqreg & INTR_CFG_CHG) ? " config" : "");
224 }
225 #else
226 #define dump_intr(x, y, z) do {} while (0)
227 #endif /* DEBUG_IRQ */
228
229 #ifdef DEBUG_EPIRQ
230 static void dump_ep_intr(const char *label, int nr, int irqreg,
231 struct device *dev)
232 {
233 dev_dbg(dev, "<%s> EP%d_INTR=[%s%s%s%s%s%s%s%s%s]\n", label, nr,
234 (irqreg & EPINTR_FIFO_FULL) ? " full" : "",
235 (irqreg & EPINTR_FIFO_EMPTY) ? " fempty" : "",
236 (irqreg & EPINTR_FIFO_ERROR) ? " ferr" : "",
237 (irqreg & EPINTR_FIFO_HIGH) ? " fhigh" : "",
238 (irqreg & EPINTR_FIFO_LOW) ? " flow" : "",
239 (irqreg & EPINTR_MDEVREQ) ? " mreq" : "",
240 (irqreg & EPINTR_EOF) ? " eof" : "",
241 (irqreg & EPINTR_DEVREQ) ? " devreq" : "",
242 (irqreg & EPINTR_EOT) ? " eot" : "");
243 }
244 #else
245 #define dump_ep_intr(x, y, z, i) do {} while (0)
246 #endif /* DEBUG_IRQ */
247
248 #ifdef DEBUG_DUMP
249 static void dump_usb_stat(const char *label,
250 struct imx_udc_struct *imx_usb)
251 {
252 int temp = __raw_readl(imx_usb->base + USB_STAT);
253
254 dev_dbg(imx_usb->dev,
255 "<%s> USB_STAT=[%s%s CFG=%d, INTF=%d, ALTR=%d]\n", label,
256 (temp & STAT_RST) ? " reset" : "",
257 (temp & STAT_SUSP) ? " suspend" : "",
258 (temp & STAT_CFG) >> 5,
259 (temp & STAT_INTF) >> 3,
260 (temp & STAT_ALTSET));
261 }
262
263 static void dump_ep_stat(const char *label,
264 struct imx_ep_struct *imx_ep)
265 {
266 int temp = __raw_readl(imx_ep->imx_usb->base
267 + USB_EP_INTR(EP_NO(imx_ep)));
268
269 dev_dbg(imx_ep->imx_usb->dev,
270 "<%s> EP%d_INTR=[%s%s%s%s%s%s%s%s%s]\n",
271 label, EP_NO(imx_ep),
272 (temp & EPINTR_FIFO_FULL) ? " full" : "",
273 (temp & EPINTR_FIFO_EMPTY) ? " fempty" : "",
274 (temp & EPINTR_FIFO_ERROR) ? " ferr" : "",
275 (temp & EPINTR_FIFO_HIGH) ? " fhigh" : "",
276 (temp & EPINTR_FIFO_LOW) ? " flow" : "",
277 (temp & EPINTR_MDEVREQ) ? " mreq" : "",
278 (temp & EPINTR_EOF) ? " eof" : "",
279 (temp & EPINTR_DEVREQ) ? " devreq" : "",
280 (temp & EPINTR_EOT) ? " eot" : "");
281
282 temp = __raw_readl(imx_ep->imx_usb->base
283 + USB_EP_STAT(EP_NO(imx_ep)));
284
285 dev_dbg(imx_ep->imx_usb->dev,
286 "<%s> EP%d_STAT=[%s%s bcount=%d]\n",
287 label, EP_NO(imx_ep),
288 (temp & EPSTAT_SIP) ? " sip" : "",
289 (temp & EPSTAT_STALL) ? " stall" : "",
290 (temp & EPSTAT_BCOUNT) >> 16);
291
292 temp = __raw_readl(imx_ep->imx_usb->base
293 + USB_EP_FSTAT(EP_NO(imx_ep)));
294
295 dev_dbg(imx_ep->imx_usb->dev,
296 "<%s> EP%d_FSTAT=[%s%s%s%s%s%s%s]\n",
297 label, EP_NO(imx_ep),
298 (temp & FSTAT_ERR) ? " ferr" : "",
299 (temp & FSTAT_UF) ? " funder" : "",
300 (temp & FSTAT_OF) ? " fover" : "",
301 (temp & FSTAT_FR) ? " fready" : "",
302 (temp & FSTAT_FULL) ? " ffull" : "",
303 (temp & FSTAT_ALRM) ? " falarm" : "",
304 (temp & FSTAT_EMPTY) ? " fempty" : "");
305 }
306
307 static void dump_req(const char *label, struct imx_ep_struct *imx_ep,
308 struct usb_request *req)
309 {
310 int i;
311
312 if (!req || !req->buf) {
313 dev_dbg(imx_ep->imx_usb->dev,
314 "<%s> req or req buf is free\n", label);
315 return;
316 }
317
318 if ((!EP_NO(imx_ep) && imx_ep->imx_usb->ep0state
319 == EP0_IN_DATA_PHASE)
320 || (EP_NO(imx_ep) && EP_DIR(imx_ep))) {
321
322 dev_dbg(imx_ep->imx_usb->dev,
323 "<%s> request dump <", label);
324 for (i = 0; i < req->length; i++)
325 printk("%02x-", *((u8 *)req->buf + i));
326 printk(">\n");
327 }
328 }
329
330 #else
331 #define dump_ep_stat(x, y) do {} while (0)
332 #define dump_usb_stat(x, y) do {} while (0)
333 #define dump_req(x, y, z) do {} while (0)
334 #endif /* DEBUG_DUMP */
335
336 #ifdef DEBUG_ERR
337 #define D_ERR(dev, args...) dev_dbg(dev, ## args)
338 #else
339 #define D_ERR(dev, args...) do {} while (0)
340 #endif
341
342 #else
343 #define D_REQ(dev, args...) do {} while (0)
344 #define D_TRX(dev, args...) do {} while (0)
345 #define D_INI(dev, args...) do {} while (0)
346 #define D_EP0(dev, args...) do {} while (0)
347 #define D_EPX(dev, args...) do {} while (0)
348 #define dump_ep_intr(x, y, z, i) do {} while (0)
349 #define dump_intr(x, y, z) do {} while (0)
350 #define dump_ep_stat(x, y) do {} while (0)
351 #define dump_usb_stat(x, y) do {} while (0)
352 #define dump_req(x, y, z) do {} while (0)
353 #define D_ERR(dev, args...) do {} while (0)
354 #endif /* DEBUG */
355
356 #endif /* __LINUX_USB_GADGET_IMX_H */
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