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ath9k: enable ANI to help with noisy environments
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath9k / hw.c
blob62e44a0ef996211a61255f16cd799e10860a4f49
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "core.h"
21 #include "hw.h"
22 #include "reg.h"
23 #include "phy.h"
24 #include "initvals.h"
25
26 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
27 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
28 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
29 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
30 u8 numChains);
31 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
32 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
33 u8 numChains);
34
35 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
36 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
37
38 static const struct hal_percal_data iq_cal_multi_sample = {
39 IQ_MISMATCH_CAL,
40 MAX_CAL_SAMPLES,
41 PER_MIN_LOG_COUNT,
42 ath9k_hw_iqcal_collect,
43 ath9k_hw_iqcalibrate
44 };
45 static const struct hal_percal_data iq_cal_single_sample = {
46 IQ_MISMATCH_CAL,
47 MIN_CAL_SAMPLES,
48 PER_MAX_LOG_COUNT,
49 ath9k_hw_iqcal_collect,
50 ath9k_hw_iqcalibrate
51 };
52 static const struct hal_percal_data adc_gain_cal_multi_sample = {
53 ADC_GAIN_CAL,
54 MAX_CAL_SAMPLES,
55 PER_MIN_LOG_COUNT,
56 ath9k_hw_adc_gaincal_collect,
57 ath9k_hw_adc_gaincal_calibrate
58 };
59 static const struct hal_percal_data adc_gain_cal_single_sample = {
60 ADC_GAIN_CAL,
61 MIN_CAL_SAMPLES,
62 PER_MAX_LOG_COUNT,
63 ath9k_hw_adc_gaincal_collect,
64 ath9k_hw_adc_gaincal_calibrate
65 };
66 static const struct hal_percal_data adc_dc_cal_multi_sample = {
67 ADC_DC_CAL,
68 MAX_CAL_SAMPLES,
69 PER_MIN_LOG_COUNT,
70 ath9k_hw_adc_dccal_collect,
71 ath9k_hw_adc_dccal_calibrate
72 };
73 static const struct hal_percal_data adc_dc_cal_single_sample = {
74 ADC_DC_CAL,
75 MIN_CAL_SAMPLES,
76 PER_MAX_LOG_COUNT,
77 ath9k_hw_adc_dccal_collect,
78 ath9k_hw_adc_dccal_calibrate
79 };
80 static const struct hal_percal_data adc_init_dc_cal = {
81 ADC_DC_INIT_CAL,
82 MIN_CAL_SAMPLES,
83 INIT_LOG_COUNT,
84 ath9k_hw_adc_dccal_collect,
85 ath9k_hw_adc_dccal_calibrate
86 };
87
88 static struct ath9k_rate_table ar5416_11a_table = {
89 8,
90 {0},
91 {
92 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
93 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
94 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
95 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
96 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
97 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
98 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
99 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
100 },
101 };
102
103 static struct ath9k_rate_table ar5416_11b_table = {
104 4,
105 {0},
106 {
107 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
108 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
109 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
110 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
111 },
112 };
113
114 static struct ath9k_rate_table ar5416_11g_table = {
115 12,
116 {0},
117 {
118 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
119 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
120 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
121 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
122
123 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
124 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
125 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
126 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
127 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
128 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
129 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
130 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
131 },
132 };
133
134 static struct ath9k_rate_table ar5416_11ng_table = {
135 28,
136 {0},
137 {
138 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
139 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
140 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
141 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
142
143 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
144 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
145 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
146 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
147 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
148 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
149 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
150 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
151 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
152 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
153 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
154 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
155 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
156 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
157 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
158 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
159 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
160 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
161 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
162 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
163 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
164 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
165 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
166 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
167 },
168 };
169
170 static struct ath9k_rate_table ar5416_11na_table = {
171 24,
172 {0},
173 {
174 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
175 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
176 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
177 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
178 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
179 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
180 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
181 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
182 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
183 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
184 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
185 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
186 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
187 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
188 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
189 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
190 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
191 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
192 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
193 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
194 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
195 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
196 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
197 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
198 },
199 };
200
201 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
202 const struct ath9k_channel *chan)
203 {
204 if (IS_CHAN_CCK(chan))
205 return ATH9K_MODE_11A;
206 if (IS_CHAN_G(chan))
207 return ATH9K_MODE_11G;
208 return ATH9K_MODE_11A;
209 }
210
211 static bool ath9k_hw_wait(struct ath_hal *ah,
212 u32 reg,
213 u32 mask,
214 u32 val)
215 {
216 int i;
217
218 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
219 if ((REG_READ(ah, reg) & mask) == val)
220 return true;
221
222 udelay(AH_TIME_QUANTUM);
223 }
224 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
225 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
226 __func__, reg, REG_READ(ah, reg), mask, val);
227 return false;
228 }
229
230 static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off,
231 u16 *data)
232 {
233 (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
234
235 if (!ath9k_hw_wait(ah,
236 AR_EEPROM_STATUS_DATA,
237 AR_EEPROM_STATUS_DATA_BUSY |
238 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
239 return false;
240 }
241
242 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
243 AR_EEPROM_STATUS_DATA_VAL);
244
245 return true;
246 }
247
248 static int ath9k_hw_flash_map(struct ath_hal *ah)
249 {
250 struct ath_hal_5416 *ahp = AH5416(ah);
251
252 ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
253
254 if (!ahp->ah_cal_mem) {
255 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
256 "%s: cannot remap eeprom region \n", __func__);
257 return -EIO;
258 }
259
260 return 0;
261 }
262
263 static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off,
264 u16 *data)
265 {
266 struct ath_hal_5416 *ahp = AH5416(ah);
267
268 *data = ioread16(ahp->ah_cal_mem + off);
269 return true;
270 }
271
272 static void ath9k_hw_read_revisions(struct ath_hal *ah)
273 {
274 u32 val;
275
276 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
277
278 if (val == 0xFF) {
279 val = REG_READ(ah, AR_SREV);
280
281 ah->ah_macVersion =
282 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
283
284 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
285 ah->ah_isPciExpress =
286 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
287
288 } else {
289 if (!AR_SREV_9100(ah))
290 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
291
292 ah->ah_macRev = val & AR_SREV_REVISION;
293
294 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
295 ah->ah_isPciExpress = true;
296 }
297 }
298
299 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
300 {
301 u32 retval;
302 int i;
303
304 for (i = 0, retval = 0; i < n; i++) {
305 retval = (retval << 1) | (val & 1);
306 val >>= 1;
307 }
308 return retval;
309 }
310
311 static void ath9k_hw_set_defaults(struct ath_hal *ah)
312 {
313 int i;
314
315 ah->ah_config.dma_beacon_response_time = 2;
316 ah->ah_config.sw_beacon_response_time = 10;
317 ah->ah_config.additional_swba_backoff = 0;
318 ah->ah_config.ack_6mb = 0x0;
319 ah->ah_config.cwm_ignore_extcca = 0;
320 ah->ah_config.pcie_powersave_enable = 0;
321 ah->ah_config.pcie_l1skp_enable = 0;
322 ah->ah_config.pcie_clock_req = 0;
323 ah->ah_config.pcie_power_reset = 0x100;
324 ah->ah_config.pcie_restore = 0;
325 ah->ah_config.pcie_waen = 0;
326 ah->ah_config.analog_shiftreg = 1;
327 ah->ah_config.ht_enable = 1;
328 ah->ah_config.ofdm_trig_low = 200;
329 ah->ah_config.ofdm_trig_high = 500;
330 ah->ah_config.cck_trig_high = 200;
331 ah->ah_config.cck_trig_low = 100;
332 ah->ah_config.enable_ani = 1;
333 ah->ah_config.noise_immunity_level = 4;
334 ah->ah_config.ofdm_weaksignal_det = 1;
335 ah->ah_config.cck_weaksignal_thr = 0;
336 ah->ah_config.spur_immunity_level = 2;
337 ah->ah_config.firstep_level = 0;
338 ah->ah_config.rssi_thr_high = 40;
339 ah->ah_config.rssi_thr_low = 7;
340 ah->ah_config.diversity_control = 0;
341 ah->ah_config.antenna_switch_swap = 0;
342
343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
344 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
345 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
346 }
347
348 ah->ah_config.intr_mitigation = 0;
349 }
350
351 static void ath9k_hw_override_ini(struct ath_hal *ah,
352 struct ath9k_channel *chan)
353 {
354 if (!AR_SREV_5416_V20_OR_LATER(ah)
355 || AR_SREV_9280_10_OR_LATER(ah))
356 return;
357
358 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
359 }
360
361 static void ath9k_hw_init_bb(struct ath_hal *ah,
362 struct ath9k_channel *chan)
363 {
364 u32 synthDelay;
365
366 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
367 if (IS_CHAN_CCK(chan))
368 synthDelay = (4 * synthDelay) / 22;
369 else
370 synthDelay /= 10;
371
372 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
373
374 udelay(synthDelay + BASE_ACTIVATE_DELAY);
375 }
376
377 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
378 enum ath9k_opmode opmode)
379 {
380 struct ath_hal_5416 *ahp = AH5416(ah);
381
382 ahp->ah_maskReg = AR_IMR_TXERR |
383 AR_IMR_TXURN |
384 AR_IMR_RXERR |
385 AR_IMR_RXORN |
386 AR_IMR_BCNMISC;
387
388 if (ahp->ah_intrMitigation)
389 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
390 else
391 ahp->ah_maskReg |= AR_IMR_RXOK;
392
393 ahp->ah_maskReg |= AR_IMR_TXOK;
394
395 if (opmode == ATH9K_M_HOSTAP)
396 ahp->ah_maskReg |= AR_IMR_MIB;
397
398 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
399 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
400
401 if (!AR_SREV_9100(ah)) {
402 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
403 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
404 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
405 }
406 }
407
408 static void ath9k_hw_init_qos(struct ath_hal *ah)
409 {
410 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
411 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
412
413 REG_WRITE(ah, AR_QOS_NO_ACK,
414 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
415 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
416 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
417
418 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
419 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
420 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
421 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
422 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
423 }
424
425 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
426 u32 reg,
427 u32 mask,
428 u32 shift,
429 u32 val)
430 {
431 u32 regVal;
432
433 regVal = REG_READ(ah, reg) & ~mask;
434 regVal |= (val << shift) & mask;
435
436 REG_WRITE(ah, reg, regVal);
437
438 if (ah->ah_config.analog_shiftreg)
439 udelay(100);
440
441 return;
442 }
443
444 static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
445 enum ieee80211_band freq_band)
446 {
447 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
448 struct modal_eep_header *pModal =
449 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]);
450 struct base_eep_header *pBase = &eep->baseEepHeader;
451 u8 num_ant_config;
452
453 num_ant_config = 1;
454
455 if (pBase->version >= 0x0E0D)
456 if (pModal->useAnt1)
457 num_ant_config += 1;
458
459 return num_ant_config;
460 }
461
462 static int
463 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
464 struct ath9k_channel *chan,
465 u8 index,
466 u16 *config)
467 {
468 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
469 struct modal_eep_header *pModal =
470 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
471 struct base_eep_header *pBase = &eep->baseEepHeader;
472
473 switch (index) {
474 case 0:
475 *config = pModal->antCtrlCommon & 0xFFFF;
476 return 0;
477 case 1:
478 if (pBase->version >= 0x0E0D) {
479 if (pModal->useAnt1) {
480 *config =
481 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
482 return 0;
483 }
484 }
485 break;
486 default:
487 break;
488 }
489
490 return -EINVAL;
491 }
492
493 static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
494 u32 off,
495 u16 *data)
496 {
497 if (ath9k_hw_use_flash(ah))
498 return ath9k_hw_flash_read(ah, off, data);
499 else
500 return ath9k_hw_eeprom_read(ah, off, data);
501 }
502
503 static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
504 {
505 struct ath_hal_5416 *ahp = AH5416(ah);
506 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
507 u16 *eep_data;
508 int addr, ar5416_eep_start_loc = 0;
509
510 if (!ath9k_hw_use_flash(ah)) {
511 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
512 "%s: Reading from EEPROM, not flash\n", __func__);
513 ar5416_eep_start_loc = 256;
514 }
515 if (AR_SREV_9100(ah))
516 ar5416_eep_start_loc = 256;
517
518 eep_data = (u16 *) eep;
519 for (addr = 0;
520 addr < sizeof(struct ar5416_eeprom) / sizeof(u16);
521 addr++) {
522 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
523 eep_data)) {
524 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
525 "%s: Unable to read eeprom region \n",
526 __func__);
527 return false;
528 }
529 eep_data++;
530 }
531 return true;
532 }
533
534 /* XXX: Clean me up, make me more legible */
535 static bool
536 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
537 struct ath9k_channel *chan)
538 {
539 struct modal_eep_header *pModal;
540 int i, regChainOffset;
541 struct ath_hal_5416 *ahp = AH5416(ah);
542 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
543 u8 txRxAttenLocal;
544 u16 ant_config;
545
546 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
547
548 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
549
550 ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config);
551 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
552
553 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
554 if (AR_SREV_9280(ah)) {
555 if (i >= 2)
556 break;
557 }
558
559 if (AR_SREV_5416_V20_OR_LATER(ah) &&
560 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
561 && (i != 0))
562 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
563 else
564 regChainOffset = i * 0x1000;
565
566 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
567 pModal->antCtrlChain[i]);
568
569 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
570 (REG_READ(ah,
571 AR_PHY_TIMING_CTRL4(0) +
572 regChainOffset) &
573 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
574 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
575 SM(pModal->iqCalICh[i],
576 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
577 SM(pModal->iqCalQCh[i],
578 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
579
580 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
581 if ((eep->baseEepHeader.version &
582 AR5416_EEP_VER_MINOR_MASK) >=
583 AR5416_EEP_MINOR_VER_3) {
584 txRxAttenLocal = pModal->txRxAttenCh[i];
585 if (AR_SREV_9280_10_OR_LATER(ah)) {
586 REG_RMW_FIELD(ah,
587 AR_PHY_GAIN_2GHZ +
588 regChainOffset,
589 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
590 pModal->
591 bswMargin[i]);
592 REG_RMW_FIELD(ah,
593 AR_PHY_GAIN_2GHZ +
594 regChainOffset,
595 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
596 pModal->
597 bswAtten[i]);
598 REG_RMW_FIELD(ah,
599 AR_PHY_GAIN_2GHZ +
600 regChainOffset,
601 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
602 pModal->
603 xatten2Margin[i]);
604 REG_RMW_FIELD(ah,
605 AR_PHY_GAIN_2GHZ +
606 regChainOffset,
607 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
608 pModal->
609 xatten2Db[i]);
610 } else {
611 REG_WRITE(ah,
612 AR_PHY_GAIN_2GHZ +
613 regChainOffset,
614 (REG_READ(ah,
615 AR_PHY_GAIN_2GHZ +
616 regChainOffset) &
617 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
618 | SM(pModal->
619 bswMargin[i],
620 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
621 REG_WRITE(ah,
622 AR_PHY_GAIN_2GHZ +
623 regChainOffset,
624 (REG_READ(ah,
625 AR_PHY_GAIN_2GHZ +
626 regChainOffset) &
627 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
628 | SM(pModal->bswAtten[i],
629 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
630 }
631 }
632 if (AR_SREV_9280_10_OR_LATER(ah)) {
633 REG_RMW_FIELD(ah,
634 AR_PHY_RXGAIN +
635 regChainOffset,
636 AR9280_PHY_RXGAIN_TXRX_ATTEN,
637 txRxAttenLocal);
638 REG_RMW_FIELD(ah,
639 AR_PHY_RXGAIN +
640 regChainOffset,
641 AR9280_PHY_RXGAIN_TXRX_MARGIN,
642 pModal->rxTxMarginCh[i]);
643 } else {
644 REG_WRITE(ah,
645 AR_PHY_RXGAIN + regChainOffset,
646 (REG_READ(ah,
647 AR_PHY_RXGAIN +
648 regChainOffset) &
649 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
650 SM(txRxAttenLocal,
651 AR_PHY_RXGAIN_TXRX_ATTEN));
652 REG_WRITE(ah,
653 AR_PHY_GAIN_2GHZ +
654 regChainOffset,
655 (REG_READ(ah,
656 AR_PHY_GAIN_2GHZ +
657 regChainOffset) &
658 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
659 SM(pModal->rxTxMarginCh[i],
660 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
661 }
662 }
663 }
664
665 if (AR_SREV_9280_10_OR_LATER(ah)) {
666 if (IS_CHAN_2GHZ(chan)) {
667 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
668 AR_AN_RF2G1_CH0_OB,
669 AR_AN_RF2G1_CH0_OB_S,
670 pModal->ob);
671 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
672 AR_AN_RF2G1_CH0_DB,
673 AR_AN_RF2G1_CH0_DB_S,
674 pModal->db);
675 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
676 AR_AN_RF2G1_CH1_OB,
677 AR_AN_RF2G1_CH1_OB_S,
678 pModal->ob_ch1);
679 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
680 AR_AN_RF2G1_CH1_DB,
681 AR_AN_RF2G1_CH1_DB_S,
682 pModal->db_ch1);
683 } else {
684 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
685 AR_AN_RF5G1_CH0_OB5,
686 AR_AN_RF5G1_CH0_OB5_S,
687 pModal->ob);
688 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
689 AR_AN_RF5G1_CH0_DB5,
690 AR_AN_RF5G1_CH0_DB5_S,
691 pModal->db);
692 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
693 AR_AN_RF5G1_CH1_OB5,
694 AR_AN_RF5G1_CH1_OB5_S,
695 pModal->ob_ch1);
696 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
697 AR_AN_RF5G1_CH1_DB5,
698 AR_AN_RF5G1_CH1_DB5_S,
699 pModal->db_ch1);
700 }
701 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
702 AR_AN_TOP2_XPABIAS_LVL,
703 AR_AN_TOP2_XPABIAS_LVL_S,
704 pModal->xpaBiasLvl);
705 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
706 AR_AN_TOP2_LOCALBIAS,
707 AR_AN_TOP2_LOCALBIAS_S,
708 pModal->local_bias);
709 DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
710 pModal->force_xpaon);
711 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
712 pModal->force_xpaon);
713 }
714
715 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
716 pModal->switchSettling);
717 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
718 pModal->adcDesiredSize);
719
720 if (!AR_SREV_9280_10_OR_LATER(ah))
721 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
722 AR_PHY_DESIRED_SZ_PGA,
723 pModal->pgaDesiredSize);
724
725 REG_WRITE(ah, AR_PHY_RF_CTL4,
726 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
727 | SM(pModal->txEndToXpaOff,
728 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
729 | SM(pModal->txFrameToXpaOn,
730 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
731 | SM(pModal->txFrameToXpaOn,
732 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
733
734 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
735 pModal->txEndToRxOn);
736 if (AR_SREV_9280_10_OR_LATER(ah)) {
737 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
738 pModal->thresh62);
739 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
740 AR_PHY_EXT_CCA0_THRESH62,
741 pModal->thresh62);
742 } else {
743 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
744 pModal->thresh62);
745 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
746 AR_PHY_EXT_CCA_THRESH62,
747 pModal->thresh62);
748 }
749
750 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
751 AR5416_EEP_MINOR_VER_2) {
752 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
753 AR_PHY_TX_END_DATA_START,
754 pModal->txFrameToDataStart);
755 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
756 pModal->txFrameToPaOn);
757 }
758
759 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
760 AR5416_EEP_MINOR_VER_3) {
761 if (IS_CHAN_HT40(chan))
762 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
763 AR_PHY_SETTLING_SWITCH,
764 pModal->swSettleHt40);
765 }
766
767 return true;
768 }
769
770 static int ath9k_hw_check_eeprom(struct ath_hal *ah)
771 {
772 u32 sum = 0, el;
773 u16 *eepdata;
774 int i;
775 struct ath_hal_5416 *ahp = AH5416(ah);
776 bool need_swap = false;
777 struct ar5416_eeprom *eep =
778 (struct ar5416_eeprom *) &ahp->ah_eeprom;
779
780 if (!ath9k_hw_use_flash(ah)) {
781 u16 magic, magic2;
782 int addr;
783
784 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
785 &magic)) {
786 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
787 "%s: Reading Magic # failed\n", __func__);
788 return false;
789 }
790 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
791 __func__, magic);
792
793 if (magic != AR5416_EEPROM_MAGIC) {
794 magic2 = swab16(magic);
795
796 if (magic2 == AR5416_EEPROM_MAGIC) {
797 need_swap = true;
798 eepdata = (u16 *) (&ahp->ah_eeprom);
799
800 for (addr = 0;
801 addr <
802 sizeof(struct ar5416_eeprom) /
803 sizeof(u16); addr++) {
804 u16 temp;
805
806 temp = swab16(*eepdata);
807 *eepdata = temp;
808 eepdata++;
809
810 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
811 "0x%04X ", *eepdata);
812 if (((addr + 1) % 6) == 0)
813 DPRINTF(ah->ah_sc,
814 ATH_DBG_EEPROM,
815 "\n");
816 }
817 } else {
818 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
819 "Invalid EEPROM Magic. "
820 "endianness missmatch.\n");
821 return -EINVAL;
822 }
823 }
824 }
825 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
826 need_swap ? "True" : "False");
827
828 if (need_swap)
829 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
830 else
831 el = ahp->ah_eeprom.baseEepHeader.length;
832
833 if (el > sizeof(struct ar5416_eeprom))
834 el = sizeof(struct ar5416_eeprom) / sizeof(u16);
835 else
836 el = el / sizeof(u16);
837
838 eepdata = (u16 *) (&ahp->ah_eeprom);
839
840 for (i = 0; i < el; i++)
841 sum ^= *eepdata++;
842
843 if (need_swap) {
844 u32 integer, j;
845 u16 word;
846
847 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
848 "EEPROM Endianness is not native.. Changing \n");
849
850 word = swab16(eep->baseEepHeader.length);
851 eep->baseEepHeader.length = word;
852
853 word = swab16(eep->baseEepHeader.checksum);
854 eep->baseEepHeader.checksum = word;
855
856 word = swab16(eep->baseEepHeader.version);
857 eep->baseEepHeader.version = word;
858
859 word = swab16(eep->baseEepHeader.regDmn[0]);
860 eep->baseEepHeader.regDmn[0] = word;
861
862 word = swab16(eep->baseEepHeader.regDmn[1]);
863 eep->baseEepHeader.regDmn[1] = word;
864
865 word = swab16(eep->baseEepHeader.rfSilent);
866 eep->baseEepHeader.rfSilent = word;
867
868 word = swab16(eep->baseEepHeader.blueToothOptions);
869 eep->baseEepHeader.blueToothOptions = word;
870
871 word = swab16(eep->baseEepHeader.deviceCap);
872 eep->baseEepHeader.deviceCap = word;
873
874 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
875 struct modal_eep_header *pModal =
876 &eep->modalHeader[j];
877 integer = swab32(pModal->antCtrlCommon);
878 pModal->antCtrlCommon = integer;
879
880 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
881 integer = swab32(pModal->antCtrlChain[i]);
882 pModal->antCtrlChain[i] = integer;
883 }
884
885 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
886 word = swab16(pModal->spurChans[i].spurChan);
887 pModal->spurChans[i].spurChan = word;
888 }
889 }
890 }
891
892 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
893 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
894 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
895 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
896 sum, ar5416_get_eep_ver(ahp));
897 return -EINVAL;
898 }
899
900 return 0;
901 }
902
903 static bool ath9k_hw_chip_test(struct ath_hal *ah)
904 {
905 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
906 u32 regHold[2];
907 u32 patternData[4] = { 0x55555555,
908 0xaaaaaaaa,
909 0x66666666,
910 0x99999999 };
911 int i, j;
912
913 for (i = 0; i < 2; i++) {
914 u32 addr = regAddr[i];
915 u32 wrData, rdData;
916
917 regHold[i] = REG_READ(ah, addr);
918 for (j = 0; j < 0x100; j++) {
919 wrData = (j << 16) | j;
920 REG_WRITE(ah, addr, wrData);
921 rdData = REG_READ(ah, addr);
922 if (rdData != wrData) {
923 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
924 "%s: address test failed "
925 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
926 __func__, addr, wrData, rdData);
927 return false;
928 }
929 }
930 for (j = 0; j < 4; j++) {
931 wrData = patternData[j];
932 REG_WRITE(ah, addr, wrData);
933 rdData = REG_READ(ah, addr);
934 if (wrData != rdData) {
935 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
936 "%s: address test failed "
937 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
938 __func__, addr, wrData, rdData);
939 return false;
940 }
941 }
942 REG_WRITE(ah, regAddr[i], regHold[i]);
943 }
944 udelay(100);
945 return true;
946 }
947
948 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
949 {
950 u32 bits = REG_READ(ah, AR_RX_FILTER);
951 u32 phybits = REG_READ(ah, AR_PHY_ERR);
952
953 if (phybits & AR_PHY_ERR_RADAR)
954 bits |= ATH9K_RX_FILTER_PHYRADAR;
955 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
956 bits |= ATH9K_RX_FILTER_PHYERR;
957 return bits;
958 }
959
960 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
961 {
962 u32 phybits;
963
964 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
965 phybits = 0;
966 if (bits & ATH9K_RX_FILTER_PHYRADAR)
967 phybits |= AR_PHY_ERR_RADAR;
968 if (bits & ATH9K_RX_FILTER_PHYERR)
969 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
970 REG_WRITE(ah, AR_PHY_ERR, phybits);
971
972 if (phybits)
973 REG_WRITE(ah, AR_RXCFG,
974 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
975 else
976 REG_WRITE(ah, AR_RXCFG,
977 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
978 }
979
980 bool ath9k_hw_setcapability(struct ath_hal *ah,
981 enum ath9k_capability_type type,
982 u32 capability,
983 u32 setting,
984 int *status)
985 {
986 struct ath_hal_5416 *ahp = AH5416(ah);
987 u32 v;
988
989 switch (type) {
990 case ATH9K_CAP_TKIP_MIC:
991 if (setting)
992 ahp->ah_staId1Defaults |=
993 AR_STA_ID1_CRPT_MIC_ENABLE;
994 else
995 ahp->ah_staId1Defaults &=
996 ~AR_STA_ID1_CRPT_MIC_ENABLE;
997 return true;
998 case ATH9K_CAP_DIVERSITY:
999 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1000 if (setting)
1001 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1002 else
1003 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1004 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1005 return true;
1006 case ATH9K_CAP_MCAST_KEYSRCH:
1007 if (setting)
1008 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1009 else
1010 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1011 return true;
1012 case ATH9K_CAP_TSF_ADJUST:
1013 if (setting)
1014 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1015 else
1016 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1017 return true;
1018 default:
1019 return false;
1020 }
1021 }
1022
1023 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1024 {
1025 u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
1026 int qcuOffset = 0, dcuOffset = 0;
1027 u32 *qcuBase = &val[0], *dcuBase = &val[4];
1028 int i;
1029
1030 REG_WRITE(ah, AR_MACMISC,
1031 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1032 (AR_MACMISC_MISC_OBS_BUS_1 <<
1033 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1034
1035 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
1036 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1037 if (i % 4 == 0)
1038 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1039
1040 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
1041 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
1042 }
1043
1044 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
1045 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1046 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1047
1048 for (i = 0; i < ATH9K_NUM_QUEUES;
1049 i++, qcuOffset += 4, dcuOffset += 5) {
1050 if (i == 8) {
1051 qcuOffset = 0;
1052 qcuBase++;
1053 }
1054
1055 if (i == 6) {
1056 dcuOffset = 0;
1057 dcuBase++;
1058 }
1059
1060 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1061 "%2d %2x %1x %2x %2x\n",
1062 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1063 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1064 3),
1065 val[2] & (0x7 << (i * 3)) >> (i * 3),
1066 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1067 }
1068
1069 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1070 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1071 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1072 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1073 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1074 "qcu_complete state: %2x dcu_complete state: %2x\n",
1075 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1076 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1077 "dcu_arb state: %2x dcu_fp state: %2x\n",
1078 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1079 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1080 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1081 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1082 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1083 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1084 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1085 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1086 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1087 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1088
1089 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
1090 REG_READ(ah, AR_OBS_BUS_1));
1091 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1092 "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1093 }
1094
1095 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1096 u32 *rxc_pcnt,
1097 u32 *rxf_pcnt,
1098 u32 *txf_pcnt)
1099 {
1100 static u32 cycles, rx_clear, rx_frame, tx_frame;
1101 u32 good = 1;
1102
1103 u32 rc = REG_READ(ah, AR_RCCNT);
1104 u32 rf = REG_READ(ah, AR_RFCNT);
1105 u32 tf = REG_READ(ah, AR_TFCNT);
1106 u32 cc = REG_READ(ah, AR_CCCNT);
1107
1108 if (cycles == 0 || cycles > cc) {
1109 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1110 "%s: cycle counter wrap. ExtBusy = 0\n",
1111 __func__);
1112 good = 0;
1113 } else {
1114 u32 cc_d = cc - cycles;
1115 u32 rc_d = rc - rx_clear;
1116 u32 rf_d = rf - rx_frame;
1117 u32 tf_d = tf - tx_frame;
1118
1119 if (cc_d != 0) {
1120 *rxc_pcnt = rc_d * 100 / cc_d;
1121 *rxf_pcnt = rf_d * 100 / cc_d;
1122 *txf_pcnt = tf_d * 100 / cc_d;
1123 } else {
1124 good = 0;
1125 }
1126 }
1127
1128 cycles = cc;
1129 rx_frame = rf;
1130 rx_clear = rc;
1131 tx_frame = tf;
1132
1133 return good;
1134 }
1135
1136 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
1137 {
1138 u32 macmode;
1139
1140 if (mode == ATH9K_HT_MACMODE_2040 &&
1141 !ah->ah_config.cwm_ignore_extcca)
1142 macmode = AR_2040_JOINED_RX_CLEAR;
1143 else
1144 macmode = 0;
1145
1146 REG_WRITE(ah, AR_2040_MODE, macmode);
1147 }
1148
1149 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1150 {
1151 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1152 }
1153
1154
1155 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1156 struct ath_softc *sc,
1157 void __iomem *mem,
1158 int *status)
1159 {
1160 static const u8 defbssidmask[ETH_ALEN] =
1161 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1162 struct ath_hal_5416 *ahp;
1163 struct ath_hal *ah;
1164
1165 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1166 if (ahp == NULL) {
1167 DPRINTF(sc, ATH_DBG_FATAL,
1168 "%s: cannot allocate memory for state block\n",
1169 __func__);
1170 *status = -ENOMEM;
1171 return NULL;
1172 }
1173
1174 ah = &ahp->ah;
1175
1176 ah->ah_sc = sc;
1177 ah->ah_sh = mem;
1178
1179 ah->ah_magic = AR5416_MAGIC;
1180 ah->ah_countryCode = CTRY_DEFAULT;
1181
1182 ah->ah_devid = devid;
1183 ah->ah_subvendorid = 0;
1184
1185 ah->ah_flags = 0;
1186 if ((devid == AR5416_AR9100_DEVID))
1187 ah->ah_macVersion = AR_SREV_VERSION_9100;
1188 if (!AR_SREV_9100(ah))
1189 ah->ah_flags = AH_USE_EEPROM;
1190
1191 ah->ah_powerLimit = MAX_RATE_POWER;
1192 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
1193
1194 ahp->ah_atimWindow = 0;
1195 ahp->ah_diversityControl = ah->ah_config.diversity_control;
1196 ahp->ah_antennaSwitchSwap =
1197 ah->ah_config.antenna_switch_swap;
1198
1199 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1200 ahp->ah_beaconInterval = 100;
1201 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
1202 ahp->ah_slottime = (u32) -1;
1203 ahp->ah_acktimeout = (u32) -1;
1204 ahp->ah_ctstimeout = (u32) -1;
1205 ahp->ah_globaltxtimeout = (u32) -1;
1206 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
1207
1208 ahp->ah_gBeaconRate = 0;
1209
1210 return ahp;
1211 }
1212
1213 static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1214 {
1215 int status;
1216
1217 if (ath9k_hw_use_flash(ah))
1218 ath9k_hw_flash_map(ah);
1219
1220 if (!ath9k_hw_fill_eeprom(ah))
1221 return -EIO;
1222
1223 status = ath9k_hw_check_eeprom(ah);
1224
1225 return status;
1226 }
1227
1228 u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1229 enum eeprom_param param)
1230 {
1231 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1232 struct modal_eep_header *pModal = eep->modalHeader;
1233 struct base_eep_header *pBase = &eep->baseEepHeader;
1234
1235 switch (param) {
1236 case EEP_NFTHRESH_5:
1237 return -pModal[0].noiseFloorThreshCh[0];
1238 case EEP_NFTHRESH_2:
1239 return -pModal[1].noiseFloorThreshCh[0];
1240 case AR_EEPROM_MAC(0):
1241 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1242 case AR_EEPROM_MAC(1):
1243 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1244 case AR_EEPROM_MAC(2):
1245 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1246 case EEP_REG_0:
1247 return pBase->regDmn[0];
1248 case EEP_REG_1:
1249 return pBase->regDmn[1];
1250 case EEP_OP_CAP:
1251 return pBase->deviceCap;
1252 case EEP_OP_MODE:
1253 return pBase->opCapFlags;
1254 case EEP_RF_SILENT:
1255 return pBase->rfSilent;
1256 case EEP_OB_5:
1257 return pModal[0].ob;
1258 case EEP_DB_5:
1259 return pModal[0].db;
1260 case EEP_OB_2:
1261 return pModal[1].ob;
1262 case EEP_DB_2:
1263 return pModal[1].db;
1264 case EEP_MINOR_REV:
1265 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1266 case EEP_TX_MASK:
1267 return pBase->txMask;
1268 case EEP_RX_MASK:
1269 return pBase->rxMask;
1270 default:
1271 return 0;
1272 }
1273 }
1274
1275 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
1276 {
1277 u32 val;
1278 int i;
1279
1280 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1281 for (i = 0; i < 8; i++)
1282 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1283 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1284 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1285 return ath9k_hw_reverse_bits(val, 8);
1286 }
1287
1288 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
1289 {
1290 u32 sum;
1291 int i;
1292 u16 eeval;
1293 struct ath_hal_5416 *ahp = AH5416(ah);
1294 DECLARE_MAC_BUF(mac);
1295
1296 sum = 0;
1297 for (i = 0; i < 3; i++) {
1298 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1299 sum += eeval;
1300 ahp->ah_macaddr[2 * i] = eeval >> 8;
1301 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1302 }
1303 if (sum == 0 || sum == 0xffff * 3) {
1304 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1305 "%s: mac address read failed: %s\n", __func__,
1306 print_mac(mac, ahp->ah_macaddr));
1307 return -EADDRNOTAVAIL;
1308 }
1309
1310 return 0;
1311 }
1312
1313 static inline int16_t ath9k_hw_interpolate(u16 target,
1314 u16 srcLeft,
1315 u16 srcRight,
1316 int16_t targetLeft,
1317 int16_t targetRight)
1318 {
1319 int16_t rv;
1320
1321 if (srcRight == srcLeft) {
1322 rv = targetLeft;
1323 } else {
1324 rv = (int16_t) (((target - srcLeft) * targetRight +
1325 (srcRight - target) * targetLeft) /
1326 (srcRight - srcLeft));
1327 }
1328 return rv;
1329 }
1330
1331 static inline u16 ath9k_hw_fbin2freq(u8 fbin,
1332 bool is2GHz)
1333 {
1334
1335 if (fbin == AR5416_BCHAN_UNUSED)
1336 return fbin;
1337
1338 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1339 }
1340
1341 static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1342 u16 i,
1343 bool is2GHz)
1344 {
1345 struct ath_hal_5416 *ahp = AH5416(ah);
1346 struct ar5416_eeprom *eep =
1347 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1348 u16 spur_val = AR_NO_SPUR;
1349
1350 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1351 "Getting spur idx %d is2Ghz. %d val %x\n",
1352 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1353
1354 switch (ah->ah_config.spurmode) {
1355 case SPUR_DISABLE:
1356 break;
1357 case SPUR_ENABLE_IOCTL:
1358 spur_val = ah->ah_config.spurchans[i][is2GHz];
1359 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1360 "Getting spur val from new loc. %d\n", spur_val);
1361 break;
1362 case SPUR_ENABLE_EEPROM:
1363 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1364 break;
1365
1366 }
1367 return spur_val;
1368 }
1369
1370 static int ath9k_hw_rfattach(struct ath_hal *ah)
1371 {
1372 bool rfStatus = false;
1373 int ecode = 0;
1374
1375 rfStatus = ath9k_hw_init_rf(ah, &ecode);
1376 if (!rfStatus) {
1377 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1378 "%s: RF setup failed, status %u\n", __func__,
1379 ecode);
1380 return ecode;
1381 }
1382
1383 return 0;
1384 }
1385
1386 static int ath9k_hw_rf_claim(struct ath_hal *ah)
1387 {
1388 u32 val;
1389
1390 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1391
1392 val = ath9k_hw_get_radiorev(ah);
1393 switch (val & AR_RADIO_SREV_MAJOR) {
1394 case 0:
1395 val = AR_RAD5133_SREV_MAJOR;
1396 break;
1397 case AR_RAD5133_SREV_MAJOR:
1398 case AR_RAD5122_SREV_MAJOR:
1399 case AR_RAD2133_SREV_MAJOR:
1400 case AR_RAD2122_SREV_MAJOR:
1401 break;
1402 default:
1403 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1404 "%s: 5G Radio Chip Rev 0x%02X is not "
1405 "supported by this driver\n",
1406 __func__, ah->ah_analog5GhzRev);
1407 return -EOPNOTSUPP;
1408 }
1409
1410 ah->ah_analog5GhzRev = val;
1411
1412 return 0;
1413 }
1414
1415 static void ath9k_hw_init_pll(struct ath_hal *ah,
1416 struct ath9k_channel *chan)
1417 {
1418 u32 pll;
1419
1420 if (AR_SREV_9100(ah)) {
1421 if (chan && IS_CHAN_5GHZ(chan))
1422 pll = 0x1450;
1423 else
1424 pll = 0x1458;
1425 } else {
1426 if (AR_SREV_9280_10_OR_LATER(ah)) {
1427 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1428
1429 if (chan && IS_CHAN_HALF_RATE(chan))
1430 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1431 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1432 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1433
1434 if (chan && IS_CHAN_5GHZ(chan)) {
1435 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1436
1437
1438 if (AR_SREV_9280_20(ah)) {
1439 if (((chan->channel % 20) == 0)
1440 || ((chan->channel % 10) == 0))
1441 pll = 0x2850;
1442 else
1443 pll = 0x142c;
1444 }
1445 } else {
1446 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1447 }
1448
1449 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1450
1451 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1452
1453 if (chan && IS_CHAN_HALF_RATE(chan))
1454 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1455 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1456 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1457
1458 if (chan && IS_CHAN_5GHZ(chan))
1459 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1460 else
1461 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1462 } else {
1463 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1464
1465 if (chan && IS_CHAN_HALF_RATE(chan))
1466 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1467 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1468 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1469
1470 if (chan && IS_CHAN_5GHZ(chan))
1471 pll |= SM(0xa, AR_RTC_PLL_DIV);
1472 else
1473 pll |= SM(0xb, AR_RTC_PLL_DIV);
1474 }
1475 }
1476 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1477
1478 udelay(RTC_PLL_SETTLE_DELAY);
1479
1480 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1481 }
1482
1483 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1484 enum ath9k_ht_macmode macmode)
1485 {
1486 u32 phymode;
1487 struct ath_hal_5416 *ahp = AH5416(ah);
1488
1489 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1490 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1491
1492 if (IS_CHAN_HT40(chan)) {
1493 phymode |= AR_PHY_FC_DYN2040_EN;
1494
1495 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1496 (chan->chanmode == CHANNEL_G_HT40PLUS))
1497 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1498
1499 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1500 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1501 }
1502 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1503
1504 ath9k_hw_set11nmac2040(ah, macmode);
1505
1506 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1507 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1508 }
1509
1510 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1511 {
1512 u32 val;
1513
1514 val = REG_READ(ah, AR_STA_ID1);
1515 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1516 switch (opmode) {
1517 case ATH9K_M_HOSTAP:
1518 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1519 | AR_STA_ID1_KSRCH_MODE);
1520 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1521 break;
1522 case ATH9K_M_IBSS:
1523 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1524 | AR_STA_ID1_KSRCH_MODE);
1525 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1526 break;
1527 case ATH9K_M_STA:
1528 case ATH9K_M_MONITOR:
1529 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1530 break;
1531 }
1532 }
1533
1534 static void
1535 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1536 {
1537 u32 rfMode = 0;
1538
1539 if (chan == NULL)
1540 return;
1541
1542 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1543 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1544
1545 if (!AR_SREV_9280_10_OR_LATER(ah))
1546 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1547 AR_PHY_MODE_RF2GHZ;
1548
1549 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1550 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1551
1552 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1553 }
1554
1555 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1556 {
1557 u32 rst_flags;
1558 u32 tmpReg;
1559
1560 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1561 AR_RTC_FORCE_WAKE_ON_INT);
1562
1563 if (AR_SREV_9100(ah)) {
1564 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1565 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1566 } else {
1567 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1568 if (tmpReg &
1569 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1570 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1571 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1572 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1573 } else {
1574 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1575 }
1576
1577 rst_flags = AR_RTC_RC_MAC_WARM;
1578 if (type == ATH9K_RESET_COLD)
1579 rst_flags |= AR_RTC_RC_MAC_COLD;
1580 }
1581
1582 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1583 udelay(50);
1584
1585 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1586 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1587 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1588 "%s: RTC stuck in MAC reset\n",
1589 __func__);
1590 return false;
1591 }
1592
1593 if (!AR_SREV_9100(ah))
1594 REG_WRITE(ah, AR_RC, 0);
1595
1596 ath9k_hw_init_pll(ah, NULL);
1597
1598 if (AR_SREV_9100(ah))
1599 udelay(50);
1600
1601 return true;
1602 }
1603
1604 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1605 {
1606 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1607 AR_RTC_FORCE_WAKE_ON_INT);
1608
1609 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1610 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1611
1612 if (!ath9k_hw_wait(ah,
1613 AR_RTC_STATUS,
1614 AR_RTC_STATUS_M,
1615 AR_RTC_STATUS_ON)) {
1616 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1617 __func__);
1618 return false;
1619 }
1620
1621 ath9k_hw_read_revisions(ah);
1622
1623 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1624 }
1625
1626 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1627 u32 type)
1628 {
1629 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1630 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1631
1632 switch (type) {
1633 case ATH9K_RESET_POWER_ON:
1634 return ath9k_hw_set_reset_power_on(ah);
1635 break;
1636 case ATH9K_RESET_WARM:
1637 case ATH9K_RESET_COLD:
1638 return ath9k_hw_set_reset(ah, type);
1639 break;
1640 default:
1641 return false;
1642 }
1643 }
1644
1645 static
1646 struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1647 struct ath9k_channel *chan)
1648 {
1649 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1650 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1651 "%s: invalid channel %u/0x%x; not marked as "
1652 "2GHz or 5GHz\n", __func__, chan->channel,
1653 chan->channelFlags);
1654 return NULL;
1655 }
1656
1657 if (!IS_CHAN_OFDM(chan) &&
1658 !IS_CHAN_CCK(chan) &&
1659 !IS_CHAN_HT20(chan) &&
1660 !IS_CHAN_HT40(chan)) {
1661 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1662 "%s: invalid channel %u/0x%x; not marked as "
1663 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1664 __func__, chan->channel, chan->channelFlags);
1665 return NULL;
1666 }
1667
1668 return ath9k_regd_check_channel(ah, chan);
1669 }
1670
1671 static inline bool
1672 ath9k_hw_get_lower_upper_index(u8 target,
1673 u8 *pList,
1674 u16 listSize,
1675 u16 *indexL,
1676 u16 *indexR)
1677 {
1678 u16 i;
1679
1680 if (target <= pList[0]) {
1681 *indexL = *indexR = 0;
1682 return true;
1683 }
1684 if (target >= pList[listSize - 1]) {
1685 *indexL = *indexR = (u16) (listSize - 1);
1686 return true;
1687 }
1688
1689 for (i = 0; i < listSize - 1; i++) {
1690 if (pList[i] == target) {
1691 *indexL = *indexR = i;
1692 return true;
1693 }
1694 if (target < pList[i + 1]) {
1695 *indexL = i;
1696 *indexR = (u16) (i + 1);
1697 return false;
1698 }
1699 }
1700 return false;
1701 }
1702
1703 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1704 {
1705 int16_t nfval;
1706 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
1707 int i, j;
1708
1709 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
1710 sort[i] = nfCalBuffer[i];
1711
1712 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
1713 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
1714 if (sort[j] > sort[j - 1]) {
1715 nfval = sort[j];
1716 sort[j] = sort[j - 1];
1717 sort[j - 1] = nfval;
1718 }
1719 }
1720 }
1721 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
1722
1723 return nfval;
1724 }
1725
1726 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
1727 int16_t *nfarray)
1728 {
1729 int i;
1730
1731 for (i = 0; i < NUM_NF_READINGS; i++) {
1732 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1733
1734 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
1735 h[i].currIndex = 0;
1736
1737 if (h[i].invalidNFcount > 0) {
1738 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1739 || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1740 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
1741 } else {
1742 h[i].invalidNFcount--;
1743 h[i].privNF = nfarray[i];
1744 }
1745 } else {
1746 h[i].privNF =
1747 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1748 }
1749 }
1750 return;
1751 }
1752
1753 static void ar5416GetNoiseFloor(struct ath_hal *ah,
1754 int16_t nfarray[NUM_NF_READINGS])
1755 {
1756 int16_t nf;
1757
1758 if (AR_SREV_9280_10_OR_LATER(ah))
1759 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1760 else
1761 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1762
1763 if (nf & 0x100)
1764 nf = 0 - ((nf ^ 0x1ff) + 1);
1765 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1766 "NF calibrated [ctl] [chain 0] is %d\n", nf);
1767 nfarray[0] = nf;
1768
1769 if (AR_SREV_9280_10_OR_LATER(ah))
1770 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1771 AR9280_PHY_CH1_MINCCA_PWR);
1772 else
1773 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1774 AR_PHY_CH1_MINCCA_PWR);
1775
1776 if (nf & 0x100)
1777 nf = 0 - ((nf ^ 0x1ff) + 1);
1778 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1779 "NF calibrated [ctl] [chain 1] is %d\n", nf);
1780 nfarray[1] = nf;
1781
1782 if (!AR_SREV_9280(ah)) {
1783 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1784 AR_PHY_CH2_MINCCA_PWR);
1785 if (nf & 0x100)
1786 nf = 0 - ((nf ^ 0x1ff) + 1);
1787 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1788 "NF calibrated [ctl] [chain 2] is %d\n", nf);
1789 nfarray[2] = nf;
1790 }
1791
1792 if (AR_SREV_9280_10_OR_LATER(ah))
1793 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1794 AR9280_PHY_EXT_MINCCA_PWR);
1795 else
1796 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1797 AR_PHY_EXT_MINCCA_PWR);
1798
1799 if (nf & 0x100)
1800 nf = 0 - ((nf ^ 0x1ff) + 1);
1801 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1802 "NF calibrated [ext] [chain 0] is %d\n", nf);
1803 nfarray[3] = nf;
1804
1805 if (AR_SREV_9280_10_OR_LATER(ah))
1806 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1807 AR9280_PHY_CH1_EXT_MINCCA_PWR);
1808 else
1809 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1810 AR_PHY_CH1_EXT_MINCCA_PWR);
1811
1812 if (nf & 0x100)
1813 nf = 0 - ((nf ^ 0x1ff) + 1);
1814 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1815 "NF calibrated [ext] [chain 1] is %d\n", nf);
1816 nfarray[4] = nf;
1817
1818 if (!AR_SREV_9280(ah)) {
1819 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1820 AR_PHY_CH2_EXT_MINCCA_PWR);
1821 if (nf & 0x100)
1822 nf = 0 - ((nf ^ 0x1ff) + 1);
1823 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1824 "NF calibrated [ext] [chain 2] is %d\n", nf);
1825 nfarray[5] = nf;
1826 }
1827 }
1828
1829 static bool
1830 getNoiseFloorThresh(struct ath_hal *ah,
1831 const struct ath9k_channel *chan,
1832 int16_t *nft)
1833 {
1834 struct ath_hal_5416 *ahp = AH5416(ah);
1835
1836 switch (chan->chanmode) {
1837 case CHANNEL_A:
1838 case CHANNEL_A_HT20:
1839 case CHANNEL_A_HT40PLUS:
1840 case CHANNEL_A_HT40MINUS:
1841 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5);
1842 break;
1843 case CHANNEL_B:
1844 case CHANNEL_G:
1845 case CHANNEL_G_HT20:
1846 case CHANNEL_G_HT40PLUS:
1847 case CHANNEL_G_HT40MINUS:
1848 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1849 break;
1850 default:
1851 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1852 "%s: invalid channel flags 0x%x\n", __func__,
1853 chan->channelFlags);
1854 return false;
1855 }
1856 return true;
1857 }
1858
1859 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1860 {
1861 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1862 AR_PHY_AGC_CONTROL_ENABLE_NF);
1863 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1864 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1865 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1866 }
1867
1868 static void
1869 ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
1870 {
1871 struct ath9k_nfcal_hist *h;
1872 int i, j;
1873 int32_t val;
1874 const u32 ar5416_cca_regs[6] = {
1875 AR_PHY_CCA,
1876 AR_PHY_CH1_CCA,
1877 AR_PHY_CH2_CCA,
1878 AR_PHY_EXT_CCA,
1879 AR_PHY_CH1_EXT_CCA,
1880 AR_PHY_CH2_EXT_CCA
1881 };
1882 u8 chainmask;
1883
1884 if (AR_SREV_9280(ah))
1885 chainmask = 0x1B;
1886 else
1887 chainmask = 0x3F;
1888
1889 #ifdef ATH_NF_PER_CHAN
1890 h = chan->nfCalHist;
1891 #else
1892 h = ah->nfCalHist;
1893 #endif
1894
1895 for (i = 0; i < NUM_NF_READINGS; i++) {
1896 if (chainmask & (1 << i)) {
1897 val = REG_READ(ah, ar5416_cca_regs[i]);
1898 val &= 0xFFFFFE00;
1899 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1900 REG_WRITE(ah, ar5416_cca_regs[i], val);
1901 }
1902 }
1903
1904 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1905 AR_PHY_AGC_CONTROL_ENABLE_NF);
1906 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1907 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1908 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1909
1910 for (j = 0; j < 1000; j++) {
1911 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1912 AR_PHY_AGC_CONTROL_NF) == 0)
1913 break;
1914 udelay(10);
1915 }
1916
1917 for (i = 0; i < NUM_NF_READINGS; i++) {
1918 if (chainmask & (1 << i)) {
1919 val = REG_READ(ah, ar5416_cca_regs[i]);
1920 val &= 0xFFFFFE00;
1921 val |= (((u32) (-50) << 1) & 0x1ff);
1922 REG_WRITE(ah, ar5416_cca_regs[i], val);
1923 }
1924 }
1925 }
1926
1927 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1928 struct ath9k_channel *chan)
1929 {
1930 int16_t nf, nfThresh;
1931 int16_t nfarray[NUM_NF_READINGS] = { 0 };
1932 struct ath9k_nfcal_hist *h;
1933 u8 chainmask;
1934
1935 if (AR_SREV_9280(ah))
1936 chainmask = 0x1B;
1937 else
1938 chainmask = 0x3F;
1939
1940 chan->channelFlags &= (~CHANNEL_CW_INT);
1941 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1942 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1943 "%s: NF did not complete in calibration window\n",
1944 __func__);
1945 nf = 0;
1946 chan->rawNoiseFloor = nf;
1947 return chan->rawNoiseFloor;
1948 } else {
1949 ar5416GetNoiseFloor(ah, nfarray);
1950 nf = nfarray[0];
1951 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1952 && nf > nfThresh) {
1953 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1954 "%s: noise floor failed detected; "
1955 "detected %d, threshold %d\n", __func__,
1956 nf, nfThresh);
1957 chan->channelFlags |= CHANNEL_CW_INT;
1958 }
1959 }
1960
1961 #ifdef ATH_NF_PER_CHAN
1962 h = chan->nfCalHist;
1963 #else
1964 h = ah->nfCalHist;
1965 #endif
1966
1967 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1968 chan->rawNoiseFloor = h[0].privNF;
1969
1970 return chan->rawNoiseFloor;
1971 }
1972
1973 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1974 struct ath9k_mib_stats *stats)
1975 {
1976 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1977 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1978 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1979 stats->rts_good += REG_READ(ah, AR_RTS_OK);
1980 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1981 }
1982
1983 static void ath9k_enable_mib_counters(struct ath_hal *ah)
1984 {
1985 struct ath_hal_5416 *ahp = AH5416(ah);
1986
1987 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
1988
1989 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
1990
1991 REG_WRITE(ah, AR_FILT_OFDM, 0);
1992 REG_WRITE(ah, AR_FILT_CCK, 0);
1993 REG_WRITE(ah, AR_MIBC,
1994 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
1995 & 0x0f);
1996 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1997 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1998 }
1999
2000 static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2001 {
2002 struct ath_hal_5416 *ahp = AH5416(ah);
2003
2004 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
2005
2006 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2007
2008 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2009
2010 REG_WRITE(ah, AR_FILT_OFDM, 0);
2011 REG_WRITE(ah, AR_FILT_CCK, 0);
2012 }
2013
2014 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2015 struct ath9k_channel *chan)
2016 {
2017 struct ath_hal_5416 *ahp = AH5416(ah);
2018 int i;
2019
2020 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2021 if (ahp->ah_ani[i].c.channel == chan->channel)
2022 return i;
2023 if (ahp->ah_ani[i].c.channel == 0) {
2024 ahp->ah_ani[i].c.channel = chan->channel;
2025 ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2026 return i;
2027 }
2028 }
2029
2030 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2031 "No more channel states left. Using channel 0\n");
2032 return 0;
2033 }
2034
2035 static void ath9k_hw_ani_attach(struct ath_hal *ah)
2036 {
2037 struct ath_hal_5416 *ahp = AH5416(ah);
2038 int i;
2039
2040 ahp->ah_hasHwPhyCounters = 1;
2041
2042 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2043 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2044 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
2045 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
2046 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
2047 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
2048 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
2049 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
2050 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2051 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
2052 ahp->ah_ani[i].cckWeakSigThreshold =
2053 ATH9K_ANI_CCK_WEAK_SIG_THR;
2054 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
2055 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
2056 if (ahp->ah_hasHwPhyCounters) {
2057 ahp->ah_ani[i].ofdmPhyErrBase =
2058 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
2059 ahp->ah_ani[i].cckPhyErrBase =
2060 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
2061 }
2062 }
2063 if (ahp->ah_hasHwPhyCounters) {
2064 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2065 "Setting OfdmErrBase = 0x%08x\n",
2066 ahp->ah_ani[0].ofdmPhyErrBase);
2067 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2068 ahp->ah_ani[0].cckPhyErrBase);
2069
2070 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2071 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2072 ath9k_enable_mib_counters(ah);
2073 }
2074 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
2075 if (ah->ah_config.enable_ani)
2076 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2077 }
2078
2079 static void ath9k_hw_ani_setup(struct ath_hal *ah)
2080 {
2081 struct ath_hal_5416 *ahp = AH5416(ah);
2082 int i;
2083
2084 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2085 const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2086 const int coarseLow[] = { -64, -64, -64, -64, -70 };
2087 const int firpwr[] = { -78, -78, -78, -78, -80 };
2088
2089 for (i = 0; i < 5; i++) {
2090 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2091 ahp->ah_coarseHigh[i] = coarseHigh[i];
2092 ahp->ah_coarseLow[i] = coarseLow[i];
2093 ahp->ah_firpwr[i] = firpwr[i];
2094 }
2095 }
2096
2097 static void ath9k_hw_ani_detach(struct ath_hal *ah)
2098 {
2099 struct ath_hal_5416 *ahp = AH5416(ah);
2100
2101 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
2102 if (ahp->ah_hasHwPhyCounters) {
2103 ath9k_hw_disable_mib_counters(ah);
2104 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2105 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2106 }
2107 }
2108
2109
2110 static bool ath9k_hw_ani_control(struct ath_hal *ah,
2111 enum ath9k_ani_cmd cmd, int param)
2112 {
2113 struct ath_hal_5416 *ahp = AH5416(ah);
2114 struct ar5416AniState *aniState = ahp->ah_curani;
2115
2116 switch (cmd & ahp->ah_ani_function) {
2117 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2118 u32 level = param;
2119
2120 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2121 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2122 "%s: level out of range (%u > %u)\n",
2123 __func__, level,
2124 (unsigned) ARRAY_SIZE(ahp->
2125 ah_totalSizeDesired));
2126 return false;
2127 }
2128
2129 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2130 AR_PHY_DESIRED_SZ_TOT_DES,
2131 ahp->ah_totalSizeDesired[level]);
2132 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2133 AR_PHY_AGC_CTL1_COARSE_LOW,
2134 ahp->ah_coarseLow[level]);
2135 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2136 AR_PHY_AGC_CTL1_COARSE_HIGH,
2137 ahp->ah_coarseHigh[level]);
2138 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2139 AR_PHY_FIND_SIG_FIRPWR,
2140 ahp->ah_firpwr[level]);
2141
2142 if (level > aniState->noiseImmunityLevel)
2143 ahp->ah_stats.ast_ani_niup++;
2144 else if (level < aniState->noiseImmunityLevel)
2145 ahp->ah_stats.ast_ani_nidown++;
2146 aniState->noiseImmunityLevel = level;
2147 break;
2148 }
2149 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2150 const int m1ThreshLow[] = { 127, 50 };
2151 const int m2ThreshLow[] = { 127, 40 };
2152 const int m1Thresh[] = { 127, 0x4d };
2153 const int m2Thresh[] = { 127, 0x40 };
2154 const int m2CountThr[] = { 31, 16 };
2155 const int m2CountThrLow[] = { 63, 48 };
2156 u32 on = param ? 1 : 0;
2157
2158 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2159 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2160 m1ThreshLow[on]);
2161 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2162 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2163 m2ThreshLow[on]);
2164 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2165 AR_PHY_SFCORR_M1_THRESH,
2166 m1Thresh[on]);
2167 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2168 AR_PHY_SFCORR_M2_THRESH,
2169 m2Thresh[on]);
2170 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2171 AR_PHY_SFCORR_M2COUNT_THR,
2172 m2CountThr[on]);
2173 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2174 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2175 m2CountThrLow[on]);
2176
2177 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2178 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2179 m1ThreshLow[on]);
2180 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2181 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2182 m2ThreshLow[on]);
2183 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2184 AR_PHY_SFCORR_EXT_M1_THRESH,
2185 m1Thresh[on]);
2186 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2187 AR_PHY_SFCORR_EXT_M2_THRESH,
2188 m2Thresh[on]);
2189
2190 if (on)
2191 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2192 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2193 else
2194 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2195 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2196
2197 if (!on != aniState->ofdmWeakSigDetectOff) {
2198 if (on)
2199 ahp->ah_stats.ast_ani_ofdmon++;
2200 else
2201 ahp->ah_stats.ast_ani_ofdmoff++;
2202 aniState->ofdmWeakSigDetectOff = !on;
2203 }
2204 break;
2205 }
2206 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2207 const int weakSigThrCck[] = { 8, 6 };
2208 u32 high = param ? 1 : 0;
2209
2210 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2211 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2212 weakSigThrCck[high]);
2213 if (high != aniState->cckWeakSigThreshold) {
2214 if (high)
2215 ahp->ah_stats.ast_ani_cckhigh++;
2216 else
2217 ahp->ah_stats.ast_ani_ccklow++;
2218 aniState->cckWeakSigThreshold = high;
2219 }
2220 break;
2221 }
2222 case ATH9K_ANI_FIRSTEP_LEVEL:{
2223 const int firstep[] = { 0, 4, 8 };
2224 u32 level = param;
2225
2226 if (level >= ARRAY_SIZE(firstep)) {
2227 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2228 "%s: level out of range (%u > %u)\n",
2229 __func__, level,
2230 (unsigned) ARRAY_SIZE(firstep));
2231 return false;
2232 }
2233 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2234 AR_PHY_FIND_SIG_FIRSTEP,
2235 firstep[level]);
2236 if (level > aniState->firstepLevel)
2237 ahp->ah_stats.ast_ani_stepup++;
2238 else if (level < aniState->firstepLevel)
2239 ahp->ah_stats.ast_ani_stepdown++;
2240 aniState->firstepLevel = level;
2241 break;
2242 }
2243 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2244 const int cycpwrThr1[] =
2245 { 2, 4, 6, 8, 10, 12, 14, 16 };
2246 u32 level = param;
2247
2248 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2249 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2250 "%s: level out of range (%u > %u)\n",
2251 __func__, level,
2252 (unsigned)
2253 ARRAY_SIZE(cycpwrThr1));
2254 return false;
2255 }
2256 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2257 AR_PHY_TIMING5_CYCPWR_THR1,
2258 cycpwrThr1[level]);
2259 if (level > aniState->spurImmunityLevel)
2260 ahp->ah_stats.ast_ani_spurup++;
2261 else if (level < aniState->spurImmunityLevel)
2262 ahp->ah_stats.ast_ani_spurdown++;
2263 aniState->spurImmunityLevel = level;
2264 break;
2265 }
2266 case ATH9K_ANI_PRESENT:
2267 break;
2268 default:
2269 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2270 "%s: invalid cmd %u\n", __func__, cmd);
2271 return false;
2272 }
2273
2274 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
2275 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2276 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2277 "ofdmWeakSigDetectOff=%d\n",
2278 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2279 !aniState->ofdmWeakSigDetectOff);
2280 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2281 "cckWeakSigThreshold=%d, "
2282 "firstepLevel=%d, listenTime=%d\n",
2283 aniState->cckWeakSigThreshold, aniState->firstepLevel,
2284 aniState->listenTime);
2285 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2286 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2287 aniState->cycleCount, aniState->ofdmPhyErrCount,
2288 aniState->cckPhyErrCount);
2289 return true;
2290 }
2291
2292 static void ath9k_ani_restart(struct ath_hal *ah)
2293 {
2294 struct ath_hal_5416 *ahp = AH5416(ah);
2295 struct ar5416AniState *aniState;
2296
2297 if (!DO_ANI(ah))
2298 return;
2299
2300 aniState = ahp->ah_curani;
2301
2302 aniState->listenTime = 0;
2303 if (ahp->ah_hasHwPhyCounters) {
2304 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2305 aniState->ofdmPhyErrBase = 0;
2306 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2307 "OFDM Trigger is too high for hw counters\n");
2308 } else {
2309 aniState->ofdmPhyErrBase =
2310 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2311 }
2312 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2313 aniState->cckPhyErrBase = 0;
2314 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2315 "CCK Trigger is too high for hw counters\n");
2316 } else {
2317 aniState->cckPhyErrBase =
2318 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2319 }
2320 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2321 "%s: Writing ofdmbase=%u cckbase=%u\n",
2322 __func__, aniState->ofdmPhyErrBase,
2323 aniState->cckPhyErrBase);
2324 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2325 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2326 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2327 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2328
2329 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2330 }
2331 aniState->ofdmPhyErrCount = 0;
2332 aniState->cckPhyErrCount = 0;
2333 }
2334
2335 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2336 {
2337 struct ath_hal_5416 *ahp = AH5416(ah);
2338 struct ath9k_channel *chan = ah->ah_curchan;
2339 struct ar5416AniState *aniState;
2340 enum wireless_mode mode;
2341 int32_t rssi;
2342
2343 if (!DO_ANI(ah))
2344 return;
2345
2346 aniState = ahp->ah_curani;
2347
2348 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2349 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2350 aniState->noiseImmunityLevel + 1)) {
2351 return;
2352 }
2353 }
2354
2355 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2356 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2357 aniState->spurImmunityLevel + 1)) {
2358 return;
2359 }
2360 }
2361
2362 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2363 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2364 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2365 aniState->firstepLevel + 1);
2366 }
2367 return;
2368 }
2369 rssi = BEACON_RSSI(ahp);
2370 if (rssi > aniState->rssiThrHigh) {
2371 if (!aniState->ofdmWeakSigDetectOff) {
2372 if (ath9k_hw_ani_control(ah,
2373 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2374 false)) {
2375 ath9k_hw_ani_control(ah,
2376 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2377 0);
2378 return;
2379 }
2380 }
2381 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2382 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2383 aniState->firstepLevel + 1);
2384 return;
2385 }
2386 } else if (rssi > aniState->rssiThrLow) {
2387 if (aniState->ofdmWeakSigDetectOff)
2388 ath9k_hw_ani_control(ah,
2389 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2390 true);
2391 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2392 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2393 aniState->firstepLevel + 1);
2394 return;
2395 } else {
2396 mode = ath9k_hw_chan2wmode(ah, chan);
2397 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2398 if (!aniState->ofdmWeakSigDetectOff)
2399 ath9k_hw_ani_control(ah,
2400 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2401 false);
2402 if (aniState->firstepLevel > 0)
2403 ath9k_hw_ani_control(ah,
2404 ATH9K_ANI_FIRSTEP_LEVEL,
2405 0);
2406 return;
2407 }
2408 }
2409 }
2410
2411 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2412 {
2413 struct ath_hal_5416 *ahp = AH5416(ah);
2414 struct ath9k_channel *chan = ah->ah_curchan;
2415 struct ar5416AniState *aniState;
2416 enum wireless_mode mode;
2417 int32_t rssi;
2418
2419 if (!DO_ANI(ah))
2420 return;
2421
2422 aniState = ahp->ah_curani;
2423 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2424 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2425 aniState->noiseImmunityLevel + 1)) {
2426 return;
2427 }
2428 }
2429 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2430 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2431 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2432 aniState->firstepLevel + 1);
2433 }
2434 return;
2435 }
2436 rssi = BEACON_RSSI(ahp);
2437 if (rssi > aniState->rssiThrLow) {
2438 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2439 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2440 aniState->firstepLevel + 1);
2441 } else {
2442 mode = ath9k_hw_chan2wmode(ah, chan);
2443 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2444 if (aniState->firstepLevel > 0)
2445 ath9k_hw_ani_control(ah,
2446 ATH9K_ANI_FIRSTEP_LEVEL,
2447 0);
2448 }
2449 }
2450 }
2451
2452 static void ath9k_ani_reset(struct ath_hal *ah)
2453 {
2454 struct ath_hal_5416 *ahp = AH5416(ah);
2455 struct ar5416AniState *aniState;
2456 struct ath9k_channel *chan = ah->ah_curchan;
2457 int index;
2458
2459 if (!DO_ANI(ah))
2460 return;
2461
2462 index = ath9k_hw_get_ani_channel_idx(ah, chan);
2463 aniState = &ahp->ah_ani[index];
2464 ahp->ah_curani = aniState;
2465
2466 if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
2467 && ah->ah_opmode != ATH9K_M_IBSS) {
2468 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2469 "%s: Reset ANI state opmode %u\n", __func__,
2470 ah->ah_opmode);
2471 ahp->ah_stats.ast_ani_reset++;
2472 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
2473 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
2474 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
2475 ath9k_hw_ani_control(ah,
2476 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2477 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
2478 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2479 ATH9K_ANI_CCK_WEAK_SIG_THR);
2480 ath9k_hw_setrxfilter(ah,
2481 ath9k_hw_getrxfilter(ah) |
2482 ATH9K_RX_FILTER_PHYERR);
2483 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2484 ahp->ah_curani->ofdmTrigHigh =
2485 ah->ah_config.ofdm_trig_high;
2486 ahp->ah_curani->ofdmTrigLow =
2487 ah->ah_config.ofdm_trig_low;
2488 ahp->ah_curani->cckTrigHigh =
2489 ah->ah_config.cck_trig_high;
2490 ahp->ah_curani->cckTrigLow =
2491 ah->ah_config.cck_trig_low;
2492 }
2493 ath9k_ani_restart(ah);
2494 return;
2495 }
2496
2497 if (aniState->noiseImmunityLevel != 0)
2498 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2499 aniState->noiseImmunityLevel);
2500 if (aniState->spurImmunityLevel != 0)
2501 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2502 aniState->spurImmunityLevel);
2503 if (aniState->ofdmWeakSigDetectOff)
2504 ath9k_hw_ani_control(ah,
2505 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2506 !aniState->ofdmWeakSigDetectOff);
2507 if (aniState->cckWeakSigThreshold)
2508 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2509 aniState->cckWeakSigThreshold);
2510 if (aniState->firstepLevel != 0)
2511 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2512 aniState->firstepLevel);
2513 if (ahp->ah_hasHwPhyCounters) {
2514 ath9k_hw_setrxfilter(ah,
2515 ath9k_hw_getrxfilter(ah) &
2516 ~ATH9K_RX_FILTER_PHYERR);
2517 ath9k_ani_restart(ah);
2518 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2519 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2520
2521 } else {
2522 ath9k_ani_restart(ah);
2523 ath9k_hw_setrxfilter(ah,
2524 ath9k_hw_getrxfilter(ah) |
2525 ATH9K_RX_FILTER_PHYERR);
2526 }
2527 }
2528
2529 /*
2530 * Process a MIB interrupt. We may potentially be invoked because
2531 * any of the MIB counters overflow/trigger so don't assume we're
2532 * here because a PHY error counter triggered.
2533 */
2534 void ath9k_hw_procmibevent(struct ath_hal *ah,
2535 const struct ath9k_node_stats *stats)
2536 {
2537 struct ath_hal_5416 *ahp = AH5416(ah);
2538 u32 phyCnt1, phyCnt2;
2539
2540 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
2541 /* Reset these counters regardless */
2542 REG_WRITE(ah, AR_FILT_OFDM, 0);
2543 REG_WRITE(ah, AR_FILT_CCK, 0);
2544 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2545 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2546
2547 /* Clear the mib counters and save them in the stats */
2548 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2549 ahp->ah_stats.ast_nodestats = *stats;
2550
2551 if (!DO_ANI(ah))
2552 return;
2553
2554 /* NB: these are not reset-on-read */
2555 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2556 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2557 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2558 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2559 struct ar5416AniState *aniState = ahp->ah_curani;
2560 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2561
2562 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
2563 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2564 ahp->ah_stats.ast_ani_ofdmerrs +=
2565 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2566 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2567
2568 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2569 ahp->ah_stats.ast_ani_cckerrs +=
2570 cckPhyErrCnt - aniState->cckPhyErrCount;
2571 aniState->cckPhyErrCount = cckPhyErrCnt;
2572
2573 /*
2574 * NB: figure out which counter triggered. If both
2575 * trigger we'll only deal with one as the processing
2576 * clobbers the error counter so the trigger threshold
2577 * check will never be true.
2578 */
2579 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2580 ath9k_hw_ani_ofdm_err_trigger(ah);
2581 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2582 ath9k_hw_ani_cck_err_trigger(ah);
2583 /* NB: always restart to insure the h/w counters are reset */
2584 ath9k_ani_restart(ah);
2585 }
2586 }
2587
2588 static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2589 {
2590 struct ath_hal_5416 *ahp = AH5416(ah);
2591 struct ar5416AniState *aniState;
2592 int32_t rssi;
2593
2594 aniState = ahp->ah_curani;
2595
2596 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2597 if (aniState->firstepLevel > 0) {
2598 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2599 aniState->firstepLevel - 1)) {
2600 return;
2601 }
2602 }
2603 } else {
2604 rssi = BEACON_RSSI(ahp);
2605 if (rssi > aniState->rssiThrHigh) {
2606 /* XXX: Handle me */
2607 } else if (rssi > aniState->rssiThrLow) {
2608 if (aniState->ofdmWeakSigDetectOff) {
2609 if (ath9k_hw_ani_control(ah,
2610 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2611 true) ==
2612 true) {
2613 return;
2614 }
2615 }
2616 if (aniState->firstepLevel > 0) {
2617 if (ath9k_hw_ani_control
2618 (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2619 aniState->firstepLevel - 1) ==
2620 true) {
2621 return;
2622 }
2623 }
2624 } else {
2625 if (aniState->firstepLevel > 0) {
2626 if (ath9k_hw_ani_control
2627 (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2628 aniState->firstepLevel - 1) ==
2629 true) {
2630 return;
2631 }
2632 }
2633 }
2634 }
2635
2636 if (aniState->spurImmunityLevel > 0) {
2637 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2638 aniState->spurImmunityLevel - 1)) {
2639 return;
2640 }
2641 }
2642
2643 if (aniState->noiseImmunityLevel > 0) {
2644 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2645 aniState->noiseImmunityLevel - 1);
2646 return;
2647 }
2648 }
2649
2650 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2651 {
2652 struct ath_hal_5416 *ahp = AH5416(ah);
2653 struct ar5416AniState *aniState;
2654 u32 txFrameCount, rxFrameCount, cycleCount;
2655 int32_t listenTime;
2656
2657 txFrameCount = REG_READ(ah, AR_TFCNT);
2658 rxFrameCount = REG_READ(ah, AR_RFCNT);
2659 cycleCount = REG_READ(ah, AR_CCCNT);
2660
2661 aniState = ahp->ah_curani;
2662 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2663
2664 listenTime = 0;
2665 ahp->ah_stats.ast_ani_lzero++;
2666 } else {
2667 int32_t ccdelta = cycleCount - aniState->cycleCount;
2668 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2669 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2670 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2671 }
2672 aniState->cycleCount = cycleCount;
2673 aniState->txFrameCount = txFrameCount;
2674 aniState->rxFrameCount = rxFrameCount;
2675
2676 return listenTime;
2677 }
2678
2679 void ath9k_hw_ani_monitor(struct ath_hal *ah,
2680 const struct ath9k_node_stats *stats,
2681 struct ath9k_channel *chan)
2682 {
2683 struct ath_hal_5416 *ahp = AH5416(ah);
2684 struct ar5416AniState *aniState;
2685 int32_t listenTime;
2686
2687 aniState = ahp->ah_curani;
2688 ahp->ah_stats.ast_nodestats = *stats;
2689
2690 listenTime = ath9k_hw_ani_get_listen_time(ah);
2691 if (listenTime < 0) {
2692 ahp->ah_stats.ast_ani_lneg++;
2693 ath9k_ani_restart(ah);
2694 return;
2695 }
2696
2697 aniState->listenTime += listenTime;
2698
2699 if (ahp->ah_hasHwPhyCounters) {
2700 u32 phyCnt1, phyCnt2;
2701 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2702
2703 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2704
2705 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2706 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2707
2708 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2709 phyCnt2 < aniState->cckPhyErrBase) {
2710 if (phyCnt1 < aniState->ofdmPhyErrBase) {
2711 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2712 "%s: phyCnt1 0x%x, resetting "
2713 "counter value to 0x%x\n",
2714 __func__, phyCnt1,
2715 aniState->ofdmPhyErrBase);
2716 REG_WRITE(ah, AR_PHY_ERR_1,
2717 aniState->ofdmPhyErrBase);
2718 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2719 AR_PHY_ERR_OFDM_TIMING);
2720 }
2721 if (phyCnt2 < aniState->cckPhyErrBase) {
2722 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2723 "%s: phyCnt2 0x%x, resetting "
2724 "counter value to 0x%x\n",
2725 __func__, phyCnt2,
2726 aniState->cckPhyErrBase);
2727 REG_WRITE(ah, AR_PHY_ERR_2,
2728 aniState->cckPhyErrBase);
2729 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2730 AR_PHY_ERR_CCK_TIMING);
2731 }
2732 return;
2733 }
2734
2735 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2736 ahp->ah_stats.ast_ani_ofdmerrs +=
2737 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2738 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2739
2740 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2741 ahp->ah_stats.ast_ani_cckerrs +=
2742 cckPhyErrCnt - aniState->cckPhyErrCount;
2743 aniState->cckPhyErrCount = cckPhyErrCnt;
2744 }
2745
2746 if (!DO_ANI(ah))
2747 return;
2748
2749 if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2750 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2751 aniState->ofdmTrigLow / 1000 &&
2752 aniState->cckPhyErrCount <= aniState->listenTime *
2753 aniState->cckTrigLow / 1000)
2754 ath9k_hw_ani_lower_immunity(ah);
2755 ath9k_ani_restart(ah);
2756 } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2757 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2758 aniState->ofdmTrigHigh / 1000) {
2759 ath9k_hw_ani_ofdm_err_trigger(ah);
2760 ath9k_ani_restart(ah);
2761 } else if (aniState->cckPhyErrCount >
2762 aniState->listenTime * aniState->cckTrigHigh /
2763 1000) {
2764 ath9k_hw_ani_cck_err_trigger(ah);
2765 ath9k_ani_restart(ah);
2766 }
2767 }
2768 }
2769
2770 #ifndef ATH_NF_PER_CHAN
2771 static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2772 {
2773 int i, j;
2774
2775 for (i = 0; i < NUM_NF_READINGS; i++) {
2776 ah->nfCalHist[i].currIndex = 0;
2777 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2778 ah->nfCalHist[i].invalidNFcount =
2779 AR_PHY_CCA_FILTERWINDOW_LENGTH;
2780 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
2781 ah->nfCalHist[i].nfCalBuffer[j] =
2782 AR_PHY_CCA_MAX_GOOD_VALUE;
2783 }
2784 }
2785 return;
2786 }
2787 #endif
2788
2789 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2790 u32 gpio, u32 type)
2791 {
2792 int addr;
2793 u32 gpio_shift, tmp;
2794
2795 if (gpio > 11)
2796 addr = AR_GPIO_OUTPUT_MUX3;
2797 else if (gpio > 5)
2798 addr = AR_GPIO_OUTPUT_MUX2;
2799 else
2800 addr = AR_GPIO_OUTPUT_MUX1;
2801
2802 gpio_shift = (gpio % 6) * 5;
2803
2804 if (AR_SREV_9280_20_OR_LATER(ah)
2805 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2806 REG_RMW(ah, addr, (type << gpio_shift),
2807 (0x1f << gpio_shift));
2808 } else {
2809 tmp = REG_READ(ah, addr);
2810 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2811 tmp &= ~(0x1f << gpio_shift);
2812 tmp |= (type << gpio_shift);
2813 REG_WRITE(ah, addr, tmp);
2814 }
2815 }
2816
2817 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
2818 u32 ah_signal_type)
2819 {
2820 u32 gpio_shift;
2821
2822 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2823
2824 gpio_shift = 2 * gpio;
2825
2826 REG_RMW(ah,
2827 AR_GPIO_OE_OUT,
2828 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2829 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2830 }
2831
2832 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
2833 {
2834 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2835 AR_GPIO_BIT(gpio));
2836 }
2837
2838 /*
2839 * Configure GPIO Input lines
2840 */
2841 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
2842 {
2843 u32 gpio_shift;
2844
2845 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
2846
2847 gpio_shift = gpio << 1;
2848
2849 REG_RMW(ah,
2850 AR_GPIO_OE_OUT,
2851 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2852 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2853 }
2854
2855 #ifdef CONFIG_RFKILL
2856 static void ath9k_enable_rfkill(struct ath_hal *ah)
2857 {
2858 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2859 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2860
2861 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2862 AR_GPIO_INPUT_MUX2_RFSILENT);
2863
2864 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
2865 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2866 }
2867 #endif
2868
2869 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
2870 {
2871 if (gpio >= ah->ah_caps.num_gpio_pins)
2872 return 0xffffffff;
2873
2874 if (AR_SREV_9280_10_OR_LATER(ah)) {
2875 return (MS
2876 (REG_READ(ah, AR_GPIO_IN_OUT),
2877 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
2878 } else {
2879 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
2880 AR_GPIO_BIT(gpio)) != 0;
2881 }
2882 }
2883
2884 static int ath9k_hw_post_attach(struct ath_hal *ah)
2885 {
2886 int ecode;
2887
2888 if (!ath9k_hw_chip_test(ah)) {
2889 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2890 "%s: hardware self-test failed\n", __func__);
2891 return -ENODEV;
2892 }
2893
2894 ecode = ath9k_hw_rf_claim(ah);
2895 if (ecode != 0)
2896 return ecode;
2897
2898 ecode = ath9k_hw_eeprom_attach(ah);
2899 if (ecode != 0)
2900 return ecode;
2901 ecode = ath9k_hw_rfattach(ah);
2902 if (ecode != 0)
2903 return ecode;
2904
2905 if (!AR_SREV_9100(ah)) {
2906 ath9k_hw_ani_setup(ah);
2907 ath9k_hw_ani_attach(ah);
2908 }
2909 return 0;
2910 }
2911
2912 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
2913 struct ar5416_eeprom *pEepData,
2914 u32 reg, u32 value)
2915 {
2916 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2917
2918 switch (ah->ah_devid) {
2919 case AR9280_DEVID_PCI:
2920 if (reg == 0x7894) {
2921 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2922 "ini VAL: %x EEPROM: %x\n", value,
2923 (pBase->version & 0xff));
2924
2925 if ((pBase->version & 0xff) > 0x0a) {
2926 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2927 "PWDCLKIND: %d\n",
2928 pBase->pwdclkind);
2929 value &= ~AR_AN_TOP2_PWDCLKIND;
2930 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2931 pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2932 } else {
2933 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2934 "PWDCLKIND Earlier Rev\n");
2935 }
2936
2937 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2938 "final ini VAL: %x\n", value);
2939 }
2940 break;
2941 }
2942 return value;
2943 }
2944
2945 static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2946 {
2947 struct ath_hal_5416 *ahp = AH5416(ah);
2948 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2949 u16 capField = 0, eeval;
2950
2951 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2952
2953 ah->ah_currentRD = eeval;
2954
2955 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2956 ah->ah_currentRDExt = eeval;
2957
2958 capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2959
2960 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
2961 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2962 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2963 ah->ah_currentRD += 5;
2964 else if (ah->ah_currentRD == 0x41)
2965 ah->ah_currentRD = 0x43;
2966 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
2967 "%s: regdomain mapped to 0x%x\n", __func__,
2968 ah->ah_currentRD);
2969 }
2970
2971 eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2972 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2973
2974 if (eeval & AR5416_OPFLAGS_11A) {
2975 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2976 if (ah->ah_config.ht_enable) {
2977 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2978 set_bit(ATH9K_MODE_11NA_HT20,
2979 pCap->wireless_modes);
2980 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2981 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2982 pCap->wireless_modes);
2983 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2984 pCap->wireless_modes);
2985 }
2986 }
2987 }
2988
2989 if (eeval & AR5416_OPFLAGS_11G) {
2990 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
2991 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2992 if (ah->ah_config.ht_enable) {
2993 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2994 set_bit(ATH9K_MODE_11NG_HT20,
2995 pCap->wireless_modes);
2996 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2997 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2998 pCap->wireless_modes);
2999 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3000 pCap->wireless_modes);
3001 }
3002 }
3003 }
3004
3005 pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
3006 if ((ah->ah_isPciExpress)
3007 || (eeval & AR5416_OPFLAGS_11A)) {
3008 pCap->rx_chainmask =
3009 ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
3010 } else {
3011 pCap->rx_chainmask =
3012 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3013 }
3014
3015 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3016 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3017
3018 pCap->low_2ghz_chan = 2312;
3019 pCap->high_2ghz_chan = 2732;
3020
3021 pCap->low_5ghz_chan = 4920;
3022 pCap->high_5ghz_chan = 6100;
3023
3024 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3025 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3026 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3027
3028 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3029 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3030 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3031
3032 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3033
3034 if (ah->ah_config.ht_enable)
3035 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3036 else
3037 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3038
3039 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3040 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3041 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3042 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3043
3044 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3045 pCap->total_queues =
3046 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3047 else
3048 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3049
3050 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3051 pCap->keycache_size =
3052 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3053 else
3054 pCap->keycache_size = AR_KEYTABLE_SIZE;
3055
3056 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3057 pCap->num_mr_retries = 4;
3058 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3059
3060 if (AR_SREV_9280_10_OR_LATER(ah))
3061 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3062 else
3063 pCap->num_gpio_pins = AR_NUM_GPIO;
3064
3065 if (AR_SREV_9280_10_OR_LATER(ah)) {
3066 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3067 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3068 } else {
3069 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3070 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3071 }
3072
3073 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3074 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3075 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3076 } else {
3077 pCap->rts_aggr_limit = (8 * 1024);
3078 }
3079
3080 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3081
3082 #ifdef CONFIG_RFKILL
3083 ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3084 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3085 ah->ah_rfkill_gpio =
3086 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3087 ah->ah_rfkill_polarity =
3088 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3089
3090 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3091 }
3092 #endif
3093
3094 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3095 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3096 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3097 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3098 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3099 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3100 else
3101 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3102
3103 if (AR_SREV_9280(ah))
3104 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3105 else
3106 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3107
3108 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3109 pCap->reg_cap =
3110 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3111 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3112 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3113 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3114 } else {
3115 pCap->reg_cap =
3116 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3117 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3118 }
3119
3120 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3121
3122 pCap->num_antcfg_5ghz =
3123 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_5GHZ);
3124 pCap->num_antcfg_2ghz =
3125 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_2GHZ);
3126
3127 return true;
3128 }
3129
3130 static void ar5416DisablePciePhy(struct ath_hal *ah)
3131 {
3132 if (!AR_SREV_9100(ah))
3133 return;
3134
3135 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3136 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3137 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3138 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3139 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3140 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3141 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3142 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3143 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3144
3145 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3146 }
3147
3148 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3149 {
3150 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3151 if (setChip) {
3152 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3153 AR_RTC_FORCE_WAKE_EN);
3154 if (!AR_SREV_9100(ah))
3155 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3156
3157 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
3158 AR_RTC_RESET_EN);
3159 }
3160 }
3161
3162 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3163 {
3164 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3165 if (setChip) {
3166 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3167
3168 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3169 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3170 AR_RTC_FORCE_WAKE_ON_INT);
3171 } else {
3172 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3173 AR_RTC_FORCE_WAKE_EN);
3174 }
3175 }
3176 }
3177
3178 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3179 int setChip)
3180 {
3181 u32 val;
3182 int i;
3183
3184 if (setChip) {
3185 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3186 AR_RTC_STATUS_SHUTDOWN) {
3187 if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
3188 != true) {
3189 return false;
3190 }
3191 }
3192 if (AR_SREV_9100(ah))
3193 REG_SET_BIT(ah, AR_RTC_RESET,
3194 AR_RTC_RESET_EN);
3195
3196 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3197 AR_RTC_FORCE_WAKE_EN);
3198 udelay(50);
3199
3200 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3201 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3202 if (val == AR_RTC_STATUS_ON)
3203 break;
3204 udelay(50);
3205 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3206 AR_RTC_FORCE_WAKE_EN);
3207 }
3208 if (i == 0) {
3209 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3210 "%s: Failed to wakeup in %uus\n",
3211 __func__, POWER_UP_TIME / 20);
3212 return false;
3213 }
3214 }
3215
3216 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3217 return true;
3218 }
3219
3220 bool ath9k_hw_setpower(struct ath_hal *ah,
3221 enum ath9k_power_mode mode)
3222 {
3223 struct ath_hal_5416 *ahp = AH5416(ah);
3224 static const char *modes[] = {
3225 "AWAKE",
3226 "FULL-SLEEP",
3227 "NETWORK SLEEP",
3228 "UNDEFINED"
3229 };
3230 int status = true, setChip = true;
3231
3232 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
3233 modes[ahp->ah_powerMode], modes[mode],
3234 setChip ? "set chip " : "");
3235
3236 switch (mode) {
3237 case ATH9K_PM_AWAKE:
3238 status = ath9k_hw_set_power_awake(ah, setChip);
3239 break;
3240 case ATH9K_PM_FULL_SLEEP:
3241 ath9k_set_power_sleep(ah, setChip);
3242 ahp->ah_chipFullSleep = true;
3243 break;
3244 case ATH9K_PM_NETWORK_SLEEP:
3245 ath9k_set_power_network_sleep(ah, setChip);
3246 break;
3247 default:
3248 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3249 "%s: unknown power mode %u\n", __func__, mode);
3250 return false;
3251 }
3252 ahp->ah_powerMode = mode;
3253 return status;
3254 }
3255
3256 static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3257 struct ath_softc *sc,
3258 void __iomem *mem,
3259 int *status)
3260 {
3261 struct ath_hal_5416 *ahp;
3262 struct ath_hal *ah;
3263 int ecode;
3264 #ifndef CONFIG_SLOW_ANT_DIV
3265 u32 i;
3266 u32 j;
3267 #endif
3268
3269 ahp = ath9k_hw_newstate(devid, sc, mem, status);
3270 if (ahp == NULL)
3271 return NULL;
3272
3273 ah = &ahp->ah;
3274
3275 ath9k_hw_set_defaults(ah);
3276
3277 if (ah->ah_config.intr_mitigation != 0)
3278 ahp->ah_intrMitigation = true;
3279
3280 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3281 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
3282 __func__);
3283 ecode = -EIO;
3284 goto bad;
3285 }
3286
3287 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3288 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
3289 __func__);
3290 ecode = -EIO;
3291 goto bad;
3292 }
3293
3294 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
3295 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
3296 ah->ah_config.serialize_regmode =
3297 SER_REG_MODE_ON;
3298 } else {
3299 ah->ah_config.serialize_regmode =
3300 SER_REG_MODE_OFF;
3301 }
3302 }
3303 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3304 "%s: serialize_regmode is %d\n",
3305 __func__, ah->ah_config.serialize_regmode);
3306
3307 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3308 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
3309 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3310 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
3311 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3312 "%s: Mac Chip Rev 0x%02x.%x is not supported by "
3313 "this driver\n", __func__,
3314 ah->ah_macVersion, ah->ah_macRev);
3315 ecode = -EOPNOTSUPP;
3316 goto bad;
3317 }
3318
3319 if (AR_SREV_9100(ah)) {
3320 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3321 ahp->ah_suppCals = IQ_MISMATCH_CAL;
3322 ah->ah_isPciExpress = false;
3323 }
3324 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
3325
3326 if (AR_SREV_9160_10_OR_LATER(ah)) {
3327 if (AR_SREV_9280_10_OR_LATER(ah)) {
3328 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
3329 ahp->ah_adcGainCalData.calData =
3330 &adc_gain_cal_single_sample;
3331 ahp->ah_adcDcCalData.calData =
3332 &adc_dc_cal_single_sample;
3333 ahp->ah_adcDcCalInitData.calData =
3334 &adc_init_dc_cal;
3335 } else {
3336 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3337 ahp->ah_adcGainCalData.calData =
3338 &adc_gain_cal_multi_sample;
3339 ahp->ah_adcDcCalData.calData =
3340 &adc_dc_cal_multi_sample;
3341 ahp->ah_adcDcCalInitData.calData =
3342 &adc_init_dc_cal;
3343 }
3344 ahp->ah_suppCals =
3345 ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3346 }
3347
3348 if (AR_SREV_9160(ah)) {
3349 ah->ah_config.enable_ani = 1;
3350 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
3351 ATH9K_ANI_FIRSTEP_LEVEL);
3352 } else {
3353 ahp->ah_ani_function = ATH9K_ANI_ALL;
3354 if (AR_SREV_9280_10_OR_LATER(ah)) {
3355 ahp->ah_ani_function &=
3356 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3357 }
3358 }
3359
3360 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3361 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
3362 ah->ah_macVersion, ah->ah_macRev);
3363
3364 if (AR_SREV_9280_20_OR_LATER(ah)) {
3365 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
3366 ARRAY_SIZE(ar9280Modes_9280_2), 6);
3367 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
3368 ARRAY_SIZE(ar9280Common_9280_2), 2);
3369
3370 if (ah->ah_config.pcie_clock_req) {
3371 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3372 ar9280PciePhy_clkreq_off_L1_9280,
3373 ARRAY_SIZE
3374 (ar9280PciePhy_clkreq_off_L1_9280),
3375 2);
3376 } else {
3377 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3378 ar9280PciePhy_clkreq_always_on_L1_9280,
3379 ARRAY_SIZE
3380 (ar9280PciePhy_clkreq_always_on_L1_9280),
3381 2);
3382 }
3383 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3384 ar9280Modes_fast_clock_9280_2,
3385 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2),
3386 3);
3387 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3388 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3389 ARRAY_SIZE(ar9280Modes_9280), 6);
3390 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
3391 ARRAY_SIZE(ar9280Common_9280), 2);
3392 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3393 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
3394 ARRAY_SIZE(ar5416Modes_9160), 6);
3395 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
3396 ARRAY_SIZE(ar5416Common_9160), 2);
3397 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
3398 ARRAY_SIZE(ar5416Bank0_9160), 2);
3399 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
3400 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
3401 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
3402 ARRAY_SIZE(ar5416Bank1_9160), 2);
3403 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
3404 ARRAY_SIZE(ar5416Bank2_9160), 2);
3405 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
3406 ARRAY_SIZE(ar5416Bank3_9160), 3);
3407 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
3408 ARRAY_SIZE(ar5416Bank6_9160), 3);
3409 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
3410 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
3411 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
3412 ARRAY_SIZE(ar5416Bank7_9160), 2);
3413 if (AR_SREV_9160_11(ah)) {
3414 INIT_INI_ARRAY(&ahp->ah_iniAddac,
3415 ar5416Addac_91601_1,
3416 ARRAY_SIZE(ar5416Addac_91601_1), 2);
3417 } else {
3418 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
3419 ARRAY_SIZE(ar5416Addac_9160), 2);
3420 }
3421 } else if (AR_SREV_9100_OR_LATER(ah)) {
3422 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
3423 ARRAY_SIZE(ar5416Modes_9100), 6);
3424 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
3425 ARRAY_SIZE(ar5416Common_9100), 2);
3426 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
3427 ARRAY_SIZE(ar5416Bank0_9100), 2);
3428 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
3429 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
3430 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
3431 ARRAY_SIZE(ar5416Bank1_9100), 2);
3432 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
3433 ARRAY_SIZE(ar5416Bank2_9100), 2);
3434 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
3435 ARRAY_SIZE(ar5416Bank3_9100), 3);
3436 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
3437 ARRAY_SIZE(ar5416Bank6_9100), 3);
3438 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
3439 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
3440 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
3441 ARRAY_SIZE(ar5416Bank7_9100), 2);
3442 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
3443 ARRAY_SIZE(ar5416Addac_9100), 2);
3444 } else {
3445 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
3446 ARRAY_SIZE(ar5416Modes), 6);
3447 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
3448 ARRAY_SIZE(ar5416Common), 2);
3449 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
3450 ARRAY_SIZE(ar5416Bank0), 2);
3451 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
3452 ARRAY_SIZE(ar5416BB_RfGain), 3);
3453 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
3454 ARRAY_SIZE(ar5416Bank1), 2);
3455 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
3456 ARRAY_SIZE(ar5416Bank2), 2);
3457 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
3458 ARRAY_SIZE(ar5416Bank3), 3);
3459 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
3460 ARRAY_SIZE(ar5416Bank6), 3);
3461 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
3462 ARRAY_SIZE(ar5416Bank6TPC), 3);
3463 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
3464 ARRAY_SIZE(ar5416Bank7), 2);
3465 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
3466 ARRAY_SIZE(ar5416Addac), 2);
3467 }
3468
3469 if (ah->ah_isPciExpress)
3470 ath9k_hw_configpcipowersave(ah, 0);
3471 else
3472 ar5416DisablePciePhy(ah);
3473
3474 ecode = ath9k_hw_post_attach(ah);
3475 if (ecode != 0)
3476 goto bad;
3477
3478 #ifndef CONFIG_SLOW_ANT_DIV
3479 if (ah->ah_devid == AR9280_DEVID_PCI) {
3480 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
3481 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
3482
3483 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
3484 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
3485
3486 INI_RA(&ahp->ah_iniModes, i, j) =
3487 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
3488 reg, val);
3489 }
3490 }
3491 }
3492 #endif
3493
3494 if (!ath9k_hw_fill_cap_info(ah)) {
3495 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3496 "%s:failed ath9k_hw_fill_cap_info\n", __func__);
3497 ecode = -EINVAL;
3498 goto bad;
3499 }
3500
3501 ecode = ath9k_hw_init_macaddr(ah);
3502 if (ecode != 0) {
3503 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3504 "%s: failed initializing mac address\n",
3505 __func__);
3506 goto bad;
3507 }
3508
3509 if (AR_SREV_9285(ah))
3510 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
3511 else
3512 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3513
3514 #ifndef ATH_NF_PER_CHAN
3515
3516 ath9k_init_nfcal_hist_buffer(ah);
3517 #endif
3518
3519 return ah;
3520
3521 bad:
3522 if (ahp)
3523 ath9k_hw_detach((struct ath_hal *) ahp);
3524 if (status)
3525 *status = ecode;
3526 return NULL;
3527 }
3528
3529 void ath9k_hw_detach(struct ath_hal *ah)
3530 {
3531 if (!AR_SREV_9100(ah))
3532 ath9k_hw_ani_detach(ah);
3533 ath9k_hw_rfdetach(ah);
3534
3535 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3536 kfree(ah);
3537 }
3538
3539 bool ath9k_get_channel_edges(struct ath_hal *ah,
3540 u16 flags, u16 *low,
3541 u16 *high)
3542 {
3543 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3544
3545 if (flags & CHANNEL_5GHZ) {
3546 *low = pCap->low_5ghz_chan;
3547 *high = pCap->high_5ghz_chan;
3548 return true;
3549 }
3550 if ((flags & CHANNEL_2GHZ)) {
3551 *low = pCap->low_2ghz_chan;
3552 *high = pCap->high_2ghz_chan;
3553
3554 return true;
3555 }
3556 return false;
3557 }
3558
3559 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin,
3560 u8 pwrMax,
3561 u8 *pPwrList,
3562 u8 *pVpdList,
3563 u16
3564 numIntercepts,
3565 u8 *pRetVpdList)
3566 {
3567 u16 i, k;
3568 u8 currPwr = pwrMin;
3569 u16 idxL = 0, idxR = 0;
3570
3571 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3572 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3573 numIntercepts, &(idxL),
3574 &(idxR));
3575 if (idxR < 1)
3576 idxR = 1;
3577 if (idxL == numIntercepts - 1)
3578 idxL = (u16) (numIntercepts - 2);
3579 if (pPwrList[idxL] == pPwrList[idxR])
3580 k = pVpdList[idxL];
3581 else
3582 k = (u16) (((currPwr -
3583 pPwrList[idxL]) *
3584 pVpdList[idxR] +
3585 (pPwrList[idxR] -
3586 currPwr) * pVpdList[idxL]) /
3587 (pPwrList[idxR] -
3588 pPwrList[idxL]));
3589 pRetVpdList[i] = (u8) k;
3590 currPwr += 2;
3591 }
3592
3593 return true;
3594 }
3595
3596 static void
3597 ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
3598 struct ath9k_channel *chan,
3599 struct cal_data_per_freq *pRawDataSet,
3600 u8 *bChans,
3601 u16 availPiers,
3602 u16 tPdGainOverlap,
3603 int16_t *pMinCalPower,
3604 u16 *pPdGainBoundaries,
3605 u8 *pPDADCValues,
3606 u16 numXpdGains)
3607 {
3608 int i, j, k;
3609 int16_t ss;
3610 u16 idxL = 0, idxR = 0, numPiers;
3611 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
3612 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3613 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
3614 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3615 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
3616 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3617
3618 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3619 u8 minPwrT4[AR5416_NUM_PD_GAINS];
3620 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
3621 int16_t vpdStep;
3622 int16_t tmpVal;
3623 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
3624 bool match;
3625 int16_t minDelta = 0;
3626 struct chan_centers centers;
3627
3628 ath9k_hw_get_channel_centers(ah, chan, &centers);
3629
3630 for (numPiers = 0; numPiers < availPiers; numPiers++) {
3631 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3632 break;
3633 }
3634
3635 match = ath9k_hw_get_lower_upper_index((u8)
3636 FREQ2FBIN(centers.
3637 synth_center,
3638 IS_CHAN_2GHZ
3639 (chan)), bChans,
3640 numPiers, &idxL, &idxR);
3641
3642 if (match) {
3643 for (i = 0; i < numXpdGains; i++) {
3644 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3645 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3646 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3647 pRawDataSet[idxL].
3648 pwrPdg[i],
3649 pRawDataSet[idxL].
3650 vpdPdg[i],
3651 AR5416_PD_GAIN_ICEPTS,
3652 vpdTableI[i]);
3653 }
3654 } else {
3655 for (i = 0; i < numXpdGains; i++) {
3656 pVpdL = pRawDataSet[idxL].vpdPdg[i];
3657 pPwrL = pRawDataSet[idxL].pwrPdg[i];
3658 pVpdR = pRawDataSet[idxR].vpdPdg[i];
3659 pPwrR = pRawDataSet[idxR].pwrPdg[i];
3660
3661 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3662
3663 maxPwrT4[i] =
3664 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3665 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3666
3667
3668 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3669 pPwrL, pVpdL,
3670 AR5416_PD_GAIN_ICEPTS,
3671 vpdTableL[i]);
3672 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3673 pPwrR, pVpdR,
3674 AR5416_PD_GAIN_ICEPTS,
3675 vpdTableR[i]);
3676
3677 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3678 vpdTableI[i][j] =
3679 (u8) (ath9k_hw_interpolate
3680 ((u16)
3681 FREQ2FBIN(centers.
3682 synth_center,
3683 IS_CHAN_2GHZ
3684 (chan)),
3685 bChans[idxL],
3686 bChans[idxR], vpdTableL[i]
3687 [j], vpdTableR[i]
3688 [j]));
3689 }
3690 }
3691 }
3692
3693 *pMinCalPower = (int16_t) (minPwrT4[0] / 2);
3694
3695 k = 0;
3696 for (i = 0; i < numXpdGains; i++) {
3697 if (i == (numXpdGains - 1))
3698 pPdGainBoundaries[i] =
3699 (u16) (maxPwrT4[i] / 2);
3700 else
3701 pPdGainBoundaries[i] =
3702 (u16) ((maxPwrT4[i] +
3703 minPwrT4[i + 1]) / 4);
3704
3705 pPdGainBoundaries[i] =
3706 min((u16) AR5416_MAX_RATE_POWER,
3707 pPdGainBoundaries[i]);
3708
3709 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
3710 minDelta = pPdGainBoundaries[0] - 23;
3711 pPdGainBoundaries[0] = 23;
3712 } else {
3713 minDelta = 0;
3714 }
3715
3716 if (i == 0) {
3717 if (AR_SREV_9280_10_OR_LATER(ah))
3718 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3719 else
3720 ss = 0;
3721 } else {
3722 ss = (int16_t) ((pPdGainBoundaries[i - 1] -
3723 (minPwrT4[i] / 2)) -
3724 tPdGainOverlap + 1 + minDelta);
3725 }
3726 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3727 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3728
3729 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3730 tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3731 pPDADCValues[k++] =
3732 (u8) ((tmpVal < 0) ? 0 : tmpVal);
3733 ss++;
3734 }
3735
3736 sizeCurrVpdTable =
3737 (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3738 tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
3739 (minPwrT4[i] / 2));
3740 maxIndex = (tgtIndex <
3741 sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3742
3743 while ((ss < maxIndex)
3744 && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3745 pPDADCValues[k++] = vpdTableI[i][ss++];
3746 }
3747
3748 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] -
3749 vpdTableI[i][sizeCurrVpdTable - 2]);
3750 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3751
3752 if (tgtIndex > maxIndex) {
3753 while ((ss <= tgtIndex)
3754 && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3755 tmpVal = (int16_t) ((vpdTableI[i]
3756 [sizeCurrVpdTable -
3757 1] + (ss - maxIndex +
3758 1) * vpdStep));
3759 pPDADCValues[k++] = (u8) ((tmpVal >
3760 255) ? 255 : tmpVal);
3761 ss++;
3762 }
3763 }
3764 }
3765
3766 while (i < AR5416_PD_GAINS_IN_MASK) {
3767 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3768 i++;
3769 }
3770
3771 while (k < AR5416_NUM_PDADC_VALUES) {
3772 pPDADCValues[k] = pPDADCValues[k - 1];
3773 k++;
3774 }
3775 return;
3776 }
3777
3778 static bool
3779 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3780 struct ar5416_eeprom *pEepData,
3781 struct ath9k_channel *chan,
3782 int16_t *pTxPowerIndexOffset)
3783 {
3784 struct cal_data_per_freq *pRawDataset;
3785 u8 *pCalBChans = NULL;
3786 u16 pdGainOverlap_t2;
3787 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
3788 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3789 u16 numPiers, i, j;
3790 int16_t tMinCalPower;
3791 u16 numXpdGain, xpdMask;
3792 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3793 u32 reg32, regOffset, regChainOffset;
3794 int16_t modalIdx;
3795 struct ath_hal_5416 *ahp = AH5416(ah);
3796
3797 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
3798 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
3799
3800 if ((pEepData->baseEepHeader.
3801 version & AR5416_EEP_VER_MINOR_MASK) >=
3802 AR5416_EEP_MINOR_VER_2) {
3803 pdGainOverlap_t2 =
3804 pEepData->modalHeader[modalIdx].pdGainOverlap;
3805 } else {
3806 pdGainOverlap_t2 =
3807 (u16) (MS
3808 (REG_READ(ah, AR_PHY_TPCRG5),
3809 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3810 }
3811
3812 if (IS_CHAN_2GHZ(chan)) {
3813 pCalBChans = pEepData->calFreqPier2G;
3814 numPiers = AR5416_NUM_2G_CAL_PIERS;
3815 } else {
3816 pCalBChans = pEepData->calFreqPier5G;
3817 numPiers = AR5416_NUM_5G_CAL_PIERS;
3818 }
3819
3820 numXpdGain = 0;
3821
3822 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
3823 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
3824 if (numXpdGain >= AR5416_NUM_PD_GAINS)
3825 break;
3826 xpdGainValues[numXpdGain] =
3827 (u16) (AR5416_PD_GAINS_IN_MASK - i);
3828 numXpdGain++;
3829 }
3830 }
3831
3832 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
3833 (numXpdGain - 1) & 0x3);
3834 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
3835 xpdGainValues[0]);
3836 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3837 xpdGainValues[1]);
3838 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3839 xpdGainValues[2]);
3840
3841 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3842 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3843 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3844 && (i != 0)) {
3845 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3846 } else
3847 regChainOffset = i * 0x1000;
3848 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3849 if (IS_CHAN_2GHZ(chan))
3850 pRawDataset = pEepData->calPierData2G[i];
3851 else
3852 pRawDataset = pEepData->calPierData5G[i];
3853
3854 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3855 pRawDataset,
3856 pCalBChans,
3857 numPiers,
3858 pdGainOverlap_t2,
3859 &tMinCalPower,
3860 gainBoundaries,
3861 pdadcValues,
3862 numXpdGain);
3863
3864 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3865
3866 REG_WRITE(ah,
3867 AR_PHY_TPCRG5 + regChainOffset,
3868 SM(pdGainOverlap_t2,
3869 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3870 | SM(gainBoundaries[0],
3871 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3872 | SM(gainBoundaries[1],
3873 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3874 | SM(gainBoundaries[2],
3875 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3876 | SM(gainBoundaries[3],
3877 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3878 }
3879
3880 regOffset =
3881 AR_PHY_BASE + (672 << 2) + regChainOffset;
3882 for (j = 0; j < 32; j++) {
3883 reg32 =
3884 ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3885 | ((pdadcValues[4 * j + 1] & 0xFF) <<
3886 8) | ((pdadcValues[4 * j + 2] &
3887 0xFF) << 16) |
3888 ((pdadcValues[4 * j + 3] & 0xFF) <<
3889 24);
3890 REG_WRITE(ah, regOffset, reg32);
3891
3892 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3893 "PDADC (%d,%4x): %4.4x %8.8x\n",
3894 i, regChainOffset, regOffset,
3895 reg32);
3896 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3897 "PDADC: Chain %d | PDADC %3d Value %3d | "
3898 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3899 "PDADC %3d Value %3d |\n",
3900 i, 4 * j, pdadcValues[4 * j],
3901 4 * j + 1, pdadcValues[4 * j + 1],
3902 4 * j + 2, pdadcValues[4 * j + 2],
3903 4 * j + 3,
3904 pdadcValues[4 * j + 3]);
3905
3906 regOffset += 4;
3907 }
3908 }
3909 }
3910 *pTxPowerIndexOffset = 0;
3911
3912 return true;
3913 }
3914
3915 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3916 {
3917 struct ath_hal_5416 *ahp = AH5416(ah);
3918 u8 i;
3919
3920 if (ah->ah_isPciExpress != true)
3921 return;
3922
3923 if (ah->ah_config.pcie_powersave_enable == 2)
3924 return;
3925
3926 if (restore)
3927 return;
3928
3929 if (AR_SREV_9280_20_OR_LATER(ah)) {
3930 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3931 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3932 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3933 }
3934 udelay(1000);
3935 } else if (AR_SREV_9280(ah)
3936 && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3937 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3938 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3939
3940 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3941 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3942 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3943
3944 if (ah->ah_config.pcie_clock_req)
3945 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3946 else
3947 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3948
3949 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3950 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3951 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3952
3953 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3954
3955 udelay(1000);
3956 } else {
3957 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3958 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3959 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3960 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3961 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3962 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3963 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3964 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3965 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3966 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3967 }
3968
3969 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3970
3971 if (ah->ah_config.pcie_waen) {
3972 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
3973 } else {
3974 if (AR_SREV_9280(ah))
3975 REG_WRITE(ah, AR_WA, 0x0040073f);
3976 else
3977 REG_WRITE(ah, AR_WA, 0x0000073f);
3978 }
3979 }
3980
3981 static void
3982 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3983 struct ath9k_channel *chan,
3984 struct cal_target_power_leg *powInfo,
3985 u16 numChannels,
3986 struct cal_target_power_leg *pNewPower,
3987 u16 numRates,
3988 bool isExtTarget)
3989 {
3990 u16 clo, chi;
3991 int i;
3992 int matchIndex = -1, lowIndex = -1;
3993 u16 freq;
3994 struct chan_centers centers;
3995
3996 ath9k_hw_get_channel_centers(ah, chan, &centers);
3997 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3998
3999 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
4000 IS_CHAN_2GHZ(chan))) {
4001 matchIndex = 0;
4002 } else {
4003 for (i = 0; (i < numChannels)
4004 && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4005 if (freq ==
4006 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4007 IS_CHAN_2GHZ(chan))) {
4008 matchIndex = i;
4009 break;
4010 } else if ((freq <
4011 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4012 IS_CHAN_2GHZ(chan)))
4013 && (freq >
4014 ath9k_hw_fbin2freq(powInfo[i - 1].
4015 bChannel,
4016 IS_CHAN_2GHZ
4017 (chan)))) {
4018 lowIndex = i - 1;
4019 break;
4020 }
4021 }
4022 if ((matchIndex == -1) && (lowIndex == -1))
4023 matchIndex = i - 1;
4024 }
4025
4026 if (matchIndex != -1) {
4027 *pNewPower = powInfo[matchIndex];
4028 } else {
4029 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4030 IS_CHAN_2GHZ(chan));
4031 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4032 IS_CHAN_2GHZ(chan));
4033
4034 for (i = 0; i < numRates; i++) {
4035 pNewPower->tPow2x[i] =
4036 (u8) ath9k_hw_interpolate(freq, clo, chi,
4037 powInfo
4038 [lowIndex].
4039 tPow2x[i],
4040 powInfo
4041 [lowIndex +
4042 1].tPow2x[i]);
4043 }
4044 }
4045 }
4046
4047 static void
4048 ath9k_hw_get_target_powers(struct ath_hal *ah,
4049 struct ath9k_channel *chan,
4050 struct cal_target_power_ht *powInfo,
4051 u16 numChannels,
4052 struct cal_target_power_ht *pNewPower,
4053 u16 numRates,
4054 bool isHt40Target)
4055 {
4056 u16 clo, chi;
4057 int i;
4058 int matchIndex = -1, lowIndex = -1;
4059 u16 freq;
4060 struct chan_centers centers;
4061
4062 ath9k_hw_get_channel_centers(ah, chan, &centers);
4063 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
4064
4065 if (freq <=
4066 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
4067 matchIndex = 0;
4068 } else {
4069 for (i = 0; (i < numChannels)
4070 && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4071 if (freq ==
4072 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4073 IS_CHAN_2GHZ(chan))) {
4074 matchIndex = i;
4075 break;
4076 } else
4077 if ((freq <
4078 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4079 IS_CHAN_2GHZ(chan)))
4080 && (freq >
4081 ath9k_hw_fbin2freq(powInfo[i - 1].
4082 bChannel,
4083 IS_CHAN_2GHZ
4084 (chan)))) {
4085 lowIndex = i - 1;
4086 break;
4087 }
4088 }
4089 if ((matchIndex == -1) && (lowIndex == -1))
4090 matchIndex = i - 1;
4091 }
4092
4093 if (matchIndex != -1) {
4094 *pNewPower = powInfo[matchIndex];
4095 } else {
4096 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4097 IS_CHAN_2GHZ(chan));
4098 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4099 IS_CHAN_2GHZ(chan));
4100
4101 for (i = 0; i < numRates; i++) {
4102 pNewPower->tPow2x[i] =
4103 (u8) ath9k_hw_interpolate(freq, clo, chi,
4104 powInfo
4105 [lowIndex].
4106 tPow2x[i],
4107 powInfo
4108 [lowIndex +
4109 1].tPow2x[i]);
4110 }
4111 }
4112 }
4113
4114 static u16
4115 ath9k_hw_get_max_edge_power(u16 freq,
4116 struct cal_ctl_edges *pRdEdgesPower,
4117 bool is2GHz)
4118 {
4119 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4120 int i;
4121
4122 for (i = 0; (i < AR5416_NUM_BAND_EDGES)
4123 && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4124 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
4125 is2GHz)) {
4126 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
4127 break;
4128 } else if ((i > 0)
4129 && (freq <
4130 ath9k_hw_fbin2freq(pRdEdgesPower[i].
4131 bChannel, is2GHz))) {
4132 if (ath9k_hw_fbin2freq
4133 (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq
4134 && pRdEdgesPower[i - 1].flag) {
4135 twiceMaxEdgePower =
4136 pRdEdgesPower[i - 1].tPower;
4137 }
4138 break;
4139 }
4140 }
4141 return twiceMaxEdgePower;
4142 }
4143
4144 static bool
4145 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
4146 struct ar5416_eeprom *pEepData,
4147 struct ath9k_channel *chan,
4148 int16_t *ratesArray,
4149 u16 cfgCtl,
4150 u8 AntennaReduction,
4151 u8 twiceMaxRegulatoryPower,
4152 u8 powerLimit)
4153 {
4154 u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4155 static const u16 tpScaleReductionTable[5] =
4156 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4157
4158 int i;
4159 int8_t twiceLargestAntenna;
4160 struct cal_ctl_data *rep;
4161 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
4162 0, { 0, 0, 0, 0}
4163 };
4164 struct cal_target_power_leg targetPowerOfdmExt = {
4165 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
4166 0, { 0, 0, 0, 0 }
4167 };
4168 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
4169 0, {0, 0, 0, 0}
4170 };
4171 u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4172 u16 ctlModesFor11a[] =
4173 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4174 u16 ctlModesFor11g[] =
4175 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4176 CTL_2GHT40
4177 };
4178 u16 numCtlModes, *pCtlMode, ctlMode, freq;
4179 struct chan_centers centers;
4180 int tx_chainmask;
4181 u8 twiceMinEdgePower;
4182 struct ath_hal_5416 *ahp = AH5416(ah);
4183
4184 tx_chainmask = ahp->ah_txchainmask;
4185
4186 ath9k_hw_get_channel_centers(ah, chan, &centers);
4187
4188 twiceLargestAntenna = max(
4189 pEepData->modalHeader
4190 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
4191 pEepData->modalHeader
4192 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
4193
4194 twiceLargestAntenna = max((u8) twiceLargestAntenna,
4195 pEepData->modalHeader
4196 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
4197
4198 twiceLargestAntenna =
4199 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0);
4200
4201 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4202
4203 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
4204 maxRegAllowedPower -=
4205 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
4206 }
4207
4208 scaledPower = min(powerLimit, maxRegAllowedPower);
4209
4210 switch (ar5416_get_ntxchains(tx_chainmask)) {
4211 case 1:
4212 break;
4213 case 2:
4214 scaledPower -=
4215 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4216 pwrDecreaseFor2Chain;
4217 break;
4218 case 3:
4219 scaledPower -=
4220 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4221 pwrDecreaseFor3Chain;
4222 break;
4223 }
4224
4225 scaledPower = max(0, (int32_t) scaledPower);
4226
4227 if (IS_CHAN_2GHZ(chan)) {
4228 numCtlModes =
4229 ARRAY_SIZE(ctlModesFor11g) -
4230 SUB_NUM_CTL_MODES_AT_2G_40;
4231 pCtlMode = ctlModesFor11g;
4232
4233 ath9k_hw_get_legacy_target_powers(ah, chan,
4234 pEepData->
4235 calTargetPowerCck,
4236 AR5416_NUM_2G_CCK_TARGET_POWERS,
4237 &targetPowerCck, 4,
4238 false);
4239 ath9k_hw_get_legacy_target_powers(ah, chan,
4240 pEepData->
4241 calTargetPower2G,
4242 AR5416_NUM_2G_20_TARGET_POWERS,
4243 &targetPowerOfdm, 4,
4244 false);
4245 ath9k_hw_get_target_powers(ah, chan,
4246 pEepData->calTargetPower2GHT20,
4247 AR5416_NUM_2G_20_TARGET_POWERS,
4248 &targetPowerHt20, 8, false);
4249
4250 if (IS_CHAN_HT40(chan)) {
4251 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4252 ath9k_hw_get_target_powers(ah, chan,
4253 pEepData->
4254 calTargetPower2GHT40,
4255 AR5416_NUM_2G_40_TARGET_POWERS,
4256 &targetPowerHt40, 8,
4257 true);
4258 ath9k_hw_get_legacy_target_powers(ah, chan,
4259 pEepData->
4260 calTargetPowerCck,
4261 AR5416_NUM_2G_CCK_TARGET_POWERS,
4262 &targetPowerCckExt,
4263 4, true);
4264 ath9k_hw_get_legacy_target_powers(ah, chan,
4265 pEepData->
4266 calTargetPower2G,
4267 AR5416_NUM_2G_20_TARGET_POWERS,
4268 &targetPowerOfdmExt,
4269 4, true);
4270 }
4271 } else {
4272
4273 numCtlModes =
4274 ARRAY_SIZE(ctlModesFor11a) -
4275 SUB_NUM_CTL_MODES_AT_5G_40;
4276 pCtlMode = ctlModesFor11a;
4277
4278 ath9k_hw_get_legacy_target_powers(ah, chan,
4279 pEepData->
4280 calTargetPower5G,
4281 AR5416_NUM_5G_20_TARGET_POWERS,
4282 &targetPowerOfdm, 4,
4283 false);
4284 ath9k_hw_get_target_powers(ah, chan,
4285 pEepData->calTargetPower5GHT20,
4286 AR5416_NUM_5G_20_TARGET_POWERS,
4287 &targetPowerHt20, 8, false);
4288
4289 if (IS_CHAN_HT40(chan)) {
4290 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4291 ath9k_hw_get_target_powers(ah, chan,
4292 pEepData->
4293 calTargetPower5GHT40,
4294 AR5416_NUM_5G_40_TARGET_POWERS,
4295 &targetPowerHt40, 8,
4296 true);
4297 ath9k_hw_get_legacy_target_powers(ah, chan,
4298 pEepData->
4299 calTargetPower5G,
4300 AR5416_NUM_5G_20_TARGET_POWERS,
4301 &targetPowerOfdmExt,
4302 4, true);
4303 }
4304 }
4305
4306 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4307 bool isHt40CtlMode =
4308 (pCtlMode[ctlMode] == CTL_5GHT40)
4309 || (pCtlMode[ctlMode] == CTL_2GHT40);
4310 if (isHt40CtlMode)
4311 freq = centers.synth_center;
4312 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4313 freq = centers.ext_center;
4314 else
4315 freq = centers.ctl_center;
4316
4317 if (ar5416_get_eep_ver(ahp) == 14
4318 && ar5416_get_eep_rev(ahp) <= 2)
4319 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4320
4321 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4322 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4323 "EXT_ADDITIVE %d\n",
4324 ctlMode, numCtlModes, isHt40CtlMode,
4325 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4326
4327 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
4328 i++) {
4329 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4330 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4331 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4332 "chan %d\n",
4333 i, cfgCtl, pCtlMode[ctlMode],
4334 pEepData->ctlIndex[i], chan->channel);
4335
4336 if ((((cfgCtl & ~CTL_MODE_M) |
4337 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4338 pEepData->ctlIndex[i])
4339 ||
4340 (((cfgCtl & ~CTL_MODE_M) |
4341 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4342 ((pEepData->
4343 ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4344 rep = &(pEepData->ctlData[i]);
4345
4346 twiceMinEdgePower =
4347 ath9k_hw_get_max_edge_power(freq,
4348 rep->
4349 ctlEdges
4350 [ar5416_get_ntxchains
4351 (tx_chainmask)
4352 - 1],
4353 IS_CHAN_2GHZ
4354 (chan));
4355
4356 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4357 " MATCH-EE_IDX %d: ch %d is2 %d "
4358 "2xMinEdge %d chainmask %d chains %d\n",
4359 i, freq, IS_CHAN_2GHZ(chan),
4360 twiceMinEdgePower, tx_chainmask,
4361 ar5416_get_ntxchains
4362 (tx_chainmask));
4363 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4364 twiceMaxEdgePower =
4365 min(twiceMaxEdgePower,
4366 twiceMinEdgePower);
4367 } else {
4368 twiceMaxEdgePower =
4369 twiceMinEdgePower;
4370 break;
4371 }
4372 }
4373 }
4374
4375 minCtlPower = min(twiceMaxEdgePower, scaledPower);
4376
4377 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4378 " SEL-Min ctlMode %d pCtlMode %d "
4379 "2xMaxEdge %d sP %d minCtlPwr %d\n",
4380 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4381 scaledPower, minCtlPower);
4382
4383 switch (pCtlMode[ctlMode]) {
4384 case CTL_11B:
4385 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4386 i++) {
4387 targetPowerCck.tPow2x[i] =
4388 min(targetPowerCck.tPow2x[i],
4389 minCtlPower);
4390 }
4391 break;
4392 case CTL_11A:
4393 case CTL_11G:
4394 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4395 i++) {
4396 targetPowerOfdm.tPow2x[i] =
4397 min(targetPowerOfdm.tPow2x[i],
4398 minCtlPower);
4399 }
4400 break;
4401 case CTL_5GHT20:
4402 case CTL_2GHT20:
4403 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4404 i++) {
4405 targetPowerHt20.tPow2x[i] =
4406 min(targetPowerHt20.tPow2x[i],
4407 minCtlPower);
4408 }
4409 break;
4410 case CTL_11B_EXT:
4411 targetPowerCckExt.tPow2x[0] =
4412 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4413 break;
4414 case CTL_11A_EXT:
4415 case CTL_11G_EXT:
4416 targetPowerOfdmExt.tPow2x[0] =
4417 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4418 break;
4419 case CTL_5GHT40:
4420 case CTL_2GHT40:
4421 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4422 i++) {
4423 targetPowerHt40.tPow2x[i] =
4424 min(targetPowerHt40.tPow2x[i],
4425 minCtlPower);
4426 }
4427 break;
4428 default:
4429 break;
4430 }
4431 }
4432
4433 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
4434 ratesArray[rate18mb] = ratesArray[rate24mb] =
4435 targetPowerOfdm.tPow2x[0];
4436 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
4437 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
4438 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
4439 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
4440
4441 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
4442 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
4443
4444 if (IS_CHAN_2GHZ(chan)) {
4445 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
4446 ratesArray[rate2s] = ratesArray[rate2l] =
4447 targetPowerCck.tPow2x[1];
4448 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4449 targetPowerCck.tPow2x[2];
4450 ;
4451 ratesArray[rate11s] = ratesArray[rate11l] =
4452 targetPowerCck.tPow2x[3];
4453 ;
4454 }
4455 if (IS_CHAN_HT40(chan)) {
4456 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
4457 ratesArray[rateHt40_0 + i] =
4458 targetPowerHt40.tPow2x[i];
4459 }
4460 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
4461 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
4462 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
4463 if (IS_CHAN_2GHZ(chan)) {
4464 ratesArray[rateExtCck] =
4465 targetPowerCckExt.tPow2x[0];
4466 }
4467 }
4468 return true;
4469 }
4470
4471 static int
4472 ath9k_hw_set_txpower(struct ath_hal *ah,
4473 struct ar5416_eeprom *pEepData,
4474 struct ath9k_channel *chan,
4475 u16 cfgCtl,
4476 u8 twiceAntennaReduction,
4477 u8 twiceMaxRegulatoryPower,
4478 u8 powerLimit)
4479 {
4480 struct modal_eep_header *pModal =
4481 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4482 int16_t ratesArray[Ar5416RateSize];
4483 int16_t txPowerIndexOffset = 0;
4484 u8 ht40PowerIncForPdadc = 2;
4485 int i;
4486
4487 memset(ratesArray, 0, sizeof(ratesArray));
4488
4489 if ((pEepData->baseEepHeader.
4490 version & AR5416_EEP_VER_MINOR_MASK) >=
4491 AR5416_EEP_MINOR_VER_2) {
4492 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4493 }
4494
4495 if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan,
4496 &ratesArray[0], cfgCtl,
4497 twiceAntennaReduction,
4498 twiceMaxRegulatoryPower,
4499 powerLimit)) {
4500 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4501 "ath9k_hw_set_txpower: unable to set "
4502 "tx power per rate table\n");
4503 return -EIO;
4504 }
4505
4506 if (!ath9k_hw_set_power_cal_table
4507 (ah, pEepData, chan, &txPowerIndexOffset)) {
4508 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4509 "ath9k_hw_set_txpower: unable to set power table\n");
4510 return -EIO;
4511 }
4512
4513 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4514 ratesArray[i] =
4515 (int16_t) (txPowerIndexOffset + ratesArray[i]);
4516 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4517 ratesArray[i] = AR5416_MAX_RATE_POWER;
4518 }
4519
4520 if (AR_SREV_9280_10_OR_LATER(ah)) {
4521 for (i = 0; i < Ar5416RateSize; i++)
4522 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
4523 }
4524
4525 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
4526 ATH9K_POW_SM(ratesArray[rate18mb], 24)
4527 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
4528 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4529 | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4530 );
4531 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4532 ATH9K_POW_SM(ratesArray[rate54mb], 24)
4533 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4534 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4535 | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4536 );
4537
4538 if (IS_CHAN_2GHZ(chan)) {
4539 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4540 ATH9K_POW_SM(ratesArray[rate2s], 24)
4541 | ATH9K_POW_SM(ratesArray[rate2l], 16)
4542 | ATH9K_POW_SM(ratesArray[rateXr], 8)
4543 | ATH9K_POW_SM(ratesArray[rate1l], 0)
4544 );
4545 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4546 ATH9K_POW_SM(ratesArray[rate11s], 24)
4547 | ATH9K_POW_SM(ratesArray[rate11l], 16)
4548 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4549 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4550 );
4551 }
4552
4553 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
4554 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
4555 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4556 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4557 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4558 );
4559 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4560 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4561 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4562 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4563 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4564 );
4565
4566 if (IS_CHAN_HT40(chan)) {
4567 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
4568 ATH9K_POW_SM(ratesArray[rateHt40_3] +
4569 ht40PowerIncForPdadc, 24)
4570 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4571 ht40PowerIncForPdadc, 16)
4572 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4573 ht40PowerIncForPdadc, 8)
4574 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4575 ht40PowerIncForPdadc, 0)
4576 );
4577 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4578 ATH9K_POW_SM(ratesArray[rateHt40_7] +
4579 ht40PowerIncForPdadc, 24)
4580 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4581 ht40PowerIncForPdadc, 16)
4582 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4583 ht40PowerIncForPdadc, 8)
4584 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4585 ht40PowerIncForPdadc, 0)
4586 );
4587
4588 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4589 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4590 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4591 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4592 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4593 );
4594 }
4595
4596 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
4597 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
4598 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)
4599 );
4600
4601 i = rate6mb;
4602 if (IS_CHAN_HT40(chan))
4603 i = rateHt40_0;
4604 else if (IS_CHAN_HT20(chan))
4605 i = rateHt20_0;
4606
4607 if (AR_SREV_9280_10_OR_LATER(ah))
4608 ah->ah_maxPowerLevel =
4609 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4610 else
4611 ah->ah_maxPowerLevel = ratesArray[i];
4612
4613 return 0;
4614 }
4615
4616 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4617 u32 coef_scaled,
4618 u32 *coef_mantissa,
4619 u32 *coef_exponent)
4620 {
4621 u32 coef_exp, coef_man;
4622
4623 for (coef_exp = 31; coef_exp > 0; coef_exp--)
4624 if ((coef_scaled >> coef_exp) & 0x1)
4625 break;
4626
4627 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
4628
4629 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
4630
4631 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
4632 *coef_exponent = coef_exp - 16;
4633 }
4634
4635 static void
4636 ath9k_hw_set_delta_slope(struct ath_hal *ah,
4637 struct ath9k_channel *chan)
4638 {
4639 u32 coef_scaled, ds_coef_exp, ds_coef_man;
4640 u32 clockMhzScaled = 0x64000000;
4641 struct chan_centers centers;
4642
4643 if (IS_CHAN_HALF_RATE(chan))
4644 clockMhzScaled = clockMhzScaled >> 1;
4645 else if (IS_CHAN_QUARTER_RATE(chan))
4646 clockMhzScaled = clockMhzScaled >> 2;
4647
4648 ath9k_hw_get_channel_centers(ah, chan, &centers);
4649 coef_scaled = clockMhzScaled / centers.synth_center;
4650
4651 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4652 &ds_coef_exp);
4653
4654 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4655 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
4656 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4657 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
4658
4659 coef_scaled = (9 * coef_scaled) / 10;
4660
4661 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4662 &ds_coef_exp);
4663
4664 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4665 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
4666 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4667 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4668 }
4669
4670 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4671 struct ath9k_channel *chan)
4672 {
4673 int bb_spur = AR_NO_SPUR;
4674 int freq;
4675 int bin, cur_bin;
4676 int bb_spur_off, spur_subchannel_sd;
4677 int spur_freq_sd;
4678 int spur_delta_phase;
4679 int denominator;
4680 int upper, lower, cur_vit_mask;
4681 int tmp, newVal;
4682 int i;
4683 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4684 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4685 };
4686 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4687 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4688 };
4689 int inc[4] = { 0, 100, 0, 0 };
4690 struct chan_centers centers;
4691
4692 int8_t mask_m[123];
4693 int8_t mask_p[123];
4694 int8_t mask_amt;
4695 int tmp_mask;
4696 int cur_bb_spur;
4697 bool is2GHz = IS_CHAN_2GHZ(chan);
4698
4699 memset(&mask_m, 0, sizeof(int8_t) * 123);
4700 memset(&mask_p, 0, sizeof(int8_t) * 123);
4701
4702 ath9k_hw_get_channel_centers(ah, chan, &centers);
4703 freq = centers.synth_center;
4704
4705 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
4706 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4707 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4708
4709 if (is2GHz)
4710 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
4711 else
4712 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
4713
4714 if (AR_NO_SPUR == cur_bb_spur)
4715 break;
4716 cur_bb_spur = cur_bb_spur - freq;
4717
4718 if (IS_CHAN_HT40(chan)) {
4719 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
4720 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
4721 bb_spur = cur_bb_spur;
4722 break;
4723 }
4724 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
4725 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
4726 bb_spur = cur_bb_spur;
4727 break;
4728 }
4729 }
4730
4731 if (AR_NO_SPUR == bb_spur) {
4732 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4733 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4734 return;
4735 } else {
4736 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4737 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4738 }
4739
4740 bin = bb_spur * 320;
4741
4742 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4743
4744 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4745 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4746 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4747 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4748 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
4749
4750 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4751 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4752 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4753 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4754 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4755 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
4756
4757 if (IS_CHAN_HT40(chan)) {
4758 if (bb_spur < 0) {
4759 spur_subchannel_sd = 1;
4760 bb_spur_off = bb_spur + 10;
4761 } else {
4762 spur_subchannel_sd = 0;
4763 bb_spur_off = bb_spur - 10;
4764 }
4765 } else {
4766 spur_subchannel_sd = 0;
4767 bb_spur_off = bb_spur;
4768 }
4769
4770 if (IS_CHAN_HT40(chan))
4771 spur_delta_phase =
4772 ((bb_spur * 262144) /
4773 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4774 else
4775 spur_delta_phase =
4776 ((bb_spur * 524288) /
4777 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4778
4779 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
4780 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
4781
4782 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4783 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4784 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4785 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
4786
4787 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
4788 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
4789
4790 cur_bin = -6000;
4791 upper = bin + 100;
4792 lower = bin - 100;
4793
4794 for (i = 0; i < 4; i++) {
4795 int pilot_mask = 0;
4796 int chan_mask = 0;
4797 int bp = 0;
4798 for (bp = 0; bp < 30; bp++) {
4799 if ((cur_bin > lower) && (cur_bin < upper)) {
4800 pilot_mask = pilot_mask | 0x1 << bp;
4801 chan_mask = chan_mask | 0x1 << bp;
4802 }
4803 cur_bin += 100;
4804 }
4805 cur_bin += inc[i];
4806 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4807 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4808 }
4809
4810 cur_vit_mask = 6100;
4811 upper = bin + 120;
4812 lower = bin - 120;
4813
4814 for (i = 0; i < 123; i++) {
4815 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4816
4817 /* workaround for gcc bug #37014 */
4818 volatile int tmp = abs(cur_vit_mask - bin);
4819
4820 if (tmp < 75)
4821 mask_amt = 1;
4822 else
4823 mask_amt = 0;
4824 if (cur_vit_mask < 0)
4825 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
4826 else
4827 mask_p[cur_vit_mask / 100] = mask_amt;
4828 }
4829 cur_vit_mask -= 100;
4830 }
4831
4832 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
4833 | (mask_m[48] << 26) | (mask_m[49] << 24)
4834 | (mask_m[50] << 22) | (mask_m[51] << 20)
4835 | (mask_m[52] << 18) | (mask_m[53] << 16)
4836 | (mask_m[54] << 14) | (mask_m[55] << 12)
4837 | (mask_m[56] << 10) | (mask_m[57] << 8)
4838 | (mask_m[58] << 6) | (mask_m[59] << 4)
4839 | (mask_m[60] << 2) | (mask_m[61] << 0);
4840 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
4841 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
4842
4843 tmp_mask = (mask_m[31] << 28)
4844 | (mask_m[32] << 26) | (mask_m[33] << 24)
4845 | (mask_m[34] << 22) | (mask_m[35] << 20)
4846 | (mask_m[36] << 18) | (mask_m[37] << 16)
4847 | (mask_m[48] << 14) | (mask_m[39] << 12)
4848 | (mask_m[40] << 10) | (mask_m[41] << 8)
4849 | (mask_m[42] << 6) | (mask_m[43] << 4)
4850 | (mask_m[44] << 2) | (mask_m[45] << 0);
4851 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
4852 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
4853
4854 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
4855 | (mask_m[18] << 26) | (mask_m[18] << 24)
4856 | (mask_m[20] << 22) | (mask_m[20] << 20)
4857 | (mask_m[22] << 18) | (mask_m[22] << 16)
4858 | (mask_m[24] << 14) | (mask_m[24] << 12)
4859 | (mask_m[25] << 10) | (mask_m[26] << 8)
4860 | (mask_m[27] << 6) | (mask_m[28] << 4)
4861 | (mask_m[29] << 2) | (mask_m[30] << 0);
4862 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
4863 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
4864
4865 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
4866 | (mask_m[2] << 26) | (mask_m[3] << 24)
4867 | (mask_m[4] << 22) | (mask_m[5] << 20)
4868 | (mask_m[6] << 18) | (mask_m[7] << 16)
4869 | (mask_m[8] << 14) | (mask_m[9] << 12)
4870 | (mask_m[10] << 10) | (mask_m[11] << 8)
4871 | (mask_m[12] << 6) | (mask_m[13] << 4)
4872 | (mask_m[14] << 2) | (mask_m[15] << 0);
4873 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
4874 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
4875
4876 tmp_mask = (mask_p[15] << 28)
4877 | (mask_p[14] << 26) | (mask_p[13] << 24)
4878 | (mask_p[12] << 22) | (mask_p[11] << 20)
4879 | (mask_p[10] << 18) | (mask_p[9] << 16)
4880 | (mask_p[8] << 14) | (mask_p[7] << 12)
4881 | (mask_p[6] << 10) | (mask_p[5] << 8)
4882 | (mask_p[4] << 6) | (mask_p[3] << 4)
4883 | (mask_p[2] << 2) | (mask_p[1] << 0);
4884 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
4885 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
4886
4887 tmp_mask = (mask_p[30] << 28)
4888 | (mask_p[29] << 26) | (mask_p[28] << 24)
4889 | (mask_p[27] << 22) | (mask_p[26] << 20)
4890 | (mask_p[25] << 18) | (mask_p[24] << 16)
4891 | (mask_p[23] << 14) | (mask_p[22] << 12)
4892 | (mask_p[21] << 10) | (mask_p[20] << 8)
4893 | (mask_p[19] << 6) | (mask_p[18] << 4)
4894 | (mask_p[17] << 2) | (mask_p[16] << 0);
4895 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
4896 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
4897
4898 tmp_mask = (mask_p[45] << 28)
4899 | (mask_p[44] << 26) | (mask_p[43] << 24)
4900 | (mask_p[42] << 22) | (mask_p[41] << 20)
4901 | (mask_p[40] << 18) | (mask_p[39] << 16)
4902 | (mask_p[38] << 14) | (mask_p[37] << 12)
4903 | (mask_p[36] << 10) | (mask_p[35] << 8)
4904 | (mask_p[34] << 6) | (mask_p[33] << 4)
4905 | (mask_p[32] << 2) | (mask_p[31] << 0);
4906 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
4907 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
4908
4909 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
4910 | (mask_p[59] << 26) | (mask_p[58] << 24)
4911 | (mask_p[57] << 22) | (mask_p[56] << 20)
4912 | (mask_p[55] << 18) | (mask_p[54] << 16)
4913 | (mask_p[53] << 14) | (mask_p[52] << 12)
4914 | (mask_p[51] << 10) | (mask_p[50] << 8)
4915 | (mask_p[49] << 6) | (mask_p[48] << 4)
4916 | (mask_p[47] << 2) | (mask_p[46] << 0);
4917 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
4918 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4919 }
4920
4921 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
4922 struct ath9k_channel *chan)
4923 {
4924 int bb_spur = AR_NO_SPUR;
4925 int bin, cur_bin;
4926 int spur_freq_sd;
4927 int spur_delta_phase;
4928 int denominator;
4929 int upper, lower, cur_vit_mask;
4930 int tmp, new;
4931 int i;
4932 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4933 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4934 };
4935 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4936 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4937 };
4938 int inc[4] = { 0, 100, 0, 0 };
4939
4940 int8_t mask_m[123];
4941 int8_t mask_p[123];
4942 int8_t mask_amt;
4943 int tmp_mask;
4944 int cur_bb_spur;
4945 bool is2GHz = IS_CHAN_2GHZ(chan);
4946
4947 memset(&mask_m, 0, sizeof(int8_t) * 123);
4948 memset(&mask_p, 0, sizeof(int8_t) * 123);
4949
4950 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4951 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4952 if (AR_NO_SPUR == cur_bb_spur)
4953 break;
4954 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
4955 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
4956 bb_spur = cur_bb_spur;
4957 break;
4958 }
4959 }
4960
4961 if (AR_NO_SPUR == bb_spur)
4962 return;
4963
4964 bin = bb_spur * 32;
4965
4966 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4967 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4968 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4969 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4970 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4971
4972 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
4973
4974 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4975 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4976 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4977 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4978 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4979 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
4980
4981 spur_delta_phase = ((bb_spur * 524288) / 100) &
4982 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4983
4984 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
4985 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
4986
4987 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4988 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4989 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4990 REG_WRITE(ah, AR_PHY_TIMING11, new);
4991
4992 cur_bin = -6000;
4993 upper = bin + 100;
4994 lower = bin - 100;
4995
4996 for (i = 0; i < 4; i++) {
4997 int pilot_mask = 0;
4998 int chan_mask = 0;
4999 int bp = 0;
5000 for (bp = 0; bp < 30; bp++) {
5001 if ((cur_bin > lower) && (cur_bin < upper)) {
5002 pilot_mask = pilot_mask | 0x1 << bp;
5003 chan_mask = chan_mask | 0x1 << bp;
5004 }
5005 cur_bin += 100;
5006 }
5007 cur_bin += inc[i];
5008 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
5009 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
5010 }
5011
5012 cur_vit_mask = 6100;
5013 upper = bin + 120;
5014 lower = bin - 120;
5015
5016 for (i = 0; i < 123; i++) {
5017 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
5018
5019 /* workaround for gcc bug #37014 */
5020 volatile int tmp = abs(cur_vit_mask - bin);
5021
5022 if (tmp < 75)
5023 mask_amt = 1;
5024 else
5025 mask_amt = 0;
5026 if (cur_vit_mask < 0)
5027 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
5028 else
5029 mask_p[cur_vit_mask / 100] = mask_amt;
5030 }
5031 cur_vit_mask -= 100;
5032 }
5033
5034 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
5035 | (mask_m[48] << 26) | (mask_m[49] << 24)
5036 | (mask_m[50] << 22) | (mask_m[51] << 20)
5037 | (mask_m[52] << 18) | (mask_m[53] << 16)
5038 | (mask_m[54] << 14) | (mask_m[55] << 12)
5039 | (mask_m[56] << 10) | (mask_m[57] << 8)
5040 | (mask_m[58] << 6) | (mask_m[59] << 4)
5041 | (mask_m[60] << 2) | (mask_m[61] << 0);
5042 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
5043 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
5044
5045 tmp_mask = (mask_m[31] << 28)
5046 | (mask_m[32] << 26) | (mask_m[33] << 24)
5047 | (mask_m[34] << 22) | (mask_m[35] << 20)
5048 | (mask_m[36] << 18) | (mask_m[37] << 16)
5049 | (mask_m[48] << 14) | (mask_m[39] << 12)
5050 | (mask_m[40] << 10) | (mask_m[41] << 8)
5051 | (mask_m[42] << 6) | (mask_m[43] << 4)
5052 | (mask_m[44] << 2) | (mask_m[45] << 0);
5053 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
5054 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
5055
5056 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
5057 | (mask_m[18] << 26) | (mask_m[18] << 24)
5058 | (mask_m[20] << 22) | (mask_m[20] << 20)
5059 | (mask_m[22] << 18) | (mask_m[22] << 16)
5060 | (mask_m[24] << 14) | (mask_m[24] << 12)
5061 | (mask_m[25] << 10) | (mask_m[26] << 8)
5062 | (mask_m[27] << 6) | (mask_m[28] << 4)
5063 | (mask_m[29] << 2) | (mask_m[30] << 0);
5064 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
5065 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
5066
5067 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
5068 | (mask_m[2] << 26) | (mask_m[3] << 24)
5069 | (mask_m[4] << 22) | (mask_m[5] << 20)
5070 | (mask_m[6] << 18) | (mask_m[7] << 16)
5071 | (mask_m[8] << 14) | (mask_m[9] << 12)
5072 | (mask_m[10] << 10) | (mask_m[11] << 8)
5073 | (mask_m[12] << 6) | (mask_m[13] << 4)
5074 | (mask_m[14] << 2) | (mask_m[15] << 0);
5075 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
5076 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
5077
5078 tmp_mask = (mask_p[15] << 28)
5079 | (mask_p[14] << 26) | (mask_p[13] << 24)
5080 | (mask_p[12] << 22) | (mask_p[11] << 20)
5081 | (mask_p[10] << 18) | (mask_p[9] << 16)
5082 | (mask_p[8] << 14) | (mask_p[7] << 12)
5083 | (mask_p[6] << 10) | (mask_p[5] << 8)
5084 | (mask_p[4] << 6) | (mask_p[3] << 4)
5085 | (mask_p[2] << 2) | (mask_p[1] << 0);
5086 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
5087 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
5088
5089 tmp_mask = (mask_p[30] << 28)
5090 | (mask_p[29] << 26) | (mask_p[28] << 24)
5091 | (mask_p[27] << 22) | (mask_p[26] << 20)
5092 | (mask_p[25] << 18) | (mask_p[24] << 16)
5093 | (mask_p[23] << 14) | (mask_p[22] << 12)
5094 | (mask_p[21] << 10) | (mask_p[20] << 8)
5095 | (mask_p[19] << 6) | (mask_p[18] << 4)
5096 | (mask_p[17] << 2) | (mask_p[16] << 0);
5097 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
5098 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
5099
5100 tmp_mask = (mask_p[45] << 28)
5101 | (mask_p[44] << 26) | (mask_p[43] << 24)
5102 | (mask_p[42] << 22) | (mask_p[41] << 20)
5103 | (mask_p[40] << 18) | (mask_p[39] << 16)
5104 | (mask_p[38] << 14) | (mask_p[37] << 12)
5105 | (mask_p[36] << 10) | (mask_p[35] << 8)
5106 | (mask_p[34] << 6) | (mask_p[33] << 4)
5107 | (mask_p[32] << 2) | (mask_p[31] << 0);
5108 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
5109 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
5110
5111 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
5112 | (mask_p[59] << 26) | (mask_p[58] << 24)
5113 | (mask_p[57] << 22) | (mask_p[56] << 20)
5114 | (mask_p[55] << 18) | (mask_p[54] << 16)
5115 | (mask_p[53] << 14) | (mask_p[52] << 12)
5116 | (mask_p[51] << 10) | (mask_p[50] << 8)
5117 | (mask_p[49] << 6) | (mask_p[48] << 4)
5118 | (mask_p[47] << 2) | (mask_p[46] << 0);
5119 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
5120 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5121 }
5122
5123 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
5124 {
5125 struct ath_hal_5416 *ahp = AH5416(ah);
5126 int rx_chainmask, tx_chainmask;
5127
5128 rx_chainmask = ahp->ah_rxchainmask;
5129 tx_chainmask = ahp->ah_txchainmask;
5130
5131 switch (rx_chainmask) {
5132 case 0x5:
5133 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5134 AR_PHY_SWAP_ALT_CHAIN);
5135 case 0x3:
5136 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5137 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5138 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5139 break;
5140 }
5141 case 0x1:
5142 case 0x2:
5143 if (!AR_SREV_9280(ah))
5144 break;
5145 case 0x7:
5146 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5147 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5148 break;
5149 default:
5150 break;
5151 }
5152
5153 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5154 if (tx_chainmask == 0x5) {
5155 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5156 AR_PHY_SWAP_ALT_CHAIN);
5157 }
5158 if (AR_SREV_9100(ah))
5159 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5160 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5161 }
5162
5163 static void ath9k_hw_set_addac(struct ath_hal *ah,
5164 struct ath9k_channel *chan)
5165 {
5166 struct modal_eep_header *pModal;
5167 struct ath_hal_5416 *ahp = AH5416(ah);
5168 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5169 u8 biaslevel;
5170
5171 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5172 return;
5173
5174 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5175 return;
5176
5177 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5178
5179 if (pModal->xpaBiasLvl != 0xff) {
5180 biaslevel = pModal->xpaBiasLvl;
5181 } else {
5182
5183 u16 resetFreqBin, freqBin, freqCount = 0;
5184 struct chan_centers centers;
5185
5186 ath9k_hw_get_channel_centers(ah, chan, &centers);
5187
5188 resetFreqBin =
5189 FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5190 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5191 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
5192
5193 freqCount++;
5194
5195 while (freqCount < 3) {
5196 if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
5197 break;
5198
5199 freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
5200 if (resetFreqBin >= freqBin) {
5201 biaslevel =
5202 (u8) (pModal->
5203 xpaBiasLvlFreq[freqCount]
5204 >> 14);
5205 } else {
5206 break;
5207 }
5208 freqCount++;
5209 }
5210 }
5211
5212 if (IS_CHAN_2GHZ(chan)) {
5213 INI_RA(&ahp->ah_iniAddac, 7, 1) =
5214 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel
5215 << 3;
5216 } else {
5217 INI_RA(&ahp->ah_iniAddac, 6, 1) =
5218 (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel
5219 << 6;
5220 }
5221 }
5222
5223 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
5224 {
5225 if (ah->ah_curchan != NULL)
5226 return clks /
5227 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
5228 else
5229 return clks / CLOCK_RATE[ATH9K_MODE_11B];
5230 }
5231
5232 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
5233 {
5234 struct ath9k_channel *chan = ah->ah_curchan;
5235
5236 if (chan && IS_CHAN_HT40(chan))
5237 return ath9k_hw_mac_usec(ah, clks) / 2;
5238 else
5239 return ath9k_hw_mac_usec(ah, clks);
5240 }
5241
5242 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
5243 {
5244 if (ah->ah_curchan != NULL)
5245 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
5246 ah->ah_curchan)];
5247 else
5248 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
5249 }
5250
5251 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
5252 {
5253 struct ath9k_channel *chan = ah->ah_curchan;
5254
5255 if (chan && IS_CHAN_HT40(chan))
5256 return ath9k_hw_mac_clks(ah, usecs) * 2;
5257 else
5258 return ath9k_hw_mac_clks(ah, usecs);
5259 }
5260
5261 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
5262 {
5263 struct ath_hal_5416 *ahp = AH5416(ah);
5264
5265 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
5266 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
5267 __func__, us);
5268 ahp->ah_acktimeout = (u32) -1;
5269 return false;
5270 } else {
5271 REG_RMW_FIELD(ah, AR_TIME_OUT,
5272 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
5273 ahp->ah_acktimeout = us;
5274 return true;
5275 }
5276 }
5277
5278 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
5279 {
5280 struct ath_hal_5416 *ahp = AH5416(ah);
5281
5282 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
5283 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
5284 __func__, us);
5285 ahp->ah_ctstimeout = (u32) -1;
5286 return false;
5287 } else {
5288 REG_RMW_FIELD(ah, AR_TIME_OUT,
5289 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
5290 ahp->ah_ctstimeout = us;
5291 return true;
5292 }
5293 }
5294 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
5295 u32 tu)
5296 {
5297 struct ath_hal_5416 *ahp = AH5416(ah);
5298
5299 if (tu > 0xFFFF) {
5300 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
5301 "%s: bad global tx timeout %u\n", __func__, tu);
5302 ahp->ah_globaltxtimeout = (u32) -1;
5303 return false;
5304 } else {
5305 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
5306 ahp->ah_globaltxtimeout = tu;
5307 return true;
5308 }
5309 }
5310
5311 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
5312 {
5313 struct ath_hal_5416 *ahp = AH5416(ah);
5314
5315 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
5316 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
5317 __func__, us);
5318 ahp->ah_slottime = (u32) -1;
5319 return false;
5320 } else {
5321 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
5322 ahp->ah_slottime = us;
5323 return true;
5324 }
5325 }
5326
5327 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
5328 {
5329 struct ath_hal_5416 *ahp = AH5416(ah);
5330
5331 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
5332 __func__, ahp->ah_miscMode);
5333 if (ahp->ah_miscMode != 0)
5334 REG_WRITE(ah, AR_PCU_MISC,
5335 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
5336 if (ahp->ah_slottime != (u32) -1)
5337 ath9k_hw_setslottime(ah, ahp->ah_slottime);
5338 if (ahp->ah_acktimeout != (u32) -1)
5339 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
5340 if (ahp->ah_ctstimeout != (u32) -1)
5341 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
5342 if (ahp->ah_globaltxtimeout != (u32) -1)
5343 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
5344 }
5345
5346 static int
5347 ath9k_hw_process_ini(struct ath_hal *ah,
5348 struct ath9k_channel *chan,
5349 enum ath9k_ht_macmode macmode)
5350 {
5351 int i, regWrites = 0;
5352 struct ath_hal_5416 *ahp = AH5416(ah);
5353 u32 modesIndex, freqIndex;
5354 int status;
5355
5356 switch (chan->chanmode) {
5357 case CHANNEL_A:
5358 case CHANNEL_A_HT20:
5359 modesIndex = 1;
5360 freqIndex = 1;
5361 break;
5362 case CHANNEL_A_HT40PLUS:
5363 case CHANNEL_A_HT40MINUS:
5364 modesIndex = 2;
5365 freqIndex = 1;
5366 break;
5367 case CHANNEL_G:
5368 case CHANNEL_G_HT20:
5369 case CHANNEL_B:
5370 modesIndex = 4;
5371 freqIndex = 2;
5372 break;
5373 case CHANNEL_G_HT40PLUS:
5374 case CHANNEL_G_HT40MINUS:
5375 modesIndex = 3;
5376 freqIndex = 2;
5377 break;
5378
5379 default:
5380 return -EINVAL;
5381 }
5382
5383 REG_WRITE(ah, AR_PHY(0), 0x00000007);
5384
5385 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
5386
5387 ath9k_hw_set_addac(ah, chan);
5388
5389 if (AR_SREV_5416_V22_OR_LATER(ah)) {
5390 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
5391 } else {
5392 struct ar5416IniArray temp;
5393 u32 addacSize =
5394 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
5395 ahp->ah_iniAddac.ia_columns;
5396
5397 memcpy(ahp->ah_addac5416_21,
5398 ahp->ah_iniAddac.ia_array, addacSize);
5399
5400 (ahp->ah_addac5416_21)[31 *
5401 ahp->ah_iniAddac.ia_columns + 1] = 0;
5402
5403 temp.ia_array = ahp->ah_addac5416_21;
5404 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
5405 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
5406 REG_WRITE_ARRAY(&temp, 1, regWrites);
5407 }
5408 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
5409
5410 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
5411 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
5412 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
5413
5414 #ifdef CONFIG_SLOW_ANT_DIV
5415 if (ah->ah_devid == AR9280_DEVID_PCI)
5416 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg,
5417 val);
5418 #endif
5419
5420 REG_WRITE(ah, reg, val);
5421
5422 if (reg >= 0x7800 && reg < 0x78a0
5423 && ah->ah_config.analog_shiftreg) {
5424 udelay(100);
5425 }
5426
5427 DO_DELAY(regWrites);
5428 }
5429
5430 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
5431 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
5432 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
5433
5434 REG_WRITE(ah, reg, val);
5435
5436 if (reg >= 0x7800 && reg < 0x78a0
5437 && ah->ah_config.analog_shiftreg) {
5438 udelay(100);
5439 }
5440
5441 DO_DELAY(regWrites);
5442 }
5443
5444 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
5445
5446 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
5447 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
5448 regWrites);
5449 }
5450
5451 ath9k_hw_override_ini(ah, chan);
5452 ath9k_hw_set_regs(ah, chan, macmode);
5453 ath9k_hw_init_chain_masks(ah);
5454
5455 status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5456 ath9k_regd_get_ctl(ah, chan),
5457 ath9k_regd_get_antenna_allowed(ah,
5458 chan),
5459 chan->maxRegTxPower * 2,
5460 min((u32) MAX_RATE_POWER,
5461 (u32) ah->ah_powerLimit));
5462 if (status != 0) {
5463 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
5464 "%s: error init'ing transmit power\n", __func__);
5465 return -EIO;
5466 }
5467
5468 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
5469 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
5470 "%s: ar5416SetRfRegs failed\n", __func__);
5471 return -EIO;
5472 }
5473
5474 return 0;
5475 }
5476
5477 static void ath9k_hw_setup_calibration(struct ath_hal *ah,
5478 struct hal_cal_list *currCal)
5479 {
5480 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
5481 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
5482 currCal->calData->calCountMax);
5483
5484 switch (currCal->calData->calType) {
5485 case IQ_MISMATCH_CAL:
5486 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
5487 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5488 "%s: starting IQ Mismatch Calibration\n",
5489 __func__);
5490 break;
5491 case ADC_GAIN_CAL:
5492 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
5493 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5494 "%s: starting ADC Gain Calibration\n", __func__);
5495 break;
5496 case ADC_DC_CAL:
5497 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
5498 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5499 "%s: starting ADC DC Calibration\n", __func__);
5500 break;
5501 case ADC_DC_INIT_CAL:
5502 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
5503 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5504 "%s: starting Init ADC DC Calibration\n",
5505 __func__);
5506 break;
5507 }
5508
5509 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
5510 AR_PHY_TIMING_CTRL4_DO_CAL);
5511 }
5512
5513 static void ath9k_hw_reset_calibration(struct ath_hal *ah,
5514 struct hal_cal_list *currCal)
5515 {
5516 struct ath_hal_5416 *ahp = AH5416(ah);
5517 int i;
5518
5519 ath9k_hw_setup_calibration(ah, currCal);
5520
5521 currCal->calState = CAL_RUNNING;
5522
5523 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5524 ahp->ah_Meas0.sign[i] = 0;
5525 ahp->ah_Meas1.sign[i] = 0;
5526 ahp->ah_Meas2.sign[i] = 0;
5527 ahp->ah_Meas3.sign[i] = 0;
5528 }
5529
5530 ahp->ah_CalSamples = 0;
5531 }
5532
5533 static void
5534 ath9k_hw_per_calibration(struct ath_hal *ah,
5535 struct ath9k_channel *ichan,
5536 u8 rxchainmask,
5537 struct hal_cal_list *currCal,
5538 bool *isCalDone)
5539 {
5540 struct ath_hal_5416 *ahp = AH5416(ah);
5541
5542 *isCalDone = false;
5543
5544 if (currCal->calState == CAL_RUNNING) {
5545 if (!(REG_READ(ah,
5546 AR_PHY_TIMING_CTRL4(0)) &
5547 AR_PHY_TIMING_CTRL4_DO_CAL)) {
5548
5549 currCal->calData->calCollect(ah);
5550
5551 ahp->ah_CalSamples++;
5552
5553 if (ahp->ah_CalSamples >=
5554 currCal->calData->calNumSamples) {
5555 int i, numChains = 0;
5556 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5557 if (rxchainmask & (1 << i))
5558 numChains++;
5559 }
5560
5561 currCal->calData->calPostProc(ah,
5562 numChains);
5563
5564 ichan->CalValid |=
5565 currCal->calData->calType;
5566 currCal->calState = CAL_DONE;
5567 *isCalDone = true;
5568 } else {
5569 ath9k_hw_setup_calibration(ah, currCal);
5570 }
5571 }
5572 } else if (!(ichan->CalValid & currCal->calData->calType)) {
5573 ath9k_hw_reset_calibration(ah, currCal);
5574 }
5575 }
5576
5577 static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
5578 int init_cal_count)
5579 {
5580 struct ath_hal_5416 *ahp = AH5416(ah);
5581 struct ath9k_channel ichan;
5582 bool isCalDone;
5583 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
5584 const struct hal_percal_data *calData = currCal->calData;
5585 int i;
5586
5587 if (currCal == NULL)
5588 return false;
5589
5590 ichan.CalValid = 0;
5591
5592 for (i = 0; i < init_cal_count; i++) {
5593 ath9k_hw_reset_calibration(ah, currCal);
5594
5595 if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
5596 AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
5597 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5598 "%s: Cal %d failed to complete in 100ms.\n",
5599 __func__, calData->calType);
5600
5601 ahp->ah_cal_list = ahp->ah_cal_list_last =
5602 ahp->ah_cal_list_curr = NULL;
5603 return false;
5604 }
5605
5606 ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
5607 currCal, &isCalDone);
5608 if (!isCalDone) {
5609 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5610 "%s: Not able to run Init Cal %d.\n",
5611 __func__, calData->calType);
5612 }
5613 if (currCal->calNext) {
5614 currCal = currCal->calNext;
5615 calData = currCal->calData;
5616 }
5617 }
5618
5619 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
5620 return true;
5621 }
5622
5623 static bool
5624 ath9k_hw_channel_change(struct ath_hal *ah,
5625 struct ath9k_channel *chan,
5626 enum ath9k_ht_macmode macmode)
5627 {
5628 u32 synthDelay, qnum;
5629 struct ath_hal_5416 *ahp = AH5416(ah);
5630
5631 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
5632 if (ath9k_hw_numtxpending(ah, qnum)) {
5633 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5634 "%s: Transmit frames pending on queue %d\n",
5635 __func__, qnum);
5636 return false;
5637 }
5638 }
5639
5640 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
5641 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
5642 AR_PHY_RFBUS_GRANT_EN)) {
5643 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
5644 "%s: Could not kill baseband RX\n", __func__);
5645 return false;
5646 }
5647
5648 ath9k_hw_set_regs(ah, chan, macmode);
5649
5650 if (AR_SREV_9280_10_OR_LATER(ah)) {
5651 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
5652 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5653 "%s: failed to set channel\n", __func__);
5654 return false;
5655 }
5656 } else {
5657 if (!(ath9k_hw_set_channel(ah, chan))) {
5658 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5659 "%s: failed to set channel\n", __func__);
5660 return false;
5661 }
5662 }
5663
5664 if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5665 ath9k_regd_get_ctl(ah, chan),
5666 ath9k_regd_get_antenna_allowed(ah, chan),
5667 chan->maxRegTxPower * 2,
5668 min((u32) MAX_RATE_POWER,
5669 (u32) ah->ah_powerLimit)) != 0) {
5670 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5671 "%s: error init'ing transmit power\n", __func__);
5672 return false;
5673 }
5674
5675 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
5676 if (IS_CHAN_CCK(chan))
5677 synthDelay = (4 * synthDelay) / 22;
5678 else
5679 synthDelay /= 10;
5680
5681 udelay(synthDelay + BASE_ACTIVATE_DELAY);
5682
5683 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
5684
5685 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5686 ath9k_hw_set_delta_slope(ah, chan);
5687
5688 if (AR_SREV_9280_10_OR_LATER(ah))
5689 ath9k_hw_9280_spur_mitigate(ah, chan);
5690 else
5691 ath9k_hw_spur_mitigate(ah, chan);
5692
5693 if (!chan->oneTimeCalsDone)
5694 chan->oneTimeCalsDone = true;
5695
5696 return true;
5697 }
5698
5699 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
5700 struct ath9k_channel *chan)
5701 {
5702 struct ath_hal_5416 *ahp = AH5416(ah);
5703
5704 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
5705 return false;
5706
5707 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5708 return false;
5709
5710 ahp->ah_chipFullSleep = false;
5711
5712 ath9k_hw_init_pll(ah, chan);
5713
5714 ath9k_hw_set_rfmode(ah, chan);
5715
5716 return true;
5717 }
5718
5719 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
5720 {
5721 u32 regval;
5722
5723 regval = REG_READ(ah, AR_AHB_MODE);
5724 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
5725
5726 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
5727 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
5728
5729 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
5730
5731 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
5732 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
5733
5734 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
5735
5736 if (AR_SREV_9285(ah)) {
5737 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5738 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
5739 } else {
5740 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5741 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
5742 }
5743 }
5744
5745 bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
5746 {
5747 REG_WRITE(ah, AR_CR, AR_CR_RXD);
5748 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
5749 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5750 "%s: dma failed to stop in 10ms\n"
5751 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
5752 __func__,
5753 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5754 return false;
5755 } else {
5756 return true;
5757 }
5758 }
5759
5760 void ath9k_hw_startpcureceive(struct ath_hal *ah)
5761 {
5762 REG_CLR_BIT(ah, AR_DIAG_SW,
5763 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
5764
5765 ath9k_enable_mib_counters(ah);
5766
5767 ath9k_ani_reset(ah);
5768 }
5769
5770 void ath9k_hw_stoppcurecv(struct ath_hal *ah)
5771 {
5772 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
5773
5774 ath9k_hw_disable_mib_counters(ah);
5775 }
5776
5777 static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
5778 struct ath9k_channel *chan,
5779 enum hal_cal_types calType)
5780 {
5781 struct ath_hal_5416 *ahp = AH5416(ah);
5782 bool retval = false;
5783
5784 switch (calType & ahp->ah_suppCals) {
5785 case IQ_MISMATCH_CAL:
5786 if (!IS_CHAN_B(chan))
5787 retval = true;
5788 break;
5789 case ADC_GAIN_CAL:
5790 case ADC_DC_CAL:
5791 if (!IS_CHAN_B(chan)
5792 && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
5793 retval = true;
5794 break;
5795 }
5796
5797 return retval;
5798 }
5799
5800 static bool ath9k_hw_init_cal(struct ath_hal *ah,
5801 struct ath9k_channel *chan)
5802 {
5803 struct ath_hal_5416 *ahp = AH5416(ah);
5804 struct ath9k_channel *ichan =
5805 ath9k_regd_check_channel(ah, chan);
5806
5807 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5808 REG_READ(ah, AR_PHY_AGC_CONTROL) |
5809 AR_PHY_AGC_CONTROL_CAL);
5810
5811 if (!ath9k_hw_wait
5812 (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
5813 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5814 "%s: offset calibration failed to complete in 1ms; "
5815 "noisy environment?\n", __func__);
5816 return false;
5817 }
5818
5819 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5820 REG_READ(ah, AR_PHY_AGC_CONTROL) |
5821 AR_PHY_AGC_CONTROL_NF);
5822
5823 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr =
5824 NULL;
5825
5826 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
5827 if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
5828 INIT_CAL(&ahp->ah_adcGainCalData);
5829 INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
5830 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5831 "%s: enabling ADC Gain Calibration.\n",
5832 __func__);
5833 }
5834 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
5835 INIT_CAL(&ahp->ah_adcDcCalData);
5836 INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
5837 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5838 "%s: enabling ADC DC Calibration.\n",
5839 __func__);
5840 }
5841 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
5842 INIT_CAL(&ahp->ah_iqCalData);
5843 INSERT_CAL(ahp, &ahp->ah_iqCalData);
5844 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5845 "%s: enabling IQ Calibration.\n",
5846 __func__);
5847 }
5848
5849 ahp->ah_cal_list_curr = ahp->ah_cal_list;
5850
5851 if (ahp->ah_cal_list_curr)
5852 ath9k_hw_reset_calibration(ah,
5853 ahp->ah_cal_list_curr);
5854 }
5855
5856 ichan->CalValid = 0;
5857
5858 return true;
5859 }
5860
5861
5862 bool ath9k_hw_reset(struct ath_hal *ah,
5863 struct ath9k_channel *chan,
5864 enum ath9k_ht_macmode macmode,
5865 u8 txchainmask, u8 rxchainmask,
5866 enum ath9k_ht_extprotspacing extprotspacing,
5867 bool bChannelChange,
5868 int *status)
5869 {
5870 #define FAIL(_code) do { ecode = _code; goto bad; } while (0)
5871 u32 saveLedState;
5872 struct ath_hal_5416 *ahp = AH5416(ah);
5873 struct ath9k_channel *curchan = ah->ah_curchan;
5874 u32 saveDefAntenna;
5875 u32 macStaId1;
5876 int ecode;
5877 int i, rx_chainmask;
5878
5879 ahp->ah_extprotspacing = extprotspacing;
5880 ahp->ah_txchainmask = txchainmask;
5881 ahp->ah_rxchainmask = rxchainmask;
5882
5883 if (AR_SREV_9280(ah)) {
5884 ahp->ah_txchainmask &= 0x3;
5885 ahp->ah_rxchainmask &= 0x3;
5886 }
5887
5888 if (ath9k_hw_check_chan(ah, chan) == NULL) {
5889 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5890 "%s: invalid channel %u/0x%x; no mapping\n",
5891 __func__, chan->channel, chan->channelFlags);
5892 FAIL(-EINVAL);
5893 }
5894
5895 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5896 return false;
5897
5898 if (curchan)
5899 ath9k_hw_getnf(ah, curchan);
5900
5901 if (bChannelChange &&
5902 (ahp->ah_chipFullSleep != true) &&
5903 (ah->ah_curchan != NULL) &&
5904 (chan->channel != ah->ah_curchan->channel) &&
5905 ((chan->channelFlags & CHANNEL_ALL) ==
5906 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
5907 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
5908 !IS_CHAN_A_5MHZ_SPACED(ah->
5909 ah_curchan)))) {
5910
5911 if (ath9k_hw_channel_change(ah, chan, macmode)) {
5912 ath9k_hw_loadnf(ah, ah->ah_curchan);
5913 ath9k_hw_start_nfcal(ah);
5914 return true;
5915 }
5916 }
5917
5918 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
5919 if (saveDefAntenna == 0)
5920 saveDefAntenna = 1;
5921
5922 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
5923
5924 saveLedState = REG_READ(ah, AR_CFG_LED) &
5925 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
5926 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
5927
5928 ath9k_hw_mark_phy_inactive(ah);
5929
5930 if (!ath9k_hw_chip_reset(ah, chan)) {
5931 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
5932 __func__);
5933 FAIL(-EIO);
5934 }
5935
5936 if (AR_SREV_9280(ah)) {
5937 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
5938 AR_GPIO_JTAG_DISABLE);
5939
5940 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
5941 if (IS_CHAN_5GHZ(chan))
5942 ath9k_hw_set_gpio(ah, 9, 0);
5943 else
5944 ath9k_hw_set_gpio(ah, 9, 1);
5945 }
5946 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
5947 }
5948
5949 ecode = ath9k_hw_process_ini(ah, chan, macmode);
5950 if (ecode != 0)
5951 goto bad;
5952
5953 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5954 ath9k_hw_set_delta_slope(ah, chan);
5955
5956 if (AR_SREV_9280_10_OR_LATER(ah))
5957 ath9k_hw_9280_spur_mitigate(ah, chan);
5958 else
5959 ath9k_hw_spur_mitigate(ah, chan);
5960
5961 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
5962 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5963 "%s: error setting board options\n", __func__);
5964 FAIL(-EIO);
5965 }
5966
5967 ath9k_hw_decrease_chain_power(ah, chan);
5968
5969 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
5970 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
5971 | macStaId1
5972 | AR_STA_ID1_RTS_USE_DEF
5973 | (ah->ah_config.
5974 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
5975 | ahp->ah_staId1Defaults);
5976 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
5977
5978 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
5979 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
5980
5981 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
5982
5983 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
5984 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
5985 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
5986
5987 REG_WRITE(ah, AR_ISR, ~0);
5988
5989 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
5990
5991 if (AR_SREV_9280_10_OR_LATER(ah)) {
5992 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
5993 FAIL(-EIO);
5994 } else {
5995 if (!(ath9k_hw_set_channel(ah, chan)))
5996 FAIL(-EIO);
5997 }
5998
5999 for (i = 0; i < AR_NUM_DCU; i++)
6000 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
6001
6002 ahp->ah_intrTxqs = 0;
6003 for (i = 0; i < ah->ah_caps.total_queues; i++)
6004 ath9k_hw_resettxqueue(ah, i);
6005
6006 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
6007 ath9k_hw_init_qos(ah);
6008
6009 #ifdef CONFIG_RFKILL
6010 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
6011 ath9k_enable_rfkill(ah);
6012 #endif
6013 ath9k_hw_init_user_settings(ah);
6014
6015 REG_WRITE(ah, AR_STA_ID1,
6016 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
6017
6018 ath9k_hw_set_dma(ah);
6019
6020 REG_WRITE(ah, AR_OBS, 8);
6021
6022 if (ahp->ah_intrMitigation) {
6023
6024 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
6025 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
6026 }
6027
6028 ath9k_hw_init_bb(ah, chan);
6029
6030 if (!ath9k_hw_init_cal(ah, chan))
6031 FAIL(-ENODEV);
6032
6033 rx_chainmask = ahp->ah_rxchainmask;
6034 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
6035 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
6036 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
6037 }
6038
6039 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
6040
6041 if (AR_SREV_9100(ah)) {
6042 u32 mask;
6043 mask = REG_READ(ah, AR_CFG);
6044 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
6045 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6046 "%s CFG Byte Swap Set 0x%x\n", __func__,
6047 mask);
6048 } else {
6049 mask =
6050 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
6051 REG_WRITE(ah, AR_CFG, mask);
6052 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6053 "%s Setting CFG 0x%x\n", __func__,
6054 REG_READ(ah, AR_CFG));
6055 }
6056 } else {
6057 #ifdef __BIG_ENDIAN
6058 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
6059 #endif
6060 }
6061
6062 return true;
6063 bad:
6064 if (status)
6065 *status = ecode;
6066 return false;
6067 #undef FAIL
6068 }
6069
6070 bool ath9k_hw_phy_disable(struct ath_hal *ah)
6071 {
6072 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
6073 }
6074
6075 bool ath9k_hw_disable(struct ath_hal *ah)
6076 {
6077 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
6078 return false;
6079
6080 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
6081 }
6082
6083 bool
6084 ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
6085 u8 rxchainmask, bool longcal,
6086 bool *isCalDone)
6087 {
6088 struct ath_hal_5416 *ahp = AH5416(ah);
6089 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6090 struct ath9k_channel *ichan =
6091 ath9k_regd_check_channel(ah, chan);
6092
6093 *isCalDone = true;
6094
6095 if (ichan == NULL) {
6096 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
6097 "%s: invalid channel %u/0x%x; no mapping\n",
6098 __func__, chan->channel, chan->channelFlags);
6099 return false;
6100 }
6101
6102 if (currCal &&
6103 (currCal->calState == CAL_RUNNING ||
6104 currCal->calState == CAL_WAITING)) {
6105 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
6106 isCalDone);
6107 if (*isCalDone) {
6108 ahp->ah_cal_list_curr = currCal = currCal->calNext;
6109
6110 if (currCal->calState == CAL_WAITING) {
6111 *isCalDone = false;
6112 ath9k_hw_reset_calibration(ah, currCal);
6113 }
6114 }
6115 }
6116
6117 if (longcal) {
6118 ath9k_hw_getnf(ah, ichan);
6119 ath9k_hw_loadnf(ah, ah->ah_curchan);
6120 ath9k_hw_start_nfcal(ah);
6121
6122 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
6123
6124 chan->channelFlags |= CHANNEL_CW_INT;
6125 ichan->channelFlags &= ~CHANNEL_CW_INT;
6126 }
6127 }
6128
6129 return true;
6130 }
6131
6132 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
6133 {
6134 struct ath_hal_5416 *ahp = AH5416(ah);
6135 int i;
6136
6137 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6138 ahp->ah_totalPowerMeasI[i] +=
6139 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6140 ahp->ah_totalPowerMeasQ[i] +=
6141 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6142 ahp->ah_totalIqCorrMeas[i] +=
6143 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6144 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6145 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
6146 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
6147 ahp->ah_totalPowerMeasQ[i],
6148 ahp->ah_totalIqCorrMeas[i]);
6149 }
6150 }
6151
6152 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
6153 {
6154 struct ath_hal_5416 *ahp = AH5416(ah);
6155 int i;
6156
6157 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6158 ahp->ah_totalAdcIOddPhase[i] +=
6159 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6160 ahp->ah_totalAdcIEvenPhase[i] +=
6161 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6162 ahp->ah_totalAdcQOddPhase[i] +=
6163 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6164 ahp->ah_totalAdcQEvenPhase[i] +=
6165 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6166
6167 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6168 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6169 "oddq=0x%08x; evenq=0x%08x;\n",
6170 ahp->ah_CalSamples, i,
6171 ahp->ah_totalAdcIOddPhase[i],
6172 ahp->ah_totalAdcIEvenPhase[i],
6173 ahp->ah_totalAdcQOddPhase[i],
6174 ahp->ah_totalAdcQEvenPhase[i]);
6175 }
6176 }
6177
6178 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
6179 {
6180 struct ath_hal_5416 *ahp = AH5416(ah);
6181 int i;
6182
6183 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6184 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
6185 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6186 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
6187 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6188 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
6189 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6190 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
6191 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6192
6193 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6194 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6195 "oddq=0x%08x; evenq=0x%08x;\n",
6196 ahp->ah_CalSamples, i,
6197 ahp->ah_totalAdcDcOffsetIOddPhase[i],
6198 ahp->ah_totalAdcDcOffsetIEvenPhase[i],
6199 ahp->ah_totalAdcDcOffsetQOddPhase[i],
6200 ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
6201 }
6202 }
6203
6204 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
6205 {
6206 struct ath_hal_5416 *ahp = AH5416(ah);
6207 u32 powerMeasQ, powerMeasI, iqCorrMeas;
6208 u32 qCoffDenom, iCoffDenom;
6209 int32_t qCoff, iCoff;
6210 int iqCorrNeg, i;
6211
6212 for (i = 0; i < numChains; i++) {
6213 powerMeasI = ahp->ah_totalPowerMeasI[i];
6214 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
6215 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
6216
6217 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6218 "Starting IQ Cal and Correction for Chain %d\n",
6219 i);
6220
6221 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6222 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
6223 i, ahp->ah_totalIqCorrMeas[i]);
6224
6225 iqCorrNeg = 0;
6226
6227
6228 if (iqCorrMeas > 0x80000000) {
6229 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
6230 iqCorrNeg = 1;
6231 }
6232
6233 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6234 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
6235 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6236 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
6237 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
6238 iqCorrNeg);
6239
6240 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
6241 qCoffDenom = powerMeasQ / 64;
6242
6243 if (powerMeasQ != 0) {
6244
6245 iCoff = iqCorrMeas / iCoffDenom;
6246 qCoff = powerMeasI / qCoffDenom - 64;
6247 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6248 "Chn %d iCoff = 0x%08x\n", i, iCoff);
6249 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6250 "Chn %d qCoff = 0x%08x\n", i, qCoff);
6251
6252
6253 iCoff = iCoff & 0x3f;
6254 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6255 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
6256 if (iqCorrNeg == 0x0)
6257 iCoff = 0x40 - iCoff;
6258
6259 if (qCoff > 15)
6260 qCoff = 15;
6261 else if (qCoff <= -16)
6262 qCoff = 16;
6263
6264 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6265 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
6266 i, iCoff, qCoff);
6267
6268 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6269 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
6270 iCoff);
6271 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6272 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
6273 qCoff);
6274 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6275 "IQ Cal and Correction done for Chain %d\n",
6276 i);
6277 }
6278 }
6279
6280 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
6281 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
6282 }
6283
6284 static void
6285 ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
6286 {
6287 struct ath_hal_5416 *ahp = AH5416(ah);
6288 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
6289 qEvenMeasOffset;
6290 u32 qGainMismatch, iGainMismatch, val, i;
6291
6292 for (i = 0; i < numChains; i++) {
6293 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
6294 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
6295 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
6296 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
6297
6298 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6299 "Starting ADC Gain Cal for Chain %d\n", i);
6300
6301 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6302 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
6303 iOddMeasOffset);
6304 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6305 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
6306 iEvenMeasOffset);
6307 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6308 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
6309 qOddMeasOffset);
6310 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6311 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
6312 qEvenMeasOffset);
6313
6314 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
6315 iGainMismatch =
6316 ((iEvenMeasOffset * 32) /
6317 iOddMeasOffset) & 0x3f;
6318 qGainMismatch =
6319 ((qOddMeasOffset * 32) /
6320 qEvenMeasOffset) & 0x3f;
6321
6322 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6323 "Chn %d gain_mismatch_i = 0x%08x\n", i,
6324 iGainMismatch);
6325 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6326 "Chn %d gain_mismatch_q = 0x%08x\n", i,
6327 qGainMismatch);
6328
6329 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6330 val &= 0xfffff000;
6331 val |= (qGainMismatch) | (iGainMismatch << 6);
6332 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6333
6334 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6335 "ADC Gain Cal done for Chain %d\n", i);
6336 }
6337 }
6338
6339 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6340 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6341 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
6342 }
6343
6344 static void
6345 ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
6346 {
6347 struct ath_hal_5416 *ahp = AH5416(ah);
6348 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
6349 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
6350 const struct hal_percal_data *calData =
6351 ahp->ah_cal_list_curr->calData;
6352 u32 numSamples =
6353 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
6354
6355 for (i = 0; i < numChains; i++) {
6356 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
6357 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
6358 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
6359 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
6360
6361 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6362 "Starting ADC DC Offset Cal for Chain %d\n", i);
6363
6364 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6365 "Chn %d pwr_meas_odd_i = %d\n", i,
6366 iOddMeasOffset);
6367 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6368 "Chn %d pwr_meas_even_i = %d\n", i,
6369 iEvenMeasOffset);
6370 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6371 "Chn %d pwr_meas_odd_q = %d\n", i,
6372 qOddMeasOffset);
6373 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6374 "Chn %d pwr_meas_even_q = %d\n", i,
6375 qEvenMeasOffset);
6376
6377 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
6378 numSamples) & 0x1ff;
6379 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
6380 numSamples) & 0x1ff;
6381
6382 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6383 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
6384 iDcMismatch);
6385 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6386 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
6387 qDcMismatch);
6388
6389 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6390 val &= 0xc0000fff;
6391 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
6392 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6393
6394 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6395 "ADC DC Offset Cal done for Chain %d\n", i);
6396 }
6397
6398 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6399 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6400 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
6401 }
6402
6403 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
6404 {
6405 struct ath_hal_5416 *ahp = AH5416(ah);
6406 struct ath9k_channel *chan = ah->ah_curchan;
6407
6408 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
6409
6410 if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
6411 ath9k_regd_get_ctl(ah, chan),
6412 ath9k_regd_get_antenna_allowed(ah,
6413 chan),
6414 chan->maxRegTxPower * 2,
6415 min((u32) MAX_RATE_POWER,
6416 (u32) ah->ah_powerLimit)) != 0)
6417 return false;
6418
6419 return true;
6420 }
6421
6422 void
6423 ath9k_hw_get_channel_centers(struct ath_hal *ah,
6424 struct ath9k_channel *chan,
6425 struct chan_centers *centers)
6426 {
6427 int8_t extoff;
6428 struct ath_hal_5416 *ahp = AH5416(ah);
6429
6430 if (!IS_CHAN_HT40(chan)) {
6431 centers->ctl_center = centers->ext_center =
6432 centers->synth_center = chan->channel;
6433 return;
6434 }
6435
6436 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
6437 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
6438 centers->synth_center =
6439 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
6440 extoff = 1;
6441 } else {
6442 centers->synth_center =
6443 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
6444 extoff = -1;
6445 }
6446
6447 centers->ctl_center = centers->synth_center - (extoff *
6448 HT40_CHANNEL_CENTER_SHIFT);
6449 centers->ext_center = centers->synth_center + (extoff *
6450 ((ahp->
6451 ah_extprotspacing
6452 ==
6453 ATH9K_HT_EXTPROTSPACING_20)
6454 ?
6455 HT40_CHANNEL_CENTER_SHIFT
6456 : 15));
6457
6458 }
6459
6460 void
6461 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
6462 bool *isCalDone)
6463 {
6464 struct ath_hal_5416 *ahp = AH5416(ah);
6465 struct ath9k_channel *ichan =
6466 ath9k_regd_check_channel(ah, chan);
6467 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6468
6469 *isCalDone = true;
6470
6471 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
6472 return;
6473
6474 if (currCal == NULL)
6475 return;
6476
6477 if (ichan == NULL) {
6478 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6479 "%s: invalid channel %u/0x%x; no mapping\n",
6480 __func__, chan->channel, chan->channelFlags);
6481 return;
6482 }
6483
6484
6485 if (currCal->calState != CAL_DONE) {
6486 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6487 "%s: Calibration state incorrect, %d\n",
6488 __func__, currCal->calState);
6489 return;
6490 }
6491
6492
6493 if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
6494 return;
6495
6496 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6497 "%s: Resetting Cal %d state for channel %u/0x%x\n",
6498 __func__, currCal->calData->calType, chan->channel,
6499 chan->channelFlags);
6500
6501 ichan->CalValid &= ~currCal->calData->calType;
6502 currCal->calState = CAL_WAITING;
6503
6504 *isCalDone = false;
6505 }
6506
6507 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
6508 {
6509 struct ath_hal_5416 *ahp = AH5416(ah);
6510
6511 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
6512 }
6513
6514 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
6515 {
6516 struct ath_hal_5416 *ahp = AH5416(ah);
6517
6518 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
6519 return true;
6520 }
6521
6522 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
6523 {
6524 struct ath_hal_5416 *ahp = AH5416(ah);
6525
6526 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
6527 }
6528
6529 bool
6530 ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
6531 {
6532 struct ath_hal_5416 *ahp = AH5416(ah);
6533
6534 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
6535
6536 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
6537 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
6538
6539 return true;
6540 }
6541
6542 void
6543 ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
6544 u16 assocId)
6545 {
6546 struct ath_hal_5416 *ahp = AH5416(ah);
6547
6548 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
6549 ahp->ah_assocId = assocId;
6550
6551 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
6552 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
6553 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
6554 }
6555
6556 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
6557 {
6558 u64 tsf;
6559
6560 tsf = REG_READ(ah, AR_TSF_U32);
6561 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
6562 return tsf;
6563 }
6564
6565 void ath9k_hw_reset_tsf(struct ath_hal *ah)
6566 {
6567 int count;
6568
6569 count = 0;
6570 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
6571 count++;
6572 if (count > 10) {
6573 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6574 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
6575 __func__);
6576 break;
6577 }
6578 udelay(10);
6579 }
6580 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
6581 }
6582
6583 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
6584 {
6585 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
6586 }
6587
6588 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
6589 {
6590 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
6591 }
6592
6593 bool
6594 ath9k_hw_setantennaswitch(struct ath_hal *ah,
6595 enum ath9k_ant_setting settings,
6596 struct ath9k_channel *chan,
6597 u8 *tx_chainmask,
6598 u8 *rx_chainmask,
6599 u8 *antenna_cfgd)
6600 {
6601 struct ath_hal_5416 *ahp = AH5416(ah);
6602 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
6603
6604 if (AR_SREV_9280(ah)) {
6605 if (!tx_chainmask_cfg) {
6606
6607 tx_chainmask_cfg = *tx_chainmask;
6608 rx_chainmask_cfg = *rx_chainmask;
6609 }
6610
6611 switch (settings) {
6612 case ATH9K_ANT_FIXED_A:
6613 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6614 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6615 *antenna_cfgd = true;
6616 break;
6617 case ATH9K_ANT_FIXED_B:
6618 if (ah->ah_caps.tx_chainmask >
6619 ATH9K_ANTENNA1_CHAINMASK) {
6620 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6621 }
6622 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6623 *antenna_cfgd = true;
6624 break;
6625 case ATH9K_ANT_VARIABLE:
6626 *tx_chainmask = tx_chainmask_cfg;
6627 *rx_chainmask = rx_chainmask_cfg;
6628 *antenna_cfgd = true;
6629 break;
6630 default:
6631 break;
6632 }
6633 } else {
6634 ahp->ah_diversityControl = settings;
6635 }
6636
6637 return true;
6638 }
6639
6640 void ath9k_hw_setopmode(struct ath_hal *ah)
6641 {
6642 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
6643 }
6644
6645 bool
6646 ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
6647 u32 capability, u32 *result)
6648 {
6649 struct ath_hal_5416 *ahp = AH5416(ah);
6650 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6651
6652 switch (type) {
6653 case ATH9K_CAP_CIPHER:
6654 switch (capability) {
6655 case ATH9K_CIPHER_AES_CCM:
6656 case ATH9K_CIPHER_AES_OCB:
6657 case ATH9K_CIPHER_TKIP:
6658 case ATH9K_CIPHER_WEP:
6659 case ATH9K_CIPHER_MIC:
6660 case ATH9K_CIPHER_CLR:
6661 return true;
6662 default:
6663 return false;
6664 }
6665 case ATH9K_CAP_TKIP_MIC:
6666 switch (capability) {
6667 case 0:
6668 return true;
6669 case 1:
6670 return (ahp->ah_staId1Defaults &
6671 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
6672 false;
6673 }
6674 case ATH9K_CAP_TKIP_SPLIT:
6675 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6676 false : true;
6677 case ATH9K_CAP_WME_TKIPMIC:
6678 return 0;
6679 case ATH9K_CAP_PHYCOUNTERS:
6680 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
6681 case ATH9K_CAP_DIVERSITY:
6682 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6683 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6684 true : false;
6685 case ATH9K_CAP_PHYDIAG:
6686 return true;
6687 case ATH9K_CAP_MCAST_KEYSRCH:
6688 switch (capability) {
6689 case 0:
6690 return true;
6691 case 1:
6692 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
6693 return false;
6694 } else {
6695 return (ahp->ah_staId1Defaults &
6696 AR_STA_ID1_MCAST_KSRCH) ? true :
6697 false;
6698 }
6699 }
6700 return false;
6701 case ATH9K_CAP_TSF_ADJUST:
6702 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6703 true : false;
6704 case ATH9K_CAP_RFSILENT:
6705 if (capability == 3)
6706 return false;
6707 case ATH9K_CAP_ANT_CFG_2GHZ:
6708 *result = pCap->num_antcfg_2ghz;
6709 return true;
6710 case ATH9K_CAP_ANT_CFG_5GHZ:
6711 *result = pCap->num_antcfg_5ghz;
6712 return true;
6713 case ATH9K_CAP_TXPOW:
6714 switch (capability) {
6715 case 0:
6716 return 0;
6717 case 1:
6718 *result = ah->ah_powerLimit;
6719 return 0;
6720 case 2:
6721 *result = ah->ah_maxPowerLevel;
6722 return 0;
6723 case 3:
6724 *result = ah->ah_tpScale;
6725 return 0;
6726 }
6727 return false;
6728 default:
6729 return false;
6730 }
6731 }
6732
6733 int
6734 ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
6735 {
6736 struct ath_hal_5416 *ahp = AH5416(ah);
6737 struct ath9k_channel *chan = ah->ah_curchan;
6738 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6739 u16 ant_config;
6740 u32 halNumAntConfig;
6741
6742 halNumAntConfig =
6743 IS_CHAN_2GHZ(chan) ? pCap->num_antcfg_2ghz : pCap->
6744 num_antcfg_5ghz;
6745
6746 if (cfg < halNumAntConfig) {
6747 if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan,
6748 cfg, &ant_config)) {
6749 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
6750 return 0;
6751 }
6752 }
6753
6754 return -EINVAL;
6755 }
6756
6757 bool ath9k_hw_intrpend(struct ath_hal *ah)
6758 {
6759 u32 host_isr;
6760
6761 if (AR_SREV_9100(ah))
6762 return true;
6763
6764 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
6765 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
6766 return true;
6767
6768 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
6769 if ((host_isr & AR_INTR_SYNC_DEFAULT)
6770 && (host_isr != AR_INTR_SPURIOUS))
6771 return true;
6772
6773 return false;
6774 }
6775
6776 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6777 {
6778 u32 isr = 0;
6779 u32 mask2 = 0;
6780 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6781 u32 sync_cause = 0;
6782 bool fatal_int = false;
6783
6784 if (!AR_SREV_9100(ah)) {
6785 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
6786 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
6787 == AR_RTC_STATUS_ON) {
6788 isr = REG_READ(ah, AR_ISR);
6789 }
6790 }
6791
6792 sync_cause =
6793 REG_READ(ah,
6794 AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
6795
6796 *masked = 0;
6797
6798 if (!isr && !sync_cause)
6799 return false;
6800 } else {
6801 *masked = 0;
6802 isr = REG_READ(ah, AR_ISR);
6803 }
6804
6805 if (isr) {
6806 struct ath_hal_5416 *ahp = AH5416(ah);
6807
6808 if (isr & AR_ISR_BCNMISC) {
6809 u32 isr2;
6810 isr2 = REG_READ(ah, AR_ISR_S2);
6811 if (isr2 & AR_ISR_S2_TIM)
6812 mask2 |= ATH9K_INT_TIM;
6813 if (isr2 & AR_ISR_S2_DTIM)
6814 mask2 |= ATH9K_INT_DTIM;
6815 if (isr2 & AR_ISR_S2_DTIMSYNC)
6816 mask2 |= ATH9K_INT_DTIMSYNC;
6817 if (isr2 & (AR_ISR_S2_CABEND))
6818 mask2 |= ATH9K_INT_CABEND;
6819 if (isr2 & AR_ISR_S2_GTT)
6820 mask2 |= ATH9K_INT_GTT;
6821 if (isr2 & AR_ISR_S2_CST)
6822 mask2 |= ATH9K_INT_CST;
6823 }
6824
6825 isr = REG_READ(ah, AR_ISR_RAC);
6826 if (isr == 0xffffffff) {
6827 *masked = 0;
6828 return false;
6829 }
6830
6831 *masked = isr & ATH9K_INT_COMMON;
6832
6833 if (ahp->ah_intrMitigation) {
6834
6835 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
6836 *masked |= ATH9K_INT_RX;
6837 }
6838
6839 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
6840 *masked |= ATH9K_INT_RX;
6841 if (isr &
6842 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
6843 AR_ISR_TXEOL)) {
6844 u32 s0_s, s1_s;
6845
6846 *masked |= ATH9K_INT_TX;
6847
6848 s0_s = REG_READ(ah, AR_ISR_S0_S);
6849 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
6850 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
6851
6852 s1_s = REG_READ(ah, AR_ISR_S1_S);
6853 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
6854 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
6855 }
6856
6857 if (isr & AR_ISR_RXORN) {
6858 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6859 "%s: receive FIFO overrun interrupt\n",
6860 __func__);
6861 }
6862
6863 if (!AR_SREV_9100(ah)) {
6864 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6865 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
6866 if (isr5 & AR_ISR_S5_TIM_TIMER)
6867 *masked |= ATH9K_INT_TIM_TIMER;
6868 }
6869 }
6870
6871 *masked |= mask2;
6872 }
6873 if (AR_SREV_9100(ah))
6874 return true;
6875 if (sync_cause) {
6876 fatal_int =
6877 (sync_cause &
6878 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
6879 ? true : false;
6880
6881 if (fatal_int) {
6882 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
6883 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6884 "%s: received PCI FATAL interrupt\n",
6885 __func__);
6886 }
6887 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
6888 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6889 "%s: received PCI PERR interrupt\n",
6890 __func__);
6891 }
6892 }
6893 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
6894 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6895 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
6896 __func__);
6897 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
6898 REG_WRITE(ah, AR_RC, 0);
6899 *masked |= ATH9K_INT_FATAL;
6900 }
6901 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
6902 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6903 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
6904 __func__);
6905 }
6906
6907 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6908 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
6909 }
6910 return true;
6911 }
6912
6913 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
6914 {
6915 return AH5416(ah)->ah_maskReg;
6916 }
6917
6918 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
6919 {
6920 struct ath_hal_5416 *ahp = AH5416(ah);
6921 u32 omask = ahp->ah_maskReg;
6922 u32 mask, mask2;
6923 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6924
6925 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
6926 omask, ints);
6927
6928 if (omask & ATH9K_INT_GLOBAL) {
6929 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
6930 __func__);
6931 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
6932 (void) REG_READ(ah, AR_IER);
6933 if (!AR_SREV_9100(ah)) {
6934 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
6935 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
6936
6937 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
6938 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
6939 }
6940 }
6941
6942 mask = ints & ATH9K_INT_COMMON;
6943 mask2 = 0;
6944
6945 if (ints & ATH9K_INT_TX) {
6946 if (ahp->ah_txOkInterruptMask)
6947 mask |= AR_IMR_TXOK;
6948 if (ahp->ah_txDescInterruptMask)
6949 mask |= AR_IMR_TXDESC;
6950 if (ahp->ah_txErrInterruptMask)
6951 mask |= AR_IMR_TXERR;
6952 if (ahp->ah_txEolInterruptMask)
6953 mask |= AR_IMR_TXEOL;
6954 }
6955 if (ints & ATH9K_INT_RX) {
6956 mask |= AR_IMR_RXERR;
6957 if (ahp->ah_intrMitigation)
6958 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
6959 else
6960 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
6961 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
6962 mask |= AR_IMR_GENTMR;
6963 }
6964
6965 if (ints & (ATH9K_INT_BMISC)) {
6966 mask |= AR_IMR_BCNMISC;
6967 if (ints & ATH9K_INT_TIM)
6968 mask2 |= AR_IMR_S2_TIM;
6969 if (ints & ATH9K_INT_DTIM)
6970 mask2 |= AR_IMR_S2_DTIM;
6971 if (ints & ATH9K_INT_DTIMSYNC)
6972 mask2 |= AR_IMR_S2_DTIMSYNC;
6973 if (ints & ATH9K_INT_CABEND)
6974 mask2 |= (AR_IMR_S2_CABEND);
6975 }
6976
6977 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
6978 mask |= AR_IMR_BCNMISC;
6979 if (ints & ATH9K_INT_GTT)
6980 mask2 |= AR_IMR_S2_GTT;
6981 if (ints & ATH9K_INT_CST)
6982 mask2 |= AR_IMR_S2_CST;
6983 }
6984
6985 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
6986 mask);
6987 REG_WRITE(ah, AR_IMR, mask);
6988 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
6989 AR_IMR_S2_DTIM |
6990 AR_IMR_S2_DTIMSYNC |
6991 AR_IMR_S2_CABEND |
6992 AR_IMR_S2_CABTO |
6993 AR_IMR_S2_TSFOOR |
6994 AR_IMR_S2_GTT | AR_IMR_S2_CST);
6995 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
6996 ahp->ah_maskReg = ints;
6997
6998 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6999 if (ints & ATH9K_INT_TIM_TIMER)
7000 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7001 else
7002 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7003 }
7004
7005 if (ints & ATH9K_INT_GLOBAL) {
7006 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
7007 __func__);
7008 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
7009 if (!AR_SREV_9100(ah)) {
7010 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
7011 AR_INTR_MAC_IRQ);
7012 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
7013
7014
7015 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
7016 AR_INTR_SYNC_DEFAULT);
7017 REG_WRITE(ah, AR_INTR_SYNC_MASK,
7018 AR_INTR_SYNC_DEFAULT);
7019 }
7020 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
7021 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
7022 }
7023
7024 return omask;
7025 }
7026
7027 void
7028 ath9k_hw_beaconinit(struct ath_hal *ah,
7029 u32 next_beacon, u32 beacon_period)
7030 {
7031 struct ath_hal_5416 *ahp = AH5416(ah);
7032 int flags = 0;
7033
7034 ahp->ah_beaconInterval = beacon_period;
7035
7036 switch (ah->ah_opmode) {
7037 case ATH9K_M_STA:
7038 case ATH9K_M_MONITOR:
7039 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7040 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
7041 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
7042 flags |= AR_TBTT_TIMER_EN;
7043 break;
7044 case ATH9K_M_IBSS:
7045 REG_SET_BIT(ah, AR_TXCFG,
7046 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
7047 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
7048 TU_TO_USEC(next_beacon +
7049 (ahp->ah_atimWindow ? ahp->
7050 ah_atimWindow : 1)));
7051 flags |= AR_NDP_TIMER_EN;
7052 case ATH9K_M_HOSTAP:
7053 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7054 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
7055 TU_TO_USEC(next_beacon -
7056 ah->ah_config.
7057 dma_beacon_response_time));
7058 REG_WRITE(ah, AR_NEXT_SWBA,
7059 TU_TO_USEC(next_beacon -
7060 ah->ah_config.
7061 sw_beacon_response_time));
7062 flags |=
7063 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
7064 break;
7065 }
7066
7067 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7068 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7069 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
7070 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
7071
7072 beacon_period &= ~ATH9K_BEACON_ENA;
7073 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
7074 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
7075 ath9k_hw_reset_tsf(ah);
7076 }
7077
7078 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
7079 }
7080
7081 void
7082 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7083 const struct ath9k_beacon_state *bs)
7084 {
7085 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
7086 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7087
7088 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
7089
7090 REG_WRITE(ah, AR_BEACON_PERIOD,
7091 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
7092 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
7093 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
7094
7095 REG_RMW_FIELD(ah, AR_RSSI_THR,
7096 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
7097
7098 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
7099
7100 if (bs->bs_sleepduration > beaconintval)
7101 beaconintval = bs->bs_sleepduration;
7102
7103 dtimperiod = bs->bs_dtimperiod;
7104 if (bs->bs_sleepduration > dtimperiod)
7105 dtimperiod = bs->bs_sleepduration;
7106
7107 if (beaconintval == dtimperiod)
7108 nextTbtt = bs->bs_nextdtim;
7109 else
7110 nextTbtt = bs->bs_nexttbtt;
7111
7112 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
7113 bs->bs_nextdtim);
7114 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
7115 nextTbtt);
7116 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
7117 beaconintval);
7118 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
7119 dtimperiod);
7120
7121 REG_WRITE(ah, AR_NEXT_DTIM,
7122 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
7123 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
7124
7125 REG_WRITE(ah, AR_SLEEP1,
7126 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
7127 | AR_SLEEP1_ASSUME_DTIM);
7128
7129 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
7130 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
7131 else
7132 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
7133
7134 REG_WRITE(ah, AR_SLEEP2,
7135 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
7136
7137 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
7138 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
7139
7140 REG_SET_BIT(ah, AR_TIMER_MODE,
7141 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
7142 AR_DTIM_TIMER_EN);
7143
7144 }
7145
7146 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
7147 {
7148 if (entry < ah->ah_caps.keycache_size) {
7149 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7150 if (val & AR_KEYTABLE_VALID)
7151 return true;
7152 }
7153 return false;
7154 }
7155
7156 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
7157 {
7158 u32 keyType;
7159
7160 if (entry >= ah->ah_caps.keycache_size) {
7161 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7162 "%s: entry %u out of range\n", __func__, entry);
7163 return false;
7164 }
7165 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
7166
7167 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
7168 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
7169 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
7170 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
7171 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
7172 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
7173 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
7174 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
7175
7176 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7177 u16 micentry = entry + 64;
7178
7179 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
7180 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7181 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
7182 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7183
7184 }
7185
7186 if (ah->ah_curchan == NULL)
7187 return true;
7188
7189 return true;
7190 }
7191
7192 bool
7193 ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
7194 const u8 *mac)
7195 {
7196 u32 macHi, macLo;
7197
7198 if (entry >= ah->ah_caps.keycache_size) {
7199 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7200 "%s: entry %u out of range\n", __func__, entry);
7201 return false;
7202 }
7203
7204 if (mac != NULL) {
7205 macHi = (mac[5] << 8) | mac[4];
7206 macLo = (mac[3] << 24) | (mac[2] << 16)
7207 | (mac[1] << 8) | mac[0];
7208 macLo >>= 1;
7209 macLo |= (macHi & 1) << 31;
7210 macHi >>= 1;
7211 } else {
7212 macLo = macHi = 0;
7213 }
7214 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
7215 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
7216
7217 return true;
7218 }
7219
7220 bool
7221 ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
7222 const struct ath9k_keyval *k,
7223 const u8 *mac, int xorKey)
7224 {
7225 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7226 u32 key0, key1, key2, key3, key4;
7227 u32 keyType;
7228 u32 xorMask = xorKey ?
7229 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
7230 | ATH9K_KEY_XOR) : 0;
7231 struct ath_hal_5416 *ahp = AH5416(ah);
7232
7233 if (entry >= pCap->keycache_size) {
7234 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7235 "%s: entry %u out of range\n", __func__, entry);
7236 return false;
7237 }
7238 switch (k->kv_type) {
7239 case ATH9K_CIPHER_AES_OCB:
7240 keyType = AR_KEYTABLE_TYPE_AES;
7241 break;
7242 case ATH9K_CIPHER_AES_CCM:
7243 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
7244 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7245 "%s: AES-CCM not supported by "
7246 "mac rev 0x%x\n", __func__,
7247 ah->ah_macRev);
7248 return false;
7249 }
7250 keyType = AR_KEYTABLE_TYPE_CCM;
7251 break;
7252 case ATH9K_CIPHER_TKIP:
7253 keyType = AR_KEYTABLE_TYPE_TKIP;
7254 if (ATH9K_IS_MIC_ENABLED(ah)
7255 && entry + 64 >= pCap->keycache_size) {
7256 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7257 "%s: entry %u inappropriate for TKIP\n",
7258 __func__, entry);
7259 return false;
7260 }
7261 break;
7262 case ATH9K_CIPHER_WEP:
7263 if (k->kv_len < LEN_WEP40) {
7264 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7265 "%s: WEP key length %u too small\n",
7266 __func__, k->kv_len);
7267 return false;
7268 }
7269 if (k->kv_len <= LEN_WEP40)
7270 keyType = AR_KEYTABLE_TYPE_40;
7271 else if (k->kv_len <= LEN_WEP104)
7272 keyType = AR_KEYTABLE_TYPE_104;
7273 else
7274 keyType = AR_KEYTABLE_TYPE_128;
7275 break;
7276 case ATH9K_CIPHER_CLR:
7277 keyType = AR_KEYTABLE_TYPE_CLR;
7278 break;
7279 default:
7280 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7281 "%s: cipher %u not supported\n", __func__,
7282 k->kv_type);
7283 return false;
7284 }
7285
7286 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
7287 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
7288 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
7289 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
7290 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
7291 if (k->kv_len <= LEN_WEP104)
7292 key4 &= 0xff;
7293
7294 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7295 u16 micentry = entry + 64;
7296
7297 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
7298 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
7299 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7300 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7301 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7302 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7303 (void) ath9k_hw_keysetmac(ah, entry, mac);
7304
7305 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
7306 u32 mic0, mic1, mic2, mic3, mic4;
7307
7308 mic0 = get_unaligned_le32(k->kv_mic + 0);
7309 mic2 = get_unaligned_le32(k->kv_mic + 4);
7310 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
7311 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
7312 mic4 = get_unaligned_le32(k->kv_txmic + 4);
7313 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7314 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
7315 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7316 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
7317 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
7318 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7319 AR_KEYTABLE_TYPE_CLR);
7320
7321 } else {
7322 u32 mic0, mic2;
7323
7324 mic0 = get_unaligned_le32(k->kv_mic + 0);
7325 mic2 = get_unaligned_le32(k->kv_mic + 4);
7326 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7327 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7328 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7329 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7330 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
7331 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7332 AR_KEYTABLE_TYPE_CLR);
7333 }
7334 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
7335 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
7336 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7337 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7338 } else {
7339 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7340 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7341 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7342 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7343 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7344 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7345
7346 (void) ath9k_hw_keysetmac(ah, entry, mac);
7347 }
7348
7349 if (ah->ah_curchan == NULL)
7350 return true;
7351
7352 return true;
7353 }
7354
7355 bool
7356 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
7357 {
7358 struct ath_hal_5416 *ahp = AH5416(ah);
7359 u32 txcfg, curLevel, newLevel;
7360 enum ath9k_int omask;
7361
7362 if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
7363 return false;
7364
7365 omask = ath9k_hw_set_interrupts(ah,
7366 ahp->ah_maskReg & ~ATH9K_INT_GLOBAL);
7367
7368 txcfg = REG_READ(ah, AR_TXCFG);
7369 curLevel = MS(txcfg, AR_FTRIG);
7370 newLevel = curLevel;
7371 if (bIncTrigLevel) {
7372 if (curLevel < MAX_TX_FIFO_THRESHOLD)
7373 newLevel++;
7374 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
7375 newLevel--;
7376 if (newLevel != curLevel)
7377 REG_WRITE(ah, AR_TXCFG,
7378 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
7379
7380 ath9k_hw_set_interrupts(ah, omask);
7381
7382 ah->ah_txTrigLevel = newLevel;
7383
7384 return newLevel != curLevel;
7385 }
7386
7387 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
7388 const struct ath9k_tx_queue_info *qinfo)
7389 {
7390 u32 cw;
7391 struct ath_hal_5416 *ahp = AH5416(ah);
7392 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7393 struct ath9k_tx_queue_info *qi;
7394
7395 if (q >= pCap->total_queues) {
7396 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7397 __func__, q);
7398 return false;
7399 }
7400
7401 qi = &ahp->ah_txq[q];
7402 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7403 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
7404 __func__);
7405 return false;
7406 }
7407
7408 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
7409
7410 qi->tqi_ver = qinfo->tqi_ver;
7411 qi->tqi_subtype = qinfo->tqi_subtype;
7412 qi->tqi_qflags = qinfo->tqi_qflags;
7413 qi->tqi_priority = qinfo->tqi_priority;
7414 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
7415 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
7416 else
7417 qi->tqi_aifs = INIT_AIFS;
7418 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
7419 cw = min(qinfo->tqi_cwmin, 1024U);
7420 qi->tqi_cwmin = 1;
7421 while (qi->tqi_cwmin < cw)
7422 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
7423 } else
7424 qi->tqi_cwmin = qinfo->tqi_cwmin;
7425 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
7426 cw = min(qinfo->tqi_cwmax, 1024U);
7427 qi->tqi_cwmax = 1;
7428 while (qi->tqi_cwmax < cw)
7429 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
7430 } else
7431 qi->tqi_cwmax = INIT_CWMAX;
7432
7433 if (qinfo->tqi_shretry != 0)
7434 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
7435 else
7436 qi->tqi_shretry = INIT_SH_RETRY;
7437 if (qinfo->tqi_lgretry != 0)
7438 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
7439 else
7440 qi->tqi_lgretry = INIT_LG_RETRY;
7441 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
7442 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
7443 qi->tqi_burstTime = qinfo->tqi_burstTime;
7444 qi->tqi_readyTime = qinfo->tqi_readyTime;
7445
7446 switch (qinfo->tqi_subtype) {
7447 case ATH9K_WME_UPSD:
7448 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
7449 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
7450 break;
7451 default:
7452 break;
7453 }
7454 return true;
7455 }
7456
7457 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
7458 struct ath9k_tx_queue_info *qinfo)
7459 {
7460 struct ath_hal_5416 *ahp = AH5416(ah);
7461 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7462 struct ath9k_tx_queue_info *qi;
7463
7464 if (q >= pCap->total_queues) {
7465 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7466 __func__, q);
7467 return false;
7468 }
7469
7470 qi = &ahp->ah_txq[q];
7471 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7472 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
7473 __func__);
7474 return false;
7475 }
7476
7477 qinfo->tqi_qflags = qi->tqi_qflags;
7478 qinfo->tqi_ver = qi->tqi_ver;
7479 qinfo->tqi_subtype = qi->tqi_subtype;
7480 qinfo->tqi_qflags = qi->tqi_qflags;
7481 qinfo->tqi_priority = qi->tqi_priority;
7482 qinfo->tqi_aifs = qi->tqi_aifs;
7483 qinfo->tqi_cwmin = qi->tqi_cwmin;
7484 qinfo->tqi_cwmax = qi->tqi_cwmax;
7485 qinfo->tqi_shretry = qi->tqi_shretry;
7486 qinfo->tqi_lgretry = qi->tqi_lgretry;
7487 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
7488 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
7489 qinfo->tqi_burstTime = qi->tqi_burstTime;
7490 qinfo->tqi_readyTime = qi->tqi_readyTime;
7491
7492 return true;
7493 }
7494
7495 int
7496 ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
7497 const struct ath9k_tx_queue_info *qinfo)
7498 {
7499 struct ath_hal_5416 *ahp = AH5416(ah);
7500 struct ath9k_tx_queue_info *qi;
7501 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7502 int q;
7503
7504 switch (type) {
7505 case ATH9K_TX_QUEUE_BEACON:
7506 q = pCap->total_queues - 1;
7507 break;
7508 case ATH9K_TX_QUEUE_CAB:
7509 q = pCap->total_queues - 2;
7510 break;
7511 case ATH9K_TX_QUEUE_PSPOLL:
7512 q = 1;
7513 break;
7514 case ATH9K_TX_QUEUE_UAPSD:
7515 q = pCap->total_queues - 3;
7516 break;
7517 case ATH9K_TX_QUEUE_DATA:
7518 for (q = 0; q < pCap->total_queues; q++)
7519 if (ahp->ah_txq[q].tqi_type ==
7520 ATH9K_TX_QUEUE_INACTIVE)
7521 break;
7522 if (q == pCap->total_queues) {
7523 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7524 "%s: no available tx queue\n", __func__);
7525 return -1;
7526 }
7527 break;
7528 default:
7529 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n",
7530 __func__, type);
7531 return -1;
7532 }
7533
7534 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
7535
7536 qi = &ahp->ah_txq[q];
7537 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
7538 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7539 "%s: tx queue %u already active\n", __func__, q);
7540 return -1;
7541 }
7542 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
7543 qi->tqi_type = type;
7544 if (qinfo == NULL) {
7545 qi->tqi_qflags =
7546 TXQ_FLAG_TXOKINT_ENABLE
7547 | TXQ_FLAG_TXERRINT_ENABLE
7548 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
7549 qi->tqi_aifs = INIT_AIFS;
7550 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
7551 qi->tqi_cwmax = INIT_CWMAX;
7552 qi->tqi_shretry = INIT_SH_RETRY;
7553 qi->tqi_lgretry = INIT_LG_RETRY;
7554 qi->tqi_physCompBuf = 0;
7555 } else {
7556 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
7557 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
7558 }
7559
7560 return q;
7561 }
7562
7563 static void
7564 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
7565 struct ath9k_tx_queue_info *qi)
7566 {
7567 struct ath_hal_5416 *ahp = AH5416(ah);
7568
7569 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
7570 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
7571 __func__, ahp->ah_txOkInterruptMask,
7572 ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
7573 ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
7574
7575 REG_WRITE(ah, AR_IMR_S0,
7576 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
7577 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
7578 REG_WRITE(ah, AR_IMR_S1,
7579 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
7580 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
7581 REG_RMW_FIELD(ah, AR_IMR_S2,
7582 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
7583 }
7584
7585 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
7586 {
7587 struct ath_hal_5416 *ahp = AH5416(ah);
7588 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7589 struct ath9k_tx_queue_info *qi;
7590
7591 if (q >= pCap->total_queues) {
7592 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7593 __func__, q);
7594 return false;
7595 }
7596 qi = &ahp->ah_txq[q];
7597 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7598 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
7599 __func__, q);
7600 return false;
7601 }
7602
7603 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
7604 __func__, q);
7605
7606 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
7607 ahp->ah_txOkInterruptMask &= ~(1 << q);
7608 ahp->ah_txErrInterruptMask &= ~(1 << q);
7609 ahp->ah_txDescInterruptMask &= ~(1 << q);
7610 ahp->ah_txEolInterruptMask &= ~(1 << q);
7611 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7612 ath9k_hw_set_txq_interrupts(ah, qi);
7613
7614 return true;
7615 }
7616
7617 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
7618 {
7619 struct ath_hal_5416 *ahp = AH5416(ah);
7620 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7621 struct ath9k_channel *chan = ah->ah_curchan;
7622 struct ath9k_tx_queue_info *qi;
7623 u32 cwMin, chanCwMin, value;
7624
7625 if (q >= pCap->total_queues) {
7626 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7627 __func__, q);
7628 return false;
7629 }
7630 qi = &ahp->ah_txq[q];
7631 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7632 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
7633 __func__, q);
7634 return true;
7635 }
7636
7637 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
7638
7639 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
7640 if (chan && IS_CHAN_B(chan))
7641 chanCwMin = INIT_CWMIN_11B;
7642 else
7643 chanCwMin = INIT_CWMIN;
7644
7645 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
7646 } else
7647 cwMin = qi->tqi_cwmin;
7648
7649 REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN)
7650 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
7651 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
7652
7653 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
7654 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
7655 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
7656 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
7657
7658 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
7659 REG_WRITE(ah, AR_DMISC(q),
7660 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
7661
7662 if (qi->tqi_cbrPeriod) {
7663 REG_WRITE(ah, AR_QCBRCFG(q),
7664 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL)
7665 | SM(qi->tqi_cbrOverflowLimit,
7666 AR_Q_CBRCFG_OVF_THRESH));
7667 REG_WRITE(ah, AR_QMISC(q),
7668 REG_READ(ah,
7669 AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi->
7670 tqi_cbrOverflowLimit
7671 ?
7672 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
7673 :
7674 0));
7675 }
7676 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
7677 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7678 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
7679 AR_Q_RDYTIMECFG_EN);
7680 }
7681
7682 REG_WRITE(ah, AR_DCHNTIME(q),
7683 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
7684 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
7685
7686 if (qi->tqi_burstTime
7687 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
7688 REG_WRITE(ah, AR_QMISC(q),
7689 REG_READ(ah,
7690 AR_QMISC(q)) |
7691 AR_Q_MISC_RDYTIME_EXP_POLICY);
7692
7693 }
7694
7695 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
7696 REG_WRITE(ah, AR_DMISC(q),
7697 REG_READ(ah, AR_DMISC(q)) |
7698 AR_D_MISC_POST_FR_BKOFF_DIS);
7699 }
7700 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
7701 REG_WRITE(ah, AR_DMISC(q),
7702 REG_READ(ah, AR_DMISC(q)) |
7703 AR_D_MISC_FRAG_BKOFF_EN);
7704 }
7705 switch (qi->tqi_type) {
7706 case ATH9K_TX_QUEUE_BEACON:
7707 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7708 | AR_Q_MISC_FSP_DBA_GATED
7709 | AR_Q_MISC_BEACON_USE
7710 | AR_Q_MISC_CBR_INCR_DIS1);
7711
7712 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7713 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7714 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
7715 | AR_D_MISC_BEACON_USE
7716 | AR_D_MISC_POST_FR_BKOFF_DIS);
7717 break;
7718 case ATH9K_TX_QUEUE_CAB:
7719 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7720 | AR_Q_MISC_FSP_DBA_GATED
7721 | AR_Q_MISC_CBR_INCR_DIS1
7722 | AR_Q_MISC_CBR_INCR_DIS0);
7723 value = (qi->tqi_readyTime
7724 - (ah->ah_config.sw_beacon_response_time -
7725 ah->ah_config.dma_beacon_response_time)
7726 -
7727 ah->ah_config.additional_swba_backoff) *
7728 1024;
7729 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7730 value | AR_Q_RDYTIMECFG_EN);
7731 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7732 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7733 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7734 break;
7735 case ATH9K_TX_QUEUE_PSPOLL:
7736 REG_WRITE(ah, AR_QMISC(q),
7737 REG_READ(ah,
7738 AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
7739 break;
7740 case ATH9K_TX_QUEUE_UAPSD:
7741 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7742 | AR_D_MISC_POST_FR_BKOFF_DIS);
7743 break;
7744 default:
7745 break;
7746 }
7747
7748 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
7749 REG_WRITE(ah, AR_DMISC(q),
7750 REG_READ(ah, AR_DMISC(q)) |
7751 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
7752 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
7753 AR_D_MISC_POST_FR_BKOFF_DIS);
7754 }
7755
7756 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
7757 ahp->ah_txOkInterruptMask |= 1 << q;
7758 else
7759 ahp->ah_txOkInterruptMask &= ~(1 << q);
7760 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
7761 ahp->ah_txErrInterruptMask |= 1 << q;
7762 else
7763 ahp->ah_txErrInterruptMask &= ~(1 << q);
7764 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
7765 ahp->ah_txDescInterruptMask |= 1 << q;
7766 else
7767 ahp->ah_txDescInterruptMask &= ~(1 << q);
7768 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
7769 ahp->ah_txEolInterruptMask |= 1 << q;
7770 else
7771 ahp->ah_txEolInterruptMask &= ~(1 << q);
7772 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
7773 ahp->ah_txUrnInterruptMask |= 1 << q;
7774 else
7775 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7776 ath9k_hw_set_txq_interrupts(ah, qi);
7777
7778 return true;
7779 }
7780
7781 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs)
7782 {
7783 struct ath_hal_5416 *ahp = AH5416(ah);
7784 *txqs &= ahp->ah_intrTxqs;
7785 ahp->ah_intrTxqs &= ~(*txqs);
7786 }
7787
7788 bool
7789 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
7790 u32 segLen, bool firstSeg,
7791 bool lastSeg, const struct ath_desc *ds0)
7792 {
7793 struct ar5416_desc *ads = AR5416DESC(ds);
7794
7795 if (firstSeg) {
7796 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
7797 } else if (lastSeg) {
7798 ads->ds_ctl0 = 0;
7799 ads->ds_ctl1 = segLen;
7800 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
7801 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
7802 } else {
7803 ads->ds_ctl0 = 0;
7804 ads->ds_ctl1 = segLen | AR_TxMore;
7805 ads->ds_ctl2 = 0;
7806 ads->ds_ctl3 = 0;
7807 }
7808 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7809 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7810 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7811 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7812 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7813 return true;
7814 }
7815
7816 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
7817 {
7818 struct ar5416_desc *ads = AR5416DESC(ds);
7819
7820 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7821 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7822 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7823 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7824 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7825 }
7826
7827 int
7828 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
7829 {
7830 struct ar5416_desc *ads = AR5416DESC(ds);
7831
7832 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
7833 return -EINPROGRESS;
7834
7835 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
7836 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
7837 ds->ds_txstat.ts_status = 0;
7838 ds->ds_txstat.ts_flags = 0;
7839
7840 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
7841 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
7842 if (ads->ds_txstatus1 & AR_Filtered)
7843 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
7844 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
7845 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
7846 if (ads->ds_txstatus9 & AR_TxOpExceeded)
7847 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
7848 if (ads->ds_txstatus1 & AR_TxTimerExpired)
7849 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
7850
7851 if (ads->ds_txstatus1 & AR_DescCfgErr)
7852 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
7853 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
7854 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
7855 ath9k_hw_updatetxtriglevel(ah, true);
7856 }
7857 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
7858 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
7859 ath9k_hw_updatetxtriglevel(ah, true);
7860 }
7861 if (ads->ds_txstatus0 & AR_TxBaStatus) {
7862 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
7863 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
7864 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
7865 }
7866
7867 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
7868 switch (ds->ds_txstat.ts_rateindex) {
7869 case 0:
7870 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
7871 break;
7872 case 1:
7873 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
7874 break;
7875 case 2:
7876 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
7877 break;
7878 case 3:
7879 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
7880 break;
7881 }
7882
7883 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
7884 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
7885 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
7886 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
7887 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
7888 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
7889 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
7890 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
7891 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
7892 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
7893 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
7894 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
7895 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
7896 ds->ds_txstat.ts_antenna = 1;
7897
7898 return 0;
7899 }
7900
7901 void
7902 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
7903 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
7904 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
7905 {
7906 struct ar5416_desc *ads = AR5416DESC(ds);
7907 struct ath_hal_5416 *ahp = AH5416(ah);
7908
7909 txPower += ahp->ah_txPowerIndexOffset;
7910 if (txPower > 63)
7911 txPower = 63;
7912
7913 ads->ds_ctl0 = (pktLen & AR_FrameLen)
7914 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
7915 | SM(txPower, AR_XmitPower)
7916 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
7917 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
7918 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
7919 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
7920
7921 ads->ds_ctl1 =
7922 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
7923 | SM(type, AR_FrameType)
7924 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
7925 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
7926 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
7927
7928 ads->ds_ctl6 = SM(keyType, AR_EncrType);
7929
7930 if (AR_SREV_9285(ah)) {
7931
7932 ads->ds_ctl8 = 0;
7933 ads->ds_ctl9 = 0;
7934 ads->ds_ctl10 = 0;
7935 ads->ds_ctl11 = 0;
7936 }
7937 }
7938
7939 void
7940 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
7941 struct ath_desc *lastds,
7942 u32 durUpdateEn, u32 rtsctsRate,
7943 u32 rtsctsDuration,
7944 struct ath9k_11n_rate_series series[],
7945 u32 nseries, u32 flags)
7946 {
7947 struct ar5416_desc *ads = AR5416DESC(ds);
7948 struct ar5416_desc *last_ads = AR5416DESC(lastds);
7949 u32 ds_ctl0;
7950
7951 (void) nseries;
7952 (void) rtsctsDuration;
7953
7954 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
7955 ds_ctl0 = ads->ds_ctl0;
7956
7957 if (flags & ATH9K_TXDESC_RTSENA) {
7958 ds_ctl0 &= ~AR_CTSEnable;
7959 ds_ctl0 |= AR_RTSEnable;
7960 } else {
7961 ds_ctl0 &= ~AR_RTSEnable;
7962 ds_ctl0 |= AR_CTSEnable;
7963 }
7964
7965 ads->ds_ctl0 = ds_ctl0;
7966 } else {
7967 ads->ds_ctl0 =
7968 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
7969 }
7970
7971 ads->ds_ctl2 = set11nTries(series, 0)
7972 | set11nTries(series, 1)
7973 | set11nTries(series, 2)
7974 | set11nTries(series, 3)
7975 | (durUpdateEn ? AR_DurUpdateEna : 0)
7976 | SM(0, AR_BurstDur);
7977
7978 ads->ds_ctl3 = set11nRate(series, 0)
7979 | set11nRate(series, 1)
7980 | set11nRate(series, 2)
7981 | set11nRate(series, 3);
7982
7983 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
7984 | set11nPktDurRTSCTS(series, 1);
7985
7986 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
7987 | set11nPktDurRTSCTS(series, 3);
7988
7989 ads->ds_ctl7 = set11nRateFlags(series, 0)
7990 | set11nRateFlags(series, 1)
7991 | set11nRateFlags(series, 2)
7992 | set11nRateFlags(series, 3)
7993 | SM(rtsctsRate, AR_RTSCTSRate);
7994 last_ads->ds_ctl2 = ads->ds_ctl2;
7995 last_ads->ds_ctl3 = ads->ds_ctl3;
7996 }
7997
7998 void
7999 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
8000 u32 aggrLen)
8001 {
8002 struct ar5416_desc *ads = AR5416DESC(ds);
8003
8004 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8005
8006 ads->ds_ctl6 &= ~AR_AggrLen;
8007 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
8008 }
8009
8010 void
8011 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
8012 u32 numDelims)
8013 {
8014 struct ar5416_desc *ads = AR5416DESC(ds);
8015 unsigned int ctl6;
8016
8017 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8018
8019 ctl6 = ads->ds_ctl6;
8020 ctl6 &= ~AR_PadDelim;
8021 ctl6 |= SM(numDelims, AR_PadDelim);
8022 ads->ds_ctl6 = ctl6;
8023 }
8024
8025 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
8026 {
8027 struct ar5416_desc *ads = AR5416DESC(ds);
8028
8029 ads->ds_ctl1 |= AR_IsAggr;
8030 ads->ds_ctl1 &= ~AR_MoreAggr;
8031 ads->ds_ctl6 &= ~AR_PadDelim;
8032 }
8033
8034 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
8035 {
8036 struct ar5416_desc *ads = AR5416DESC(ds);
8037
8038 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
8039 }
8040
8041 void
8042 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
8043 u32 burstDuration)
8044 {
8045 struct ar5416_desc *ads = AR5416DESC(ds);
8046
8047 ads->ds_ctl2 &= ~AR_BurstDur;
8048 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
8049 }
8050
8051 void
8052 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
8053 u32 vmf)
8054 {
8055 struct ar5416_desc *ads = AR5416DESC(ds);
8056
8057 if (vmf)
8058 ads->ds_ctl0 |= AR_VirtMoreFrag;
8059 else
8060 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
8061 }
8062
8063 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp)
8064 {
8065 REG_WRITE(ah, AR_RXDP, rxdp);
8066 }
8067
8068 void ath9k_hw_rxena(struct ath_hal *ah)
8069 {
8070 REG_WRITE(ah, AR_CR, AR_CR_RXE);
8071 }
8072
8073 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
8074 {
8075 if (set) {
8076
8077 REG_SET_BIT(ah, AR_DIAG_SW,
8078 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8079
8080 if (!ath9k_hw_wait
8081 (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
8082 u32 reg;
8083
8084 REG_CLR_BIT(ah, AR_DIAG_SW,
8085 (AR_DIAG_RX_DIS |
8086 AR_DIAG_RX_ABORT));
8087
8088 reg = REG_READ(ah, AR_OBS_BUS_1);
8089 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
8090 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
8091 __func__, reg);
8092
8093 return false;
8094 }
8095 } else {
8096 REG_CLR_BIT(ah, AR_DIAG_SW,
8097 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8098 }
8099
8100 return true;
8101 }
8102
8103 void
8104 ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
8105 u32 filter1)
8106 {
8107 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8108 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8109 }
8110
8111 bool
8112 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8113 u32 size, u32 flags)
8114 {
8115 struct ar5416_desc *ads = AR5416DESC(ds);
8116 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
8117
8118 ads->ds_ctl1 = size & AR_BufLen;
8119 if (flags & ATH9K_RXDESC_INTREQ)
8120 ads->ds_ctl1 |= AR_RxIntrReq;
8121
8122 ads->ds_rxstatus8 &= ~AR_RxDone;
8123 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
8124 memset(&(ads->u), 0, sizeof(ads->u));
8125 return true;
8126 }
8127
8128 int
8129 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
8130 u32 pa, struct ath_desc *nds, u64 tsf)
8131 {
8132 struct ar5416_desc ads;
8133 struct ar5416_desc *adsp = AR5416DESC(ds);
8134
8135 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
8136 return -EINPROGRESS;
8137
8138 ads.u.rx = adsp->u.rx;
8139
8140 ds->ds_rxstat.rs_status = 0;
8141 ds->ds_rxstat.rs_flags = 0;
8142
8143 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
8144 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
8145
8146 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
8147 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
8148 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
8149 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
8150 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
8151 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
8152 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
8153 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8154 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
8155 else
8156 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
8157
8158 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
8159 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
8160
8161 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
8162 ds->ds_rxstat.rs_moreaggr =
8163 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8164 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
8165 ds->ds_rxstat.rs_flags =
8166 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
8167 ds->ds_rxstat.rs_flags |=
8168 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
8169
8170 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8171 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
8172 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8173 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
8174 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8175 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
8176
8177 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
8178
8179 if (ads.ds_rxstatus8 & AR_CRCErr)
8180 ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
8181 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8182 u32 phyerr;
8183
8184 ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
8185 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8186 ds->ds_rxstat.rs_phyerr = phyerr;
8187 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8188 ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
8189 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8190 ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
8191 }
8192
8193 return 0;
8194 }
8195
8196 static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
8197 struct ath9k_rate_table *rt)
8198 {
8199 int i;
8200
8201 if (rt->rateCodeToIndex[0] != 0)
8202 return;
8203 for (i = 0; i < 256; i++)
8204 rt->rateCodeToIndex[i] = (u8) -1;
8205 for (i = 0; i < rt->rateCount; i++) {
8206 u8 code = rt->info[i].rateCode;
8207 u8 cix = rt->info[i].controlRate;
8208
8209 rt->rateCodeToIndex[code] = i;
8210 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
8211
8212 rt->info[i].lpAckDuration =
8213 ath9k_hw_computetxtime(ah, rt,
8214 WLAN_CTRL_FRAME_SIZE,
8215 cix,
8216 false);
8217 rt->info[i].spAckDuration =
8218 ath9k_hw_computetxtime(ah, rt,
8219 WLAN_CTRL_FRAME_SIZE,
8220 cix,
8221 true);
8222 }
8223 }
8224
8225 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
8226 u32 mode)
8227 {
8228 struct ath9k_rate_table *rt;
8229 switch (mode) {
8230 case ATH9K_MODE_11A:
8231 rt = &ar5416_11a_table;
8232 break;
8233 case ATH9K_MODE_11B:
8234 rt = &ar5416_11b_table;
8235 break;
8236 case ATH9K_MODE_11G:
8237 rt = &ar5416_11g_table;
8238 break;
8239 case ATH9K_MODE_11NG_HT20:
8240 case ATH9K_MODE_11NG_HT40PLUS:
8241 case ATH9K_MODE_11NG_HT40MINUS:
8242 rt = &ar5416_11ng_table;
8243 break;
8244 case ATH9K_MODE_11NA_HT20:
8245 case ATH9K_MODE_11NA_HT40PLUS:
8246 case ATH9K_MODE_11NA_HT40MINUS:
8247 rt = &ar5416_11na_table;
8248 break;
8249 default:
8250 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
8251 __func__, mode);
8252 return NULL;
8253 }
8254 ath9k_hw_setup_rate_table(ah, rt);
8255 return rt;
8256 }
8257
8258 static const char *ath9k_hw_devname(u16 devid)
8259 {
8260 switch (devid) {
8261 case AR5416_DEVID_PCI:
8262 case AR5416_DEVID_PCIE:
8263 return "Atheros 5416";
8264 case AR9160_DEVID_PCI:
8265 return "Atheros 9160";
8266 case AR9280_DEVID_PCI:
8267 case AR9280_DEVID_PCIE:
8268 return "Atheros 9280";
8269 }
8270 return NULL;
8271 }
8272
8273 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
8274 {
8275 return vendorid == ATHEROS_VENDOR_ID ?
8276 ath9k_hw_devname(devid) : NULL;
8277 }
8278
8279 struct ath_hal *ath9k_hw_attach(u16 devid,
8280 struct ath_softc *sc,
8281 void __iomem *mem,
8282 int *error)
8283 {
8284 struct ath_hal *ah = NULL;
8285
8286 switch (devid) {
8287 case AR5416_DEVID_PCI:
8288 case AR5416_DEVID_PCIE:
8289 case AR9160_DEVID_PCI:
8290 case AR9280_DEVID_PCI:
8291 case AR9280_DEVID_PCIE:
8292 ah = ath9k_hw_do_attach(devid, sc, mem, error);
8293 break;
8294 default:
8295 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
8296 "devid=0x%x not supported.\n", devid);
8297 ah = NULL;
8298 *error = -ENXIO;
8299 break;
8300 }
8301
8302 return ah;
8303 }
8304
8305 u16
8306 ath9k_hw_computetxtime(struct ath_hal *ah,
8307 const struct ath9k_rate_table *rates,
8308 u32 frameLen, u16 rateix,
8309 bool shortPreamble)
8310 {
8311 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
8312 u32 kbps;
8313
8314 kbps = rates->info[rateix].rateKbps;
8315
8316 if (kbps == 0)
8317 return 0;
8318 switch (rates->info[rateix].phy) {
8319
8320 case PHY_CCK:
8321 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
8322 if (shortPreamble && rates->info[rateix].shortPreamble)
8323 phyTime >>= 1;
8324 numBits = frameLen << 3;
8325 txTime = CCK_SIFS_TIME + phyTime
8326 + ((numBits * 1000) / kbps);
8327 break;
8328 case PHY_OFDM:
8329 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
8330 bitsPerSymbol =
8331 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
8332
8333 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8334 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8335 txTime = OFDM_SIFS_TIME_QUARTER
8336 + OFDM_PREAMBLE_TIME_QUARTER
8337 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
8338 } else if (ah->ah_curchan &&
8339 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
8340 bitsPerSymbol =
8341 (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
8342
8343 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8344 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8345 txTime = OFDM_SIFS_TIME_HALF +
8346 OFDM_PREAMBLE_TIME_HALF
8347 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
8348 } else {
8349 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
8350
8351 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8352 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8353 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
8354 + (numSymbols * OFDM_SYMBOL_TIME);
8355 }
8356 break;
8357
8358 default:
8359 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
8360 "%s: unknown phy %u (rate ix %u)\n", __func__,
8361 rates->info[rateix].phy, rateix);
8362 txTime = 0;
8363 break;
8364 }
8365 return txTime;
8366 }
8367
8368 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
8369 {
8370 if (flags & CHANNEL_2GHZ) {
8371 if (freq == 2484)
8372 return 14;
8373 if (freq < 2484)
8374 return (freq - 2407) / 5;
8375 else
8376 return 15 + ((freq - 2512) / 20);
8377 } else if (flags & CHANNEL_5GHZ) {
8378 if (ath9k_regd_is_public_safety_sku(ah) &&
8379 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8380 return ((freq * 10) +
8381 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
8382 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
8383 return (freq - 4000) / 5;
8384 } else {
8385 return (freq - 5000) / 5;
8386 }
8387 } else {
8388 if (freq == 2484)
8389 return 14;
8390 if (freq < 2484)
8391 return (freq - 2407) / 5;
8392 if (freq < 5000) {
8393 if (ath9k_regd_is_public_safety_sku(ah)
8394 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8395 return ((freq * 10) +
8396 (((freq % 5) ==
8397 2) ? 5 : 0) - 49400) / 5;
8398 } else if (freq > 4900) {
8399 return (freq - 4000) / 5;
8400 } else {
8401 return 15 + ((freq - 2512) / 20);
8402 }
8403 }
8404 return (freq - 5000) / 5;
8405 }
8406 }
8407
8408 /* We can tune this as we go by monitoring really low values */
8409 #define ATH9K_NF_TOO_LOW -60
8410
8411 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
8412 * is incorrect and we should use the static NF value. Later we can try to
8413 * find out why they are reporting these values */
8414 static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
8415 {
8416 if (nf > ATH9K_NF_TOO_LOW) {
8417 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8418 "%s: noise floor value detected (%d) is "
8419 "lower than what we think is a "
8420 "reasonable value (%d)\n",
8421 __func__, nf, ATH9K_NF_TOO_LOW);
8422 return false;
8423 }
8424 return true;
8425 }
8426
8427 s16
8428 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
8429 {
8430 struct ath9k_channel *ichan;
8431 s16 nf;
8432
8433 ichan = ath9k_regd_check_channel(ah, chan);
8434 if (ichan == NULL) {
8435 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8436 "%s: invalid channel %u/0x%x; no mapping\n",
8437 __func__, chan->channel, chan->channelFlags);
8438 return ATH_DEFAULT_NOISE_FLOOR;
8439 }
8440 if (ichan->rawNoiseFloor == 0) {
8441 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
8442 nf = NOISE_FLOOR[mode];
8443 } else
8444 nf = ichan->rawNoiseFloor;
8445
8446 if (!ath9k_hw_nf_in_range(ah, nf))
8447 nf = ATH_DEFAULT_NOISE_FLOOR;
8448
8449 return nf;
8450 }
8451
8452 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
8453 {
8454 struct ath_hal_5416 *ahp = AH5416(ah);
8455
8456 if (setting)
8457 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8458 else
8459 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8460 return true;
8461 }
8462
8463 bool ath9k_hw_phycounters(struct ath_hal *ah)
8464 {
8465 struct ath_hal_5416 *ahp = AH5416(ah);
8466
8467 return ahp->ah_hasHwPhyCounters ? true : false;
8468 }
8469
8470 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q)
8471 {
8472 return REG_READ(ah, AR_QTXDP(q));
8473 }
8474
8475 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
8476 u32 txdp)
8477 {
8478 REG_WRITE(ah, AR_QTXDP(q), txdp);
8479
8480 return true;
8481 }
8482
8483 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
8484 {
8485 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
8486
8487 REG_WRITE(ah, AR_Q_TXE, 1 << q);
8488
8489 return true;
8490 }
8491
8492 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q)
8493 {
8494 u32 npend;
8495
8496 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
8497 if (npend == 0) {
8498
8499 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
8500 npend = 1;
8501 }
8502 return npend;
8503 }
8504
8505 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
8506 {
8507 u32 wait;
8508
8509 REG_WRITE(ah, AR_Q_TXD, 1 << q);
8510
8511 for (wait = 1000; wait != 0; wait--) {
8512 if (ath9k_hw_numtxpending(ah, q) == 0)
8513 break;
8514 udelay(100);
8515 }
8516
8517 if (ath9k_hw_numtxpending(ah, q)) {
8518 u32 tsfLow, j;
8519
8520 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8521 "%s: Num of pending TX Frames %d on Q %d\n",
8522 __func__, ath9k_hw_numtxpending(ah, q), q);
8523
8524 for (j = 0; j < 2; j++) {
8525 tsfLow = REG_READ(ah, AR_TSF_L32);
8526 REG_WRITE(ah, AR_QUIET2,
8527 SM(10, AR_QUIET2_QUIET_DUR));
8528 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
8529 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
8530 REG_SET_BIT(ah, AR_TIMER_MODE,
8531 AR_QUIET_TIMER_EN);
8532
8533 if ((REG_READ(ah, AR_TSF_L32) >> 10) ==
8534 (tsfLow >> 10)) {
8535 break;
8536 }
8537 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8538 "%s: TSF have moved while trying to set "
8539 "quiet time TSF: 0x%08x\n",
8540 __func__, tsfLow);
8541 }
8542
8543 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8544
8545 udelay(200);
8546 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
8547
8548 wait = 1000;
8549
8550 while (ath9k_hw_numtxpending(ah, q)) {
8551 if ((--wait) == 0) {
8552 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
8553 "%s: Failed to stop Tx DMA in 100 "
8554 "msec after killing last frame\n",
8555 __func__);
8556 break;
8557 }
8558 udelay(100);
8559 }
8560
8561 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8562 }
8563
8564 REG_WRITE(ah, AR_Q_TXD, 0);
8565 return wait != 0;
8566 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree