drivers/net/wireless/ath9k/core.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef CORE_H
  18 #define CORE_H
  19
  20 #include <linux/version.h>
  21 #include <linux/autoconf.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/skbuff.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/ip.h>
  30 #include <linux/tcp.h>
  31 #include <linux/in.h>
  32 #include <linux/delay.h>
  33 #include <linux/wait.h>
  34 #include <linux/pci.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/sched.h>
  37 #include <linux/list.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/scatterlist.h>
  40 #include <asm/page.h>
  41 #include <net/mac80211.h>
  42 #include <linux/leds.h>
  43 #include <linux/rfkill.h>
  44
  45 #include "ath9k.h"
  46 #include "rc.h"
  47
  48 struct ath_node;
  49
  50 /******************/
  51 /* Utility macros */
  52 /******************/
  53
  54 /* Macro to expand scalars to 64-bit objects */
  55
  56 #define ito64(x) (sizeof(x) == 8) ?                     \
  57         (((unsigned long long int)(x)) & (0xff)) :      \
  58         (sizeof(x) == 16) ?                             \
  59         (((unsigned long long int)(x)) & 0xffff) :      \
  60         ((sizeof(x) == 32) ?                            \
  61          (((unsigned long long int)(x)) & 0xffffffff) : \
  62          (unsigned long long int)(x))
  63
  64 /* increment with wrap-around */
  65 #define INCR(_l, _sz)   do {                    \
  66                 (_l)++;                         \
  67                 (_l) &= ((_sz) - 1);            \
  68         } while (0)
  69
  70 /* decrement with wrap-around */
  71 #define DECR(_l,  _sz)  do {                    \
  72                 (_l)--;                         \
  73                 (_l) &= ((_sz) - 1);            \
  74         } while (0)
  75
  76 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  77
  78 #define ASSERT(exp) do {                        \
  79                 if (unlikely(!(exp))) {         \
  80                         BUG();                  \
  81                 }                               \
  82         } while (0)
  83
  84 #define TSF_TO_TU(_h,_l) \
  85         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  86
  87 #define ATH9K_BH_STATUS_INTACT          0
  88 #define ATH9K_BH_STATUS_CHANGE          1
  89
  90 #define ATH_TXQ_SETUP(sc, i)        ((sc)->sc_txqsetup & (1<<i))
  91
  92 static inline unsigned long get_timestamp(void)
  93 {
  94         return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
  95 }
  96
  97 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  98
  99 /*************/
 100 /* Debugging */
 101 /*************/
 102
 103 enum ATH_DEBUG {
 104         ATH_DBG_RESET           = 0x00000001,
 105         ATH_DBG_PHY_IO          = 0x00000002,
 106         ATH_DBG_REG_IO          = 0x00000004,
 107         ATH_DBG_QUEUE           = 0x00000008,
 108         ATH_DBG_EEPROM          = 0x00000010,
 109         ATH_DBG_NF_CAL          = 0x00000020,
 110         ATH_DBG_CALIBRATE       = 0x00000040,
 111         ATH_DBG_CHANNEL         = 0x00000080,
 112         ATH_DBG_INTERRUPT       = 0x00000100,
 113         ATH_DBG_REGULATORY      = 0x00000200,
 114         ATH_DBG_ANI             = 0x00000400,
 115         ATH_DBG_POWER_MGMT      = 0x00000800,
 116         ATH_DBG_XMIT            = 0x00001000,
 117         ATH_DBG_BEACON          = 0x00002000,
 118         ATH_DBG_RATE            = 0x00004000,
 119         ATH_DBG_CONFIG          = 0x00008000,
 120         ATH_DBG_KEYCACHE        = 0x00010000,
 121         ATH_DBG_AGGR            = 0x00020000,
 122         ATH_DBG_FATAL           = 0x00040000,
 123         ATH_DBG_ANY             = 0xffffffff
 124 };
 125
 126 #define DBG_DEFAULT (ATH_DBG_FATAL)
 127
 128 #define DPRINTF(sc, _m, _fmt, ...) do {                 \
 129                 if (sc->sc_debug & (_m))                \
 130                         printk(_fmt , ##__VA_ARGS__);   \
 131         } while (0)
 132
 133 /***************************/
 134 /* Load-time Configuration */
 135 /***************************/
 136
 137 /* Per-instance load-time (note: NOT run-time) configurations
 138  * for Atheros Device */
 139 struct ath_config {
 140         u32 ath_aggr_prot;
 141         u16 txpowlimit;
 142         u16 txpowlimit_override;
 143         u8 cabqReadytime; /* Cabq Readytime % */
 144         u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
 145 };
 146
 147 /***********************/
 148 /* Chainmask Selection */
 149 /***********************/
 150
 151 #define ATH_CHAINMASK_SEL_TIMEOUT          6000
 152 /* Default - Number of last RSSI values that is used for
 153  * chainmask selection */
 154 #define ATH_CHAINMASK_SEL_RSSI_CNT         10
 155 /* Means use 3x3 chainmask instead of configured chainmask */
 156 #define ATH_CHAINMASK_SEL_3X3              7
 157 /* Default - Rssi threshold below which we have to switch to 3x3 */
 158 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES    20
 159 /* Default - Rssi threshold above which we have to switch to
 160  * user configured values */
 161 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES  35
 162 /* Struct to store the chainmask select related info */
 163 struct ath_chainmask_sel {
 164         struct timer_list timer;
 165         int cur_tx_mask;        /* user configured or 3x3 */
 166         int cur_rx_mask;        /* user configured or 3x3 */
 167         int tx_avgrssi;
 168         u8 switch_allowed:1,    /* timer will set this */
 169            cm_sel_enabled : 1;
 170 };
 171
 172 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
 173 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 174
 175 /*************************/
 176 /* Descriptor Management */
 177 /*************************/
 178
 179 #define ATH_TXBUF_RESET(_bf) do {                               \
 180                 (_bf)->bf_status = 0;                           \
 181                 (_bf)->bf_lastbf = NULL;                        \
 182                 (_bf)->bf_lastfrm = NULL;                       \
 183                 (_bf)->bf_next = NULL;                          \
 184                 memset(&((_bf)->bf_state), 0,                   \
 185                             sizeof(struct ath_buf_state));      \
 186         } while (0)
 187
 188 enum buffer_type {
 189         BUF_DATA                = BIT(0),
 190         BUF_AGGR                = BIT(1),
 191         BUF_AMPDU               = BIT(2),
 192         BUF_HT                  = BIT(3),
 193         BUF_RETRY               = BIT(4),
 194         BUF_XRETRY              = BIT(5),
 195         BUF_SHORT_PREAMBLE      = BIT(6),
 196         BUF_BAR                 = BIT(7),
 197         BUF_PSPOLL              = BIT(8),
 198         BUF_AGGR_BURST          = BIT(9),
 199         BUF_CALC_AIRTIME        = BIT(10),
 200 };
 201
 202 struct ath_buf_state {
 203         int bfs_nframes;                        /* # frames in aggregate */
 204         u16 bfs_al;                             /* length of aggregate */
 205         u16 bfs_frmlen;                         /* length of frame */
 206         int bfs_seqno;                          /* sequence number */
 207         int bfs_tidno;                          /* tid of this frame */
 208         int bfs_retries;                        /* current retries */
 209         struct ath_rc_series bfs_rcs[4];        /* rate series */
 210         u32 bf_type;                            /* BUF_* (enum buffer_type) */
 211         /* key type use to encrypt this frame */
 212         enum ath9k_key_type bfs_keytype;
 213 };
 214
 215 #define bf_nframes              bf_state.bfs_nframes
 216 #define bf_al                   bf_state.bfs_al
 217 #define bf_frmlen               bf_state.bfs_frmlen
 218 #define bf_retries              bf_state.bfs_retries
 219 #define bf_seqno                bf_state.bfs_seqno
 220 #define bf_tidno                bf_state.bfs_tidno
 221 #define bf_rcs                  bf_state.bfs_rcs
 222 #define bf_keytype              bf_state.bfs_keytype
 223 #define bf_isdata(bf)           (bf->bf_state.bf_type & BUF_DATA)
 224 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 225 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 226 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 227 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 228 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 229 #define bf_isshpreamble(bf)     (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
 230 #define bf_isbar(bf)            (bf->bf_state.bf_type & BUF_BAR)
 231 #define bf_ispspoll(bf)         (bf->bf_state.bf_type & BUF_PSPOLL)
 232 #define bf_isaggrburst(bf)      (bf->bf_state.bf_type & BUF_AGGR_BURST)
 233
 234 /*
 235  * Abstraction of a contiguous buffer to transmit/receive.  There is only
 236  * a single hw descriptor encapsulated here.
 237  */
 238 struct ath_buf {
 239         struct list_head list;
 240         struct list_head *last;
 241         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 242                                            an aggregate) */
 243         struct ath_buf *bf_lastfrm;     /* last buf of this frame */
 244         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 245         struct ath_buf *bf_rifslast;    /* last buf for RIFS burst */
 246         void *bf_mpdu;                  /* enclosing frame structure */
 247         void *bf_node;                  /* pointer to the node */
 248         struct ath_desc *bf_desc;       /* virtual addr of desc */
 249         dma_addr_t bf_daddr;            /* physical addr of desc */
 250         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 251         u32 bf_status;
 252         u16 bf_flags;                   /* tx descriptor flags */
 253         struct ath_buf_state bf_state;  /* buffer state */
 254         dma_addr_t bf_dmacontext;
 255 };
 256
 257 /*
 258  * reset the rx buffer.
 259  * any new fields added to the athbuf and require
 260  * reset need to be added to this macro.
 261  * currently bf_status is the only one requires that
 262  * requires reset.
 263  */
 264 #define ATH_RXBUF_RESET(_bf)    ((_bf)->bf_status = 0)
 265
 266 /* hw processing complete, desc processed by hal */
 267 #define ATH_BUFSTATUS_DONE      0x00000001
 268 /* hw processing complete, desc hold for hw */
 269 #define ATH_BUFSTATUS_STALE     0x00000002
 270 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
 271 #define ATH_BUFSTATUS_FREE      0x00000004
 272
 273 /* DMA state for tx/rx descriptors */
 274
 275 struct ath_descdma {
 276         const char *dd_name;
 277         struct ath_desc *dd_desc;       /* descriptors  */
 278         dma_addr_t dd_desc_paddr;       /* physical addr of dd_desc  */
 279         u32 dd_desc_len;                /* size of dd_desc  */
 280         struct ath_buf *dd_bufptr;      /* associated buffers */
 281         dma_addr_t dd_dmacontext;
 282 };
 283
 284 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
 285
 286 struct ath_rx_context {
 287         struct ath_buf *ctx_rxbuf;      /* associated ath_buf for rx */
 288 };
 289 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
 290
 291 int ath_descdma_setup(struct ath_softc *sc,
 292                       struct ath_descdma *dd,
 293                       struct list_head *head,
 294                       const char *name,
 295                       int nbuf,
 296                       int ndesc);
 297 int ath_desc_alloc(struct ath_softc *sc);
 298 void ath_desc_free(struct ath_softc *sc);
 299 void ath_descdma_cleanup(struct ath_softc *sc,
 300                          struct ath_descdma *dd,
 301                          struct list_head *head);
 302
 303 /******/
 304 /* RX */
 305 /******/
 306
 307 #define ATH_MAX_ANTENNA          3
 308 #define ATH_RXBUF                512
 309 #define ATH_RX_TIMEOUT           40      /* 40 milliseconds */
 310 #define WME_NUM_TID              16
 311 #define IEEE80211_BAR_CTL_TID_M  0xF000  /* tid mask */
 312 #define IEEE80211_BAR_CTL_TID_S  12      /* tid shift */
 313
 314 enum ATH_RX_TYPE {
 315         ATH_RX_NON_CONSUMED = 0,
 316         ATH_RX_CONSUMED
 317 };
 318
 319 /* per frame rx status block */
 320 struct ath_recv_status {
 321         u64 tsf;                /* mac tsf */
 322         int8_t rssi;            /* RSSI (noise floor ajusted) */
 323         int8_t rssictl[ATH_MAX_ANTENNA];        /* RSSI (noise floor ajusted) */
 324         int8_t rssiextn[ATH_MAX_ANTENNA];       /* RSSI (noise floor ajusted) */
 325         int8_t abs_rssi;        /* absolute RSSI */
 326         u8 rateieee;            /* data rate received (IEEE rate code) */
 327         u8 ratecode;            /* phy rate code */
 328         int rateKbps;           /* data rate received (Kbps) */
 329         int antenna;            /* rx antenna */
 330         int flags;              /* status of associated skb */
 331 #define ATH_RX_FCS_ERROR        0x01
 332 #define ATH_RX_MIC_ERROR        0x02
 333 #define ATH_RX_DECRYPT_ERROR    0x04
 334 #define ATH_RX_RSSI_VALID       0x08
 335 /* if any of ctl,extn chainrssis are valid */
 336 #define ATH_RX_CHAIN_RSSI_VALID 0x10
 337 /* if extn chain rssis are valid */
 338 #define ATH_RX_RSSI_EXTN_VALID  0x20
 339 /* set if 40Mhz, clear if 20Mhz */
 340 #define ATH_RX_40MHZ            0x40
 341 /* set if short GI, clear if full GI */
 342 #define ATH_RX_SHORT_GI         0x80
 343 };
 344
 345 struct ath_rxbuf {
 346         struct sk_buff *rx_wbuf;
 347         unsigned long rx_time;                  /* system time when received */
 348         struct ath_recv_status rx_status;       /* cached rx status */
 349 };
 350
 351 /* Per-TID aggregate receiver state for a node */
 352 struct ath_arx_tid {
 353         struct ath_node *an;
 354         struct ath_rxbuf *rxbuf;        /* re-ordering buffer */
 355         struct timer_list timer;
 356         spinlock_t tidlock;
 357         int baw_head;                   /* seq_next at head */
 358         int baw_tail;                   /* tail of block-ack window */
 359         int seq_reset;                  /* need to reset start sequence */
 360         int addba_exchangecomplete;
 361         u16 seq_next;                   /* next expected sequence */
 362         u16 baw_size;                   /* block-ack window size */
 363 };
 364
 365 /* Per-node receiver aggregate state */
 366 struct ath_arx {
 367         struct ath_arx_tid tid[WME_NUM_TID];
 368 };
 369
 370 int ath_startrecv(struct ath_softc *sc);
 371 bool ath_stoprecv(struct ath_softc *sc);
 372 void ath_flushrecv(struct ath_softc *sc);
 373 u32 ath_calcrxfilter(struct ath_softc *sc);
 374 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
 375 void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
 376 void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 377 void ath_handle_rx_intr(struct ath_softc *sc);
 378 int ath_rx_init(struct ath_softc *sc, int nbufs);
 379 void ath_rx_cleanup(struct ath_softc *sc);
 380 int ath_rx_tasklet(struct ath_softc *sc, int flush);
 381 int ath_rx_input(struct ath_softc *sc,
 382                  struct ath_node *node,
 383                  int is_ampdu,
 384                  struct sk_buff *skb,
 385                  struct ath_recv_status *rx_status,
 386                  enum ATH_RX_TYPE *status);
 387 int _ath_rx_indicate(struct ath_softc *sc,
 388                      struct sk_buff *skb,
 389                      struct ath_recv_status *status,
 390                      u16 keyix);
 391 int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
 392                     struct ath_recv_status *status);
 393
 394 /******/
 395 /* TX */
 396 /******/
 397
 398 #define ATH_TXBUF               512
 399 /* max number of transmit attempts (tries) */
 400 #define ATH_TXMAXTRY            13
 401 /* max number of 11n transmit attempts (tries) */
 402 #define ATH_11N_TXMAXTRY        10
 403 /* max number of tries for management and control frames */
 404 #define ATH_MGT_TXMAXTRY        4
 405 #define WME_BA_BMP_SIZE         64
 406 #define WME_MAX_BA              WME_BA_BMP_SIZE
 407 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 408 #define TID_TO_WME_AC(_tid)                             \
 409         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 410          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 411          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 412          WME_AC_VO)
 413
 414
 415 /* Wireless Multimedia Extension Defines */
 416 #define WME_AC_BE               0 /* best effort */
 417 #define WME_AC_BK               1 /* background */
 418 #define WME_AC_VI               2 /* video */
 419 #define WME_AC_VO               3 /* voice */
 420 #define WME_NUM_AC              4
 421
 422 enum ATH_SM_PWRSAV{
 423         ATH_SM_ENABLE,
 424         ATH_SM_PWRSAV_STATIC,
 425         ATH_SM_PWRSAV_DYNAMIC,
 426 };
 427
 428 /*
 429  * Data transmit queue state.  One of these exists for each
 430  * hardware transmit queue.  Packets sent to us from above
 431  * are assigned to queues based on their priority.  Not all
 432  * devices support a complete set of hardware transmit queues.
 433  * For those devices the array sc_ac2q will map multiple
 434  * priorities to fewer hardware queues (typically all to one
 435  * hardware queue).
 436  */
 437 struct ath_txq {
 438         u32 axq_qnum;                   /* hardware q number */
 439         u32 *axq_link;                  /* link ptr in last TX desc */
 440         struct list_head axq_q;         /* transmit queue */
 441         spinlock_t axq_lock;
 442         unsigned long axq_lockflags;    /* intr state when must cli */
 443         u32 axq_depth;                  /* queue depth */
 444         u8 axq_aggr_depth;              /* aggregates queued */
 445         u32 axq_totalqueued;            /* total ever queued */
 446
 447         /* count to determine if descriptor should generate int on this txq. */
 448         u32 axq_intrcnt;
 449
 450         bool stopped;                   /* Is mac80211 queue stopped ? */
 451         struct ath_buf *axq_linkbuf;    /* virtual addr of last buffer*/
 452
 453         /* first desc of the last descriptor that contains CTS */
 454         struct ath_desc *axq_lastdsWithCTS;
 455
 456         /* final desc of the gating desc that determines whether
 457            lastdsWithCTS has been DMA'ed or not */
 458         struct ath_desc *axq_gatingds;
 459
 460         struct list_head axq_acq;
 461 };
 462
 463 /* per TID aggregate tx state for a destination */
 464 struct ath_atx_tid {
 465         struct list_head list;          /* round-robin tid entry */
 466         struct list_head buf_q;         /* pending buffers */
 467         struct ath_node *an;
 468         struct ath_atx_ac *ac;
 469         struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
 470         u16 seq_start;
 471         u16 seq_next;
 472         u16 baw_size;
 473         int tidno;
 474         int baw_head;                   /* first un-acked tx buffer */
 475         int baw_tail;                   /* next unused tx buffer slot */
 476         int sched;
 477         int paused;
 478         int cleanup_inprogress;
 479         u32 addba_exchangecomplete:1;
 480         int32_t addba_exchangeinprogress;
 481         int addba_exchangeattempts;
 482 };
 483
 484 /* per access-category aggregate tx state for a destination */
 485 struct ath_atx_ac {
 486         int sched;                      /* dest-ac is scheduled */
 487         int qnum;                       /* H/W queue number associated
 488                                            with this AC */
 489         struct list_head list;          /* round-robin txq entry */
 490         struct list_head tid_q;         /* queue of TIDs with buffers */
 491 };
 492
 493 /* per dest tx state */
 494 struct ath_atx {
 495         struct ath_atx_tid tid[WME_NUM_TID];
 496         struct ath_atx_ac ac[WME_NUM_AC];
 497 };
 498
 499 /* per-frame tx control block */
 500 struct ath_tx_control {
 501         struct ath_node *an;
 502         int if_id;
 503         int qnum;
 504         u32 ht:1;
 505         u32 ps:1;
 506         u32 use_minrate:1;
 507         enum ath9k_pkt_type atype;
 508         enum ath9k_key_type keytype;
 509         u32 flags;
 510         u16 seqno;
 511         u16 tidno;
 512         u16 txpower;
 513         u16 frmlen;
 514         u32 keyix;
 515         int min_rate;
 516         int mcast_rate;
 517         struct ath_softc *dev;
 518         dma_addr_t dmacontext;
 519 };
 520
 521 /* per frame tx status block */
 522 struct ath_xmit_status {
 523         int retries;    /* number of retries to successufully
 524                            transmit this frame */
 525         int flags;      /* status of transmit */
 526 #define ATH_TX_ERROR        0x01
 527 #define ATH_TX_XRETRY       0x02
 528 #define ATH_TX_BAR          0x04
 529 };
 530
 531 struct ath_tx_stat {
 532         int rssi;               /* RSSI (noise floor ajusted) */
 533         int rssictl[ATH_MAX_ANTENNA];   /* RSSI (noise floor ajusted) */
 534         int rssiextn[ATH_MAX_ANTENNA];  /* RSSI (noise floor ajusted) */
 535         int rateieee;           /* data rate xmitted (IEEE rate code) */
 536         int rateKbps;           /* data rate xmitted (Kbps) */
 537         int ratecode;           /* phy rate code */
 538         int flags;              /* validity flags */
 539 /* if any of ctl,extn chain rssis are valid */
 540 #define ATH_TX_CHAIN_RSSI_VALID 0x01
 541 /* if extn chain rssis are valid */
 542 #define ATH_TX_RSSI_EXTN_VALID  0x02
 543         u32 airtime;    /* time on air per final tx rate */
 544 };
 545
 546 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 547 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 548 int ath_tx_setup(struct ath_softc *sc, int haltype);
 549 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
 550 void ath_tx_draintxq(struct ath_softc *sc,
 551                      struct ath_txq *txq, bool retry_tx);
 552 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 553 void ath_tx_node_cleanup(struct ath_softc *sc,
 554                          struct ath_node *an, bool bh_flag);
 555 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
 556 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 557 int ath_tx_init(struct ath_softc *sc, int nbufs);
 558 int ath_tx_cleanup(struct ath_softc *sc);
 559 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
 560 int ath_txq_update(struct ath_softc *sc, int qnum,
 561                    struct ath9k_tx_queue_info *q);
 562 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
 563 void ath_tx_tasklet(struct ath_softc *sc);
 564 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
 565 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
 566 void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
 567 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 568                      struct ath_xmit_status *tx_status, struct ath_node *an);
 569 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
 570
 571 /**********************/
 572 /* Node / Aggregation */
 573 /**********************/
 574
 575 /* indicates the node is clened up */
 576 #define ATH_NODE_CLEAN          0x1
 577 /* indicates the node is 80211 power save */
 578 #define ATH_NODE_PWRSAVE        0x2
 579
 580 #define ADDBA_EXCHANGE_ATTEMPTS    10
 581 #define ATH_AGGR_DELIM_SZ          4   /* delimiter size   */
 582 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 583 /* number of delimiters for encryption padding */
 584 #define ATH_AGGR_ENCRYPTDELIM      10
 585 /* minimum h/w qdepth to be sustained to maximize aggregation */
 586 #define ATH_AGGR_MIN_QDEPTH        2
 587 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 588 #define IEEE80211_SEQ_SEQ_SHIFT    4
 589 #define IEEE80211_SEQ_MAX          4096
 590 #define IEEE80211_MIN_AMPDU_BUF    0x8
 591
 592 /* return whether a bit at index _n in bitmap _bm is set
 593  * _sz is the size of the bitmap  */
 594 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 595                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 596
 597 /* return block-ack bitmap index given sequence and starting sequence */
 598 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 599
 600 /* returns delimiter padding required given the packet length */
 601 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 602         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 603           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 604
 605 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 606         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 607
 608 #define ATH_DS_BA_SEQ(_ds)               ((_ds)->ds_us.tx.ts_seqnum)
 609 #define ATH_DS_BA_BITMAP(_ds)            (&(_ds)->ds_us.tx.ba_low)
 610 #define ATH_DS_TX_BA(_ds)       ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 611 #define ATH_AN_2_TID(_an, _tidno)        (&(_an)->an_aggr.tx.tid[(_tidno)])
 612
 613 enum ATH_AGGR_STATUS {
 614         ATH_AGGR_DONE,
 615         ATH_AGGR_BAW_CLOSED,
 616         ATH_AGGR_LIMITED,
 617         ATH_AGGR_SHORTPKT,
 618         ATH_AGGR_8K_LIMITED,
 619 };
 620
 621 enum ATH_AGGR_CHECK {
 622         AGGR_NOT_REQUIRED,
 623         AGGR_REQUIRED,
 624         AGGR_CLEANUP_PROGRESS,
 625         AGGR_EXCHANGE_PROGRESS,
 626         AGGR_EXCHANGE_DONE
 627 };
 628
 629 struct aggr_rifs_param {
 630         int param_max_frames;
 631         int param_max_len;
 632         int param_rl;
 633         int param_al;
 634         struct ath_rc_series *param_rcs;
 635 };
 636
 637 /* Per-node aggregation state */
 638 struct ath_node_aggr {
 639         struct ath_atx tx;      /* node transmit state */
 640         struct ath_arx rx;      /* node receive state */
 641 };
 642
 643 /* driver-specific node state */
 644 struct ath_node {
 645         struct list_head list;
 646         struct ath_softc *an_sc;
 647         atomic_t an_refcnt;
 648         struct ath_chainmask_sel an_chainmask_sel;
 649         struct ath_node_aggr an_aggr;
 650         u8 an_smmode; /* SM Power save mode */
 651         u8 an_flags;
 652         u8 an_addr[ETH_ALEN];
 653 };
 654
 655 void ath_tx_resume_tid(struct ath_softc *sc,
 656         struct ath_atx_tid *tid);
 657 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
 658         struct ath_node *an, u8 tidno);
 659 void ath_tx_aggr_teardown(struct ath_softc *sc,
 660         struct ath_node *an, u8 tidno);
 661 void ath_rx_aggr_teardown(struct ath_softc *sc,
 662         struct ath_node *an, u8 tidno);
 663 int ath_rx_aggr_start(struct ath_softc *sc,
 664                       const u8 *addr,
 665                       u16 tid,
 666                       u16 *ssn);
 667 int ath_rx_aggr_stop(struct ath_softc *sc,
 668                      const u8 *addr,
 669                      u16 tid);
 670 int ath_tx_aggr_start(struct ath_softc *sc,
 671                       const u8 *addr,
 672                       u16 tid,
 673                       u16 *ssn);
 674 int ath_tx_aggr_stop(struct ath_softc *sc,
 675                      const u8 *addr,
 676                      u16 tid);
 677 void ath_newassoc(struct ath_softc *sc,
 678         struct ath_node *node, int isnew, int isuapsd);
 679 struct ath_node *ath_node_attach(struct ath_softc *sc,
 680         u8 addr[ETH_ALEN], int if_id);
 681 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
 682 struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
 683 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
 684 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
 685
 686 /*******************/
 687 /* Beacon Handling */
 688 /*******************/
 689
 690 /*
 691  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 692  * number of BSSIDs) if a given beacon does not go out even after waiting this
 693  * number of beacon intervals, the game's up.
 694  */
 695 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 696 #define ATH_BCBUF                       4   /* number of beacon buffers */
 697 #define ATH_DEFAULT_BINTVAL             100 /* default beacon interval in TU */
 698 #define ATH_DEFAULT_BMISS_LIMIT         10
 699 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 700
 701 /* beacon configuration */
 702 struct ath_beacon_config {
 703         u16 beacon_interval;
 704         u16 listen_interval;
 705         u16 dtim_period;
 706         u16 bmiss_timeout;
 707         u8 dtim_count;
 708         u8 tim_offset;
 709         union {
 710                 u64 last_tsf;
 711                 u8 last_tstamp[8];
 712         } u; /* last received beacon/probe response timestamp of this BSS. */
 713 };
 714
 715 void ath9k_beacon_tasklet(unsigned long data);
 716 void ath_beacon_config(struct ath_softc *sc, int if_id);
 717 int ath_beaconq_setup(struct ath_hal *ah);
 718 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
 719 void ath_bstuck_process(struct ath_softc *sc);
 720 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
 721 void ath_beacon_sync(struct ath_softc *sc, int if_id);
 722 void ath_get_beaconconfig(struct ath_softc *sc,
 723                           int if_id,
 724                           struct ath_beacon_config *conf);
 725 /********/
 726 /* VAPs */
 727 /********/
 728
 729 /*
 730  * Define the scheme that we select MAC address for multiple
 731  * BSS on the same radio. The very first VAP will just use the MAC
 732  * address from the EEPROM. For the next 3 VAPs, we set the
 733  * U/L bit (bit 1) in MAC address, and use the next two bits as the
 734  * index of the VAP.
 735  */
 736
 737 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
 738         ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
 739
 740 /* VAP configuration (from protocol layer) */
 741 struct ath_vap_config {
 742         u32 av_fixed_rateset;
 743         u32 av_fixed_retryset;
 744 };
 745
 746 /* driver-specific vap state */
 747 struct ath_vap {
 748         struct ieee80211_vif *av_if_data;
 749         enum ath9k_opmode av_opmode;    /* VAP operational mode */
 750         struct ath_buf *av_bcbuf;       /* beacon buffer */
 751         struct ath_tx_control av_btxctl;  /* txctl information for beacon */
 752         int av_bslot;                   /* beacon slot index */
 753         struct ath_vap_config av_config;/* vap configuration parameters*/
 754         struct ath_rate_node *rc_node;
 755 };
 756
 757 int ath_vap_attach(struct ath_softc *sc,
 758                    int if_id,
 759                    struct ieee80211_vif *if_data,
 760                    enum ath9k_opmode opmode);
 761 int ath_vap_detach(struct ath_softc *sc, int if_id);
 762 int ath_vap_config(struct ath_softc *sc,
 763                    int if_id, struct ath_vap_config *if_config);
 764
 765 /*********************/
 766 /* Antenna diversity */
 767 /*********************/
 768
 769 #define ATH_ANT_DIV_MAX_CFG      2
 770 #define ATH_ANT_DIV_MIN_IDLE_US  1000000  /* us */
 771 #define ATH_ANT_DIV_MIN_SCAN_US  50000    /* us */
 772
 773 enum ATH_ANT_DIV_STATE{
 774         ATH_ANT_DIV_IDLE,
 775         ATH_ANT_DIV_SCAN,       /* evaluating antenna */
 776 };
 777
 778 struct ath_antdiv {
 779         struct ath_softc *antdiv_sc;
 780         u8 antdiv_start;
 781         enum ATH_ANT_DIV_STATE antdiv_state;
 782         u8 antdiv_num_antcfg;
 783         u8 antdiv_curcfg;
 784         u8 antdiv_bestcfg;
 785         int32_t antdivf_rssitrig;
 786         int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
 787         u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
 788         u64 antdiv_laststatetsf;
 789         u8 antdiv_bssid[ETH_ALEN];
 790 };
 791
 792 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
 793         struct ath_softc *sc, int32_t rssitrig);
 794 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
 795                             u8 num_antcfg,
 796                             const u8 *bssid);
 797 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
 798 void ath_slow_ant_div(struct ath_antdiv *antdiv,
 799                       struct ieee80211_hdr *wh,
 800                       struct ath_rx_status *rx_stats);
 801 void ath_setdefantenna(void *sc, u32 antenna);
 802
 803 /*******/
 804 /* ANI */
 805 /*******/
 806
 807 /* ANI values for STA only.
 808    FIXME: Add appropriate values for AP later */
 809
 810 #define ATH_ANI_POLLINTERVAL    100     /* 100 milliseconds between ANI poll */
 811 #define ATH_SHORT_CALINTERVAL   1000    /* 1 second between calibrations */
 812 #define ATH_LONG_CALINTERVAL    30000   /* 30 seconds between calibrations */
 813 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
 814
 815 struct ath_ani {
 816         bool sc_caldone;
 817         int16_t sc_noise_floor;
 818         unsigned int sc_longcal_timer;
 819         unsigned int sc_shortcal_timer;
 820         unsigned int sc_resetcal_timer;
 821         unsigned int sc_checkani_timer;
 822         struct timer_list timer;
 823 };
 824
 825 /********************/
 826 /*   LED Control    */
 827 /********************/
 828
 829 #define ATH_LED_PIN     1
 830
 831 enum ath_led_type {
 832         ATH_LED_RADIO,
 833         ATH_LED_ASSOC,
 834         ATH_LED_TX,
 835         ATH_LED_RX
 836 };
 837
 838 struct ath_led {
 839         struct ath_softc *sc;
 840         struct led_classdev led_cdev;
 841         enum ath_led_type led_type;
 842         char name[32];
 843         bool registered;
 844 };
 845
 846 /* Rfkill */
 847 #define ATH_RFKILL_POLL_INTERVAL        2000 /* msecs */
 848
 849 struct ath_rfkill {
 850         struct rfkill *rfkill;
 851         struct delayed_work rfkill_poll;
 852         char rfkill_name[32];
 853 };
 854
 855 /********************/
 856 /* Main driver core */
 857 /********************/
 858
 859 /*
 860  * Default cache line size, in bytes.
 861  * Used when PCI device not fully initialized by bootrom/BIOS
 862 */
 863 #define DEFAULT_CACHELINE       32
 864 #define ATH_DEFAULT_NOISE_FLOOR -95
 865 #define ATH_REGCLASSIDS_MAX     10
 866 #define ATH_CABQ_READY_TIME     80  /* % of beacon interval */
 867 #define ATH_MAX_SW_RETRIES      10
 868 #define ATH_CHAN_MAX            255
 869 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 870 #define IEEE80211_RATE_VAL      0x7f
 871 /*
 872  * The key cache is used for h/w cipher state and also for
 873  * tracking station state such as the current tx antenna.
 874  * We also setup a mapping table between key cache slot indices
 875  * and station state to short-circuit node lookups on rx.
 876  * Different parts have different size key caches.  We handle
 877  * up to ATH_KEYMAX entries (could dynamically allocate state).
 878  */
 879 #define ATH_KEYMAX              128        /* max key cache size we handle */
 880
 881 #define ATH_IF_ID_ANY           0xff
 882 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 883
 884 #define RSSI_LPF_THRESHOLD         -20
 885 #define ATH_RSSI_EP_MULTIPLIER     (1<<7)  /* pow2 to optimize out * and / */
 886 #define ATH_RATE_DUMMY_MARKER      0
 887 #define ATH_RSSI_LPF_LEN           10
 888 #define ATH_RSSI_DUMMY_MARKER      0x127
 889
 890 #define ATH_EP_MUL(x, mul)         ((x) * (mul))
 891 #define ATH_EP_RND(x, mul)                                              \
 892         ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
 893 #define ATH_RSSI_OUT(x)                                                 \
 894         (((x) != ATH_RSSI_DUMMY_MARKER) ?                               \
 895          (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
 896 #define ATH_RSSI_IN(x)                                  \
 897         (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
 898 #define ATH_LPF_RSSI(x, y, len)                                         \
 899         ((x != ATH_RSSI_DUMMY_MARKER) ? \
 900                 (((x) * ((len) - 1) + (y)) / (len)) : (y))
 901 #define ATH_RSSI_LPF(x, y) do {                                         \
 902                 if ((y) >= RSSI_LPF_THRESHOLD)                          \
 903                         x = ATH_LPF_RSSI((x), \
 904                                 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
 905         } while (0)
 906
 907
 908 enum PROT_MODE {
 909         PROT_M_NONE = 0,
 910         PROT_M_RTSCTS,
 911         PROT_M_CTSONLY
 912 };
 913
 914 enum RATE_TYPE {
 915         NORMAL_RATE = 0,
 916         HALF_RATE,
 917         QUARTER_RATE
 918 };
 919
 920 struct ath_ht_info {
 921         enum ath9k_ht_macmode tx_chan_width;
 922         u16 maxampdu;
 923         u8 mpdudensity;
 924         u8 ext_chan_offset;
 925 };
 926
 927 #define SC_OP_INVALID           BIT(0)
 928 #define SC_OP_BEACONS           BIT(1)
 929 #define SC_OP_RXAGGR            BIT(2)
 930 #define SC_OP_TXAGGR            BIT(3)
 931 #define SC_OP_CHAINMASK_UPDATE  BIT(4)
 932 #define SC_OP_FULL_RESET        BIT(5)
 933 #define SC_OP_NO_RESET          BIT(6)
 934 #define SC_OP_PREAMBLE_SHORT    BIT(7)
 935 #define SC_OP_PROTECT_ENABLE    BIT(8)
 936 #define SC_OP_RXFLUSH           BIT(9)
 937 #define SC_OP_LED_ASSOCIATED    BIT(10)
 938 #define SC_OP_RFKILL_REGISTERED BIT(11)
 939 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
 940 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
 941
 942 struct ath_softc {
 943         struct ieee80211_hw *hw;
 944         struct pci_dev *pdev;
 945         struct tasklet_struct intr_tq;
 946         struct tasklet_struct bcon_tasklet;
 947         struct ath_config sc_config;
 948         struct ath_hal *sc_ah;
 949         struct ath_rate_softc *sc_rc;
 950         void __iomem *mem;
 951
 952         u8 sc_curbssid[ETH_ALEN];
 953         u8 sc_myaddr[ETH_ALEN];
 954         u8 sc_bssidmask[ETH_ALEN];
 955
 956         int sc_debug;
 957         u32 sc_intrstatus;
 958         u32 sc_flags; /* SC_OP_* */
 959         unsigned int rx_filter;
 960         u16 sc_curtxpow;
 961         u16 sc_curaid;
 962         u16 sc_cachelsz;
 963         int sc_slotupdate;              /* slot to next advance fsm */
 964         int sc_slottime;
 965         int sc_bslot[ATH_BCBUF];
 966         u8 sc_tx_chainmask;
 967         u8 sc_rx_chainmask;
 968         enum ath9k_int sc_imask;
 969         enum wireless_mode sc_curmode;  /* current phy mode */
 970         enum PROT_MODE sc_protmode;
 971
 972         u8 sc_nbcnvaps;                 /* # of vaps sending beacons */
 973         u16 sc_nvaps;                   /* # of active virtual ap's */
 974         struct ath_vap *sc_vaps[ATH_BCBUF];
 975
 976         u8 sc_mcastantenna;
 977         u8 sc_defant;                   /* current default antenna */
 978         u8 sc_rxotherant;               /* rx's on non-default antenna */
 979
 980         struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
 981         struct list_head node_list;
 982         struct ath_ht_info sc_ht_info;
 983         enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
 984
 985 #ifdef CONFIG_SLOW_ANT_DIV
 986         struct ath_antdiv sc_antdiv;
 987 #endif
 988         enum {
 989                 OK,             /* no change needed */
 990                 UPDATE,         /* update pending */
 991                 COMMIT          /* beacon sent, commit change */
 992         } sc_updateslot;        /* slot time update fsm */
 993
 994         /* Crypto */
 995         u32 sc_keymax;          /* size of key cache */
 996         DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);  /* key use bit map */
 997         u8 sc_splitmic;         /* split TKIP MIC keys */
 998
 999         /* RX */
1000         struct list_head sc_rxbuf;
1001         struct ath_descdma sc_rxdma;
1002         int sc_rxbufsize;       /* rx size based on mtu */
1003         u32 *sc_rxlink;         /* link ptr in last RX desc */
1004
1005         /* TX */
1006         struct list_head sc_txbuf;
1007         struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
1008         struct ath_descdma sc_txdma;
1009         u32 sc_txqsetup;
1010         u32 sc_txintrperiod;    /* tx interrupt batching */
1011         int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
1012         u16 seq_no; /* TX sequence number */
1013
1014         /* Beacon */
1015         struct ath9k_tx_queue_info sc_beacon_qi;
1016         struct ath_descdma sc_bdma;
1017         struct ath_txq *sc_cabq;
1018         struct list_head sc_bbuf;
1019         u32 sc_bhalq;
1020         u32 sc_bmisscount;
1021         u32 ast_be_xmit;        /* beacons transmitted */
1022         u64 bc_tstamp;
1023
1024         /* Rate */
1025         struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
1026         const struct ath9k_rate_table *sc_currates;
1027         u8 sc_rixmap[256];      /* IEEE to h/w rate table ix */
1028         u8 sc_protrix;          /* protection rate index */
1029         struct {
1030                 u32 rateKbps;   /* transfer rate in kbs */
1031                 u8 ieeerate;    /* IEEE rate */
1032         } sc_hwmap[256];        /* h/w rate ix mappings */
1033
1034         /* Channel, Band */
1035         struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
1036         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1037
1038         /* Locks */
1039         spinlock_t sc_rxflushlock;
1040         spinlock_t sc_rxbuflock;
1041         spinlock_t sc_txbuflock;
1042         spinlock_t sc_resetlock;
1043         spinlock_t node_lock;
1044
1045         /* LEDs */
1046         struct ath_led radio_led;
1047         struct ath_led assoc_led;
1048         struct ath_led tx_led;
1049         struct ath_led rx_led;
1050
1051         /* Rfkill */
1052         struct ath_rfkill rf_kill;
1053
1054         /* ANI */
1055         struct ath_ani sc_ani;
1056 };
1057
1058 int ath_init(u16 devid, struct ath_softc *sc);
1059 void ath_deinit(struct ath_softc *sc);
1060 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1061 int ath_suspend(struct ath_softc *sc);
1062 irqreturn_t ath_isr(int irq, void *dev);
1063 int ath_reset(struct ath_softc *sc, bool retry_tx);
1064 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
1065
1066 /*********************/
1067 /* Utility Functions */
1068 /*********************/
1069
1070 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1071 int ath_keyset(struct ath_softc *sc,
1072                u16 keyix,
1073                struct ath9k_keyval *hk,
1074                const u8 mac[ETH_ALEN]);
1075 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1076 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1077 void ath_setslottime(struct ath_softc *sc);
1078 void ath_update_txpow(struct ath_softc *sc);
1079 int ath_cabq_update(struct ath_softc *);
1080 void ath_get_currentCountry(struct ath_softc *sc,
1081         struct ath9k_country_entry *ctry);
1082 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
1083
1084 #endif /* CORE_H */